operands.isa revision 12110 
1// -*- mode:c++ -*-
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14// Copyright (c) 2007-2008 The Florida State University
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39//
40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : 'int8_t',
44    'ub' : 'uint8_t',
45    'sh' : 'int16_t',
46    'uh' : 'uint16_t',
47    'sw' : 'int32_t',
48    'uw' : 'uint32_t',
49    'ud' : 'uint64_t',
50    'tud' : 'Twin64_t',
51    'sf' : 'float',
52    'df' : 'double',
53    'vc' : 'TheISA::VecRegContainer',
54    # For operations that are implemented as a template
55    'x' : 'TPElem',
56}};
57
58let {{
59    maybePCRead = '''
60        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
61    '''
62    maybeAlignedPCRead = '''
63        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
64         xc->%(func)s(this, %(op_idx)s))
65    '''
66    maybePCWrite = '''
67        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
68         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
69    '''
70    maybeIWPCWrite = '''
71        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
72         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
73    '''
74    maybeAIWPCWrite = '''
75        if (%(reg_idx)s == PCReg) {
76            bool thumb = THUMB;
77            if (thumb) {
78                setNextPC(xc, %(final_val)s);
79            } else {
80                setIWNextPC(xc, %(final_val)s);
81            }
82        } else {
83            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
84        }
85    '''
86    aarch64Read = '''
87        ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
88    '''
89    aarch64Write = '''
90        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
91    '''
92    aarchX64Read = '''
93        ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
94    '''
95    aarchX64Write = '''
96        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
97    '''
98    aarchW64Read = '''
99        ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
100    '''
101    aarchW64Write = '''
102        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
103    '''
104    cntrlNsBankedWrite = '''
105        xc->setMiscReg(flattenMiscRegNsBanked(dest, xc->tcBase()), %(final_val)s)
106    '''
107
108    cntrlNsBankedRead = '''
109        xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
110    '''
111
112    #PCState operands need to have a sorting index (the number at the end)
113    #less than all the integer registers which might update the PC. That way
114    #if the flag bits of the pc state are updated and a branch happens through
115    #R15, the updates are layered properly and the R15 update isn't lost.
116    srtNormal = 5
117    srtCpsr = 4
118    srtBase = 3
119    srtPC = 2
120    srtMode = 1
121    srtEPC = 0
122
123    def vectorElem(idx, elem):
124        return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
125
126    def vectorReg(idx, elems = None):
127        return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
128
129    def vectorRegElem(elem, ext = 'sf', zeroing = False):
130        return (elem, ext, zeroing)
131
132    def floatReg(idx):
133        return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
134
135    def intReg(idx):
136        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
137                maybePCRead, maybePCWrite)
138
139    def intReg64(idx):
140        return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
141                aarch64Read, aarch64Write)
142
143    def intRegX64(idx, id = srtNormal):
144        return ('IntReg', 'ud', idx, 'IsInteger', id,
145                aarchX64Read, aarchX64Write)
146
147    def intRegW64(idx, id = srtNormal):
148        return ('IntReg', 'ud', idx, 'IsInteger', id,
149                aarchW64Read, aarchW64Write)
150
151    def intRegNPC(idx):
152        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
153
154    def intRegAPC(idx, id = srtNormal):
155        return ('IntReg', 'uw', idx, 'IsInteger', id,
156                maybeAlignedPCRead, maybePCWrite)
157
158    def intRegIWPC(idx):
159        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
160                maybePCRead, maybeIWPCWrite)
161
162    def intRegAIWPC(idx):
163        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
164                maybePCRead, maybeAIWPCWrite)
165
166    def ccReg(idx):
167        return ('CCReg', 'uw', idx, None, srtNormal)
168
169    def cntrlReg(idx, id = srtNormal, type = 'uw'):
170        return ('ControlReg', type, idx, None, id)
171
172    def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
173        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
174
175    def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
176        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
177
178    def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
179        return ('ControlReg', type, idx, None, id)
180
181    def pcStateReg(idx, id):
182        return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
183}};
184
185def operands {{
186    #Abstracted integer reg operands
187    'Dest': intReg('dest'),
188    'Dest64': intReg64('dest'),
189    'XDest': intRegX64('dest'),
190    'WDest': intRegW64('dest'),
191    'IWDest': intRegIWPC('dest'),
192    'AIWDest': intRegAIWPC('dest'),
193    'Dest2': intReg('dest2'),
194    'XDest2': intRegX64('dest2'),
195    'FDest2': floatReg('dest2'),
196    'Result': intReg('result'),
197    'XResult': intRegX64('result'),
198    'XBase': intRegX64('base', id = srtBase),
199    'Base': intRegAPC('base', id = srtBase),
200    'XOffset': intRegX64('offset'),
201    'Index': intReg('index'),
202    'Shift': intReg('shift'),
203    'Op1': intReg('op1'),
204    'Op2': intReg('op2'),
205    'Op3': intReg('op3'),
206    'Op164': intReg64('op1'),
207    'Op264': intReg64('op2'),
208    'Op364': intReg64('op3'),
209    'XOp1': intRegX64('op1'),
210    'XOp2': intRegX64('op2'),
211    'XOp3': intRegX64('op3'),
212    'WOp1': intRegW64('op1'),
213    'WOp2': intRegW64('op2'),
214    'WOp3': intRegW64('op3'),
215    'Reg0': intReg('reg0'),
216    'Reg1': intReg('reg1'),
217    'Reg2': intReg('reg2'),
218    'Reg3': intReg('reg3'),
219
220    #Fixed index integer reg operands
221    'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
222    'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
223    'LR': intRegNPC('INTREG_LR'),
224    'XLR': intRegX64('INTREG_X30'),
225    'R7': intRegNPC('7'),
226    # First four arguments are passed in registers
227    'R0': intRegNPC('0'),
228    'R1': intRegNPC('1'),
229    'R2': intRegNPC('2'),
230    'R3': intRegNPC('3'),
231    'X0': intRegX64('0'),
232    'X1': intRegX64('1'),
233    'X2': intRegX64('2'),
234    'X3': intRegX64('3'),
235
236    # Condition code registers
237    'CondCodesNZ': ccReg('CCREG_NZ'),
238    'CondCodesC': ccReg('CCREG_C'),
239    'CondCodesV': ccReg('CCREG_V'),
240    'CondCodesGE': ccReg('CCREG_GE'),
241    'OptCondCodesNZ': ccReg(
242            '''((condCode == COND_AL || condCode == COND_UC ||
243                 condCode == COND_CC || condCode == COND_CS ||
244                 condCode == COND_VS || condCode == COND_VC) ?
245                CCREG_ZERO : CCREG_NZ)'''),
246    'OptCondCodesC': ccReg(
247             '''((condCode == COND_HI || condCode == COND_LS ||
248                condCode == COND_CS || condCode == COND_CC) ?
249               CCREG_C : CCREG_ZERO)'''),
250    'OptShiftRmCondCodesC': ccReg(
251            '''((condCode == COND_HI || condCode == COND_LS ||
252                 condCode == COND_CS || condCode == COND_CC ||
253                 shiftType == ROR) ?
254                CCREG_C : CCREG_ZERO)'''),
255    'OptCondCodesV': ccReg(
256            '''((condCode == COND_VS || condCode == COND_VC ||
257                 condCode == COND_GE || condCode == COND_LT ||
258                 condCode == COND_GT || condCode == COND_LE) ?
259                CCREG_V : CCREG_ZERO)'''),
260    'FpCondCodes': ccReg('CCREG_FP'),
261
262    #Abstracted floating point reg operands
263    'FpDest': floatReg('(dest + 0)'),
264    'FpDestP0': floatReg('(dest + 0)'),
265    'FpDestP1': floatReg('(dest + 1)'),
266    'FpDestP2': floatReg('(dest + 2)'),
267    'FpDestP3': floatReg('(dest + 3)'),
268    'FpDestP4': floatReg('(dest + 4)'),
269    'FpDestP5': floatReg('(dest + 5)'),
270    'FpDestP6': floatReg('(dest + 6)'),
271    'FpDestP7': floatReg('(dest + 7)'),
272    'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
273    'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
274    'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
275    'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
276    'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
277    'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
278    'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
279    'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
280
281    'FpDest2': floatReg('(dest2 + 0)'),
282    'FpDest2P0': floatReg('(dest2 + 0)'),
283    'FpDest2P1': floatReg('(dest2 + 1)'),
284    'FpDest2P2': floatReg('(dest2 + 2)'),
285    'FpDest2P3': floatReg('(dest2 + 3)'),
286
287    'FpOp1': floatReg('(op1 + 0)'),
288    'FpOp1P0': floatReg('(op1 + 0)'),
289    'FpOp1P1': floatReg('(op1 + 1)'),
290    'FpOp1P2': floatReg('(op1 + 2)'),
291    'FpOp1P3': floatReg('(op1 + 3)'),
292    'FpOp1P4': floatReg('(op1 + 4)'),
293    'FpOp1P5': floatReg('(op1 + 5)'),
294    'FpOp1P6': floatReg('(op1 + 6)'),
295    'FpOp1P7': floatReg('(op1 + 7)'),
296    'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
297    'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
298    'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
299    'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
300    'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
301    'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
302    'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
303    'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
304
305    'FpOp2': floatReg('(op2 + 0)'),
306    'FpOp2P0': floatReg('(op2 + 0)'),
307    'FpOp2P1': floatReg('(op2 + 1)'),
308    'FpOp2P2': floatReg('(op2 + 2)'),
309    'FpOp2P3': floatReg('(op2 + 3)'),
310
311    # Create AArch64 unpacked view of the FP registers
312    # Name   ::= 'AA64Vec' OpSpec [LaneSpec]
313    # OpSpec ::= IOSpec [Index] [Plus]
314    # IOSpec ::= 'S' | 'D'
315    # Index  ::= '0' | ... | '9'
316    # Plus  ::= [PlusAmount] ['l']
317    # PlusAmount ::= 'p' [PlusAmount]
318    # LaneSpec ::= 'L' Index
319    #
320    # All the constituents are hierarchically defined as part of the Vector
321    # Register they belong to
322
323    'AA64FpOp1':       vectorReg('op1',
324    {
325        'AA64FpOp1P0': vectorRegElem('0'),
326        'AA64FpOp1P1': vectorRegElem('1'),
327        'AA64FpOp1P2': vectorRegElem('2'),
328        'AA64FpOp1P3': vectorRegElem('3'),
329        'AA64FpOp1S':  vectorRegElem('0', 'sf', zeroing = True),
330        'AA64FpOp1D':  vectorRegElem('0', 'df', zeroing = True),
331        'AA64FpOp1Q':  vectorRegElem('0', 'tud', zeroing = True)
332    }),
333
334    'AA64FpOp2':       vectorReg('op2',
335    {
336        'AA64FpOp2P0': vectorRegElem('0'),
337        'AA64FpOp2P1': vectorRegElem('1'),
338        'AA64FpOp2P2': vectorRegElem('2'),
339        'AA64FpOp2P3': vectorRegElem('3'),
340        'AA64FpOp2S':  vectorRegElem('0', 'sf', zeroing = True),
341        'AA64FpOp2D':  vectorRegElem('0', 'df', zeroing = True),
342        'AA64FpOp2Q':  vectorRegElem('0', 'tud', zeroing = True)
343    }),
344
345    'AA64FpOp3':       vectorReg('op3',
346    {
347        'AA64FpOp3P0': vectorRegElem('0'),
348        'AA64FpOp3P1': vectorRegElem('1'),
349        'AA64FpOp3P2': vectorRegElem('2'),
350        'AA64FpOp3P3': vectorRegElem('3'),
351        'AA64FpOp3S':  vectorRegElem('0', 'sf', zeroing = True),
352        'AA64FpOp3D':  vectorRegElem('0', 'df', zeroing = True),
353        'AA64FpOp3Q':  vectorRegElem('0', 'tud', zeroing = True)
354    }),
355
356    'AA64FpDest':       vectorReg('dest',
357    {
358        'AA64FpDestP0': vectorRegElem('0'),
359        'AA64FpDestP1': vectorRegElem('1'),
360        'AA64FpDestP2': vectorRegElem('2'),
361        'AA64FpDestP3': vectorRegElem('3'),
362        'AA64FpDestS':  vectorRegElem('0', 'sf', zeroing = True),
363        'AA64FpDestD':  vectorRegElem('0', 'df', zeroing = True),
364        'AA64FpDestQ':  vectorRegElem('0', 'tud', zeroing = True)
365    }),
366
367    'AA64FpDest2':       vectorReg('dest2',
368    {
369        'AA64FpDest2P0': vectorRegElem('0'),
370        'AA64FpDest2P1': vectorRegElem('1'),
371        'AA64FpDest2P2': vectorRegElem('2'),
372        'AA64FpDest2P3': vectorRegElem('3'),
373        'AA64FpDest2S':  vectorRegElem('0', 'sf', zeroing = True),
374        'AA64FpDest2D':  vectorRegElem('0', 'df', zeroing = True),
375        'AA64FpDest2Q':  vectorRegElem('0', 'tud', zeroing = True)
376    }),
377
378    'AA64FpOp1V0':       vectorReg('op1',
379    {
380        'AA64FpOp1P0V0': vectorRegElem('0'),
381        'AA64FpOp1P1V0': vectorRegElem('1'),
382        'AA64FpOp1P2V0': vectorRegElem('2'),
383        'AA64FpOp1P3V0': vectorRegElem('3'),
384        'AA64FpOp1SV0':  vectorRegElem('0', 'sf', zeroing = True),
385        'AA64FpOp1DV0':  vectorRegElem('0', 'df', zeroing = True),
386        'AA64FpOp1QV0':  vectorRegElem('0', 'tud', zeroing = True)
387    }),
388
389    'AA64FpOp1V1':       vectorReg('op1+1',
390    {
391        'AA64FpOp1P0V1': vectorRegElem('0'),
392        'AA64FpOp1P1V1': vectorRegElem('1'),
393        'AA64FpOp1P2V1': vectorRegElem('2'),
394        'AA64FpOp1P3V1': vectorRegElem('3'),
395        'AA64FpOp1SV1':  vectorRegElem('0', 'sf', zeroing = True),
396        'AA64FpOp1DV1':  vectorRegElem('0', 'df', zeroing = True),
397        'AA64FpOp1QV1':  vectorRegElem('0', 'tud', zeroing = True)
398    }),
399
400    'AA64FpOp1V2':       vectorReg('op1+2',
401    {
402        'AA64FpOp1P0V2': vectorRegElem('0'),
403        'AA64FpOp1P1V2': vectorRegElem('1'),
404        'AA64FpOp1P2V2': vectorRegElem('2'),
405        'AA64FpOp1P3V2': vectorRegElem('3'),
406        'AA64FpOp1SV2':  vectorRegElem('0', 'sf', zeroing = True),
407        'AA64FpOp1DV2':  vectorRegElem('0', 'df', zeroing = True),
408        'AA64FpOp1QV2':  vectorRegElem('0', 'tud', zeroing = True)
409    }),
410
411    'AA64FpOp1V3':       vectorReg('op1+3',
412    {
413        'AA64FpOp1P0V3': vectorRegElem('0'),
414        'AA64FpOp1P1V3': vectorRegElem('1'),
415        'AA64FpOp1P2V3': vectorRegElem('2'),
416        'AA64FpOp1P3V3': vectorRegElem('3'),
417        'AA64FpOp1SV3':  vectorRegElem('0', 'sf', zeroing = True),
418        'AA64FpOp1DV3':  vectorRegElem('0', 'df', zeroing = True),
419        'AA64FpOp1QV3':  vectorRegElem('0', 'tud', zeroing = True)
420    }),
421
422    'AA64FpOp1V0S':       vectorReg('(op1+0)%32',
423    {
424        'AA64FpOp1P0V0S': vectorRegElem('0'),
425        'AA64FpOp1P1V0S': vectorRegElem('1'),
426        'AA64FpOp1P2V0S': vectorRegElem('2'),
427        'AA64FpOp1P3V0S': vectorRegElem('3'),
428        'AA64FpOp1SV0S':  vectorRegElem('0', 'sf', zeroing = True),
429        'AA64FpOp1DV0S':  vectorRegElem('0', 'df', zeroing = True),
430        'AA64FpOp1QV0S':  vectorRegElem('0', 'tud', zeroing = True)
431    }),
432
433    'AA64FpOp1V1S':       vectorReg('(op1+1)%32',
434    {
435        'AA64FpOp1P0V1S': vectorRegElem('0'),
436        'AA64FpOp1P1V1S': vectorRegElem('1'),
437        'AA64FpOp1P2V1S': vectorRegElem('2'),
438        'AA64FpOp1P3V1S': vectorRegElem('3'),
439        'AA64FpOp1SV1S':  vectorRegElem('0', 'sf', zeroing = True),
440        'AA64FpOp1DV1S':  vectorRegElem('0', 'df', zeroing = True),
441        'AA64FpOp1QV1S':  vectorRegElem('0', 'tud', zeroing = True)
442    }),
443
444    'AA64FpOp1V2S':       vectorReg('(op1+2)%32',
445    {
446        'AA64FpOp1P0V2S': vectorRegElem('0'),
447        'AA64FpOp1P1V2S': vectorRegElem('1'),
448        'AA64FpOp1P2V2S': vectorRegElem('2'),
449        'AA64FpOp1P3V2S': vectorRegElem('3'),
450        'AA64FpOp1SV2S':  vectorRegElem('0', 'sf', zeroing = True),
451        'AA64FpOp1DV2S':  vectorRegElem('0', 'df', zeroing = True),
452        'AA64FpOp1QV2S':  vectorRegElem('0', 'tud', zeroing = True)
453    }),
454
455    'AA64FpOp1V3S':       vectorReg('(op1+3)%32',
456    {
457        'AA64FpOp1P0V3S': vectorRegElem('0'),
458        'AA64FpOp1P1V3S': vectorRegElem('1'),
459        'AA64FpOp1P2V3S': vectorRegElem('2'),
460        'AA64FpOp1P3V3S': vectorRegElem('3'),
461        'AA64FpOp1SV3S':  vectorRegElem('0', 'sf', zeroing = True),
462        'AA64FpOp1DV3S':  vectorRegElem('0', 'df', zeroing = True),
463        'AA64FpOp1QV3S':  vectorRegElem('0', 'tud', zeroing = True)
464    }),
465
466    'AA64FpDestV0':       vectorReg('(dest+0)',
467    {
468        'AA64FpDestP0V0': vectorRegElem('0'),
469        'AA64FpDestP1V0': vectorRegElem('1'),
470        'AA64FpDestP2V0': vectorRegElem('2'),
471        'AA64FpDestP3V0': vectorRegElem('3'),
472        'AA64FpDestSV0':  vectorRegElem('0', 'sf', zeroing = True),
473        'AA64FpDestDV0':  vectorRegElem('0', 'df', zeroing = True),
474        'AA64FpDestQV0':  vectorRegElem('0', 'tud', zeroing = True)
475    }),
476
477    'AA64FpDestV1':       vectorReg('(dest+1)',
478    {
479        'AA64FpDestP0V1': vectorRegElem('0'),
480        'AA64FpDestP1V1': vectorRegElem('1'),
481        'AA64FpDestP2V1': vectorRegElem('2'),
482        'AA64FpDestP3V1': vectorRegElem('3'),
483        'AA64FpDestSV1':  vectorRegElem('0', 'sf', zeroing = True),
484        'AA64FpDestDV1':  vectorRegElem('0', 'df', zeroing = True),
485        'AA64FpDestQV1':  vectorRegElem('0', 'tud', zeroing = True)
486    }),
487
488    'AA64FpDestV0L':       vectorReg('(dest+0)%32',
489    {
490        'AA64FpDestP0V0L': vectorRegElem('0'),
491        'AA64FpDestP1V0L': vectorRegElem('1'),
492        'AA64FpDestP2V0L': vectorRegElem('2'),
493        'AA64FpDestP3V0L': vectorRegElem('3'),
494        'AA64FpDestSV0L':  vectorRegElem('0', 'sf', zeroing = True),
495        'AA64FpDestDV0L':  vectorRegElem('0', 'df', zeroing = True),
496        'AA64FpDestQV0L':  vectorRegElem('0', 'tud', zeroing = True)
497    }),
498
499    'AA64FpDestV1L':       vectorReg('(dest+1)%32',
500    {
501        'AA64FpDestP0V1L': vectorRegElem('0'),
502        'AA64FpDestP1V1L': vectorRegElem('1'),
503        'AA64FpDestP2V1L': vectorRegElem('2'),
504        'AA64FpDestP3V1L': vectorRegElem('3'),
505        'AA64FpDestSV1L':  vectorRegElem('0', 'sf', zeroing = True),
506        'AA64FpDestDV1L':  vectorRegElem('0', 'df', zeroing = True),
507        'AA64FpDestQV1L':  vectorRegElem('0', 'tud', zeroing = True)
508    }),
509
510    #Abstracted control reg operands
511    'MiscDest': cntrlReg('dest'),
512    'MiscOp1': cntrlReg('op1'),
513    'MiscNsBankedDest': cntrlNsBankedReg('dest'),
514    'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
515    'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
516    'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
517
518    #Fixed index control regs
519    'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
520    'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
521    'Spsr': cntrlRegNC('MISCREG_SPSR'),
522    'Fpsr': cntrlRegNC('MISCREG_FPSR'),
523    'Fpsid': cntrlRegNC('MISCREG_FPSID'),
524    'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
525    'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
526    'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
527    'Cpacr': cntrlReg('MISCREG_CPACR'),
528    'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
529    'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
530    'Nsacr': cntrlReg('MISCREG_NSACR'),
531    'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
532    'Hcr': cntrlReg('MISCREG_HCR'),
533    'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
534    'Hdcr': cntrlReg('MISCREG_HDCR'),
535    'Hcptr': cntrlReg('MISCREG_HCPTR'),
536    'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
537    'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
538    'Hstr': cntrlReg('MISCREG_HSTR'),
539    'Scr': cntrlReg('MISCREG_SCR'),
540    'Scr64': cntrlReg('MISCREG_SCR_EL3'),
541    'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
542    'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
543    'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
544    'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
545
546    #Register fields for microops
547    'URa' : intReg('ura'),
548    'XURa' : intRegX64('ura'),
549    'WURa' : intRegW64('ura'),
550    'IWRa' : intRegIWPC('ura'),
551    'Fa' : floatReg('ura'),
552    'FaP1' : floatReg('ura + 1'),
553    'URb' : intReg('urb'),
554    'XURb' : intRegX64('urb'),
555    'URc' : intReg('urc'),
556    'XURc' : intRegX64('urc'),
557
558    #Memory Operand
559    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
560
561    #PCState fields
562    'RawPC': pcStateReg('pc', srtPC),
563    'PC': pcStateReg('instPC', srtPC),
564    'NPC': pcStateReg('instNPC', srtPC),
565    'pNPC': pcStateReg('instNPC', srtEPC),
566    'IWNPC': pcStateReg('instIWNPC', srtPC),
567    'Thumb': pcStateReg('thumb', srtPC),
568    'NextThumb': pcStateReg('nextThumb', srtMode),
569    'NextJazelle': pcStateReg('nextJazelle', srtMode),
570    'NextItState': pcStateReg('nextItstate', srtMode),
571    'Itstate': pcStateReg('itstate', srtMode),
572    'NextAArch64': pcStateReg('nextAArch64', srtMode),
573
574    #Register operands depending on a field in the instruction encoding. These
575    #should be avoided since they may not be portable across different
576    #encodings of the same instruction.
577    'Rd': intReg('RD'),
578    'Rm': intReg('RM'),
579    'Rs': intReg('RS'),
580    'Rn': intReg('RN'),
581    'Rt': intReg('RT')
582}};
583