sve_mem.isa revision 14028
114028Sgiacomo.gabrielli@arm.com// Copyright (c) 2017-2018 ARM Limited 213955Sgiacomo.gabrielli@arm.com// All rights reserved 313955Sgiacomo.gabrielli@arm.com// 413955Sgiacomo.gabrielli@arm.com// The license below extends only to copyright in the software and shall 513955Sgiacomo.gabrielli@arm.com// not be construed as granting a license to any other intellectual 613955Sgiacomo.gabrielli@arm.com// property including but not limited to intellectual property relating 713955Sgiacomo.gabrielli@arm.com// to a hardware implementation of the functionality of the software 813955Sgiacomo.gabrielli@arm.com// licensed hereunder. You may use the software subject to the license 913955Sgiacomo.gabrielli@arm.com// terms below provided that you ensure that this notice is replicated 1013955Sgiacomo.gabrielli@arm.com// unmodified and in its entirety in all distributions of the software, 1113955Sgiacomo.gabrielli@arm.com// modified or unmodified, in source code or in binary form. 1213955Sgiacomo.gabrielli@arm.com// 1313955Sgiacomo.gabrielli@arm.com// Redistribution and use in source and binary forms, with or without 1413955Sgiacomo.gabrielli@arm.com// modification, are permitted provided that the following conditions are 1513955Sgiacomo.gabrielli@arm.com// met: redistributions of source code must retain the above copyright 1613955Sgiacomo.gabrielli@arm.com// notice, this list of conditions and the following disclaimer; 1713955Sgiacomo.gabrielli@arm.com// redistributions in binary form must reproduce the above copyright 1813955Sgiacomo.gabrielli@arm.com// notice, this list of conditions and the following disclaimer in the 1913955Sgiacomo.gabrielli@arm.com// documentation and/or other materials provided with the distribution; 2013955Sgiacomo.gabrielli@arm.com// neither the name of the copyright holders nor the names of its 2113955Sgiacomo.gabrielli@arm.com// contributors may be used to endorse or promote products derived from 2213955Sgiacomo.gabrielli@arm.com// this software without specific prior written permission. 2313955Sgiacomo.gabrielli@arm.com// 2413955Sgiacomo.gabrielli@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2513955Sgiacomo.gabrielli@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2613955Sgiacomo.gabrielli@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2713955Sgiacomo.gabrielli@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2813955Sgiacomo.gabrielli@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2913955Sgiacomo.gabrielli@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3013955Sgiacomo.gabrielli@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3113955Sgiacomo.gabrielli@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3213955Sgiacomo.gabrielli@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3313955Sgiacomo.gabrielli@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3413955Sgiacomo.gabrielli@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3513955Sgiacomo.gabrielli@arm.com// 3613955Sgiacomo.gabrielli@arm.com// Authors: Giacomo Gabrielli 3713955Sgiacomo.gabrielli@arm.com 3813955Sgiacomo.gabrielli@arm.com// @file Definition of SVE memory access instructions. 3913955Sgiacomo.gabrielli@arm.com 4013955Sgiacomo.gabrielli@arm.comoutput header {{ 4113955Sgiacomo.gabrielli@arm.com 4213955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous load instructions, scalar plus scalar form. 4313955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 4413955Sgiacomo.gabrielli@arm.com StaticInstPtr 4513955Sgiacomo.gabrielli@arm.com decodeSveContigLoadSSInsts(uint8_t dtype, ExtMachInst machInst, 4613955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 4713955Sgiacomo.gabrielli@arm.com IntRegIndex rm, bool firstFaulting) 4813955Sgiacomo.gabrielli@arm.com { 4913955Sgiacomo.gabrielli@arm.com const char* mn = firstFaulting ? "ldff1" : "ld1"; 5013955Sgiacomo.gabrielli@arm.com switch (dtype) { 5113955Sgiacomo.gabrielli@arm.com case 0x0: 5213955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5313955Sgiacomo.gabrielli@arm.com case 0x1: 5413955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5513955Sgiacomo.gabrielli@arm.com case 0x2: 5613955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5713955Sgiacomo.gabrielli@arm.com case 0x3: 5813955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5913955Sgiacomo.gabrielli@arm.com case 0x4: 6013955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int32_t>(mn, machInst, zt, pg, rn, rm); 6113955Sgiacomo.gabrielli@arm.com case 0x5: 6213955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 6313955Sgiacomo.gabrielli@arm.com case 0x6: 6413955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 6513955Sgiacomo.gabrielli@arm.com case 0x7: 6613955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 6713955Sgiacomo.gabrielli@arm.com case 0x8: 6813955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int16_t>(mn, machInst, zt, pg, rn, rm); 6913955Sgiacomo.gabrielli@arm.com case 0x9: 7013955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int16_t>(mn, machInst, zt, pg, rn, rm); 7113955Sgiacomo.gabrielli@arm.com case 0xa: 7213955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 7313955Sgiacomo.gabrielli@arm.com case 0xb: 7413955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 7513955Sgiacomo.gabrielli@arm.com case 0xc: 7613955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int8_t>(mn, machInst, zt, pg, rn, rm); 7713955Sgiacomo.gabrielli@arm.com case 0xd: 7813955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int8_t>(mn, machInst, zt, pg, rn, rm); 7913955Sgiacomo.gabrielli@arm.com case 0xe: 8013955Sgiacomo.gabrielli@arm.com return new Base<int16_t, int8_t>(mn, machInst, zt, pg, rn, rm); 8113955Sgiacomo.gabrielli@arm.com case 0xf: 8213955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, rm); 8313955Sgiacomo.gabrielli@arm.com } 8413955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 8513955Sgiacomo.gabrielli@arm.com } 8613955Sgiacomo.gabrielli@arm.com 8713955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous load instructions, scalar plus immediate form. 8813955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 8913955Sgiacomo.gabrielli@arm.com StaticInstPtr 9013955Sgiacomo.gabrielli@arm.com decodeSveContigLoadSIInsts(uint8_t dtype, ExtMachInst machInst, 9113955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 9213955Sgiacomo.gabrielli@arm.com uint64_t imm, bool firstFaulting, 9313955Sgiacomo.gabrielli@arm.com bool replicate = false) 9413955Sgiacomo.gabrielli@arm.com { 9513955Sgiacomo.gabrielli@arm.com assert(!(replicate && firstFaulting)); 9613955Sgiacomo.gabrielli@arm.com 9713955Sgiacomo.gabrielli@arm.com const char* mn = replicate ? "ld1r" : 9813955Sgiacomo.gabrielli@arm.com (firstFaulting ? "ldff1" : "ld1"); 9913955Sgiacomo.gabrielli@arm.com switch (dtype) { 10013955Sgiacomo.gabrielli@arm.com case 0x0: 10113955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10213955Sgiacomo.gabrielli@arm.com case 0x1: 10313955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10413955Sgiacomo.gabrielli@arm.com case 0x2: 10513955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10613955Sgiacomo.gabrielli@arm.com case 0x3: 10713955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10813955Sgiacomo.gabrielli@arm.com case 0x4: 10913955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int32_t>(mn, machInst, zt, pg, rn, imm); 11013955Sgiacomo.gabrielli@arm.com case 0x5: 11113955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 11213955Sgiacomo.gabrielli@arm.com case 0x6: 11313955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 11413955Sgiacomo.gabrielli@arm.com case 0x7: 11513955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 11613955Sgiacomo.gabrielli@arm.com case 0x8: 11713955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int16_t>(mn, machInst, zt, pg, rn, imm); 11813955Sgiacomo.gabrielli@arm.com case 0x9: 11913955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int16_t>(mn, machInst, zt, pg, rn, imm); 12013955Sgiacomo.gabrielli@arm.com case 0xa: 12113955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 12213955Sgiacomo.gabrielli@arm.com case 0xb: 12313955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 12413955Sgiacomo.gabrielli@arm.com case 0xc: 12513955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int8_t>(mn, machInst, zt, pg, rn, imm); 12613955Sgiacomo.gabrielli@arm.com case 0xd: 12713955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int8_t>(mn, machInst, zt, pg, rn, imm); 12813955Sgiacomo.gabrielli@arm.com case 0xe: 12913955Sgiacomo.gabrielli@arm.com return new Base<int16_t, int8_t>(mn, machInst, zt, pg, rn, imm); 13013955Sgiacomo.gabrielli@arm.com case 0xf: 13113955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, imm); 13213955Sgiacomo.gabrielli@arm.com } 13313955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 13413955Sgiacomo.gabrielli@arm.com } 13513955Sgiacomo.gabrielli@arm.com 13613955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous store instructions, scalar plus scalar form. 13713955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 13813955Sgiacomo.gabrielli@arm.com StaticInstPtr 13913955Sgiacomo.gabrielli@arm.com decodeSveContigStoreSSInsts(uint8_t dtype, ExtMachInst machInst, 14013955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 14113955Sgiacomo.gabrielli@arm.com IntRegIndex rm) 14213955Sgiacomo.gabrielli@arm.com { 14313955Sgiacomo.gabrielli@arm.com const char* mn = "st1"; 14413955Sgiacomo.gabrielli@arm.com switch (dtype) { 14513955Sgiacomo.gabrielli@arm.com case 0x0: 14613955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 14713955Sgiacomo.gabrielli@arm.com case 0x1: 14813955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 14913955Sgiacomo.gabrielli@arm.com case 0x2: 15013955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 15113955Sgiacomo.gabrielli@arm.com case 0x3: 15213955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 15313955Sgiacomo.gabrielli@arm.com case 0x5: 15413955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 15513955Sgiacomo.gabrielli@arm.com case 0x6: 15613955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 15713955Sgiacomo.gabrielli@arm.com case 0x7: 15813955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 15913955Sgiacomo.gabrielli@arm.com case 0xa: 16013955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 16113955Sgiacomo.gabrielli@arm.com case 0xb: 16213955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 16313955Sgiacomo.gabrielli@arm.com case 0xf: 16413955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, rm); 16513955Sgiacomo.gabrielli@arm.com } 16613955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 16713955Sgiacomo.gabrielli@arm.com } 16813955Sgiacomo.gabrielli@arm.com 16913955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous store instructions, scalar plus immediate form. 17013955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 17113955Sgiacomo.gabrielli@arm.com StaticInstPtr 17213955Sgiacomo.gabrielli@arm.com decodeSveContigStoreSIInsts(uint8_t dtype, ExtMachInst machInst, 17313955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 17413955Sgiacomo.gabrielli@arm.com int8_t imm) 17513955Sgiacomo.gabrielli@arm.com { 17613955Sgiacomo.gabrielli@arm.com const char* mn = "st1"; 17713955Sgiacomo.gabrielli@arm.com switch (dtype) { 17813955Sgiacomo.gabrielli@arm.com case 0x0: 17913955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18013955Sgiacomo.gabrielli@arm.com case 0x1: 18113955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18213955Sgiacomo.gabrielli@arm.com case 0x2: 18313955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18413955Sgiacomo.gabrielli@arm.com case 0x3: 18513955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18613955Sgiacomo.gabrielli@arm.com case 0x5: 18713955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 18813955Sgiacomo.gabrielli@arm.com case 0x6: 18913955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 19013955Sgiacomo.gabrielli@arm.com case 0x7: 19113955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 19213955Sgiacomo.gabrielli@arm.com case 0xa: 19313955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 19413955Sgiacomo.gabrielli@arm.com case 0xb: 19513955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 19613955Sgiacomo.gabrielli@arm.com case 0xf: 19713955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, imm); 19813955Sgiacomo.gabrielli@arm.com } 19913955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 20013955Sgiacomo.gabrielli@arm.com } 20113955Sgiacomo.gabrielli@arm.com 20213955Sgiacomo.gabrielli@arm.com // NOTE: SVE load-and-replicate instructions are decoded with 20313955Sgiacomo.gabrielli@arm.com // decodeSveContigLoadSIInsts(...). 20413955Sgiacomo.gabrielli@arm.com 20513955Sgiacomo.gabrielli@arm.com}}; 20613955Sgiacomo.gabrielli@arm.com 20714028Sgiacomo.gabrielli@arm.comoutput decoder {{ 20814028Sgiacomo.gabrielli@arm.com 20914028Sgiacomo.gabrielli@arm.com StaticInstPtr 21014028Sgiacomo.gabrielli@arm.com decodeSveGatherLoadVIInsts(uint8_t dtype, ExtMachInst machInst, 21114028Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex zn, 21214028Sgiacomo.gabrielli@arm.com uint64_t imm, bool esizeIs32, 21314028Sgiacomo.gabrielli@arm.com bool firstFaulting) 21414028Sgiacomo.gabrielli@arm.com { 21514028Sgiacomo.gabrielli@arm.com const char* mn = firstFaulting ? "ldff1" : "ld1"; 21614028Sgiacomo.gabrielli@arm.com switch (dtype) { 21714028Sgiacomo.gabrielli@arm.com case 0x0: 21814028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 21914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<int32_t, int8_t, 22014028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 22114028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 22214028Sgiacomo.gabrielli@arm.com } else { 22314028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<int64_t, int8_t, 22414028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 22514028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 22614028Sgiacomo.gabrielli@arm.com } 22714028Sgiacomo.gabrielli@arm.com case 0x1: 22814028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 22914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint32_t, uint8_t, 23014028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 23114028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 23214028Sgiacomo.gabrielli@arm.com } else { 23314028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint8_t, 23414028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 23514028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 23614028Sgiacomo.gabrielli@arm.com } 23714028Sgiacomo.gabrielli@arm.com case 0x2: 23814028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 23914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<int32_t, int16_t, 24014028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 24114028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 24214028Sgiacomo.gabrielli@arm.com } else { 24314028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<int64_t, int16_t, 24414028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 24514028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 24614028Sgiacomo.gabrielli@arm.com } 24714028Sgiacomo.gabrielli@arm.com case 0x3: 24814028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 24914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint32_t, uint16_t, 25014028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 25114028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 25214028Sgiacomo.gabrielli@arm.com } else { 25314028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint16_t, 25414028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 25514028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 25614028Sgiacomo.gabrielli@arm.com } 25714028Sgiacomo.gabrielli@arm.com case 0x4: 25814028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 25914028Sgiacomo.gabrielli@arm.com break; 26014028Sgiacomo.gabrielli@arm.com } else { 26114028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<int64_t, int32_t, 26214028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 26314028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 26414028Sgiacomo.gabrielli@arm.com } 26514028Sgiacomo.gabrielli@arm.com case 0x5: 26614028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 26714028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint32_t, uint32_t, 26814028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 26914028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 27014028Sgiacomo.gabrielli@arm.com } else { 27114028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint32_t, 27214028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 27314028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 27414028Sgiacomo.gabrielli@arm.com } 27514028Sgiacomo.gabrielli@arm.com case 0x7: 27614028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 27714028Sgiacomo.gabrielli@arm.com break; 27814028Sgiacomo.gabrielli@arm.com } else { 27914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint64_t, 28014028Sgiacomo.gabrielli@arm.com SveGatherLoadVIMicroop>( 28114028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, zn, imm); 28214028Sgiacomo.gabrielli@arm.com } 28314028Sgiacomo.gabrielli@arm.com } 28414028Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 28514028Sgiacomo.gabrielli@arm.com } 28614028Sgiacomo.gabrielli@arm.com 28714028Sgiacomo.gabrielli@arm.com StaticInstPtr 28814028Sgiacomo.gabrielli@arm.com decodeSveGatherLoadSVInsts(uint8_t dtype, ExtMachInst machInst, 28914028Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 29014028Sgiacomo.gabrielli@arm.com IntRegIndex zm, bool esizeIs32, bool offsetIs32, 29114028Sgiacomo.gabrielli@arm.com bool offsetIsSigned, bool offsetIsScaled, 29214028Sgiacomo.gabrielli@arm.com bool firstFaulting) 29314028Sgiacomo.gabrielli@arm.com { 29414028Sgiacomo.gabrielli@arm.com const char* mn = firstFaulting ? "ldff1" : "ld1"; 29514028Sgiacomo.gabrielli@arm.com switch (dtype) { 29614028Sgiacomo.gabrielli@arm.com case 0x0: 29714028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 29814028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<int32_t, int8_t, 29914028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 30014028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 30114028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 30214028Sgiacomo.gabrielli@arm.com } else { 30314028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<int64_t, int8_t, 30414028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 30514028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 30614028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 30714028Sgiacomo.gabrielli@arm.com } 30814028Sgiacomo.gabrielli@arm.com case 0x1: 30914028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 31014028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint32_t, uint8_t, 31114028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 31214028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 31314028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 31414028Sgiacomo.gabrielli@arm.com } else { 31514028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint8_t, 31614028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 31714028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 31814028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 31914028Sgiacomo.gabrielli@arm.com } 32014028Sgiacomo.gabrielli@arm.com case 0x2: 32114028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 32214028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<int32_t, int16_t, 32314028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 32414028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 32514028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 32614028Sgiacomo.gabrielli@arm.com } else { 32714028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<int64_t, int16_t, 32814028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 32914028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 33014028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 33114028Sgiacomo.gabrielli@arm.com } 33214028Sgiacomo.gabrielli@arm.com case 0x3: 33314028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 33414028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint32_t, uint16_t, 33514028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 33614028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 33714028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 33814028Sgiacomo.gabrielli@arm.com } else { 33914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint16_t, 34014028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 34114028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 34214028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 34314028Sgiacomo.gabrielli@arm.com } 34414028Sgiacomo.gabrielli@arm.com case 0x4: 34514028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 34614028Sgiacomo.gabrielli@arm.com break; 34714028Sgiacomo.gabrielli@arm.com } else { 34814028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<int64_t, int32_t, 34914028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 35014028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 35114028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 35214028Sgiacomo.gabrielli@arm.com } 35314028Sgiacomo.gabrielli@arm.com case 0x5: 35414028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 35514028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint32_t, uint32_t, 35614028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 35714028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 35814028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 35914028Sgiacomo.gabrielli@arm.com } else { 36014028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint32_t, 36114028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 36214028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 36314028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 36414028Sgiacomo.gabrielli@arm.com } 36514028Sgiacomo.gabrielli@arm.com case 0x7: 36614028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 36714028Sgiacomo.gabrielli@arm.com break; 36814028Sgiacomo.gabrielli@arm.com } else { 36914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint64_t, 37014028Sgiacomo.gabrielli@arm.com SveGatherLoadSVMicroop>( 37114028Sgiacomo.gabrielli@arm.com mn, machInst, MemReadOp, zt, pg, rn, zm, 37214028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 37314028Sgiacomo.gabrielli@arm.com } 37414028Sgiacomo.gabrielli@arm.com } 37514028Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 37614028Sgiacomo.gabrielli@arm.com } 37714028Sgiacomo.gabrielli@arm.com 37814028Sgiacomo.gabrielli@arm.com StaticInstPtr 37914028Sgiacomo.gabrielli@arm.com decodeSveScatterStoreVIInsts(uint8_t msz, ExtMachInst machInst, 38014028Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, 38114028Sgiacomo.gabrielli@arm.com IntRegIndex zn, uint64_t imm, 38214028Sgiacomo.gabrielli@arm.com bool esizeIs32) 38314028Sgiacomo.gabrielli@arm.com { 38414028Sgiacomo.gabrielli@arm.com const char* mn = "st1"; 38514028Sgiacomo.gabrielli@arm.com switch (msz) { 38614028Sgiacomo.gabrielli@arm.com case 0x0: 38714028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 38814028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint32_t, uint8_t, 38914028Sgiacomo.gabrielli@arm.com SveScatterStoreVIMicroop>( 39014028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, zn, imm); 39114028Sgiacomo.gabrielli@arm.com } else { 39214028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint8_t, 39314028Sgiacomo.gabrielli@arm.com SveScatterStoreVIMicroop>( 39414028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, zn, imm); 39514028Sgiacomo.gabrielli@arm.com } 39614028Sgiacomo.gabrielli@arm.com case 0x1: 39714028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 39814028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint32_t, uint16_t, 39914028Sgiacomo.gabrielli@arm.com SveScatterStoreVIMicroop>( 40014028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, zn, imm); 40114028Sgiacomo.gabrielli@arm.com } else { 40214028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint16_t, 40314028Sgiacomo.gabrielli@arm.com SveScatterStoreVIMicroop>( 40414028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, zn, imm); 40514028Sgiacomo.gabrielli@arm.com } 40614028Sgiacomo.gabrielli@arm.com case 0x2: 40714028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 40814028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint32_t, uint32_t, 40914028Sgiacomo.gabrielli@arm.com SveScatterStoreVIMicroop>( 41014028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, zn, imm); 41114028Sgiacomo.gabrielli@arm.com } else { 41214028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint32_t, 41314028Sgiacomo.gabrielli@arm.com SveScatterStoreVIMicroop>( 41414028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, zn, imm); 41514028Sgiacomo.gabrielli@arm.com } 41614028Sgiacomo.gabrielli@arm.com case 0x3: 41714028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 41814028Sgiacomo.gabrielli@arm.com break; 41914028Sgiacomo.gabrielli@arm.com } else { 42014028Sgiacomo.gabrielli@arm.com return new SveIndexedMemVI<uint64_t, uint64_t, 42114028Sgiacomo.gabrielli@arm.com SveScatterStoreVIMicroop>( 42214028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, zn, imm); 42314028Sgiacomo.gabrielli@arm.com } 42414028Sgiacomo.gabrielli@arm.com } 42514028Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 42614028Sgiacomo.gabrielli@arm.com } 42714028Sgiacomo.gabrielli@arm.com 42814028Sgiacomo.gabrielli@arm.com StaticInstPtr 42914028Sgiacomo.gabrielli@arm.com decodeSveScatterStoreSVInsts(uint8_t msz, ExtMachInst machInst, 43014028Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, 43114028Sgiacomo.gabrielli@arm.com IntRegIndex rn, IntRegIndex zm, 43214028Sgiacomo.gabrielli@arm.com bool esizeIs32, bool offsetIs32, 43314028Sgiacomo.gabrielli@arm.com bool offsetIsSigned, bool offsetIsScaled) 43414028Sgiacomo.gabrielli@arm.com { 43514028Sgiacomo.gabrielli@arm.com const char* mn = "st1"; 43614028Sgiacomo.gabrielli@arm.com switch (msz) { 43714028Sgiacomo.gabrielli@arm.com case 0x0: 43814028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 43914028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint32_t, uint8_t, 44014028Sgiacomo.gabrielli@arm.com SveScatterStoreSVMicroop>( 44114028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, rn, zm, 44214028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 44314028Sgiacomo.gabrielli@arm.com } else { 44414028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint8_t, 44514028Sgiacomo.gabrielli@arm.com SveScatterStoreSVMicroop>( 44614028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, rn, zm, 44714028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 44814028Sgiacomo.gabrielli@arm.com } 44914028Sgiacomo.gabrielli@arm.com case 0x1: 45014028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 45114028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint32_t, uint16_t, 45214028Sgiacomo.gabrielli@arm.com SveScatterStoreSVMicroop>( 45314028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, rn, zm, 45414028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 45514028Sgiacomo.gabrielli@arm.com } else { 45614028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint16_t, 45714028Sgiacomo.gabrielli@arm.com SveScatterStoreSVMicroop>( 45814028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, rn, zm, 45914028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 46014028Sgiacomo.gabrielli@arm.com } 46114028Sgiacomo.gabrielli@arm.com case 0x2: 46214028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 46314028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint32_t, uint32_t, 46414028Sgiacomo.gabrielli@arm.com SveScatterStoreSVMicroop>( 46514028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, rn, zm, 46614028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 46714028Sgiacomo.gabrielli@arm.com } else { 46814028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint32_t, 46914028Sgiacomo.gabrielli@arm.com SveScatterStoreSVMicroop>( 47014028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, rn, zm, 47114028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 47214028Sgiacomo.gabrielli@arm.com } 47314028Sgiacomo.gabrielli@arm.com case 0x3: 47414028Sgiacomo.gabrielli@arm.com if (esizeIs32) { 47514028Sgiacomo.gabrielli@arm.com break; 47614028Sgiacomo.gabrielli@arm.com } else { 47714028Sgiacomo.gabrielli@arm.com return new SveIndexedMemSV<uint64_t, uint64_t, 47814028Sgiacomo.gabrielli@arm.com SveScatterStoreSVMicroop>( 47914028Sgiacomo.gabrielli@arm.com mn, machInst, MemWriteOp, zt, pg, rn, zm, 48014028Sgiacomo.gabrielli@arm.com offsetIs32, offsetIsSigned, offsetIsScaled); 48114028Sgiacomo.gabrielli@arm.com } 48214028Sgiacomo.gabrielli@arm.com } 48314028Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 48414028Sgiacomo.gabrielli@arm.com } 48514028Sgiacomo.gabrielli@arm.com 48614028Sgiacomo.gabrielli@arm.com}}; 48714028Sgiacomo.gabrielli@arm.com 48814028Sgiacomo.gabrielli@arm.com 48913955Sgiacomo.gabrielli@arm.comlet {{ 49013955Sgiacomo.gabrielli@arm.com 49113955Sgiacomo.gabrielli@arm.com header_output = '' 49213955Sgiacomo.gabrielli@arm.com exec_output = '' 49313955Sgiacomo.gabrielli@arm.com decoders = { 'Generic': {} } 49413955Sgiacomo.gabrielli@arm.com 49513955Sgiacomo.gabrielli@arm.com SPAlignmentCheckCode = ''' 49613955Sgiacomo.gabrielli@arm.com if (this->baseIsSP && bits(XBase, 3, 0) && 49713955Sgiacomo.gabrielli@arm.com SPAlignmentCheckEnabled(xc->tcBase())) { 49813955Sgiacomo.gabrielli@arm.com return std::make_shared<SPAlignmentFault>(); 49913955Sgiacomo.gabrielli@arm.com } 50013955Sgiacomo.gabrielli@arm.com ''' 50113955Sgiacomo.gabrielli@arm.com 50213955Sgiacomo.gabrielli@arm.com def emitSveMemFillSpill(isPred): 50313955Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 50413955Sgiacomo.gabrielli@arm.com eaCode = SPAlignmentCheckCode + ''' 50513955Sgiacomo.gabrielli@arm.com int memAccessSize = %(memacc_size)s; 50613955Sgiacomo.gabrielli@arm.com EA = XBase + ((int64_t) imm * %(memacc_size)s)''' % { 50713955Sgiacomo.gabrielli@arm.com 'memacc_size': 'eCount / 8' if isPred else 'eCount'} 50813955Sgiacomo.gabrielli@arm.com if isPred: 50913955Sgiacomo.gabrielli@arm.com loadMemAccCode = ''' 51013955Sgiacomo.gabrielli@arm.com int index = 0; 51113955Sgiacomo.gabrielli@arm.com uint8_t byte; 51213955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount / 8; i++) { 51313955Sgiacomo.gabrielli@arm.com byte = memDataView[i]; 51413955Sgiacomo.gabrielli@arm.com for (int j = 0; j < 8; j++, index++) { 51513955Sgiacomo.gabrielli@arm.com PDest_x[index] = (byte >> j) & 1; 51613955Sgiacomo.gabrielli@arm.com } 51713955Sgiacomo.gabrielli@arm.com } 51813955Sgiacomo.gabrielli@arm.com ''' 51913955Sgiacomo.gabrielli@arm.com storeMemAccCode = ''' 52013955Sgiacomo.gabrielli@arm.com int index = 0; 52113955Sgiacomo.gabrielli@arm.com uint8_t byte; 52213955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount / 8; i++) { 52313955Sgiacomo.gabrielli@arm.com byte = 0; 52413955Sgiacomo.gabrielli@arm.com for (int j = 0; j < 8; j++, index++) { 52513955Sgiacomo.gabrielli@arm.com byte |= PDest_x[index] << j; 52613955Sgiacomo.gabrielli@arm.com } 52713955Sgiacomo.gabrielli@arm.com memDataView[i] = byte; 52813955Sgiacomo.gabrielli@arm.com } 52913955Sgiacomo.gabrielli@arm.com ''' 53013955Sgiacomo.gabrielli@arm.com storeWrEnableCode = ''' 53113955Sgiacomo.gabrielli@arm.com auto wrEn = std::vector<bool>(eCount / 8, true); 53213955Sgiacomo.gabrielli@arm.com ''' 53313955Sgiacomo.gabrielli@arm.com else: 53413955Sgiacomo.gabrielli@arm.com loadMemAccCode = ''' 53513955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 53613955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = memDataView[i]; 53713955Sgiacomo.gabrielli@arm.com } 53813955Sgiacomo.gabrielli@arm.com ''' 53913955Sgiacomo.gabrielli@arm.com storeMemAccCode = ''' 54013955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 54113955Sgiacomo.gabrielli@arm.com memDataView[i] = AA64FpDest_x[i]; 54213955Sgiacomo.gabrielli@arm.com } 54313955Sgiacomo.gabrielli@arm.com ''' 54413955Sgiacomo.gabrielli@arm.com storeWrEnableCode = ''' 54513955Sgiacomo.gabrielli@arm.com auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true); 54613955Sgiacomo.gabrielli@arm.com ''' 54713955Sgiacomo.gabrielli@arm.com loadIop = InstObjParams('ldr', 54813955Sgiacomo.gabrielli@arm.com 'SveLdrPred' if isPred else 'SveLdrVec', 54913955Sgiacomo.gabrielli@arm.com 'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill', 55013955Sgiacomo.gabrielli@arm.com {'tpl_header': '', 55113955Sgiacomo.gabrielli@arm.com 'tpl_args': '', 55213955Sgiacomo.gabrielli@arm.com 'memacc_code': loadMemAccCode, 55313955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 55413955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 55513955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsLoad']) 55613955Sgiacomo.gabrielli@arm.com storeIop = InstObjParams('str', 55713955Sgiacomo.gabrielli@arm.com 'SveStrPred' if isPred else 'SveStrVec', 55813955Sgiacomo.gabrielli@arm.com 'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill', 55913955Sgiacomo.gabrielli@arm.com {'tpl_header': '', 56013955Sgiacomo.gabrielli@arm.com 'tpl_args': '', 56113955Sgiacomo.gabrielli@arm.com 'wren_code': storeWrEnableCode, 56213955Sgiacomo.gabrielli@arm.com 'memacc_code': storeMemAccCode, 56313955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 56413955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 56513955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsStore']) 56613955Sgiacomo.gabrielli@arm.com header_output += SveMemFillSpillOpDeclare.subst(loadIop) 56713955Sgiacomo.gabrielli@arm.com header_output += SveMemFillSpillOpDeclare.subst(storeIop) 56813955Sgiacomo.gabrielli@arm.com exec_output += ( 56913955Sgiacomo.gabrielli@arm.com SveContigLoadExecute.subst(loadIop) + 57013955Sgiacomo.gabrielli@arm.com SveContigLoadInitiateAcc.subst(loadIop) + 57113955Sgiacomo.gabrielli@arm.com SveContigLoadCompleteAcc.subst(loadIop) + 57213955Sgiacomo.gabrielli@arm.com SveContigStoreExecute.subst(storeIop) + 57313955Sgiacomo.gabrielli@arm.com SveContigStoreInitiateAcc.subst(storeIop) + 57413955Sgiacomo.gabrielli@arm.com SveContigStoreCompleteAcc.subst(storeIop)) 57513955Sgiacomo.gabrielli@arm.com 57613955Sgiacomo.gabrielli@arm.com loadTplArgs = ( 57713955Sgiacomo.gabrielli@arm.com ('uint8_t', 'uint8_t'), 57813955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint8_t'), 57913955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint8_t'), 58013955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint8_t'), 58113955Sgiacomo.gabrielli@arm.com ('int64_t', 'int32_t'), 58213955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint16_t'), 58313955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint16_t'), 58413955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint16_t'), 58513955Sgiacomo.gabrielli@arm.com ('int64_t', 'int16_t'), 58613955Sgiacomo.gabrielli@arm.com ('int32_t', 'int16_t'), 58713955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint32_t'), 58813955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint32_t'), 58913955Sgiacomo.gabrielli@arm.com ('int64_t', 'int8_t'), 59013955Sgiacomo.gabrielli@arm.com ('int32_t', 'int8_t'), 59113955Sgiacomo.gabrielli@arm.com ('int16_t', 'int8_t'), 59213955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint64_t'), 59313955Sgiacomo.gabrielli@arm.com ) 59413955Sgiacomo.gabrielli@arm.com 59513955Sgiacomo.gabrielli@arm.com storeTplArgs = ( 59613955Sgiacomo.gabrielli@arm.com ('uint8_t', 'uint8_t'), 59713955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint8_t'), 59813955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint8_t'), 59913955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint8_t'), 60013955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint16_t'), 60113955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint16_t'), 60213955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint16_t'), 60313955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint32_t'), 60413955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint32_t'), 60513955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint64_t'), 60613955Sgiacomo.gabrielli@arm.com ) 60713955Sgiacomo.gabrielli@arm.com 60814028Sgiacomo.gabrielli@arm.com gatherLoadTplArgs = ( 60914028Sgiacomo.gabrielli@arm.com ('int32_t', 'int8_t'), 61014028Sgiacomo.gabrielli@arm.com ('int64_t', 'int8_t'), 61114028Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint8_t'), 61214028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint8_t'), 61314028Sgiacomo.gabrielli@arm.com ('int32_t', 'int16_t'), 61414028Sgiacomo.gabrielli@arm.com ('int64_t', 'int16_t'), 61514028Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint16_t'), 61614028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint16_t'), 61714028Sgiacomo.gabrielli@arm.com ('int64_t', 'int32_t'), 61814028Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint32_t'), 61914028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint32_t'), 62014028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint64_t'), 62114028Sgiacomo.gabrielli@arm.com ) 62214028Sgiacomo.gabrielli@arm.com 62314028Sgiacomo.gabrielli@arm.com scatterStoreTplArgs = ( 62414028Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint8_t'), 62514028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint8_t'), 62614028Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint16_t'), 62714028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint16_t'), 62814028Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint32_t'), 62914028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint32_t'), 63014028Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint64_t'), 63114028Sgiacomo.gabrielli@arm.com ) 63214028Sgiacomo.gabrielli@arm.com 63313955Sgiacomo.gabrielli@arm.com # Generates definitions for SVE contiguous loads 63413955Sgiacomo.gabrielli@arm.com def emitSveContigMemInsts(offsetIsImm): 63513955Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 63613955Sgiacomo.gabrielli@arm.com tplHeader = 'template <class RegElemType, class MemElemType>' 63713955Sgiacomo.gabrielli@arm.com tplArgs = '<RegElemType, MemElemType>' 63813955Sgiacomo.gabrielli@arm.com eaCode = SPAlignmentCheckCode + ''' 63913955Sgiacomo.gabrielli@arm.com int memAccessSize = eCount * sizeof(MemElemType); 64013955Sgiacomo.gabrielli@arm.com EA = XBase + ''' 64113955Sgiacomo.gabrielli@arm.com if offsetIsImm: 64213955Sgiacomo.gabrielli@arm.com eaCode += '((int64_t) this->imm * eCount * sizeof(MemElemType))' 64313955Sgiacomo.gabrielli@arm.com else: 64413955Sgiacomo.gabrielli@arm.com eaCode += '(XOffset * sizeof(MemElemType));' 64513955Sgiacomo.gabrielli@arm.com loadMemAccCode = ''' 64613955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 64713955Sgiacomo.gabrielli@arm.com if (GpOp_x[i]) { 64813955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = memDataView[i]; 64913955Sgiacomo.gabrielli@arm.com } else { 65013955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = 0; 65113955Sgiacomo.gabrielli@arm.com } 65213955Sgiacomo.gabrielli@arm.com } 65313955Sgiacomo.gabrielli@arm.com ''' 65413955Sgiacomo.gabrielli@arm.com storeMemAccCode = ''' 65513955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 65613955Sgiacomo.gabrielli@arm.com if (GpOp_x[i]) { 65713955Sgiacomo.gabrielli@arm.com memDataView[i] = AA64FpDest_x[i]; 65813955Sgiacomo.gabrielli@arm.com } else { 65913955Sgiacomo.gabrielli@arm.com memDataView[i] = 0; 66013955Sgiacomo.gabrielli@arm.com for (int j = 0; j < sizeof(MemElemType); j++) { 66113955Sgiacomo.gabrielli@arm.com wrEn[sizeof(MemElemType) * i + j] = false; 66213955Sgiacomo.gabrielli@arm.com } 66313955Sgiacomo.gabrielli@arm.com } 66413955Sgiacomo.gabrielli@arm.com } 66513955Sgiacomo.gabrielli@arm.com ''' 66613955Sgiacomo.gabrielli@arm.com storeWrEnableCode = ''' 66713955Sgiacomo.gabrielli@arm.com auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true); 66813955Sgiacomo.gabrielli@arm.com ''' 66913955Sgiacomo.gabrielli@arm.com loadIop = InstObjParams('ld1', 67013955Sgiacomo.gabrielli@arm.com 'SveContigLoadSI' if offsetIsImm else 'SveContigLoadSS', 67113955Sgiacomo.gabrielli@arm.com 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', 67213955Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 67313955Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 67413955Sgiacomo.gabrielli@arm.com 'memacc_code': loadMemAccCode, 67513955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 67613955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 67713955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsLoad']) 67813955Sgiacomo.gabrielli@arm.com storeIop = InstObjParams('st1', 67913955Sgiacomo.gabrielli@arm.com 'SveContigStoreSI' if offsetIsImm else 'SveContigStoreSS', 68013955Sgiacomo.gabrielli@arm.com 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', 68113955Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 68213955Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 68313955Sgiacomo.gabrielli@arm.com 'wren_code': storeWrEnableCode, 68413955Sgiacomo.gabrielli@arm.com 'memacc_code': storeMemAccCode, 68513955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 68613955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 68713955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsStore']) 68813955Sgiacomo.gabrielli@arm.com if offsetIsImm: 68913955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSIOpDeclare.subst(loadIop) 69013955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSIOpDeclare.subst(storeIop) 69113955Sgiacomo.gabrielli@arm.com else: 69213955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSSOpDeclare.subst(loadIop) 69313955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSSOpDeclare.subst(storeIop) 69413955Sgiacomo.gabrielli@arm.com exec_output += ( 69513955Sgiacomo.gabrielli@arm.com SveContigLoadExecute.subst(loadIop) + 69613955Sgiacomo.gabrielli@arm.com SveContigLoadInitiateAcc.subst(loadIop) + 69713955Sgiacomo.gabrielli@arm.com SveContigLoadCompleteAcc.subst(loadIop) + 69813955Sgiacomo.gabrielli@arm.com SveContigStoreExecute.subst(storeIop) + 69913955Sgiacomo.gabrielli@arm.com SveContigStoreInitiateAcc.subst(storeIop) + 70013955Sgiacomo.gabrielli@arm.com SveContigStoreCompleteAcc.subst(storeIop)) 70113955Sgiacomo.gabrielli@arm.com for args in loadTplArgs: 70213955Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 70313955Sgiacomo.gabrielli@arm.com 'class_name': 'SveContigLoadSI' if offsetIsImm 70413955Sgiacomo.gabrielli@arm.com else 'SveContigLoadSS'} 70513955Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 70613955Sgiacomo.gabrielli@arm.com for args in storeTplArgs: 70713955Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 70813955Sgiacomo.gabrielli@arm.com 'class_name': 'SveContigStoreSI' if offsetIsImm 70913955Sgiacomo.gabrielli@arm.com else 'SveContigStoreSS'} 71013955Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 71113955Sgiacomo.gabrielli@arm.com 71213955Sgiacomo.gabrielli@arm.com # Generates definitions for SVE load-and-replicate instructions 71313955Sgiacomo.gabrielli@arm.com def emitSveLoadAndRepl(): 71413955Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 71513955Sgiacomo.gabrielli@arm.com tplHeader = 'template <class RegElemType, class MemElemType>' 71613955Sgiacomo.gabrielli@arm.com tplArgs = '<RegElemType, MemElemType>' 71713955Sgiacomo.gabrielli@arm.com eaCode = SPAlignmentCheckCode + ''' 71813955Sgiacomo.gabrielli@arm.com EA = XBase + imm * sizeof(MemElemType);''' 71913955Sgiacomo.gabrielli@arm.com memAccCode = ''' 72013955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 72113955Sgiacomo.gabrielli@arm.com if (GpOp_x[i]) { 72213955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = memData; 72313955Sgiacomo.gabrielli@arm.com } else { 72413955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = 0; 72513955Sgiacomo.gabrielli@arm.com } 72613955Sgiacomo.gabrielli@arm.com } 72713955Sgiacomo.gabrielli@arm.com ''' 72813955Sgiacomo.gabrielli@arm.com iop = InstObjParams('ld1r', 72913955Sgiacomo.gabrielli@arm.com 'SveLoadAndRepl', 73013955Sgiacomo.gabrielli@arm.com 'SveContigMemSI', 73113955Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 73213955Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 73313955Sgiacomo.gabrielli@arm.com 'memacc_code': memAccCode, 73413955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 73513955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 73613955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsLoad']) 73713955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSIOpDeclare.subst(iop) 73813955Sgiacomo.gabrielli@arm.com exec_output += ( 73913955Sgiacomo.gabrielli@arm.com SveLoadAndReplExecute.subst(iop) + 74013955Sgiacomo.gabrielli@arm.com SveLoadAndReplInitiateAcc.subst(iop) + 74113955Sgiacomo.gabrielli@arm.com SveLoadAndReplCompleteAcc.subst(iop)) 74213955Sgiacomo.gabrielli@arm.com for args in loadTplArgs: 74313955Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 74413955Sgiacomo.gabrielli@arm.com 'class_name': 'SveLoadAndRepl'} 74513955Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 74613955Sgiacomo.gabrielli@arm.com 74714028Sgiacomo.gabrielli@arm.com class IndexedAddrForm: 74814028Sgiacomo.gabrielli@arm.com VEC_PLUS_IMM = 0 74914028Sgiacomo.gabrielli@arm.com SCA_PLUS_VEC = 1 75014028Sgiacomo.gabrielli@arm.com 75114028Sgiacomo.gabrielli@arm.com # Generates definitions for the transfer microops of SVE indexed memory 75214028Sgiacomo.gabrielli@arm.com # operations (gather loads, scatter stores) 75314028Sgiacomo.gabrielli@arm.com def emitSveIndexedMemMicroops(indexed_addr_form): 75414028Sgiacomo.gabrielli@arm.com assert indexed_addr_form in (IndexedAddrForm.VEC_PLUS_IMM, 75514028Sgiacomo.gabrielli@arm.com IndexedAddrForm.SCA_PLUS_VEC) 75614028Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 75714028Sgiacomo.gabrielli@arm.com tplHeader = 'template <class RegElemType, class MemElemType>' 75814028Sgiacomo.gabrielli@arm.com tplArgs = '<RegElemType, MemElemType>' 75914028Sgiacomo.gabrielli@arm.com if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM: 76014028Sgiacomo.gabrielli@arm.com eaCode = ''' 76114028Sgiacomo.gabrielli@arm.com EA = AA64FpBase_x[elemIndex] + imm * sizeof(MemElemType)''' 76214028Sgiacomo.gabrielli@arm.com else: 76314028Sgiacomo.gabrielli@arm.com eaCode = ''' 76414028Sgiacomo.gabrielli@arm.com uint64_t offset = AA64FpOffset_x[elemIndex]; 76514028Sgiacomo.gabrielli@arm.com if (offsetIs32) { 76614028Sgiacomo.gabrielli@arm.com offset &= (1ULL << 32) - 1; 76714028Sgiacomo.gabrielli@arm.com } 76814028Sgiacomo.gabrielli@arm.com if (offsetIsSigned) { 76914028Sgiacomo.gabrielli@arm.com offset = sext<32>(offset); 77014028Sgiacomo.gabrielli@arm.com } 77114028Sgiacomo.gabrielli@arm.com if (offsetIsScaled) { 77214028Sgiacomo.gabrielli@arm.com offset *= sizeof(MemElemType); 77314028Sgiacomo.gabrielli@arm.com } 77414028Sgiacomo.gabrielli@arm.com EA = XBase + offset''' 77514028Sgiacomo.gabrielli@arm.com loadMemAccCode = ''' 77614028Sgiacomo.gabrielli@arm.com if (GpOp_x[elemIndex]) { 77714028Sgiacomo.gabrielli@arm.com AA64FpDest_x[elemIndex] = memData; 77814028Sgiacomo.gabrielli@arm.com } else { 77914028Sgiacomo.gabrielli@arm.com AA64FpDest_x[elemIndex] = 0; 78014028Sgiacomo.gabrielli@arm.com } 78114028Sgiacomo.gabrielli@arm.com ''' 78214028Sgiacomo.gabrielli@arm.com storeMemAccCode = ''' 78314028Sgiacomo.gabrielli@arm.com memData = AA64FpDest_x[elemIndex]; 78414028Sgiacomo.gabrielli@arm.com ''' 78514028Sgiacomo.gabrielli@arm.com predCheckCode = 'GpOp_x[elemIndex]' 78614028Sgiacomo.gabrielli@arm.com loadIop = InstObjParams('ld1', 78714028Sgiacomo.gabrielli@arm.com ('SveGatherLoadVIMicroop' 78814028Sgiacomo.gabrielli@arm.com if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM 78914028Sgiacomo.gabrielli@arm.com else 'SveGatherLoadSVMicroop'), 79014028Sgiacomo.gabrielli@arm.com 'MicroOp', 79114028Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 79214028Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 79314028Sgiacomo.gabrielli@arm.com 'memacc_code': loadMemAccCode, 79414028Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 79514028Sgiacomo.gabrielli@arm.com 'pred_check_code' : predCheckCode, 79614028Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 79714028Sgiacomo.gabrielli@arm.com ['IsMicroop', 'IsMemRef', 'IsLoad']) 79814028Sgiacomo.gabrielli@arm.com storeIop = InstObjParams('st1', 79914028Sgiacomo.gabrielli@arm.com ('SveScatterStoreVIMicroop' 80014028Sgiacomo.gabrielli@arm.com if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM 80114028Sgiacomo.gabrielli@arm.com else 'SveScatterStoreSVMicroop'), 80214028Sgiacomo.gabrielli@arm.com 'MicroOp', 80314028Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 80414028Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 80514028Sgiacomo.gabrielli@arm.com 'memacc_code': storeMemAccCode, 80614028Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 80714028Sgiacomo.gabrielli@arm.com 'pred_check_code' : predCheckCode, 80814028Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 80914028Sgiacomo.gabrielli@arm.com ['IsMicroop', 'IsMemRef', 'IsStore']) 81014028Sgiacomo.gabrielli@arm.com if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM: 81114028Sgiacomo.gabrielli@arm.com header_output += SveIndexedMemVIMicroopDeclare.subst(loadIop) 81214028Sgiacomo.gabrielli@arm.com header_output += SveIndexedMemVIMicroopDeclare.subst(storeIop) 81314028Sgiacomo.gabrielli@arm.com else: 81414028Sgiacomo.gabrielli@arm.com header_output += SveIndexedMemSVMicroopDeclare.subst(loadIop) 81514028Sgiacomo.gabrielli@arm.com header_output += SveIndexedMemSVMicroopDeclare.subst(storeIop) 81614028Sgiacomo.gabrielli@arm.com exec_output += ( 81714028Sgiacomo.gabrielli@arm.com SveGatherLoadMicroopExecute.subst(loadIop) + 81814028Sgiacomo.gabrielli@arm.com SveGatherLoadMicroopInitiateAcc.subst(loadIop) + 81914028Sgiacomo.gabrielli@arm.com SveGatherLoadMicroopCompleteAcc.subst(loadIop) + 82014028Sgiacomo.gabrielli@arm.com SveScatterStoreMicroopExecute.subst(storeIop) + 82114028Sgiacomo.gabrielli@arm.com SveScatterStoreMicroopInitiateAcc.subst(storeIop) + 82214028Sgiacomo.gabrielli@arm.com SveScatterStoreMicroopCompleteAcc.subst(storeIop)) 82314028Sgiacomo.gabrielli@arm.com for args in gatherLoadTplArgs: 82414028Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 82514028Sgiacomo.gabrielli@arm.com 'class_name': ( 82614028Sgiacomo.gabrielli@arm.com 'SveGatherLoadVIMicroop' 82714028Sgiacomo.gabrielli@arm.com if indexed_addr_form == \ 82814028Sgiacomo.gabrielli@arm.com IndexedAddrForm.VEC_PLUS_IMM 82914028Sgiacomo.gabrielli@arm.com else 'SveGatherLoadSVMicroop')} 83014028Sgiacomo.gabrielli@arm.com # TODO: this should become SveMemExecDeclare 83114028Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 83214028Sgiacomo.gabrielli@arm.com for args in scatterStoreTplArgs: 83314028Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 83414028Sgiacomo.gabrielli@arm.com 'class_name': ( 83514028Sgiacomo.gabrielli@arm.com 'SveScatterStoreVIMicroop' 83614028Sgiacomo.gabrielli@arm.com if indexed_addr_form == \ 83714028Sgiacomo.gabrielli@arm.com IndexedAddrForm.VEC_PLUS_IMM 83814028Sgiacomo.gabrielli@arm.com else 'SveScatterStoreSVMicroop')} 83914028Sgiacomo.gabrielli@arm.com # TODO: this should become SveMemExecDeclare 84014028Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 84114028Sgiacomo.gabrielli@arm.com 84214028Sgiacomo.gabrielli@arm.com # Generates definitions for the first microop of SVE gather loads, required 84314028Sgiacomo.gabrielli@arm.com # to propagate the source vector register to the transfer microops 84414028Sgiacomo.gabrielli@arm.com def emitSveGatherLoadCpySrcVecMicroop(): 84514028Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 84614028Sgiacomo.gabrielli@arm.com code = sveEnabledCheckCode + ''' 84714028Sgiacomo.gabrielli@arm.com unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>( 84814028Sgiacomo.gabrielli@arm.com xc->tcBase()); 84914028Sgiacomo.gabrielli@arm.com for (unsigned i = 0; i < eCount; i++) { 85014028Sgiacomo.gabrielli@arm.com AA64FpUreg0_ub[i] = AA64FpOp1_ub[i]; 85114028Sgiacomo.gabrielli@arm.com }''' 85214028Sgiacomo.gabrielli@arm.com iop = InstObjParams('ld1', 85314028Sgiacomo.gabrielli@arm.com 'SveGatherLoadCpySrcVecMicroop', 85414028Sgiacomo.gabrielli@arm.com 'MicroOp', 85514028Sgiacomo.gabrielli@arm.com {'code': code}, 85614028Sgiacomo.gabrielli@arm.com ['IsMicroop']) 85714028Sgiacomo.gabrielli@arm.com header_output += SveGatherLoadCpySrcVecMicroopDeclare.subst(iop) 85814028Sgiacomo.gabrielli@arm.com exec_output += SveGatherLoadCpySrcVecMicroopExecute.subst(iop) 85914028Sgiacomo.gabrielli@arm.com 86013955Sgiacomo.gabrielli@arm.com # LD1[S]{B,H,W,D} (scalar plus immediate) 86114028Sgiacomo.gabrielli@arm.com # ST1[S]{B,H,W,D} (scalar plus immediate) 86213955Sgiacomo.gabrielli@arm.com emitSveContigMemInsts(True) 86313955Sgiacomo.gabrielli@arm.com # LD1[S]{B,H,W,D} (scalar plus scalar) 86414028Sgiacomo.gabrielli@arm.com # ST1[S]{B,H,W,D} (scalar plus scalar) 86513955Sgiacomo.gabrielli@arm.com emitSveContigMemInsts(False) 86613955Sgiacomo.gabrielli@arm.com 86713955Sgiacomo.gabrielli@arm.com # LD1R[S]{B,H,W,D} 86813955Sgiacomo.gabrielli@arm.com emitSveLoadAndRepl() 86913955Sgiacomo.gabrielli@arm.com 87013955Sgiacomo.gabrielli@arm.com # LDR (predicate), STR (predicate) 87113955Sgiacomo.gabrielli@arm.com emitSveMemFillSpill(True) 87213955Sgiacomo.gabrielli@arm.com # LDR (vector), STR (vector) 87313955Sgiacomo.gabrielli@arm.com emitSveMemFillSpill(False) 87413955Sgiacomo.gabrielli@arm.com 87514028Sgiacomo.gabrielli@arm.com # LD1[S]{B,H,W,D} (vector plus immediate) 87614028Sgiacomo.gabrielli@arm.com # ST1[S]{B,H,W,D} (vector plus immediate) 87714028Sgiacomo.gabrielli@arm.com emitSveIndexedMemMicroops(IndexedAddrForm.VEC_PLUS_IMM) 87814028Sgiacomo.gabrielli@arm.com # LD1[S]{B,H,W,D} (scalar plus vector) 87914028Sgiacomo.gabrielli@arm.com # ST1[S]{B,H,W,D} (scalar plus vector) 88014028Sgiacomo.gabrielli@arm.com emitSveIndexedMemMicroops(IndexedAddrForm.SCA_PLUS_VEC) 88114028Sgiacomo.gabrielli@arm.com 88214028Sgiacomo.gabrielli@arm.com # Source vector copy microop for gather loads 88314028Sgiacomo.gabrielli@arm.com emitSveGatherLoadCpySrcVecMicroop() 88414028Sgiacomo.gabrielli@arm.com 88513955Sgiacomo.gabrielli@arm.com}}; 886