sve_mem.isa revision 13955
113955Sgiacomo.gabrielli@arm.com// Copyright (c) 2017 ARM Limited 213955Sgiacomo.gabrielli@arm.com// All rights reserved 313955Sgiacomo.gabrielli@arm.com// 413955Sgiacomo.gabrielli@arm.com// The license below extends only to copyright in the software and shall 513955Sgiacomo.gabrielli@arm.com// not be construed as granting a license to any other intellectual 613955Sgiacomo.gabrielli@arm.com// property including but not limited to intellectual property relating 713955Sgiacomo.gabrielli@arm.com// to a hardware implementation of the functionality of the software 813955Sgiacomo.gabrielli@arm.com// licensed hereunder. You may use the software subject to the license 913955Sgiacomo.gabrielli@arm.com// terms below provided that you ensure that this notice is replicated 1013955Sgiacomo.gabrielli@arm.com// unmodified and in its entirety in all distributions of the software, 1113955Sgiacomo.gabrielli@arm.com// modified or unmodified, in source code or in binary form. 1213955Sgiacomo.gabrielli@arm.com// 1313955Sgiacomo.gabrielli@arm.com// Redistribution and use in source and binary forms, with or without 1413955Sgiacomo.gabrielli@arm.com// modification, are permitted provided that the following conditions are 1513955Sgiacomo.gabrielli@arm.com// met: redistributions of source code must retain the above copyright 1613955Sgiacomo.gabrielli@arm.com// notice, this list of conditions and the following disclaimer; 1713955Sgiacomo.gabrielli@arm.com// redistributions in binary form must reproduce the above copyright 1813955Sgiacomo.gabrielli@arm.com// notice, this list of conditions and the following disclaimer in the 1913955Sgiacomo.gabrielli@arm.com// documentation and/or other materials provided with the distribution; 2013955Sgiacomo.gabrielli@arm.com// neither the name of the copyright holders nor the names of its 2113955Sgiacomo.gabrielli@arm.com// contributors may be used to endorse or promote products derived from 2213955Sgiacomo.gabrielli@arm.com// this software without specific prior written permission. 2313955Sgiacomo.gabrielli@arm.com// 2413955Sgiacomo.gabrielli@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2513955Sgiacomo.gabrielli@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2613955Sgiacomo.gabrielli@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2713955Sgiacomo.gabrielli@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2813955Sgiacomo.gabrielli@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2913955Sgiacomo.gabrielli@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3013955Sgiacomo.gabrielli@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3113955Sgiacomo.gabrielli@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3213955Sgiacomo.gabrielli@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3313955Sgiacomo.gabrielli@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3413955Sgiacomo.gabrielli@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3513955Sgiacomo.gabrielli@arm.com// 3613955Sgiacomo.gabrielli@arm.com// Authors: Giacomo Gabrielli 3713955Sgiacomo.gabrielli@arm.com 3813955Sgiacomo.gabrielli@arm.com// @file Definition of SVE memory access instructions. 3913955Sgiacomo.gabrielli@arm.com 4013955Sgiacomo.gabrielli@arm.comoutput header {{ 4113955Sgiacomo.gabrielli@arm.com 4213955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous load instructions, scalar plus scalar form. 4313955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 4413955Sgiacomo.gabrielli@arm.com StaticInstPtr 4513955Sgiacomo.gabrielli@arm.com decodeSveContigLoadSSInsts(uint8_t dtype, ExtMachInst machInst, 4613955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 4713955Sgiacomo.gabrielli@arm.com IntRegIndex rm, bool firstFaulting) 4813955Sgiacomo.gabrielli@arm.com { 4913955Sgiacomo.gabrielli@arm.com const char* mn = firstFaulting ? "ldff1" : "ld1"; 5013955Sgiacomo.gabrielli@arm.com switch (dtype) { 5113955Sgiacomo.gabrielli@arm.com case 0x0: 5213955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5313955Sgiacomo.gabrielli@arm.com case 0x1: 5413955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5513955Sgiacomo.gabrielli@arm.com case 0x2: 5613955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5713955Sgiacomo.gabrielli@arm.com case 0x3: 5813955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 5913955Sgiacomo.gabrielli@arm.com case 0x4: 6013955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int32_t>(mn, machInst, zt, pg, rn, rm); 6113955Sgiacomo.gabrielli@arm.com case 0x5: 6213955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 6313955Sgiacomo.gabrielli@arm.com case 0x6: 6413955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 6513955Sgiacomo.gabrielli@arm.com case 0x7: 6613955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 6713955Sgiacomo.gabrielli@arm.com case 0x8: 6813955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int16_t>(mn, machInst, zt, pg, rn, rm); 6913955Sgiacomo.gabrielli@arm.com case 0x9: 7013955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int16_t>(mn, machInst, zt, pg, rn, rm); 7113955Sgiacomo.gabrielli@arm.com case 0xa: 7213955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 7313955Sgiacomo.gabrielli@arm.com case 0xb: 7413955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 7513955Sgiacomo.gabrielli@arm.com case 0xc: 7613955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int8_t>(mn, machInst, zt, pg, rn, rm); 7713955Sgiacomo.gabrielli@arm.com case 0xd: 7813955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int8_t>(mn, machInst, zt, pg, rn, rm); 7913955Sgiacomo.gabrielli@arm.com case 0xe: 8013955Sgiacomo.gabrielli@arm.com return new Base<int16_t, int8_t>(mn, machInst, zt, pg, rn, rm); 8113955Sgiacomo.gabrielli@arm.com case 0xf: 8213955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, rm); 8313955Sgiacomo.gabrielli@arm.com } 8413955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 8513955Sgiacomo.gabrielli@arm.com } 8613955Sgiacomo.gabrielli@arm.com 8713955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous load instructions, scalar plus immediate form. 8813955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 8913955Sgiacomo.gabrielli@arm.com StaticInstPtr 9013955Sgiacomo.gabrielli@arm.com decodeSveContigLoadSIInsts(uint8_t dtype, ExtMachInst machInst, 9113955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 9213955Sgiacomo.gabrielli@arm.com uint64_t imm, bool firstFaulting, 9313955Sgiacomo.gabrielli@arm.com bool replicate = false) 9413955Sgiacomo.gabrielli@arm.com { 9513955Sgiacomo.gabrielli@arm.com assert(!(replicate && firstFaulting)); 9613955Sgiacomo.gabrielli@arm.com 9713955Sgiacomo.gabrielli@arm.com const char* mn = replicate ? "ld1r" : 9813955Sgiacomo.gabrielli@arm.com (firstFaulting ? "ldff1" : "ld1"); 9913955Sgiacomo.gabrielli@arm.com switch (dtype) { 10013955Sgiacomo.gabrielli@arm.com case 0x0: 10113955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10213955Sgiacomo.gabrielli@arm.com case 0x1: 10313955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10413955Sgiacomo.gabrielli@arm.com case 0x2: 10513955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10613955Sgiacomo.gabrielli@arm.com case 0x3: 10713955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 10813955Sgiacomo.gabrielli@arm.com case 0x4: 10913955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int32_t>(mn, machInst, zt, pg, rn, imm); 11013955Sgiacomo.gabrielli@arm.com case 0x5: 11113955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 11213955Sgiacomo.gabrielli@arm.com case 0x6: 11313955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 11413955Sgiacomo.gabrielli@arm.com case 0x7: 11513955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 11613955Sgiacomo.gabrielli@arm.com case 0x8: 11713955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int16_t>(mn, machInst, zt, pg, rn, imm); 11813955Sgiacomo.gabrielli@arm.com case 0x9: 11913955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int16_t>(mn, machInst, zt, pg, rn, imm); 12013955Sgiacomo.gabrielli@arm.com case 0xa: 12113955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 12213955Sgiacomo.gabrielli@arm.com case 0xb: 12313955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 12413955Sgiacomo.gabrielli@arm.com case 0xc: 12513955Sgiacomo.gabrielli@arm.com return new Base<int64_t, int8_t>(mn, machInst, zt, pg, rn, imm); 12613955Sgiacomo.gabrielli@arm.com case 0xd: 12713955Sgiacomo.gabrielli@arm.com return new Base<int32_t, int8_t>(mn, machInst, zt, pg, rn, imm); 12813955Sgiacomo.gabrielli@arm.com case 0xe: 12913955Sgiacomo.gabrielli@arm.com return new Base<int16_t, int8_t>(mn, machInst, zt, pg, rn, imm); 13013955Sgiacomo.gabrielli@arm.com case 0xf: 13113955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, imm); 13213955Sgiacomo.gabrielli@arm.com } 13313955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 13413955Sgiacomo.gabrielli@arm.com } 13513955Sgiacomo.gabrielli@arm.com 13613955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous store instructions, scalar plus scalar form. 13713955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 13813955Sgiacomo.gabrielli@arm.com StaticInstPtr 13913955Sgiacomo.gabrielli@arm.com decodeSveContigStoreSSInsts(uint8_t dtype, ExtMachInst machInst, 14013955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 14113955Sgiacomo.gabrielli@arm.com IntRegIndex rm) 14213955Sgiacomo.gabrielli@arm.com { 14313955Sgiacomo.gabrielli@arm.com const char* mn = "st1"; 14413955Sgiacomo.gabrielli@arm.com switch (dtype) { 14513955Sgiacomo.gabrielli@arm.com case 0x0: 14613955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 14713955Sgiacomo.gabrielli@arm.com case 0x1: 14813955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 14913955Sgiacomo.gabrielli@arm.com case 0x2: 15013955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 15113955Sgiacomo.gabrielli@arm.com case 0x3: 15213955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, rm); 15313955Sgiacomo.gabrielli@arm.com case 0x5: 15413955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 15513955Sgiacomo.gabrielli@arm.com case 0x6: 15613955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 15713955Sgiacomo.gabrielli@arm.com case 0x7: 15813955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, rm); 15913955Sgiacomo.gabrielli@arm.com case 0xa: 16013955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 16113955Sgiacomo.gabrielli@arm.com case 0xb: 16213955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, rm); 16313955Sgiacomo.gabrielli@arm.com case 0xf: 16413955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, rm); 16513955Sgiacomo.gabrielli@arm.com } 16613955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 16713955Sgiacomo.gabrielli@arm.com } 16813955Sgiacomo.gabrielli@arm.com 16913955Sgiacomo.gabrielli@arm.com // Decodes SVE contiguous store instructions, scalar plus immediate form. 17013955Sgiacomo.gabrielli@arm.com template <template <typename T1, typename T2> class Base> 17113955Sgiacomo.gabrielli@arm.com StaticInstPtr 17213955Sgiacomo.gabrielli@arm.com decodeSveContigStoreSIInsts(uint8_t dtype, ExtMachInst machInst, 17313955Sgiacomo.gabrielli@arm.com IntRegIndex zt, IntRegIndex pg, IntRegIndex rn, 17413955Sgiacomo.gabrielli@arm.com int8_t imm) 17513955Sgiacomo.gabrielli@arm.com { 17613955Sgiacomo.gabrielli@arm.com const char* mn = "st1"; 17713955Sgiacomo.gabrielli@arm.com switch (dtype) { 17813955Sgiacomo.gabrielli@arm.com case 0x0: 17913955Sgiacomo.gabrielli@arm.com return new Base<uint8_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18013955Sgiacomo.gabrielli@arm.com case 0x1: 18113955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18213955Sgiacomo.gabrielli@arm.com case 0x2: 18313955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18413955Sgiacomo.gabrielli@arm.com case 0x3: 18513955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint8_t>(mn, machInst, zt, pg, rn, imm); 18613955Sgiacomo.gabrielli@arm.com case 0x5: 18713955Sgiacomo.gabrielli@arm.com return new Base<uint16_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 18813955Sgiacomo.gabrielli@arm.com case 0x6: 18913955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 19013955Sgiacomo.gabrielli@arm.com case 0x7: 19113955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint16_t>(mn, machInst, zt, pg, rn, imm); 19213955Sgiacomo.gabrielli@arm.com case 0xa: 19313955Sgiacomo.gabrielli@arm.com return new Base<uint32_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 19413955Sgiacomo.gabrielli@arm.com case 0xb: 19513955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint32_t>(mn, machInst, zt, pg, rn, imm); 19613955Sgiacomo.gabrielli@arm.com case 0xf: 19713955Sgiacomo.gabrielli@arm.com return new Base<uint64_t, uint64_t>(mn, machInst, zt, pg, rn, imm); 19813955Sgiacomo.gabrielli@arm.com } 19913955Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 20013955Sgiacomo.gabrielli@arm.com } 20113955Sgiacomo.gabrielli@arm.com 20213955Sgiacomo.gabrielli@arm.com // NOTE: SVE load-and-replicate instructions are decoded with 20313955Sgiacomo.gabrielli@arm.com // decodeSveContigLoadSIInsts(...). 20413955Sgiacomo.gabrielli@arm.com 20513955Sgiacomo.gabrielli@arm.com}}; 20613955Sgiacomo.gabrielli@arm.com 20713955Sgiacomo.gabrielli@arm.comlet {{ 20813955Sgiacomo.gabrielli@arm.com 20913955Sgiacomo.gabrielli@arm.com header_output = '' 21013955Sgiacomo.gabrielli@arm.com exec_output = '' 21113955Sgiacomo.gabrielli@arm.com decoders = { 'Generic': {} } 21213955Sgiacomo.gabrielli@arm.com 21313955Sgiacomo.gabrielli@arm.com SPAlignmentCheckCode = ''' 21413955Sgiacomo.gabrielli@arm.com if (this->baseIsSP && bits(XBase, 3, 0) && 21513955Sgiacomo.gabrielli@arm.com SPAlignmentCheckEnabled(xc->tcBase())) { 21613955Sgiacomo.gabrielli@arm.com return std::make_shared<SPAlignmentFault>(); 21713955Sgiacomo.gabrielli@arm.com } 21813955Sgiacomo.gabrielli@arm.com ''' 21913955Sgiacomo.gabrielli@arm.com 22013955Sgiacomo.gabrielli@arm.com def emitSveMemFillSpill(isPred): 22113955Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 22213955Sgiacomo.gabrielli@arm.com eaCode = SPAlignmentCheckCode + ''' 22313955Sgiacomo.gabrielli@arm.com int memAccessSize = %(memacc_size)s; 22413955Sgiacomo.gabrielli@arm.com EA = XBase + ((int64_t) imm * %(memacc_size)s)''' % { 22513955Sgiacomo.gabrielli@arm.com 'memacc_size': 'eCount / 8' if isPred else 'eCount'} 22613955Sgiacomo.gabrielli@arm.com if isPred: 22713955Sgiacomo.gabrielli@arm.com loadMemAccCode = ''' 22813955Sgiacomo.gabrielli@arm.com int index = 0; 22913955Sgiacomo.gabrielli@arm.com uint8_t byte; 23013955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount / 8; i++) { 23113955Sgiacomo.gabrielli@arm.com byte = memDataView[i]; 23213955Sgiacomo.gabrielli@arm.com for (int j = 0; j < 8; j++, index++) { 23313955Sgiacomo.gabrielli@arm.com PDest_x[index] = (byte >> j) & 1; 23413955Sgiacomo.gabrielli@arm.com } 23513955Sgiacomo.gabrielli@arm.com } 23613955Sgiacomo.gabrielli@arm.com ''' 23713955Sgiacomo.gabrielli@arm.com storeMemAccCode = ''' 23813955Sgiacomo.gabrielli@arm.com int index = 0; 23913955Sgiacomo.gabrielli@arm.com uint8_t byte; 24013955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount / 8; i++) { 24113955Sgiacomo.gabrielli@arm.com byte = 0; 24213955Sgiacomo.gabrielli@arm.com for (int j = 0; j < 8; j++, index++) { 24313955Sgiacomo.gabrielli@arm.com byte |= PDest_x[index] << j; 24413955Sgiacomo.gabrielli@arm.com } 24513955Sgiacomo.gabrielli@arm.com memDataView[i] = byte; 24613955Sgiacomo.gabrielli@arm.com } 24713955Sgiacomo.gabrielli@arm.com ''' 24813955Sgiacomo.gabrielli@arm.com storeWrEnableCode = ''' 24913955Sgiacomo.gabrielli@arm.com auto wrEn = std::vector<bool>(eCount / 8, true); 25013955Sgiacomo.gabrielli@arm.com ''' 25113955Sgiacomo.gabrielli@arm.com else: 25213955Sgiacomo.gabrielli@arm.com loadMemAccCode = ''' 25313955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 25413955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = memDataView[i]; 25513955Sgiacomo.gabrielli@arm.com } 25613955Sgiacomo.gabrielli@arm.com ''' 25713955Sgiacomo.gabrielli@arm.com storeMemAccCode = ''' 25813955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 25913955Sgiacomo.gabrielli@arm.com memDataView[i] = AA64FpDest_x[i]; 26013955Sgiacomo.gabrielli@arm.com } 26113955Sgiacomo.gabrielli@arm.com ''' 26213955Sgiacomo.gabrielli@arm.com storeWrEnableCode = ''' 26313955Sgiacomo.gabrielli@arm.com auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true); 26413955Sgiacomo.gabrielli@arm.com ''' 26513955Sgiacomo.gabrielli@arm.com loadIop = InstObjParams('ldr', 26613955Sgiacomo.gabrielli@arm.com 'SveLdrPred' if isPred else 'SveLdrVec', 26713955Sgiacomo.gabrielli@arm.com 'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill', 26813955Sgiacomo.gabrielli@arm.com {'tpl_header': '', 26913955Sgiacomo.gabrielli@arm.com 'tpl_args': '', 27013955Sgiacomo.gabrielli@arm.com 'memacc_code': loadMemAccCode, 27113955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 27213955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 27313955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsLoad']) 27413955Sgiacomo.gabrielli@arm.com storeIop = InstObjParams('str', 27513955Sgiacomo.gabrielli@arm.com 'SveStrPred' if isPred else 'SveStrVec', 27613955Sgiacomo.gabrielli@arm.com 'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill', 27713955Sgiacomo.gabrielli@arm.com {'tpl_header': '', 27813955Sgiacomo.gabrielli@arm.com 'tpl_args': '', 27913955Sgiacomo.gabrielli@arm.com 'wren_code': storeWrEnableCode, 28013955Sgiacomo.gabrielli@arm.com 'memacc_code': storeMemAccCode, 28113955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 28213955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 28313955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsStore']) 28413955Sgiacomo.gabrielli@arm.com header_output += SveMemFillSpillOpDeclare.subst(loadIop) 28513955Sgiacomo.gabrielli@arm.com header_output += SveMemFillSpillOpDeclare.subst(storeIop) 28613955Sgiacomo.gabrielli@arm.com exec_output += ( 28713955Sgiacomo.gabrielli@arm.com SveContigLoadExecute.subst(loadIop) + 28813955Sgiacomo.gabrielli@arm.com SveContigLoadInitiateAcc.subst(loadIop) + 28913955Sgiacomo.gabrielli@arm.com SveContigLoadCompleteAcc.subst(loadIop) + 29013955Sgiacomo.gabrielli@arm.com SveContigStoreExecute.subst(storeIop) + 29113955Sgiacomo.gabrielli@arm.com SveContigStoreInitiateAcc.subst(storeIop) + 29213955Sgiacomo.gabrielli@arm.com SveContigStoreCompleteAcc.subst(storeIop)) 29313955Sgiacomo.gabrielli@arm.com 29413955Sgiacomo.gabrielli@arm.com loadTplArgs = ( 29513955Sgiacomo.gabrielli@arm.com ('uint8_t', 'uint8_t'), 29613955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint8_t'), 29713955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint8_t'), 29813955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint8_t'), 29913955Sgiacomo.gabrielli@arm.com ('int64_t', 'int32_t'), 30013955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint16_t'), 30113955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint16_t'), 30213955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint16_t'), 30313955Sgiacomo.gabrielli@arm.com ('int64_t', 'int16_t'), 30413955Sgiacomo.gabrielli@arm.com ('int32_t', 'int16_t'), 30513955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint32_t'), 30613955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint32_t'), 30713955Sgiacomo.gabrielli@arm.com ('int64_t', 'int8_t'), 30813955Sgiacomo.gabrielli@arm.com ('int32_t', 'int8_t'), 30913955Sgiacomo.gabrielli@arm.com ('int16_t', 'int8_t'), 31013955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint64_t'), 31113955Sgiacomo.gabrielli@arm.com ) 31213955Sgiacomo.gabrielli@arm.com 31313955Sgiacomo.gabrielli@arm.com storeTplArgs = ( 31413955Sgiacomo.gabrielli@arm.com ('uint8_t', 'uint8_t'), 31513955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint8_t'), 31613955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint8_t'), 31713955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint8_t'), 31813955Sgiacomo.gabrielli@arm.com ('uint16_t', 'uint16_t'), 31913955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint16_t'), 32013955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint16_t'), 32113955Sgiacomo.gabrielli@arm.com ('uint32_t', 'uint32_t'), 32213955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint32_t'), 32313955Sgiacomo.gabrielli@arm.com ('uint64_t', 'uint64_t'), 32413955Sgiacomo.gabrielli@arm.com ) 32513955Sgiacomo.gabrielli@arm.com 32613955Sgiacomo.gabrielli@arm.com # Generates definitions for SVE contiguous loads 32713955Sgiacomo.gabrielli@arm.com def emitSveContigMemInsts(offsetIsImm): 32813955Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 32913955Sgiacomo.gabrielli@arm.com tplHeader = 'template <class RegElemType, class MemElemType>' 33013955Sgiacomo.gabrielli@arm.com tplArgs = '<RegElemType, MemElemType>' 33113955Sgiacomo.gabrielli@arm.com eaCode = SPAlignmentCheckCode + ''' 33213955Sgiacomo.gabrielli@arm.com int memAccessSize = eCount * sizeof(MemElemType); 33313955Sgiacomo.gabrielli@arm.com EA = XBase + ''' 33413955Sgiacomo.gabrielli@arm.com if offsetIsImm: 33513955Sgiacomo.gabrielli@arm.com eaCode += '((int64_t) this->imm * eCount * sizeof(MemElemType))' 33613955Sgiacomo.gabrielli@arm.com else: 33713955Sgiacomo.gabrielli@arm.com eaCode += '(XOffset * sizeof(MemElemType));' 33813955Sgiacomo.gabrielli@arm.com loadMemAccCode = ''' 33913955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 34013955Sgiacomo.gabrielli@arm.com if (GpOp_x[i]) { 34113955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = memDataView[i]; 34213955Sgiacomo.gabrielli@arm.com } else { 34313955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = 0; 34413955Sgiacomo.gabrielli@arm.com } 34513955Sgiacomo.gabrielli@arm.com } 34613955Sgiacomo.gabrielli@arm.com ''' 34713955Sgiacomo.gabrielli@arm.com storeMemAccCode = ''' 34813955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 34913955Sgiacomo.gabrielli@arm.com if (GpOp_x[i]) { 35013955Sgiacomo.gabrielli@arm.com memDataView[i] = AA64FpDest_x[i]; 35113955Sgiacomo.gabrielli@arm.com } else { 35213955Sgiacomo.gabrielli@arm.com memDataView[i] = 0; 35313955Sgiacomo.gabrielli@arm.com for (int j = 0; j < sizeof(MemElemType); j++) { 35413955Sgiacomo.gabrielli@arm.com wrEn[sizeof(MemElemType) * i + j] = false; 35513955Sgiacomo.gabrielli@arm.com } 35613955Sgiacomo.gabrielli@arm.com } 35713955Sgiacomo.gabrielli@arm.com } 35813955Sgiacomo.gabrielli@arm.com ''' 35913955Sgiacomo.gabrielli@arm.com storeWrEnableCode = ''' 36013955Sgiacomo.gabrielli@arm.com auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true); 36113955Sgiacomo.gabrielli@arm.com ''' 36213955Sgiacomo.gabrielli@arm.com loadIop = InstObjParams('ld1', 36313955Sgiacomo.gabrielli@arm.com 'SveContigLoadSI' if offsetIsImm else 'SveContigLoadSS', 36413955Sgiacomo.gabrielli@arm.com 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', 36513955Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 36613955Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 36713955Sgiacomo.gabrielli@arm.com 'memacc_code': loadMemAccCode, 36813955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 36913955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 37013955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsLoad']) 37113955Sgiacomo.gabrielli@arm.com storeIop = InstObjParams('st1', 37213955Sgiacomo.gabrielli@arm.com 'SveContigStoreSI' if offsetIsImm else 'SveContigStoreSS', 37313955Sgiacomo.gabrielli@arm.com 'SveContigMemSI' if offsetIsImm else 'SveContigMemSS', 37413955Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 37513955Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 37613955Sgiacomo.gabrielli@arm.com 'wren_code': storeWrEnableCode, 37713955Sgiacomo.gabrielli@arm.com 'memacc_code': storeMemAccCode, 37813955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 37913955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 38013955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsStore']) 38113955Sgiacomo.gabrielli@arm.com if offsetIsImm: 38213955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSIOpDeclare.subst(loadIop) 38313955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSIOpDeclare.subst(storeIop) 38413955Sgiacomo.gabrielli@arm.com else: 38513955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSSOpDeclare.subst(loadIop) 38613955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSSOpDeclare.subst(storeIop) 38713955Sgiacomo.gabrielli@arm.com exec_output += ( 38813955Sgiacomo.gabrielli@arm.com SveContigLoadExecute.subst(loadIop) + 38913955Sgiacomo.gabrielli@arm.com SveContigLoadInitiateAcc.subst(loadIop) + 39013955Sgiacomo.gabrielli@arm.com SveContigLoadCompleteAcc.subst(loadIop) + 39113955Sgiacomo.gabrielli@arm.com SveContigStoreExecute.subst(storeIop) + 39213955Sgiacomo.gabrielli@arm.com SveContigStoreInitiateAcc.subst(storeIop) + 39313955Sgiacomo.gabrielli@arm.com SveContigStoreCompleteAcc.subst(storeIop)) 39413955Sgiacomo.gabrielli@arm.com for args in loadTplArgs: 39513955Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 39613955Sgiacomo.gabrielli@arm.com 'class_name': 'SveContigLoadSI' if offsetIsImm 39713955Sgiacomo.gabrielli@arm.com else 'SveContigLoadSS'} 39813955Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 39913955Sgiacomo.gabrielli@arm.com for args in storeTplArgs: 40013955Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 40113955Sgiacomo.gabrielli@arm.com 'class_name': 'SveContigStoreSI' if offsetIsImm 40213955Sgiacomo.gabrielli@arm.com else 'SveContigStoreSS'} 40313955Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 40413955Sgiacomo.gabrielli@arm.com 40513955Sgiacomo.gabrielli@arm.com # Generates definitions for SVE load-and-replicate instructions 40613955Sgiacomo.gabrielli@arm.com def emitSveLoadAndRepl(): 40713955Sgiacomo.gabrielli@arm.com global header_output, exec_output, decoders 40813955Sgiacomo.gabrielli@arm.com tplHeader = 'template <class RegElemType, class MemElemType>' 40913955Sgiacomo.gabrielli@arm.com tplArgs = '<RegElemType, MemElemType>' 41013955Sgiacomo.gabrielli@arm.com eaCode = SPAlignmentCheckCode + ''' 41113955Sgiacomo.gabrielli@arm.com EA = XBase + imm * sizeof(MemElemType);''' 41213955Sgiacomo.gabrielli@arm.com memAccCode = ''' 41313955Sgiacomo.gabrielli@arm.com for (int i = 0; i < eCount; i++) { 41413955Sgiacomo.gabrielli@arm.com if (GpOp_x[i]) { 41513955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = memData; 41613955Sgiacomo.gabrielli@arm.com } else { 41713955Sgiacomo.gabrielli@arm.com AA64FpDest_x[i] = 0; 41813955Sgiacomo.gabrielli@arm.com } 41913955Sgiacomo.gabrielli@arm.com } 42013955Sgiacomo.gabrielli@arm.com ''' 42113955Sgiacomo.gabrielli@arm.com iop = InstObjParams('ld1r', 42213955Sgiacomo.gabrielli@arm.com 'SveLoadAndRepl', 42313955Sgiacomo.gabrielli@arm.com 'SveContigMemSI', 42413955Sgiacomo.gabrielli@arm.com {'tpl_header': tplHeader, 42513955Sgiacomo.gabrielli@arm.com 'tpl_args': tplArgs, 42613955Sgiacomo.gabrielli@arm.com 'memacc_code': memAccCode, 42713955Sgiacomo.gabrielli@arm.com 'ea_code' : sveEnabledCheckCode + eaCode, 42813955Sgiacomo.gabrielli@arm.com 'fa_code' : ''}, 42913955Sgiacomo.gabrielli@arm.com ['IsMemRef', 'IsLoad']) 43013955Sgiacomo.gabrielli@arm.com header_output += SveContigMemSIOpDeclare.subst(iop) 43113955Sgiacomo.gabrielli@arm.com exec_output += ( 43213955Sgiacomo.gabrielli@arm.com SveLoadAndReplExecute.subst(iop) + 43313955Sgiacomo.gabrielli@arm.com SveLoadAndReplInitiateAcc.subst(iop) + 43413955Sgiacomo.gabrielli@arm.com SveLoadAndReplCompleteAcc.subst(iop)) 43513955Sgiacomo.gabrielli@arm.com for args in loadTplArgs: 43613955Sgiacomo.gabrielli@arm.com substDict = {'tpl_args': '<%s>' % ', '.join(args), 43713955Sgiacomo.gabrielli@arm.com 'class_name': 'SveLoadAndRepl'} 43813955Sgiacomo.gabrielli@arm.com exec_output += SveContigMemExecDeclare.subst(substDict) 43913955Sgiacomo.gabrielli@arm.com 44013955Sgiacomo.gabrielli@arm.com # LD1[S]{B,H,W,D} (scalar plus immediate) 44113955Sgiacomo.gabrielli@arm.com emitSveContigMemInsts(True) 44213955Sgiacomo.gabrielli@arm.com # LD1[S]{B,H,W,D} (scalar plus scalar) 44313955Sgiacomo.gabrielli@arm.com emitSveContigMemInsts(False) 44413955Sgiacomo.gabrielli@arm.com 44513955Sgiacomo.gabrielli@arm.com # LD1R[S]{B,H,W,D} 44613955Sgiacomo.gabrielli@arm.com emitSveLoadAndRepl() 44713955Sgiacomo.gabrielli@arm.com 44813955Sgiacomo.gabrielli@arm.com # LDR (predicate), STR (predicate) 44913955Sgiacomo.gabrielli@arm.com emitSveMemFillSpill(True) 45013955Sgiacomo.gabrielli@arm.com # LDR (vector), STR (vector) 45113955Sgiacomo.gabrielli@arm.com emitSveMemFillSpill(False) 45213955Sgiacomo.gabrielli@arm.com 45313955Sgiacomo.gabrielli@arm.com}}; 454