neon64.isa revision 10474
110037SARM gem5 Developers// -*- mode: c++ -*- 210037SARM gem5 Developers 310037SARM gem5 Developers// Copyright (c) 2012-2013 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Giacomo Gabrielli 3910037SARM gem5 Developers// Mbou Eyole 4010037SARM gem5 Developers 4110037SARM gem5 Developerslet {{ 4210037SARM gem5 Developers 4310037SARM gem5 Developers header_output = "" 4410037SARM gem5 Developers exec_output = "" 4510037SARM gem5 Developers 4610037SARM gem5 Developers # FP types (FP operations always work with unsigned representations) 4710037SARM gem5 Developers floatTypes = ("uint32_t", "uint64_t") 4810037SARM gem5 Developers smallFloatTypes = ("uint32_t",) 4910037SARM gem5 Developers 5010037SARM gem5 Developers def threeEqualRegInstX(name, Name, opClass, types, rCount, op, 5110037SARM gem5 Developers readDest=False, pairwise=False, scalar=False, 5210037SARM gem5 Developers byElem=False): 5310037SARM gem5 Developers assert (not pairwise) or ((not byElem) and (not scalar)) 5410037SARM gem5 Developers global header_output, exec_output 5510037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 5610037SARM gem5 Developers RegVect srcReg1, destReg; 5710037SARM gem5 Developers ''' 5810037SARM gem5 Developers if byElem: 5910037SARM gem5 Developers # 2nd register operand has to be read fully 6010037SARM gem5 Developers eWalkCode += ''' 6110037SARM gem5 Developers FullRegVect srcReg2; 6210037SARM gem5 Developers ''' 6310037SARM gem5 Developers else: 6410037SARM gem5 Developers eWalkCode += ''' 6510037SARM gem5 Developers RegVect srcReg2; 6610037SARM gem5 Developers ''' 6710037SARM gem5 Developers for reg in range(rCount): 6810037SARM gem5 Developers eWalkCode += ''' 6910037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 7010037SARM gem5 Developers srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw); 7110037SARM gem5 Developers ''' % { "reg" : reg } 7210037SARM gem5 Developers if readDest: 7310037SARM gem5 Developers eWalkCode += ''' 7410037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 7510037SARM gem5 Developers ''' % { "reg" : reg } 7610037SARM gem5 Developers if byElem: 7710037SARM gem5 Developers # 2nd operand has to be read fully 7810037SARM gem5 Developers for reg in range(rCount, 4): 7910037SARM gem5 Developers eWalkCode += ''' 8010037SARM gem5 Developers srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw); 8110037SARM gem5 Developers ''' % { "reg" : reg } 8210037SARM gem5 Developers readDestCode = '' 8310037SARM gem5 Developers if readDest: 8410037SARM gem5 Developers readDestCode = 'destElem = gtoh(destReg.elements[i]);' 8510037SARM gem5 Developers if pairwise: 8610037SARM gem5 Developers eWalkCode += ''' 8710037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 8810037SARM gem5 Developers Element srcElem1 = gtoh(2 * i < eCount ? 8910037SARM gem5 Developers srcReg1.elements[2 * i] : 9010037SARM gem5 Developers srcReg2.elements[2 * i - eCount]); 9110037SARM gem5 Developers Element srcElem2 = gtoh(2 * i < eCount ? 9210037SARM gem5 Developers srcReg1.elements[2 * i + 1] : 9310037SARM gem5 Developers srcReg2.elements[2 * i + 1 - eCount]); 9410037SARM gem5 Developers Element destElem; 9510037SARM gem5 Developers %(readDest)s 9610037SARM gem5 Developers %(op)s 9710037SARM gem5 Developers destReg.elements[i] = htog(destElem); 9810037SARM gem5 Developers } 9910037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode } 10010037SARM gem5 Developers else: 10110037SARM gem5 Developers scalarCheck = ''' 10210037SARM gem5 Developers if (i != 0) { 10310037SARM gem5 Developers destReg.elements[i] = 0; 10410037SARM gem5 Developers continue; 10510037SARM gem5 Developers } 10610037SARM gem5 Developers ''' 10710037SARM gem5 Developers eWalkCode += ''' 10810037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 10910037SARM gem5 Developers %(scalarCheck)s 11010037SARM gem5 Developers Element srcElem1 = gtoh(srcReg1.elements[i]); 11110037SARM gem5 Developers Element srcElem2 = gtoh(srcReg2.elements[%(src2Index)s]); 11210037SARM gem5 Developers Element destElem; 11310037SARM gem5 Developers %(readDest)s 11410037SARM gem5 Developers %(op)s 11510037SARM gem5 Developers destReg.elements[i] = htog(destElem); 11610037SARM gem5 Developers } 11710037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode, 11810037SARM gem5 Developers "scalarCheck" : scalarCheck if scalar else "", 11910037SARM gem5 Developers "src2Index" : "imm" if byElem else "i" } 12010037SARM gem5 Developers for reg in range(rCount): 12110037SARM gem5 Developers eWalkCode += ''' 12210037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 12310037SARM gem5 Developers ''' % { "reg" : reg } 12410037SARM gem5 Developers if rCount < 4: # zero upper half 12510037SARM gem5 Developers for reg in range(rCount, 4): 12610037SARM gem5 Developers eWalkCode += ''' 12710037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 12810037SARM gem5 Developers ''' % { "reg" : reg } 12910037SARM gem5 Developers iop = InstObjParams(name, Name, 13010037SARM gem5 Developers "DataX2RegImmOp" if byElem else "DataX2RegOp", 13110037SARM gem5 Developers { "code": eWalkCode, 13210037SARM gem5 Developers "r_count": rCount, 13310037SARM gem5 Developers "op_class": opClass }, []) 13410037SARM gem5 Developers if byElem: 13510037SARM gem5 Developers header_output += NeonX2RegImmOpDeclare.subst(iop) 13610037SARM gem5 Developers else: 13710037SARM gem5 Developers header_output += NeonX2RegOpDeclare.subst(iop) 13810037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 13910037SARM gem5 Developers for type in types: 14010037SARM gem5 Developers substDict = { "targs" : type, 14110037SARM gem5 Developers "class_name" : Name } 14210037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 14310037SARM gem5 Developers 14410037SARM gem5 Developers def threeUnequalRegInstX(name, Name, opClass, types, op, 14510037SARM gem5 Developers bigSrc1, bigSrc2, bigDest, readDest, scalar=False, 14610037SARM gem5 Developers byElem=False, hi=False): 14710037SARM gem5 Developers assert not (scalar and hi) 14810037SARM gem5 Developers global header_output, exec_output 14910037SARM gem5 Developers src1Cnt = src2Cnt = destCnt = 2 15010037SARM gem5 Developers src1Prefix = src2Prefix = destPrefix = '' 15110037SARM gem5 Developers if bigSrc1: 15210037SARM gem5 Developers src1Cnt = 4 15310037SARM gem5 Developers src1Prefix = 'Big' 15410037SARM gem5 Developers if bigSrc2: 15510037SARM gem5 Developers src2Cnt = 4 15610037SARM gem5 Developers src2Prefix = 'Big' 15710037SARM gem5 Developers if bigDest: 15810037SARM gem5 Developers destCnt = 4 15910037SARM gem5 Developers destPrefix = 'Big' 16010037SARM gem5 Developers if byElem: 16110037SARM gem5 Developers src2Prefix = 'Full' 16210037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 16310037SARM gem5 Developers %sRegVect srcReg1; 16410037SARM gem5 Developers %sRegVect srcReg2; 16510037SARM gem5 Developers %sRegVect destReg; 16610037SARM gem5 Developers ''' % (src1Prefix, src2Prefix, destPrefix) 16710037SARM gem5 Developers srcReg1 = 0 16810037SARM gem5 Developers if hi and not bigSrc1: # long/widening operations 16910037SARM gem5 Developers srcReg1 = 2 17010037SARM gem5 Developers for reg in range(src1Cnt): 17110037SARM gem5 Developers eWalkCode += ''' 17210037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(srcReg1)d_uw); 17310037SARM gem5 Developers ''' % { "reg" : reg, "srcReg1" : srcReg1 } 17410037SARM gem5 Developers srcReg1 += 1 17510037SARM gem5 Developers srcReg2 = 0 17610037SARM gem5 Developers if (not byElem) and (hi and not bigSrc2): # long/widening operations 17710037SARM gem5 Developers srcReg2 = 2 17810037SARM gem5 Developers for reg in range(src2Cnt): 17910037SARM gem5 Developers eWalkCode += ''' 18010037SARM gem5 Developers srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(srcReg2)d_uw); 18110037SARM gem5 Developers ''' % { "reg" : reg, "srcReg2" : srcReg2 } 18210037SARM gem5 Developers srcReg2 += 1 18310037SARM gem5 Developers if byElem: 18410037SARM gem5 Developers # 2nd operand has to be read fully 18510037SARM gem5 Developers for reg in range(src2Cnt, 4): 18610037SARM gem5 Developers eWalkCode += ''' 18710037SARM gem5 Developers srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw); 18810037SARM gem5 Developers ''' % { "reg" : reg } 18910037SARM gem5 Developers if readDest: 19010037SARM gem5 Developers for reg in range(destCnt): 19110037SARM gem5 Developers eWalkCode += ''' 19210037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 19310037SARM gem5 Developers ''' % { "reg" : reg } 19410037SARM gem5 Developers readDestCode = '' 19510037SARM gem5 Developers if readDest: 19610037SARM gem5 Developers readDestCode = 'destElem = gtoh(destReg.elements[i]);' 19710037SARM gem5 Developers scalarCheck = ''' 19810037SARM gem5 Developers if (i != 0) { 19910037SARM gem5 Developers destReg.elements[i] = 0; 20010037SARM gem5 Developers continue; 20110037SARM gem5 Developers } 20210037SARM gem5 Developers ''' 20310037SARM gem5 Developers eWalkCode += ''' 20410037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 20510037SARM gem5 Developers %(scalarCheck)s 20610037SARM gem5 Developers %(src1Prefix)sElement srcElem1 = gtoh(srcReg1.elements[i]); 20710037SARM gem5 Developers %(src1Prefix)sElement srcElem2 = gtoh(srcReg2.elements[%(src2Index)s]); 20810037SARM gem5 Developers %(destPrefix)sElement destElem; 20910037SARM gem5 Developers %(readDest)s 21010037SARM gem5 Developers %(op)s 21110037SARM gem5 Developers destReg.elements[i] = htog(destElem); 21210037SARM gem5 Developers } 21310037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode, 21410037SARM gem5 Developers "src1Prefix" : src1Prefix, "src2Prefix" : src2Prefix, 21510037SARM gem5 Developers "destPrefix" : destPrefix, 21610037SARM gem5 Developers "scalarCheck" : scalarCheck if scalar else "", 21710037SARM gem5 Developers "src2Index" : "imm" if byElem else "i" } 21810037SARM gem5 Developers destReg = 0 21910037SARM gem5 Developers if hi and not bigDest: 22010037SARM gem5 Developers # narrowing operations 22110037SARM gem5 Developers destReg = 2 22210037SARM gem5 Developers for reg in range(destCnt): 22310037SARM gem5 Developers eWalkCode += ''' 22410037SARM gem5 Developers AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]); 22510037SARM gem5 Developers ''' % { "reg" : reg, "destReg": destReg } 22610037SARM gem5 Developers destReg += 1 22710037SARM gem5 Developers if destCnt < 4 and not hi: # zero upper half 22810037SARM gem5 Developers for reg in range(destCnt, 4): 22910037SARM gem5 Developers eWalkCode += ''' 23010037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 23110037SARM gem5 Developers ''' % { "reg" : reg } 23210037SARM gem5 Developers iop = InstObjParams(name, Name, 23310037SARM gem5 Developers "DataX2RegImmOp" if byElem else "DataX2RegOp", 23410037SARM gem5 Developers { "code": eWalkCode, 23510037SARM gem5 Developers "r_count": 2, 23610037SARM gem5 Developers "op_class": opClass }, []) 23710037SARM gem5 Developers if byElem: 23810037SARM gem5 Developers header_output += NeonX2RegImmOpDeclare.subst(iop) 23910037SARM gem5 Developers else: 24010037SARM gem5 Developers header_output += NeonX2RegOpDeclare.subst(iop) 24110037SARM gem5 Developers exec_output += NeonXUnequalRegOpExecute.subst(iop) 24210037SARM gem5 Developers for type in types: 24310037SARM gem5 Developers substDict = { "targs" : type, 24410037SARM gem5 Developers "class_name" : Name } 24510037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 24610037SARM gem5 Developers 24710037SARM gem5 Developers def threeRegNarrowInstX(name, Name, opClass, types, op, readDest=False, 24810037SARM gem5 Developers scalar=False, byElem=False, hi=False): 24910037SARM gem5 Developers assert not byElem 25010037SARM gem5 Developers threeUnequalRegInstX(name, Name, opClass, types, op, 25110037SARM gem5 Developers True, True, False, readDest, scalar, byElem, hi) 25210037SARM gem5 Developers 25310037SARM gem5 Developers def threeRegLongInstX(name, Name, opClass, types, op, readDest=False, 25410037SARM gem5 Developers scalar=False, byElem=False, hi=False): 25510037SARM gem5 Developers threeUnequalRegInstX(name, Name, opClass, types, op, 25610037SARM gem5 Developers False, False, True, readDest, scalar, byElem, hi) 25710037SARM gem5 Developers 25810037SARM gem5 Developers def threeRegWideInstX(name, Name, opClass, types, op, readDest=False, 25910037SARM gem5 Developers scalar=False, byElem=False, hi=False): 26010037SARM gem5 Developers assert not byElem 26110037SARM gem5 Developers threeUnequalRegInstX(name, Name, opClass, types, op, 26210037SARM gem5 Developers True, False, True, readDest, scalar, byElem, hi) 26310037SARM gem5 Developers 26410037SARM gem5 Developers def twoEqualRegInstX(name, Name, opClass, types, rCount, op, 26510037SARM gem5 Developers readDest=False, scalar=False, byElem=False, 26610037SARM gem5 Developers hasImm=False, isDup=False): 26710037SARM gem5 Developers global header_output, exec_output 26810037SARM gem5 Developers assert (not isDup) or byElem 26910037SARM gem5 Developers if byElem: 27010037SARM gem5 Developers hasImm = True 27110037SARM gem5 Developers if isDup: 27210037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 27310037SARM gem5 Developers FullRegVect srcReg1; 27410037SARM gem5 Developers RegVect destReg; 27510037SARM gem5 Developers ''' 27610037SARM gem5 Developers else: 27710037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 27810037SARM gem5 Developers RegVect srcReg1, destReg; 27910037SARM gem5 Developers ''' 28010037SARM gem5 Developers for reg in range(4 if isDup else rCount): 28110037SARM gem5 Developers eWalkCode += ''' 28210037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 28310037SARM gem5 Developers ''' % { "reg" : reg } 28410037SARM gem5 Developers if readDest: 28510037SARM gem5 Developers eWalkCode += ''' 28610037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 28710037SARM gem5 Developers ''' % { "reg" : reg } 28810037SARM gem5 Developers readDestCode = '' 28910037SARM gem5 Developers if readDest: 29010037SARM gem5 Developers readDestCode = 'destElem = gtoh(destReg.elements[i]);' 29110037SARM gem5 Developers scalarCheck = ''' 29210037SARM gem5 Developers if (i != 0) { 29310037SARM gem5 Developers destReg.elements[i] = 0; 29410037SARM gem5 Developers continue; 29510037SARM gem5 Developers } 29610037SARM gem5 Developers ''' 29710037SARM gem5 Developers eWalkCode += ''' 29810037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 29910037SARM gem5 Developers %(scalarCheck)s 30010037SARM gem5 Developers unsigned j = i; 30110037SARM gem5 Developers Element srcElem1 = gtoh(srcReg1.elements[%(src1Index)s]); 30210037SARM gem5 Developers Element destElem; 30310037SARM gem5 Developers %(readDest)s 30410037SARM gem5 Developers %(op)s 30510037SARM gem5 Developers destReg.elements[j] = htog(destElem); 30610037SARM gem5 Developers } 30710037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode, 30810037SARM gem5 Developers "scalarCheck" : scalarCheck if scalar else "", 30910037SARM gem5 Developers "src1Index" : "imm" if byElem else "i" } 31010037SARM gem5 Developers for reg in range(rCount): 31110037SARM gem5 Developers eWalkCode += ''' 31210037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 31310037SARM gem5 Developers ''' % { "reg" : reg } 31410037SARM gem5 Developers if rCount < 4: # zero upper half 31510037SARM gem5 Developers for reg in range(rCount, 4): 31610037SARM gem5 Developers eWalkCode += ''' 31710037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 31810037SARM gem5 Developers ''' % { "reg" : reg } 31910037SARM gem5 Developers iop = InstObjParams(name, Name, 32010037SARM gem5 Developers "DataX1RegImmOp" if hasImm else "DataX1RegOp", 32110037SARM gem5 Developers { "code": eWalkCode, 32210037SARM gem5 Developers "r_count": rCount, 32310037SARM gem5 Developers "op_class": opClass }, []) 32410037SARM gem5 Developers if hasImm: 32510037SARM gem5 Developers header_output += NeonX1RegImmOpDeclare.subst(iop) 32610037SARM gem5 Developers else: 32710037SARM gem5 Developers header_output += NeonX1RegOpDeclare.subst(iop) 32810037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 32910037SARM gem5 Developers for type in types: 33010037SARM gem5 Developers substDict = { "targs" : type, 33110037SARM gem5 Developers "class_name" : Name } 33210037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 33310037SARM gem5 Developers 33410037SARM gem5 Developers def twoRegLongInstX(name, Name, opClass, types, op, readDest=False, 33510037SARM gem5 Developers hi=False, hasImm=False): 33610037SARM gem5 Developers global header_output, exec_output 33710037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 33810037SARM gem5 Developers RegVect srcReg1; 33910037SARM gem5 Developers BigRegVect destReg; 34010037SARM gem5 Developers ''' 34110037SARM gem5 Developers destReg = 0 if not hi else 2 34210037SARM gem5 Developers for reg in range(2): 34310037SARM gem5 Developers eWalkCode += ''' 34410037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(destReg)d_uw); 34510037SARM gem5 Developers ''' % { "reg" : reg, "destReg": destReg } 34610037SARM gem5 Developers destReg += 1 34710037SARM gem5 Developers destReg = 0 if not hi else 2 34810037SARM gem5 Developers if readDest: 34910037SARM gem5 Developers for reg in range(4): 35010037SARM gem5 Developers eWalkCode += ''' 35110037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 35210037SARM gem5 Developers ''' % { "reg" : reg } 35310037SARM gem5 Developers destReg += 1 35410037SARM gem5 Developers readDestCode = '' 35510037SARM gem5 Developers if readDest: 35610037SARM gem5 Developers readDestCode = 'destReg = gtoh(destReg.elements[i]);' 35710037SARM gem5 Developers eWalkCode += ''' 35810037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 35910037SARM gem5 Developers Element srcElem1 = gtoh(srcReg1.elements[i]); 36010037SARM gem5 Developers BigElement destElem; 36110037SARM gem5 Developers %(readDest)s 36210037SARM gem5 Developers %(op)s 36310037SARM gem5 Developers destReg.elements[i] = htog(destElem); 36410037SARM gem5 Developers } 36510037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode } 36610037SARM gem5 Developers for reg in range(4): 36710037SARM gem5 Developers eWalkCode += ''' 36810037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 36910037SARM gem5 Developers ''' % { "reg" : reg } 37010037SARM gem5 Developers iop = InstObjParams(name, Name, 37110037SARM gem5 Developers "DataX1RegImmOp" if hasImm else "DataX1RegOp", 37210037SARM gem5 Developers { "code": eWalkCode, 37310037SARM gem5 Developers "r_count": 2, 37410037SARM gem5 Developers "op_class": opClass }, []) 37510037SARM gem5 Developers if hasImm: 37610037SARM gem5 Developers header_output += NeonX1RegImmOpDeclare.subst(iop) 37710037SARM gem5 Developers else: 37810037SARM gem5 Developers header_output += NeonX1RegOpDeclare.subst(iop) 37910037SARM gem5 Developers exec_output += NeonXUnequalRegOpExecute.subst(iop) 38010037SARM gem5 Developers for type in types: 38110037SARM gem5 Developers substDict = { "targs" : type, 38210037SARM gem5 Developers "class_name" : Name } 38310037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 38410037SARM gem5 Developers 38510037SARM gem5 Developers def twoRegNarrowInstX(name, Name, opClass, types, op, readDest=False, 38610037SARM gem5 Developers scalar=False, hi=False, hasImm=False): 38710037SARM gem5 Developers global header_output, exec_output 38810037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 38910037SARM gem5 Developers BigRegVect srcReg1; 39010037SARM gem5 Developers RegVect destReg; 39110037SARM gem5 Developers ''' 39210037SARM gem5 Developers for reg in range(4): 39310037SARM gem5 Developers eWalkCode += ''' 39410037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 39510037SARM gem5 Developers ''' % { "reg" : reg } 39610037SARM gem5 Developers if readDest: 39710037SARM gem5 Developers for reg in range(2): 39810037SARM gem5 Developers eWalkCode += ''' 39910037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 40010037SARM gem5 Developers ''' % { "reg" : reg } 40110037SARM gem5 Developers else: 40210037SARM gem5 Developers eWalkCode += ''' 40310037SARM gem5 Developers destReg.elements[0] = 0; 40410037SARM gem5 Developers ''' % { "reg" : reg } 40510037SARM gem5 Developers readDestCode = '' 40610037SARM gem5 Developers if readDest: 40710037SARM gem5 Developers readDestCode = 'destElem = gtoh(destReg.elements[i]);' 40810037SARM gem5 Developers scalarCheck = ''' 40910037SARM gem5 Developers if (i != 0) { 41010037SARM gem5 Developers destReg.elements[i] = 0; 41110037SARM gem5 Developers continue; 41210037SARM gem5 Developers } 41310037SARM gem5 Developers ''' 41410037SARM gem5 Developers eWalkCode += ''' 41510037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 41610037SARM gem5 Developers %(scalarCheck)s 41710037SARM gem5 Developers BigElement srcElem1 = gtoh(srcReg1.elements[i]); 41810037SARM gem5 Developers Element destElem; 41910037SARM gem5 Developers %(readDest)s 42010037SARM gem5 Developers %(op)s 42110037SARM gem5 Developers destReg.elements[i] = htog(destElem); 42210037SARM gem5 Developers } 42310037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode, 42410037SARM gem5 Developers "scalarCheck" : scalarCheck if scalar else "" } 42510037SARM gem5 Developers destReg = 0 if not hi else 2 42610037SARM gem5 Developers for reg in range(2): 42710037SARM gem5 Developers eWalkCode += ''' 42810037SARM gem5 Developers AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]); 42910037SARM gem5 Developers ''' % { "reg" : reg, "destReg": destReg } 43010037SARM gem5 Developers destReg += 1 43110037SARM gem5 Developers if not hi: 43210037SARM gem5 Developers for reg in range(2, 4): # zero upper half 43310037SARM gem5 Developers eWalkCode += ''' 43410037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 43510037SARM gem5 Developers ''' % { "reg" : reg } 43610037SARM gem5 Developers iop = InstObjParams(name, Name, 43710037SARM gem5 Developers "DataX1RegImmOp" if hasImm else "DataX1RegOp", 43810037SARM gem5 Developers { "code": eWalkCode, 43910037SARM gem5 Developers "r_count": 2, 44010037SARM gem5 Developers "op_class": opClass }, []) 44110037SARM gem5 Developers if hasImm: 44210037SARM gem5 Developers header_output += NeonX1RegImmOpDeclare.subst(iop) 44310037SARM gem5 Developers else: 44410037SARM gem5 Developers header_output += NeonX1RegOpDeclare.subst(iop) 44510037SARM gem5 Developers exec_output += NeonXUnequalRegOpExecute.subst(iop) 44610037SARM gem5 Developers for type in types: 44710037SARM gem5 Developers substDict = { "targs" : type, 44810037SARM gem5 Developers "class_name" : Name } 44910037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 45010037SARM gem5 Developers 45110037SARM gem5 Developers def threeRegScrambleInstX(name, Name, opClass, types, rCount, op): 45210037SARM gem5 Developers global header_output, exec_output 45310037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 45410037SARM gem5 Developers RegVect srcReg1, srcReg2, destReg; 45510037SARM gem5 Developers ''' 45610037SARM gem5 Developers for reg in range(rCount): 45710037SARM gem5 Developers eWalkCode += ''' 45810037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 45910037SARM gem5 Developers srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw); 46010037SARM gem5 Developers ''' % { "reg" : reg } 46110037SARM gem5 Developers eWalkCode += op 46210037SARM gem5 Developers for reg in range(rCount): 46310037SARM gem5 Developers eWalkCode += ''' 46410037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 46510037SARM gem5 Developers ''' % { "reg" : reg } 46610037SARM gem5 Developers if rCount < 4: 46710037SARM gem5 Developers for reg in range(rCount, 4): 46810037SARM gem5 Developers eWalkCode += ''' 46910037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 47010037SARM gem5 Developers ''' % { "reg" : reg } 47110037SARM gem5 Developers iop = InstObjParams(name, Name, 47210037SARM gem5 Developers "DataX2RegOp", 47310037SARM gem5 Developers { "code": eWalkCode, 47410037SARM gem5 Developers "r_count": rCount, 47510037SARM gem5 Developers "op_class": opClass }, []) 47610037SARM gem5 Developers header_output += NeonX2RegOpDeclare.subst(iop) 47710037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 47810037SARM gem5 Developers for type in types: 47910037SARM gem5 Developers substDict = { "targs" : type, 48010037SARM gem5 Developers "class_name" : Name } 48110037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 48210037SARM gem5 Developers 48310037SARM gem5 Developers def insFromVecElemInstX(name, Name, opClass, types, rCount): 48410037SARM gem5 Developers global header_output, exec_output 48510037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 48610037SARM gem5 Developers FullRegVect srcReg1; 48710037SARM gem5 Developers RegVect destReg; 48810037SARM gem5 Developers ''' 48910037SARM gem5 Developers for reg in range(4): 49010037SARM gem5 Developers eWalkCode += ''' 49110037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 49210037SARM gem5 Developers ''' % { "reg" : reg } 49310037SARM gem5 Developers for reg in range(rCount): 49410037SARM gem5 Developers eWalkCode += ''' 49510037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 49610037SARM gem5 Developers ''' % { "reg" : reg } 49710037SARM gem5 Developers eWalkCode += ''' 49810037SARM gem5 Developers Element srcElem1 = gtoh(srcReg1.elements[imm2]); 49910037SARM gem5 Developers Element destElem = srcElem1; 50010037SARM gem5 Developers destReg.elements[imm1] = htog(destElem); 50110037SARM gem5 Developers ''' 50210037SARM gem5 Developers for reg in range(rCount): 50310037SARM gem5 Developers eWalkCode += ''' 50410037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 50510037SARM gem5 Developers ''' % { "reg" : reg } 50610037SARM gem5 Developers iop = InstObjParams(name, Name, 50710037SARM gem5 Developers "DataX1Reg2ImmOp", 50810037SARM gem5 Developers { "code": eWalkCode, 50910037SARM gem5 Developers "r_count": rCount, 51010037SARM gem5 Developers "op_class": opClass }, []) 51110037SARM gem5 Developers header_output += NeonX1Reg2ImmOpDeclare.subst(iop) 51210037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 51310037SARM gem5 Developers for type in types: 51410037SARM gem5 Developers substDict = { "targs" : type, 51510037SARM gem5 Developers "class_name" : Name } 51610037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 51710037SARM gem5 Developers 51810037SARM gem5 Developers def twoRegPairwiseScInstX(name, Name, opClass, types, rCount, op): 51910037SARM gem5 Developers global header_output, exec_output 52010037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 52110037SARM gem5 Developers RegVect srcReg1, destReg; 52210037SARM gem5 Developers ''' 52310037SARM gem5 Developers for reg in range(rCount): 52410037SARM gem5 Developers eWalkCode += ''' 52510037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 52610037SARM gem5 Developers ''' % { "reg" : reg } 52710037SARM gem5 Developers eWalkCode += ''' 52810037SARM gem5 Developers Element srcElem1 = gtoh(srcReg1.elements[0]); 52910037SARM gem5 Developers Element srcElem2 = gtoh(srcReg1.elements[1]); 53010037SARM gem5 Developers Element destElem; 53110037SARM gem5 Developers %(op)s 53210037SARM gem5 Developers destReg.elements[0] = htog(destElem); 53310037SARM gem5 Developers ''' % { "op" : op } 53410037SARM gem5 Developers destCnt = rCount / 2 53510037SARM gem5 Developers for reg in range(destCnt): 53610037SARM gem5 Developers eWalkCode += ''' 53710037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 53810037SARM gem5 Developers ''' % { "reg" : reg } 53910037SARM gem5 Developers for reg in range(destCnt, 4): # zero upper half 54010037SARM gem5 Developers eWalkCode += ''' 54110037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 54210037SARM gem5 Developers ''' % { "reg" : reg } 54310037SARM gem5 Developers iop = InstObjParams(name, Name, 54410037SARM gem5 Developers "DataX1RegOp", 54510037SARM gem5 Developers { "code": eWalkCode, 54610037SARM gem5 Developers "r_count": rCount, 54710037SARM gem5 Developers "op_class": opClass }, []) 54810037SARM gem5 Developers header_output += NeonX1RegOpDeclare.subst(iop) 54910037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 55010037SARM gem5 Developers for type in types: 55110037SARM gem5 Developers substDict = { "targs" : type, 55210037SARM gem5 Developers "class_name" : Name } 55310037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 55410037SARM gem5 Developers 55510037SARM gem5 Developers def twoRegAcrossInstX(name, Name, opClass, types, rCount, op, 55610037SARM gem5 Developers doubleDest=False, long=False): 55710037SARM gem5 Developers global header_output, exec_output 55810037SARM gem5 Developers destPrefix = "Big" if long else "" 55910037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 56010037SARM gem5 Developers RegVect srcReg1; 56110037SARM gem5 Developers %sRegVect destReg; 56210037SARM gem5 Developers ''' % destPrefix 56310037SARM gem5 Developers for reg in range(rCount): 56410037SARM gem5 Developers eWalkCode += ''' 56510037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 56610037SARM gem5 Developers ''' % { "reg" : reg } 56710037SARM gem5 Developers eWalkCode += ''' 56810037SARM gem5 Developers destReg.regs[0] = 0; 56910037SARM gem5 Developers %(destPrefix)sElement destElem = 0; 57010037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 57110037SARM gem5 Developers Element srcElem1 = gtoh(srcReg1.elements[i]); 57210037SARM gem5 Developers if (i == 0) { 57310037SARM gem5 Developers destElem = srcElem1; 57410037SARM gem5 Developers } else { 57510037SARM gem5 Developers %(op)s 57610037SARM gem5 Developers } 57710037SARM gem5 Developers } 57810037SARM gem5 Developers destReg.elements[0] = htog(destElem); 57910037SARM gem5 Developers ''' % { "op" : op, "destPrefix" : destPrefix } 58010037SARM gem5 Developers destCnt = 2 if doubleDest else 1 58110037SARM gem5 Developers for reg in range(destCnt): 58210037SARM gem5 Developers eWalkCode += ''' 58310037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 58410037SARM gem5 Developers ''' % { "reg" : reg } 58510037SARM gem5 Developers for reg in range(destCnt, 4): # zero upper half 58610037SARM gem5 Developers eWalkCode += ''' 58710037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 58810037SARM gem5 Developers ''' % { "reg" : reg } 58910037SARM gem5 Developers iop = InstObjParams(name, Name, 59010037SARM gem5 Developers "DataX1RegOp", 59110037SARM gem5 Developers { "code": eWalkCode, 59210037SARM gem5 Developers "r_count": rCount, 59310037SARM gem5 Developers "op_class": opClass }, []) 59410037SARM gem5 Developers header_output += NeonX1RegOpDeclare.subst(iop) 59510037SARM gem5 Developers if long: 59610037SARM gem5 Developers exec_output += NeonXUnequalRegOpExecute.subst(iop) 59710037SARM gem5 Developers else: 59810037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 59910037SARM gem5 Developers for type in types: 60010037SARM gem5 Developers substDict = { "targs" : type, 60110037SARM gem5 Developers "class_name" : Name } 60210037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 60310037SARM gem5 Developers 60410037SARM gem5 Developers def twoRegCondenseInstX(name, Name, opClass, types, rCount, op, 60510037SARM gem5 Developers readDest=False): 60610037SARM gem5 Developers global header_output, exec_output 60710037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 60810037SARM gem5 Developers RegVect srcRegs; 60910037SARM gem5 Developers BigRegVect destReg; 61010037SARM gem5 Developers ''' 61110037SARM gem5 Developers for reg in range(rCount): 61210037SARM gem5 Developers eWalkCode += ''' 61310037SARM gem5 Developers srcRegs.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 61410037SARM gem5 Developers ''' % { "reg" : reg } 61510037SARM gem5 Developers if readDest: 61610037SARM gem5 Developers eWalkCode += ''' 61710037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 61810037SARM gem5 Developers ''' % { "reg" : reg } 61910037SARM gem5 Developers readDestCode = '' 62010037SARM gem5 Developers if readDest: 62110037SARM gem5 Developers readDestCode = 'destElem = gtoh(destReg.elements[i]);' 62210037SARM gem5 Developers eWalkCode += ''' 62310037SARM gem5 Developers for (unsigned i = 0; i < eCount / 2; i++) { 62410037SARM gem5 Developers Element srcElem1 = gtoh(srcRegs.elements[2 * i]); 62510037SARM gem5 Developers Element srcElem2 = gtoh(srcRegs.elements[2 * i + 1]); 62610037SARM gem5 Developers BigElement destElem; 62710037SARM gem5 Developers %(readDest)s 62810037SARM gem5 Developers %(op)s 62910037SARM gem5 Developers destReg.elements[i] = htog(destElem); 63010037SARM gem5 Developers } 63110037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode } 63210037SARM gem5 Developers for reg in range(rCount): 63310037SARM gem5 Developers eWalkCode += ''' 63410037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 63510037SARM gem5 Developers ''' % { "reg" : reg } 63610037SARM gem5 Developers if rCount < 4: # zero upper half 63710037SARM gem5 Developers for reg in range(rCount, 4): 63810037SARM gem5 Developers eWalkCode += ''' 63910037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 64010037SARM gem5 Developers ''' % { "reg" : reg } 64110037SARM gem5 Developers iop = InstObjParams(name, Name, 64210037SARM gem5 Developers "DataX1RegOp", 64310037SARM gem5 Developers { "code": eWalkCode, 64410037SARM gem5 Developers "r_count": rCount, 64510037SARM gem5 Developers "op_class": opClass }, []) 64610037SARM gem5 Developers header_output += NeonX1RegOpDeclare.subst(iop) 64710037SARM gem5 Developers exec_output += NeonXUnequalRegOpExecute.subst(iop) 64810037SARM gem5 Developers for type in types: 64910037SARM gem5 Developers substDict = { "targs" : type, 65010037SARM gem5 Developers "class_name" : Name } 65110037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 65210037SARM gem5 Developers 65310037SARM gem5 Developers def oneRegImmInstX(name, Name, opClass, types, rCount, op, readDest=False): 65410037SARM gem5 Developers global header_output, exec_output 65510037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 65610037SARM gem5 Developers RegVect destReg; 65710037SARM gem5 Developers ''' 65810037SARM gem5 Developers if readDest: 65910037SARM gem5 Developers for reg in range(rCount): 66010037SARM gem5 Developers eWalkCode += ''' 66110037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 66210037SARM gem5 Developers ''' % { "reg" : reg } 66310037SARM gem5 Developers readDestCode = '' 66410037SARM gem5 Developers if readDest: 66510037SARM gem5 Developers readDestCode = 'destElem = gtoh(destReg.elements[i]);' 66610037SARM gem5 Developers eWalkCode += ''' 66710037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 66810037SARM gem5 Developers Element destElem; 66910037SARM gem5 Developers %(readDest)s 67010037SARM gem5 Developers %(op)s 67110037SARM gem5 Developers destReg.elements[i] = htog(destElem); 67210037SARM gem5 Developers } 67310037SARM gem5 Developers ''' % { "op" : op, "readDest" : readDestCode } 67410037SARM gem5 Developers for reg in range(rCount): 67510037SARM gem5 Developers eWalkCode += ''' 67610037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 67710037SARM gem5 Developers ''' % { "reg" : reg } 67810037SARM gem5 Developers if rCount < 4: # zero upper half 67910037SARM gem5 Developers for reg in range(rCount, 4): 68010037SARM gem5 Developers eWalkCode += ''' 68110037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 68210037SARM gem5 Developers ''' % { "reg" : reg } 68310037SARM gem5 Developers iop = InstObjParams(name, Name, 68410037SARM gem5 Developers "DataXImmOnlyOp", 68510037SARM gem5 Developers { "code": eWalkCode, 68610037SARM gem5 Developers "r_count": rCount, 68710037SARM gem5 Developers "op_class": opClass }, []) 68810037SARM gem5 Developers header_output += NeonX1RegImmOnlyOpDeclare.subst(iop) 68910037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 69010037SARM gem5 Developers for type in types: 69110037SARM gem5 Developers substDict = { "targs" : type, 69210037SARM gem5 Developers "class_name" : Name } 69310037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 69410037SARM gem5 Developers 69510037SARM gem5 Developers def dupGprInstX(name, Name, opClass, types, rCount, gprSpec): 69610037SARM gem5 Developers global header_output, exec_output 69710037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 69810037SARM gem5 Developers RegVect destReg; 69910037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 70010037SARM gem5 Developers destReg.elements[i] = htog((Element) %sOp1); 70110037SARM gem5 Developers } 70210037SARM gem5 Developers ''' % gprSpec 70310037SARM gem5 Developers for reg in range(rCount): 70410037SARM gem5 Developers eWalkCode += ''' 70510037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 70610037SARM gem5 Developers ''' % { "reg" : reg } 70710037SARM gem5 Developers if rCount < 4: # zero upper half 70810037SARM gem5 Developers for reg in range(rCount, 4): 70910037SARM gem5 Developers eWalkCode += ''' 71010037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 71110037SARM gem5 Developers ''' % { "reg" : reg } 71210037SARM gem5 Developers iop = InstObjParams(name, Name, 71310037SARM gem5 Developers "DataX1RegOp", 71410037SARM gem5 Developers { "code": eWalkCode, 71510037SARM gem5 Developers "r_count": rCount, 71610037SARM gem5 Developers "op_class": opClass }, []) 71710037SARM gem5 Developers header_output += NeonX1RegOpDeclare.subst(iop) 71810037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 71910037SARM gem5 Developers for type in types: 72010037SARM gem5 Developers substDict = { "targs" : type, 72110037SARM gem5 Developers "class_name" : Name } 72210037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 72310037SARM gem5 Developers 72410037SARM gem5 Developers def extInstX(name, Name, opClass, types, rCount, op): 72510037SARM gem5 Developers global header_output, exec_output 72610037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 72710037SARM gem5 Developers RegVect srcReg1, srcReg2, destReg; 72810037SARM gem5 Developers ''' 72910037SARM gem5 Developers for reg in range(rCount): 73010037SARM gem5 Developers eWalkCode += ''' 73110037SARM gem5 Developers srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 73210037SARM gem5 Developers srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw); 73310037SARM gem5 Developers ''' % { "reg" : reg } 73410037SARM gem5 Developers eWalkCode += op 73510037SARM gem5 Developers for reg in range(rCount): 73610037SARM gem5 Developers eWalkCode += ''' 73710037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 73810037SARM gem5 Developers ''' % { "reg" : reg } 73910037SARM gem5 Developers if rCount < 4: # zero upper half 74010037SARM gem5 Developers for reg in range(rCount, 4): 74110037SARM gem5 Developers eWalkCode += ''' 74210037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 74310037SARM gem5 Developers ''' % { "reg" : reg } 74410037SARM gem5 Developers iop = InstObjParams(name, Name, 74510037SARM gem5 Developers "DataX2RegImmOp", 74610037SARM gem5 Developers { "code": eWalkCode, 74710037SARM gem5 Developers "r_count": rCount, 74810037SARM gem5 Developers "op_class": opClass }, []) 74910037SARM gem5 Developers header_output += NeonX2RegImmOpDeclare.subst(iop) 75010037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 75110037SARM gem5 Developers for type in types: 75210037SARM gem5 Developers substDict = { "targs" : type, 75310037SARM gem5 Developers "class_name" : Name } 75410037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 75510037SARM gem5 Developers 75610037SARM gem5 Developers def insFromGprInstX(name, Name, opClass, types, rCount, gprSpec): 75710037SARM gem5 Developers global header_output, exec_output 75810037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 75910037SARM gem5 Developers RegVect destReg; 76010037SARM gem5 Developers ''' 76110037SARM gem5 Developers for reg in range(rCount): 76210037SARM gem5 Developers eWalkCode += ''' 76310037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 76410037SARM gem5 Developers ''' % { "reg" : reg } 76510037SARM gem5 Developers eWalkCode += ''' 76610037SARM gem5 Developers destReg.elements[imm] = htog((Element) %sOp1); 76710037SARM gem5 Developers ''' % gprSpec 76810037SARM gem5 Developers for reg in range(rCount): 76910037SARM gem5 Developers eWalkCode += ''' 77010037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 77110037SARM gem5 Developers ''' % { "reg" : reg } 77210037SARM gem5 Developers iop = InstObjParams(name, Name, 77310037SARM gem5 Developers "DataX1RegImmOp", 77410037SARM gem5 Developers { "code": eWalkCode, 77510037SARM gem5 Developers "r_count": rCount, 77610037SARM gem5 Developers "op_class": opClass }, []) 77710037SARM gem5 Developers header_output += NeonX1RegImmOpDeclare.subst(iop) 77810037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 77910037SARM gem5 Developers for type in types: 78010037SARM gem5 Developers substDict = { "targs" : type, 78110037SARM gem5 Developers "class_name" : Name } 78210037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 78310037SARM gem5 Developers 78410037SARM gem5 Developers def insToGprInstX(name, Name, opClass, types, rCount, gprSpec, 78510037SARM gem5 Developers signExt=False): 78610037SARM gem5 Developers global header_output, exec_output 78710037SARM gem5 Developers eWalkCode = simd64EnabledCheckCode + ''' 78810037SARM gem5 Developers FullRegVect srcReg; 78910037SARM gem5 Developers ''' 79010037SARM gem5 Developers for reg in range(4): 79110037SARM gem5 Developers eWalkCode += ''' 79210037SARM gem5 Developers srcReg.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw); 79310037SARM gem5 Developers ''' % { "reg" : reg } 79410037SARM gem5 Developers if signExt: 79510037SARM gem5 Developers eWalkCode += ''' 79610037SARM gem5 Developers %sDest = sext<sizeof(Element) * 8>(srcReg.elements[imm]); 79710037SARM gem5 Developers ''' % gprSpec 79810037SARM gem5 Developers else: 79910037SARM gem5 Developers eWalkCode += ''' 80010037SARM gem5 Developers %sDest = srcReg.elements[imm]; 80110037SARM gem5 Developers ''' % gprSpec 80210037SARM gem5 Developers iop = InstObjParams(name, Name, 80310037SARM gem5 Developers "DataX1RegImmOp", 80410037SARM gem5 Developers { "code": eWalkCode, 80510037SARM gem5 Developers "r_count": rCount, 80610037SARM gem5 Developers "op_class": opClass }, []) 80710037SARM gem5 Developers header_output += NeonX1RegImmOpDeclare.subst(iop) 80810037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 80910037SARM gem5 Developers for type in types: 81010037SARM gem5 Developers substDict = { "targs" : type, 81110037SARM gem5 Developers "class_name" : Name } 81210037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 81310037SARM gem5 Developers 81410037SARM gem5 Developers def tbxTblInstX(name, Name, opClass, types, length, isTbl, rCount): 81510037SARM gem5 Developers global header_output, decoder_output, exec_output 81610037SARM gem5 Developers code = simd64EnabledCheckCode + ''' 81710037SARM gem5 Developers union 81810037SARM gem5 Developers { 81910037SARM gem5 Developers uint8_t bytes[64]; 82010037SARM gem5 Developers FloatRegBits regs[16]; 82110037SARM gem5 Developers } table; 82210037SARM gem5 Developers 82310037SARM gem5 Developers union 82410037SARM gem5 Developers { 82510037SARM gem5 Developers uint8_t bytes[%(rCount)d * 4]; 82610037SARM gem5 Developers FloatRegBits regs[%(rCount)d]; 82710037SARM gem5 Developers } destReg, srcReg2; 82810037SARM gem5 Developers 82910037SARM gem5 Developers const unsigned length = %(length)d; 83010037SARM gem5 Developers const bool isTbl = %(isTbl)s; 83110037SARM gem5 Developers ''' % { "rCount" : rCount, "length" : length, "isTbl" : isTbl } 83210037SARM gem5 Developers for reg in range(rCount): 83310037SARM gem5 Developers code += ''' 83410037SARM gem5 Developers srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw); 83510037SARM gem5 Developers destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw); 83610037SARM gem5 Developers ''' % { "reg" : reg } 83710037SARM gem5 Developers for reg in range(16): 83810037SARM gem5 Developers if reg < length * 4: 83910037SARM gem5 Developers code += ''' 84010037SARM gem5 Developers table.regs[%(reg)d] = htog(AA64FpOp1P%(p)dV%(v)dS_uw); 84110037SARM gem5 Developers ''' % { "reg" : reg, "p" : reg % 4, "v" : reg / 4 } 84210037SARM gem5 Developers else: 84310037SARM gem5 Developers code += ''' 84410037SARM gem5 Developers table.regs[%(reg)d] = 0; 84510037SARM gem5 Developers ''' % { "reg" : reg } 84610037SARM gem5 Developers code += ''' 84710037SARM gem5 Developers for (unsigned i = 0; i < sizeof(destReg); i++) { 84810037SARM gem5 Developers uint8_t index = srcReg2.bytes[i]; 84910037SARM gem5 Developers if (index < 16 * length) { 85010037SARM gem5 Developers destReg.bytes[i] = table.bytes[index]; 85110037SARM gem5 Developers } else { 85210037SARM gem5 Developers if (isTbl) 85310037SARM gem5 Developers destReg.bytes[i] = 0; 85410037SARM gem5 Developers // else destReg.bytes[i] unchanged 85510037SARM gem5 Developers } 85610037SARM gem5 Developers } 85710037SARM gem5 Developers ''' 85810037SARM gem5 Developers for reg in range(rCount): 85910037SARM gem5 Developers code += ''' 86010037SARM gem5 Developers AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 86110037SARM gem5 Developers ''' % { "reg" : reg } 86210037SARM gem5 Developers if rCount < 4: # zero upper half 86310037SARM gem5 Developers for reg in range(rCount, 4): 86410037SARM gem5 Developers code += ''' 86510037SARM gem5 Developers AA64FpDestP%(reg)d_uw = 0; 86610037SARM gem5 Developers ''' % { "reg" : reg } 86710037SARM gem5 Developers iop = InstObjParams(name, Name, 86810037SARM gem5 Developers "DataX2RegOp", 86910037SARM gem5 Developers { "code": code, 87010037SARM gem5 Developers "r_count": rCount, 87110037SARM gem5 Developers "op_class": opClass }, []) 87210037SARM gem5 Developers header_output += NeonX2RegOpDeclare.subst(iop) 87310037SARM gem5 Developers exec_output += NeonXEqualRegOpExecute.subst(iop) 87410037SARM gem5 Developers for type in types: 87510037SARM gem5 Developers substDict = { "targs" : type, 87610037SARM gem5 Developers "class_name" : Name } 87710037SARM gem5 Developers exec_output += NeonXExecDeclare.subst(substDict) 87810037SARM gem5 Developers 87910037SARM gem5 Developers # ABS 88010037SARM gem5 Developers absCode = ''' 88110037SARM gem5 Developers if (srcElem1 < 0) { 88210037SARM gem5 Developers destElem = -srcElem1; 88310037SARM gem5 Developers } else { 88410037SARM gem5 Developers destElem = srcElem1; 88510037SARM gem5 Developers } 88610037SARM gem5 Developers ''' 88710037SARM gem5 Developers twoEqualRegInstX("abs", "AbsDX", "SimdAluOp", signedTypes, 2, absCode) 88810037SARM gem5 Developers twoEqualRegInstX("abs", "AbsQX", "SimdAluOp", signedTypes, 4, absCode) 88910037SARM gem5 Developers # ADD 89010037SARM gem5 Developers addCode = "destElem = srcElem1 + srcElem2;" 89110037SARM gem5 Developers threeEqualRegInstX("add", "AddDX", "SimdAddOp", unsignedTypes, 2, addCode) 89210037SARM gem5 Developers threeEqualRegInstX("add", "AddQX", "SimdAddOp", unsignedTypes, 4, addCode) 89310037SARM gem5 Developers # ADDHN, ADDHN2 89410037SARM gem5 Developers addhnCode = ''' 89510037SARM gem5 Developers destElem = ((BigElement)srcElem1 + (BigElement)srcElem2) >> 89610037SARM gem5 Developers (sizeof(Element) * 8); 89710037SARM gem5 Developers ''' 89810037SARM gem5 Developers threeRegNarrowInstX("addhn", "AddhnX", "SimdAddOp", smallUnsignedTypes, 89910037SARM gem5 Developers addhnCode) 90010037SARM gem5 Developers threeRegNarrowInstX("addhn2", "Addhn2X", "SimdAddOp", smallUnsignedTypes, 90110037SARM gem5 Developers addhnCode, hi=True) 90210037SARM gem5 Developers # ADDP (scalar) 90310037SARM gem5 Developers twoRegPairwiseScInstX("addp", "AddpScQX", "SimdAddOp", ("uint64_t",), 4, 90410037SARM gem5 Developers addCode) 90510037SARM gem5 Developers # ADDP (vector) 90610037SARM gem5 Developers threeEqualRegInstX("addp", "AddpDX", "SimdAddOp", smallUnsignedTypes, 2, 90710037SARM gem5 Developers addCode, pairwise=True) 90810037SARM gem5 Developers threeEqualRegInstX("addp", "AddpQX", "SimdAddOp", unsignedTypes, 4, 90910037SARM gem5 Developers addCode, pairwise=True) 91010037SARM gem5 Developers # ADDV 91110037SARM gem5 Developers # Note: SimdAddOp can be a bit optimistic here 91210037SARM gem5 Developers addAcrossCode = "destElem += srcElem1;" 91310037SARM gem5 Developers twoRegAcrossInstX("addv", "AddvDX", "SimdAddOp", ("uint8_t", "uint16_t"), 91410037SARM gem5 Developers 2, addAcrossCode) 91510037SARM gem5 Developers twoRegAcrossInstX("addv", "AddvQX", "SimdAddOp", smallUnsignedTypes, 4, 91610037SARM gem5 Developers addAcrossCode) 91710037SARM gem5 Developers # AND 91810037SARM gem5 Developers andCode = "destElem = srcElem1 & srcElem2;" 91910037SARM gem5 Developers threeEqualRegInstX("and", "AndDX", "SimdAluOp", ("uint64_t",), 2, andCode) 92010037SARM gem5 Developers threeEqualRegInstX("and", "AndQX", "SimdAluOp", ("uint64_t",), 4, andCode) 92110037SARM gem5 Developers # BIC (immediate) 92210037SARM gem5 Developers bicImmCode = "destElem &= ~imm;" 92310037SARM gem5 Developers oneRegImmInstX("bic", "BicImmDX", "SimdAluOp", ("uint64_t",), 2, 92410037SARM gem5 Developers bicImmCode, True) 92510037SARM gem5 Developers oneRegImmInstX("bic", "BicImmQX", "SimdAluOp", ("uint64_t",), 4, 92610037SARM gem5 Developers bicImmCode, True) 92710037SARM gem5 Developers # BIC (register) 92810037SARM gem5 Developers bicCode = "destElem = srcElem1 & ~srcElem2;" 92910037SARM gem5 Developers threeEqualRegInstX("bic", "BicDX", "SimdAluOp", ("uint64_t",), 2, bicCode) 93010037SARM gem5 Developers threeEqualRegInstX("bic", "BicQX", "SimdAluOp", ("uint64_t",), 4, bicCode) 93110037SARM gem5 Developers # BIF 93210037SARM gem5 Developers bifCode = "destElem = (destElem & srcElem2) | (srcElem1 & ~srcElem2);" 93310037SARM gem5 Developers threeEqualRegInstX("bif", "BifDX", "SimdAluOp", ("uint64_t",), 2, bifCode, 93410037SARM gem5 Developers True) 93510037SARM gem5 Developers threeEqualRegInstX("bif", "BifQX", "SimdAluOp", ("uint64_t",), 4, bifCode, 93610037SARM gem5 Developers True) 93710037SARM gem5 Developers # BIT 93810037SARM gem5 Developers bitCode = "destElem = (srcElem1 & srcElem2) | (destElem & ~srcElem2);" 93910037SARM gem5 Developers threeEqualRegInstX("bit", "BitDX", "SimdAluOp", ("uint64_t",), 2, bitCode, 94010037SARM gem5 Developers True) 94110037SARM gem5 Developers threeEqualRegInstX("bit", "BitQX", "SimdAluOp", ("uint64_t",), 4, bitCode, 94210037SARM gem5 Developers True) 94310037SARM gem5 Developers # BSL 94410037SARM gem5 Developers bslCode = "destElem = (srcElem1 & destElem) | (srcElem2 & ~destElem);" 94510037SARM gem5 Developers threeEqualRegInstX("bsl", "BslDX", "SimdAluOp", ("uint64_t",), 2, bslCode, 94610037SARM gem5 Developers True) 94710037SARM gem5 Developers threeEqualRegInstX("bsl", "BslQX", "SimdAluOp", ("uint64_t",), 4, bslCode, 94810037SARM gem5 Developers True) 94910037SARM gem5 Developers # CLS 95010037SARM gem5 Developers clsCode = ''' 95110037SARM gem5 Developers unsigned count = 0; 95210037SARM gem5 Developers if (srcElem1 < 0) { 95310037SARM gem5 Developers srcElem1 <<= 1; 95410037SARM gem5 Developers while (srcElem1 < 0 && count < sizeof(Element) * 8 - 1) { 95510037SARM gem5 Developers count++; 95610037SARM gem5 Developers srcElem1 <<= 1; 95710037SARM gem5 Developers } 95810037SARM gem5 Developers } else { 95910037SARM gem5 Developers srcElem1 <<= 1; 96010037SARM gem5 Developers while (srcElem1 >= 0 && count < sizeof(Element) * 8 - 1) { 96110037SARM gem5 Developers count++; 96210037SARM gem5 Developers srcElem1 <<= 1; 96310037SARM gem5 Developers } 96410037SARM gem5 Developers } 96510037SARM gem5 Developers destElem = count; 96610037SARM gem5 Developers ''' 96710037SARM gem5 Developers twoEqualRegInstX("cls", "ClsDX", "SimdAluOp", smallSignedTypes, 2, clsCode) 96810037SARM gem5 Developers twoEqualRegInstX("cls", "ClsQX", "SimdAluOp", smallSignedTypes, 4, clsCode) 96910037SARM gem5 Developers # CLZ 97010037SARM gem5 Developers clzCode = ''' 97110037SARM gem5 Developers unsigned count = 0; 97210037SARM gem5 Developers while (srcElem1 >= 0 && count < sizeof(Element) * 8) { 97310037SARM gem5 Developers count++; 97410037SARM gem5 Developers srcElem1 <<= 1; 97510037SARM gem5 Developers } 97610037SARM gem5 Developers destElem = count; 97710037SARM gem5 Developers ''' 97810037SARM gem5 Developers twoEqualRegInstX("clz", "ClzDX", "SimdAluOp", smallSignedTypes, 2, clzCode) 97910037SARM gem5 Developers twoEqualRegInstX("clz", "ClzQX", "SimdAluOp", smallSignedTypes, 4, clzCode) 98010037SARM gem5 Developers # CMEQ (register) 98110037SARM gem5 Developers cmeqCode = "destElem = (srcElem1 == srcElem2) ? (Element)(-1) : 0;" 98210037SARM gem5 Developers threeEqualRegInstX("cmeq", "CmeqDX", "SimdCmpOp", unsignedTypes, 2, 98310037SARM gem5 Developers cmeqCode) 98410037SARM gem5 Developers threeEqualRegInstX("cmeq", "CmeqQX", "SimdCmpOp", unsignedTypes, 4, 98510037SARM gem5 Developers cmeqCode) 98610037SARM gem5 Developers # CMEQ (zero) 98710037SARM gem5 Developers cmeqZeroCode = "destElem = (srcElem1 == 0) ? (Element)(-1) : 0;" 98810037SARM gem5 Developers twoEqualRegInstX("cmeq", "CmeqZeroDX", "SimdCmpOp", signedTypes, 2, 98910037SARM gem5 Developers cmeqZeroCode) 99010037SARM gem5 Developers twoEqualRegInstX("cmeq", "CmeqZeroQX", "SimdCmpOp", signedTypes, 4, 99110037SARM gem5 Developers cmeqZeroCode) 99210037SARM gem5 Developers # CMGE (register) 99310037SARM gem5 Developers cmgeCode = "destElem = (srcElem1 >= srcElem2) ? (Element)(-1) : 0;" 99410037SARM gem5 Developers threeEqualRegInstX("cmge", "CmgeDX", "SimdCmpOp", signedTypes, 2, cmgeCode) 99510037SARM gem5 Developers threeEqualRegInstX("cmge", "CmgeQX", "SimdCmpOp", signedTypes, 4, cmgeCode) 99610037SARM gem5 Developers # CMGE (zero) 99710037SARM gem5 Developers cmgeZeroCode = "destElem = (srcElem1 >= 0) ? (Element)(-1) : 0;" 99810037SARM gem5 Developers twoEqualRegInstX("cmge", "CmgeZeroDX", "SimdCmpOp", signedTypes, 2, 99910037SARM gem5 Developers cmgeZeroCode) 100010037SARM gem5 Developers twoEqualRegInstX("cmge", "CmgeZeroQX", "SimdCmpOp", signedTypes, 4, 100110037SARM gem5 Developers cmgeZeroCode) 100210037SARM gem5 Developers # CMGT (register) 100310037SARM gem5 Developers cmgtCode = "destElem = (srcElem1 > srcElem2) ? (Element)(-1) : 0;" 100410037SARM gem5 Developers threeEqualRegInstX("cmgt", "CmgtDX", "SimdCmpOp", signedTypes, 2, cmgtCode) 100510037SARM gem5 Developers threeEqualRegInstX("cmgt", "CmgtQX", "SimdCmpOp", signedTypes, 4, cmgtCode) 100610037SARM gem5 Developers # CMGT (zero) 100710037SARM gem5 Developers cmgtZeroCode = "destElem = (srcElem1 > 0) ? (Element)(-1) : 0;" 100810037SARM gem5 Developers twoEqualRegInstX("cmgt", "CmgtZeroDX", "SimdCmpOp", signedTypes, 2, 100910037SARM gem5 Developers cmgtZeroCode) 101010037SARM gem5 Developers twoEqualRegInstX("cmgt", "CmgtZeroQX", "SimdCmpOp", signedTypes, 4, 101110037SARM gem5 Developers cmgtZeroCode) 101210037SARM gem5 Developers # CMHI (register) 101310037SARM gem5 Developers threeEqualRegInstX("cmhi", "CmhiDX", "SimdCmpOp", unsignedTypes, 2, 101410037SARM gem5 Developers cmgtCode) 101510037SARM gem5 Developers threeEqualRegInstX("cmhi", "CmhiQX", "SimdCmpOp", unsignedTypes, 4, 101610037SARM gem5 Developers cmgtCode) 101710037SARM gem5 Developers # CMHS (register) 101810037SARM gem5 Developers threeEqualRegInstX("cmhs", "CmhsDX", "SimdCmpOp", unsignedTypes, 2, 101910037SARM gem5 Developers cmgeCode) 102010037SARM gem5 Developers threeEqualRegInstX("cmhs", "CmhsQX", "SimdCmpOp", unsignedTypes, 4, 102110037SARM gem5 Developers cmgeCode) 102210037SARM gem5 Developers # CMLE (zero) 102310037SARM gem5 Developers cmleZeroCode = "destElem = (srcElem1 <= 0) ? (Element)(-1) : 0;" 102410037SARM gem5 Developers twoEqualRegInstX("cmle", "CmleZeroDX", "SimdCmpOp", signedTypes, 2, 102510037SARM gem5 Developers cmleZeroCode) 102610037SARM gem5 Developers twoEqualRegInstX("cmle", "CmleZeroQX", "SimdCmpOp", signedTypes, 4, 102710037SARM gem5 Developers cmleZeroCode) 102810037SARM gem5 Developers # CMLT (zero) 102910037SARM gem5 Developers cmltZeroCode = "destElem = (srcElem1 < 0) ? (Element)(-1) : 0;" 103010037SARM gem5 Developers twoEqualRegInstX("cmlt", "CmltZeroDX", "SimdCmpOp", signedTypes, 2, 103110037SARM gem5 Developers cmltZeroCode) 103210037SARM gem5 Developers twoEqualRegInstX("cmlt", "CmltZeroQX", "SimdCmpOp", signedTypes, 4, 103310037SARM gem5 Developers cmltZeroCode) 103410037SARM gem5 Developers # CMTST (register) 103510037SARM gem5 Developers tstCode = "destElem = (srcElem1 & srcElem2) ? (Element)(-1) : 0;" 103610037SARM gem5 Developers threeEqualRegInstX("cmtst", "CmtstDX", "SimdAluOp", unsignedTypes, 2, 103710037SARM gem5 Developers tstCode) 103810037SARM gem5 Developers threeEqualRegInstX("cmtst", "CmtstQX", "SimdAluOp", unsignedTypes, 4, 103910037SARM gem5 Developers tstCode) 104010037SARM gem5 Developers # CNT 104110037SARM gem5 Developers cntCode = ''' 104210037SARM gem5 Developers unsigned count = 0; 104310037SARM gem5 Developers while (srcElem1 && count < sizeof(Element) * 8) { 104410037SARM gem5 Developers count += srcElem1 & 0x1; 104510037SARM gem5 Developers srcElem1 >>= 1; 104610037SARM gem5 Developers } 104710037SARM gem5 Developers destElem = count; 104810037SARM gem5 Developers ''' 104910037SARM gem5 Developers twoEqualRegInstX("cnt", "CntDX", "SimdAluOp", ("uint8_t",), 2, cntCode) 105010037SARM gem5 Developers twoEqualRegInstX("cnt", "CntQX", "SimdAluOp", ("uint8_t",), 4, cntCode) 105110037SARM gem5 Developers # DUP (element) 105210037SARM gem5 Developers dupCode = "destElem = srcElem1;" 105310037SARM gem5 Developers twoEqualRegInstX("dup", "DupElemDX", "SimdMiscOp", smallUnsignedTypes, 2, 105410037SARM gem5 Developers dupCode, isDup=True, byElem=True) 105510037SARM gem5 Developers twoEqualRegInstX("dup", "DupElemQX", "SimdMiscOp", unsignedTypes, 4, 105610037SARM gem5 Developers dupCode, isDup=True, byElem=True) 105710037SARM gem5 Developers twoEqualRegInstX("dup", "DupElemScX", "SimdMiscOp", unsignedTypes, 4, 105810037SARM gem5 Developers dupCode, isDup=True, byElem=True, scalar=True) 105910037SARM gem5 Developers # DUP (general register) 106010037SARM gem5 Developers dupGprInstX("dup", "DupGprWDX", "SimdMiscOp", smallUnsignedTypes, 2, 'W') 106110037SARM gem5 Developers dupGprInstX("dup", "DupGprWQX", "SimdMiscOp", smallUnsignedTypes, 4, 'W') 106210037SARM gem5 Developers dupGprInstX("dup", "DupGprXQX", "SimdMiscOp", ("uint64_t",), 4, 'X') 106310037SARM gem5 Developers # EOR 106410037SARM gem5 Developers eorCode = "destElem = srcElem1 ^ srcElem2;" 106510037SARM gem5 Developers threeEqualRegInstX("eor", "EorDX", "SimdAluOp", ("uint64_t",), 2, eorCode) 106610037SARM gem5 Developers threeEqualRegInstX("eor", "EorQX", "SimdAluOp", ("uint64_t",), 4, eorCode) 106710037SARM gem5 Developers # EXT 106810037SARM gem5 Developers extCode = ''' 106910037SARM gem5 Developers for (unsigned i = 0; i < eCount; i++) { 107010037SARM gem5 Developers unsigned index = i + imm; 107110037SARM gem5 Developers if (index < eCount) { 107210037SARM gem5 Developers destReg.elements[i] = srcReg1.elements[index]; 107310037SARM gem5 Developers } else { 107410037SARM gem5 Developers index -= eCount; 107510037SARM gem5 Developers if (index >= eCount) { 107610474Sandreas.hansson@arm.com fault = std::make_shared<UndefinedInstruction>( 107710474Sandreas.hansson@arm.com machInst, false, mnemonic); 107810037SARM gem5 Developers } else { 107910037SARM gem5 Developers destReg.elements[i] = srcReg2.elements[index]; 108010037SARM gem5 Developers } 108110037SARM gem5 Developers } 108210037SARM gem5 Developers } 108310037SARM gem5 Developers ''' 108410037SARM gem5 Developers extInstX("Ext", "ExtDX", "SimdMiscOp", ("uint8_t",), 2, extCode) 108510037SARM gem5 Developers extInstX("Ext", "ExtQX", "SimdMiscOp", ("uint8_t",), 4, extCode) 108610037SARM gem5 Developers # FABD 108710037SARM gem5 Developers fpOp = ''' 108810037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 108910037SARM gem5 Developers destElem = %s; 109010037SARM gem5 Developers FpscrExc = fpscr; 109110037SARM gem5 Developers ''' 109210037SARM gem5 Developers fabdCode = fpOp % "fplibAbs<Element>(fplibSub(srcElem1, srcElem2, fpscr))" 109310037SARM gem5 Developers threeEqualRegInstX("fabd", "FabdDX", "SimdFloatAddOp", smallFloatTypes, 2, 109410037SARM gem5 Developers fabdCode) 109510037SARM gem5 Developers threeEqualRegInstX("fabd", "FabdQX", "SimdFloatAddOp", floatTypes, 4, 109610037SARM gem5 Developers fabdCode) 109710037SARM gem5 Developers threeEqualRegInstX("fabd", "FabdScX", "SimdFloatAddOp", floatTypes, 4, 109810037SARM gem5 Developers fabdCode, scalar=True) 109910037SARM gem5 Developers # FABS 110010037SARM gem5 Developers fabsCode = fpOp % "fplibAbs<Element>(srcElem1)" 110110037SARM gem5 Developers twoEqualRegInstX("Abs", "FabsDX", "SimdFloatAluOp", smallFloatTypes, 2, 110210037SARM gem5 Developers fabsCode) 110310037SARM gem5 Developers twoEqualRegInstX("Abs", "FabsQX", "SimdFloatAluOp", floatTypes, 4, 110410037SARM gem5 Developers fabsCode) 110510037SARM gem5 Developers # FACGE 110610037SARM gem5 Developers fpCmpAbsOp = fpOp % ("fplibCompare%s<Element>(fplibAbs<Element>(srcElem1)," 110710037SARM gem5 Developers " fplibAbs<Element>(srcElem2), fpscr) ? -1 : 0") 110810037SARM gem5 Developers facgeCode = fpCmpAbsOp % "GE" 110910037SARM gem5 Developers threeEqualRegInstX("facge", "FacgeDX", "SimdFloatCmpOp", smallFloatTypes, 111010037SARM gem5 Developers 2, facgeCode) 111110037SARM gem5 Developers threeEqualRegInstX("facge", "FacgeQX", "SimdFloatCmpOp", floatTypes, 4, 111210037SARM gem5 Developers facgeCode) 111310037SARM gem5 Developers threeEqualRegInstX("facge", "FacgeScX", "SimdFloatCmpOp", floatTypes, 4, 111410037SARM gem5 Developers facgeCode, scalar=True) 111510037SARM gem5 Developers # FACGT 111610037SARM gem5 Developers facgtCode = fpCmpAbsOp % "GT" 111710037SARM gem5 Developers threeEqualRegInstX("facgt", "FacgtDX", "SimdFloatCmpOp", smallFloatTypes, 111810037SARM gem5 Developers 2, facgtCode) 111910037SARM gem5 Developers threeEqualRegInstX("facgt", "FacgtQX", "SimdFloatCmpOp", floatTypes, 4, 112010037SARM gem5 Developers facgtCode) 112110037SARM gem5 Developers threeEqualRegInstX("facgt", "FacgtScX", "SimdFloatCmpOp", floatTypes, 4, 112210037SARM gem5 Developers facgtCode, scalar=True) 112310037SARM gem5 Developers # FADD 112410037SARM gem5 Developers fpBinOp = fpOp % "fplib%s<Element>(srcElem1, srcElem2, fpscr)" 112510037SARM gem5 Developers faddCode = fpBinOp % "Add" 112610037SARM gem5 Developers threeEqualRegInstX("fadd", "FaddDX", "SimdFloatAddOp", smallFloatTypes, 2, 112710037SARM gem5 Developers faddCode) 112810037SARM gem5 Developers threeEqualRegInstX("fadd", "FaddQX", "SimdFloatAddOp", floatTypes, 4, 112910037SARM gem5 Developers faddCode) 113010037SARM gem5 Developers # FADDP (scalar) 113110037SARM gem5 Developers twoRegPairwiseScInstX("faddp", "FaddpScDX", "SimdFloatAddOp", 113210037SARM gem5 Developers ("uint32_t",), 2, faddCode) 113310037SARM gem5 Developers twoRegPairwiseScInstX("faddp", "FaddpScQX", "SimdFloatAddOp", 113410037SARM gem5 Developers ("uint64_t",), 4, faddCode) 113510037SARM gem5 Developers # FADDP (vector) 113610037SARM gem5 Developers threeEqualRegInstX("faddp", "FaddpDX", "SimdFloatAddOp", smallFloatTypes, 113710037SARM gem5 Developers 2, faddCode, pairwise=True) 113810037SARM gem5 Developers threeEqualRegInstX("faddp", "FaddpQX", "SimdFloatAddOp", floatTypes, 4, 113910037SARM gem5 Developers faddCode, pairwise=True) 114010037SARM gem5 Developers # FCMEQ (register) 114110037SARM gem5 Developers fpCmpOp = fpOp % ("fplibCompare%s<Element>(srcElem1, srcElem2, fpscr) ?" 114210037SARM gem5 Developers " -1 : 0") 114310037SARM gem5 Developers fcmeqCode = fpCmpOp % "EQ" 114410037SARM gem5 Developers threeEqualRegInstX("fcmeq", "FcmeqDX", "SimdFloatCmpOp", smallFloatTypes, 114510037SARM gem5 Developers 2, fcmeqCode) 114610037SARM gem5 Developers threeEqualRegInstX("fcmeq", "FcmeqQX", "SimdFloatCmpOp", floatTypes, 4, 114710037SARM gem5 Developers fcmeqCode) 114810037SARM gem5 Developers threeEqualRegInstX("fcmeq", "FcmeqScX", "SimdFloatCmpOp", floatTypes, 4, 114910037SARM gem5 Developers fcmeqCode, scalar=True) 115010037SARM gem5 Developers # FCMEQ (zero) 115110037SARM gem5 Developers fpCmpZeroOp = fpOp % "fplibCompare%s<Element>(srcElem1, 0, fpscr) ? -1 : 0" 115210037SARM gem5 Developers fcmeqZeroCode = fpCmpZeroOp % "EQ" 115310037SARM gem5 Developers twoEqualRegInstX("fcmeq", "FcmeqZeroDX", "SimdFloatCmpOp", smallFloatTypes, 115410037SARM gem5 Developers 2, fcmeqZeroCode) 115510037SARM gem5 Developers twoEqualRegInstX("fcmeq", "FcmeqZeroQX", "SimdFloatCmpOp", floatTypes, 4, 115610037SARM gem5 Developers fcmeqZeroCode) 115710037SARM gem5 Developers twoEqualRegInstX("fcmeq", "FcmeqZeroScX", "SimdFloatCmpOp", floatTypes, 4, 115810037SARM gem5 Developers fcmeqZeroCode, scalar=True) 115910037SARM gem5 Developers # FCMGE (register) 116010037SARM gem5 Developers fcmgeCode = fpCmpOp % "GE" 116110037SARM gem5 Developers threeEqualRegInstX("fcmge", "FcmgeDX", "SimdFloatCmpOp", smallFloatTypes, 116210037SARM gem5 Developers 2, fcmgeCode) 116310037SARM gem5 Developers threeEqualRegInstX("fcmge", "FcmgeQX", "SimdFloatCmpOp", floatTypes, 4, 116410037SARM gem5 Developers fcmgeCode) 116510037SARM gem5 Developers threeEqualRegInstX("fcmge", "FcmgeScX", "SimdFloatCmpOp", floatTypes, 4, 116610037SARM gem5 Developers fcmgeCode, scalar=True) 116710037SARM gem5 Developers # FCMGE (zero) 116810037SARM gem5 Developers fcmgeZeroCode = fpCmpZeroOp % "GE" 116910037SARM gem5 Developers twoEqualRegInstX("fcmge", "FcmgeZeroDX", "SimdFloatCmpOp", smallFloatTypes, 117010037SARM gem5 Developers 2, fcmgeZeroCode) 117110037SARM gem5 Developers twoEqualRegInstX("fcmge", "FcmgeZeroQX", "SimdFloatCmpOp", floatTypes, 4, 117210037SARM gem5 Developers fcmgeZeroCode) 117310037SARM gem5 Developers twoEqualRegInstX("fcmge", "FcmgeZeroScX", "SimdFloatCmpOp", floatTypes, 4, 117410037SARM gem5 Developers fcmgeZeroCode, scalar=True) 117510037SARM gem5 Developers # FCMGT (register) 117610037SARM gem5 Developers fcmgtCode = fpCmpOp % "GT" 117710037SARM gem5 Developers threeEqualRegInstX("fcmgt", "FcmgtDX", "SimdFloatCmpOp", smallFloatTypes, 117810037SARM gem5 Developers 2, fcmgtCode) 117910037SARM gem5 Developers threeEqualRegInstX("fcmgt", "FcmgtQX", "SimdFloatCmpOp", floatTypes, 4, 118010037SARM gem5 Developers fcmgtCode) 118110037SARM gem5 Developers threeEqualRegInstX("fcmgt", "FcmgtScX", "SimdFloatCmpOp", floatTypes, 4, 118210037SARM gem5 Developers fcmgtCode, scalar=True) 118310037SARM gem5 Developers # FCMGT (zero) 118410037SARM gem5 Developers fcmgtZeroCode = fpCmpZeroOp % "GT" 118510037SARM gem5 Developers twoEqualRegInstX("fcmgt", "FcmgtZeroDX", "SimdFloatCmpOp", smallFloatTypes, 118610037SARM gem5 Developers 2, fcmgtZeroCode) 118710037SARM gem5 Developers twoEqualRegInstX("fcmgt", "FcmgtZeroQX", "SimdFloatCmpOp", floatTypes, 4, 118810037SARM gem5 Developers fcmgtZeroCode) 118910037SARM gem5 Developers twoEqualRegInstX("fcmgt", "FcmgtZeroScX", "SimdFloatCmpOp", floatTypes, 4, 119010037SARM gem5 Developers fcmgtZeroCode, scalar=True) 119110037SARM gem5 Developers # FCMLE (zero) 119210037SARM gem5 Developers fpCmpRevZeroOp = fpOp % ("fplibCompare%s<Element>(0, srcElem1, fpscr) ?" 119310037SARM gem5 Developers " -1 : 0") 119410037SARM gem5 Developers fcmleZeroCode = fpCmpRevZeroOp % "GE" 119510037SARM gem5 Developers twoEqualRegInstX("fcmle", "FcmleZeroDX", "SimdFloatCmpOp", smallFloatTypes, 119610037SARM gem5 Developers 2, fcmleZeroCode) 119710037SARM gem5 Developers twoEqualRegInstX("fcmle", "FcmleZeroQX", "SimdFloatCmpOp", floatTypes, 4, 119810037SARM gem5 Developers fcmleZeroCode) 119910037SARM gem5 Developers twoEqualRegInstX("fcmle", "FcmleZeroScX", "SimdFloatCmpOp", floatTypes, 4, 120010037SARM gem5 Developers fcmleZeroCode, scalar=True) 120110037SARM gem5 Developers # FCMLT (zero) 120210037SARM gem5 Developers fcmltZeroCode = fpCmpRevZeroOp % "GT" 120310037SARM gem5 Developers twoEqualRegInstX("fcmlt", "FcmltZeroDX", "SimdFloatCmpOp", smallFloatTypes, 120410037SARM gem5 Developers 2, fcmltZeroCode) 120510037SARM gem5 Developers twoEqualRegInstX("fcmlt", "FcmltZeroQX", "SimdFloatCmpOp", floatTypes, 4, 120610037SARM gem5 Developers fcmltZeroCode) 120710037SARM gem5 Developers twoEqualRegInstX("fcmlt", "FcmltZeroScX", "SimdFloatCmpOp", floatTypes, 4, 120810037SARM gem5 Developers fcmltZeroCode, scalar=True) 120910037SARM gem5 Developers # FCVTAS 121010037SARM gem5 Developers fcvtCode = fpOp % ("fplibFPToFixed<Element, Element>(" 121110037SARM gem5 Developers "srcElem1, %s, %s, %s, fpscr)") 121210037SARM gem5 Developers fcvtasCode = fcvtCode % ("0", "false", "FPRounding_TIEAWAY") 121310037SARM gem5 Developers twoEqualRegInstX("fcvtas", "FcvtasDX", "SimdCvtOp", smallFloatTypes, 2, 121410037SARM gem5 Developers fcvtasCode) 121510037SARM gem5 Developers twoEqualRegInstX("fcvtas", "FcvtasQX", "SimdCvtOp", floatTypes, 4, 121610037SARM gem5 Developers fcvtasCode) 121710037SARM gem5 Developers twoEqualRegInstX("fcvtas", "FcvtasScX", "SimdCvtOp", floatTypes, 4, 121810037SARM gem5 Developers fcvtasCode, scalar=True) 121910037SARM gem5 Developers # FCVTAU 122010037SARM gem5 Developers fcvtauCode = fcvtCode % ("0", "true", "FPRounding_TIEAWAY") 122110037SARM gem5 Developers twoEqualRegInstX("fcvtau", "FcvtauDX", "SimdCvtOp", smallFloatTypes, 2, 122210037SARM gem5 Developers fcvtauCode) 122310037SARM gem5 Developers twoEqualRegInstX("fcvtau", "FcvtauQX", "SimdCvtOp", floatTypes, 4, 122410037SARM gem5 Developers fcvtauCode) 122510037SARM gem5 Developers twoEqualRegInstX("fcvtau", "FcvtauScX", "SimdCvtOp", floatTypes, 4, 122610037SARM gem5 Developers fcvtauCode, scalar=True) 122710037SARM gem5 Developers # FCVTL, FCVTL2 122810037SARM gem5 Developers fcvtlCode = fpOp % ("fplibConvert<Element, BigElement>(" 122910037SARM gem5 Developers "srcElem1, FPCRRounding(fpscr), fpscr)") 123010037SARM gem5 Developers twoRegLongInstX("fcvtl", "FcvtlX", "SimdCvtOp", ("uint16_t", "uint32_t"), 123110037SARM gem5 Developers fcvtlCode) 123210037SARM gem5 Developers twoRegLongInstX("fcvtl", "Fcvtl2X", "SimdCvtOp", ("uint16_t", "uint32_t"), 123310037SARM gem5 Developers fcvtlCode, hi=True) 123410037SARM gem5 Developers # FCVTMS 123510037SARM gem5 Developers fcvtmsCode = fcvtCode % ("0", "false", "FPRounding_NEGINF") 123610037SARM gem5 Developers twoEqualRegInstX("fcvtms", "FcvtmsDX", "SimdCvtOp", smallFloatTypes, 2, 123710037SARM gem5 Developers fcvtmsCode) 123810037SARM gem5 Developers twoEqualRegInstX("fcvtms", "FcvtmsQX", "SimdCvtOp", floatTypes, 4, 123910037SARM gem5 Developers fcvtmsCode) 124010037SARM gem5 Developers twoEqualRegInstX("fcvtms", "FcvtmsScX", "SimdCvtOp", floatTypes, 4, 124110037SARM gem5 Developers fcvtmsCode, scalar=True) 124210037SARM gem5 Developers # FCVTMU 124310037SARM gem5 Developers fcvtmuCode = fcvtCode % ("0", "true", "FPRounding_NEGINF") 124410037SARM gem5 Developers twoEqualRegInstX("fcvtmu", "FcvtmuDX", "SimdCvtOp", smallFloatTypes, 2, 124510037SARM gem5 Developers fcvtmuCode) 124610037SARM gem5 Developers twoEqualRegInstX("fcvtmu", "FcvtmuQX", "SimdCvtOp", floatTypes, 4, 124710037SARM gem5 Developers fcvtmuCode) 124810037SARM gem5 Developers twoEqualRegInstX("fcvtmu", "FcvtmuScX", "SimdCvtOp", floatTypes, 4, 124910037SARM gem5 Developers fcvtmuCode, scalar=True) 125010037SARM gem5 Developers # FCVTN, FCVTN2 125110037SARM gem5 Developers fcvtnCode = fpOp % ("fplibConvert<BigElement, Element>(" 125210037SARM gem5 Developers "srcElem1, FPCRRounding(fpscr), fpscr)") 125310037SARM gem5 Developers twoRegNarrowInstX("fcvtn", "FcvtnX", "SimdCvtOp", 125410037SARM gem5 Developers ("uint16_t", "uint32_t"), fcvtnCode) 125510037SARM gem5 Developers twoRegNarrowInstX("fcvtn", "Fcvtn2X", "SimdCvtOp", 125610037SARM gem5 Developers ("uint16_t", "uint32_t"), fcvtnCode, hi=True) 125710037SARM gem5 Developers # FCVTNS 125810037SARM gem5 Developers fcvtnsCode = fcvtCode % ("0", "false", "FPRounding_TIEEVEN") 125910037SARM gem5 Developers twoEqualRegInstX("fcvtns", "FcvtnsDX", "SimdCvtOp", smallFloatTypes, 2, 126010037SARM gem5 Developers fcvtnsCode) 126110037SARM gem5 Developers twoEqualRegInstX("fcvtns", "FcvtnsQX", "SimdCvtOp", floatTypes, 4, 126210037SARM gem5 Developers fcvtnsCode) 126310037SARM gem5 Developers twoEqualRegInstX("fcvtns", "FcvtnsScX", "SimdCvtOp", floatTypes, 4, 126410037SARM gem5 Developers fcvtnsCode, scalar=True) 126510037SARM gem5 Developers # FCVTNU 126610037SARM gem5 Developers fcvtnuCode = fcvtCode % ("0", "true", "FPRounding_TIEEVEN") 126710037SARM gem5 Developers twoEqualRegInstX("fcvtnu", "FcvtnuDX", "SimdCvtOp", smallFloatTypes, 2, 126810037SARM gem5 Developers fcvtnuCode) 126910037SARM gem5 Developers twoEqualRegInstX("fcvtnu", "FcvtnuQX", "SimdCvtOp", floatTypes, 4, 127010037SARM gem5 Developers fcvtnuCode) 127110037SARM gem5 Developers twoEqualRegInstX("fcvtnu", "FcvtnuScX", "SimdCvtOp", floatTypes, 4, 127210037SARM gem5 Developers fcvtnuCode, scalar=True) 127310037SARM gem5 Developers # FCVTPS 127410037SARM gem5 Developers fcvtpsCode = fcvtCode % ("0", "false", "FPRounding_POSINF") 127510037SARM gem5 Developers twoEqualRegInstX("fcvtps", "FcvtpsDX", "SimdCvtOp", smallFloatTypes, 2, 127610037SARM gem5 Developers fcvtpsCode) 127710037SARM gem5 Developers twoEqualRegInstX("fcvtps", "FcvtpsQX", "SimdCvtOp", floatTypes, 4, 127810037SARM gem5 Developers fcvtpsCode) 127910037SARM gem5 Developers twoEqualRegInstX("fcvtps", "FcvtpsScX", "SimdCvtOp", floatTypes, 4, 128010037SARM gem5 Developers fcvtpsCode, scalar=True) 128110037SARM gem5 Developers # FCVTPU 128210037SARM gem5 Developers fcvtpuCode = fcvtCode % ("0", "true", "FPRounding_POSINF") 128310037SARM gem5 Developers twoEqualRegInstX("fcvtpu", "FcvtpuDX", "SimdCvtOp", smallFloatTypes, 2, 128410037SARM gem5 Developers fcvtpuCode) 128510037SARM gem5 Developers twoEqualRegInstX("fcvtpu", "FcvtpuQX", "SimdCvtOp", floatTypes, 4, 128610037SARM gem5 Developers fcvtpuCode) 128710037SARM gem5 Developers twoEqualRegInstX("fcvtpu", "FcvtpuScX", "SimdCvtOp", floatTypes, 4, 128810037SARM gem5 Developers fcvtpuCode, scalar=True) 128910037SARM gem5 Developers # FCVTXN, FCVTXN2 129010037SARM gem5 Developers fcvtxnCode = fpOp % ("fplibConvert<BigElement, Element>(" 129110037SARM gem5 Developers "srcElem1, FPRounding_ODD, fpscr)") 129210037SARM gem5 Developers twoRegNarrowInstX("fcvtxn", "FcvtxnX", "SimdCvtOp", smallFloatTypes, 129310037SARM gem5 Developers fcvtxnCode) 129410037SARM gem5 Developers twoRegNarrowInstX("fcvtxn", "Fcvtxn2X", "SimdCvtOp", smallFloatTypes, 129510037SARM gem5 Developers fcvtxnCode, hi=True) 129610037SARM gem5 Developers twoRegNarrowInstX("fcvtxn", "FcvtxnScX", "SimdCvtOp", smallFloatTypes, 129710037SARM gem5 Developers fcvtxnCode, scalar=True) 129810037SARM gem5 Developers # FCVTZS (fixed-point) 129910037SARM gem5 Developers fcvtzsCode = fcvtCode % ("imm", "false", "FPRounding_ZERO") 130010037SARM gem5 Developers twoEqualRegInstX("fcvtzs", "FcvtzsFixedDX", "SimdCvtOp", smallFloatTypes, 130110037SARM gem5 Developers 2, fcvtzsCode, hasImm=True) 130210037SARM gem5 Developers twoEqualRegInstX("fcvtzs", "FcvtzsFixedQX", "SimdCvtOp", floatTypes, 4, 130310037SARM gem5 Developers fcvtzsCode, hasImm=True) 130410037SARM gem5 Developers twoEqualRegInstX("fcvtzs", "FcvtzsFixedScX", "SimdCvtOp", floatTypes, 4, 130510037SARM gem5 Developers fcvtzsCode, hasImm=True, scalar=True) 130610037SARM gem5 Developers # FCVTZS (integer) 130710037SARM gem5 Developers fcvtzsIntCode = fcvtCode % ("0", "false", "FPRounding_ZERO") 130810037SARM gem5 Developers twoEqualRegInstX("fcvtzs", "FcvtzsIntDX", "SimdCvtOp", smallFloatTypes, 130910037SARM gem5 Developers 2, fcvtzsIntCode) 131010037SARM gem5 Developers twoEqualRegInstX("fcvtzs", "FcvtzsIntQX", "SimdCvtOp", floatTypes, 4, 131110037SARM gem5 Developers fcvtzsIntCode) 131210037SARM gem5 Developers twoEqualRegInstX("fcvtzs", "FcvtzsIntScX", "SimdCvtOp", floatTypes, 4, 131310037SARM gem5 Developers fcvtzsIntCode, scalar=True) 131410037SARM gem5 Developers # FCVTZU (fixed-point) 131510037SARM gem5 Developers fcvtzuCode = fcvtCode % ("imm", "true", "FPRounding_ZERO") 131610037SARM gem5 Developers twoEqualRegInstX("fcvtzu", "FcvtzuFixedDX", "SimdCvtOp", smallFloatTypes, 131710037SARM gem5 Developers 2, fcvtzuCode, hasImm=True) 131810037SARM gem5 Developers twoEqualRegInstX("fcvtzu", "FcvtzuFixedQX", "SimdCvtOp", floatTypes, 4, 131910037SARM gem5 Developers fcvtzuCode, hasImm=True) 132010037SARM gem5 Developers twoEqualRegInstX("fcvtzu", "FcvtzuFixedScX", "SimdCvtOp", floatTypes, 4, 132110037SARM gem5 Developers fcvtzuCode, hasImm=True, scalar=True) 132210037SARM gem5 Developers # FCVTZU (integer) 132310037SARM gem5 Developers fcvtzuIntCode = fcvtCode % ("0", "true", "FPRounding_ZERO") 132410037SARM gem5 Developers twoEqualRegInstX("fcvtzu", "FcvtzuIntDX", "SimdCvtOp", smallFloatTypes, 2, 132510037SARM gem5 Developers fcvtzuIntCode) 132610037SARM gem5 Developers twoEqualRegInstX("fcvtzu", "FcvtzuIntQX", "SimdCvtOp", floatTypes, 4, 132710037SARM gem5 Developers fcvtzuIntCode) 132810037SARM gem5 Developers twoEqualRegInstX("fcvtzu", "FcvtzuIntScX", "SimdCvtOp", floatTypes, 4, 132910037SARM gem5 Developers fcvtzuIntCode, scalar=True) 133010037SARM gem5 Developers # FDIV 133110037SARM gem5 Developers fdivCode = fpBinOp % "Div" 133210037SARM gem5 Developers threeEqualRegInstX("fdiv", "FdivDX", "SimdFloatDivOp", smallFloatTypes, 2, 133310037SARM gem5 Developers fdivCode) 133410037SARM gem5 Developers threeEqualRegInstX("fdiv", "FdivQX", "SimdFloatDivOp", floatTypes, 4, 133510037SARM gem5 Developers fdivCode) 133610037SARM gem5 Developers # FMAX 133710037SARM gem5 Developers fmaxCode = fpBinOp % "Max" 133810037SARM gem5 Developers threeEqualRegInstX("fmax", "FmaxDX", "SimdFloatCmpOp", smallFloatTypes, 2, 133910037SARM gem5 Developers fmaxCode) 134010037SARM gem5 Developers threeEqualRegInstX("fmax", "FmaxQX", "SimdFloatCmpOp", floatTypes, 4, 134110037SARM gem5 Developers fmaxCode) 134210037SARM gem5 Developers # FMAXNM 134310037SARM gem5 Developers fmaxnmCode = fpBinOp % "MaxNum" 134410037SARM gem5 Developers threeEqualRegInstX("fmaxnm", "FmaxnmDX", "SimdFloatCmpOp", smallFloatTypes, 134510037SARM gem5 Developers 2, fmaxnmCode) 134610037SARM gem5 Developers threeEqualRegInstX("fmaxnm", "FmaxnmQX", "SimdFloatCmpOp", floatTypes, 4, 134710037SARM gem5 Developers fmaxnmCode) 134810037SARM gem5 Developers # FMAXNMP (scalar) 134910037SARM gem5 Developers twoRegPairwiseScInstX("fmaxnmp", "FmaxnmpScDX", "SimdFloatCmpOp", 135010037SARM gem5 Developers ("uint32_t",), 2, fmaxnmCode) 135110037SARM gem5 Developers twoRegPairwiseScInstX("fmaxnmp", "FmaxnmpScQX", "SimdFloatCmpOp", 135210037SARM gem5 Developers ("uint64_t",), 4, fmaxnmCode) 135310037SARM gem5 Developers # FMAXNMP (vector) 135410037SARM gem5 Developers threeEqualRegInstX("fmaxnmp", "FmaxnmpDX", "SimdFloatCmpOp", 135510037SARM gem5 Developers smallFloatTypes, 2, fmaxnmCode, pairwise=True) 135610037SARM gem5 Developers threeEqualRegInstX("fmaxnmp", "FmaxnmpQX", "SimdFloatCmpOp", floatTypes, 4, 135710037SARM gem5 Developers fmaxnmCode, pairwise=True) 135810037SARM gem5 Developers # FMAXNMV 135910037SARM gem5 Developers # Note: SimdFloatCmpOp can be a bit optimistic here 136010037SARM gem5 Developers fpAcrossOp = fpOp % "fplib%s<Element>(destElem, srcElem1, fpscr)" 136110037SARM gem5 Developers fmaxnmAcrossCode = fpAcrossOp % "MaxNum" 136210037SARM gem5 Developers twoRegAcrossInstX("fmaxnmv", "FmaxnmvQX", "SimdFloatCmpOp", ("uint32_t",), 136310037SARM gem5 Developers 4, fmaxnmAcrossCode) 136410037SARM gem5 Developers # FMAXP (scalar) 136510037SARM gem5 Developers twoRegPairwiseScInstX("fmaxp", "FmaxpScDX", "SimdFloatCmpOp", 136610037SARM gem5 Developers ("uint32_t",), 2, fmaxCode) 136710037SARM gem5 Developers twoRegPairwiseScInstX("fmaxp", "FmaxpScQX", "SimdFloatCmpOp", 136810037SARM gem5 Developers ("uint64_t",), 4, fmaxCode) 136910037SARM gem5 Developers # FMAXP (vector) 137010037SARM gem5 Developers threeEqualRegInstX("fmaxp", "FmaxpDX", "SimdFloatCmpOp", smallFloatTypes, 137110037SARM gem5 Developers 2, fmaxCode, pairwise=True) 137210037SARM gem5 Developers threeEqualRegInstX("fmaxp", "FmaxpQX", "SimdFloatCmpOp", floatTypes, 4, 137310037SARM gem5 Developers fmaxCode, pairwise=True) 137410037SARM gem5 Developers # FMAXV 137510037SARM gem5 Developers # Note: SimdFloatCmpOp can be a bit optimistic here 137610037SARM gem5 Developers fmaxAcrossCode = fpAcrossOp % "Max" 137710037SARM gem5 Developers twoRegAcrossInstX("fmaxv", "FmaxvQX", "SimdFloatCmpOp", ("uint32_t",), 4, 137810037SARM gem5 Developers fmaxAcrossCode) 137910037SARM gem5 Developers # FMIN 138010037SARM gem5 Developers fminCode = fpBinOp % "Min" 138110037SARM gem5 Developers threeEqualRegInstX("fmin", "FminDX", "SimdFloatCmpOp", smallFloatTypes, 2, 138210037SARM gem5 Developers fminCode) 138310037SARM gem5 Developers threeEqualRegInstX("fmin", "FminQX", "SimdFloatCmpOp", floatTypes, 4, 138410037SARM gem5 Developers fminCode) 138510037SARM gem5 Developers # FMINNM 138610037SARM gem5 Developers fminnmCode = fpBinOp % "MinNum" 138710037SARM gem5 Developers threeEqualRegInstX("fminnm", "FminnmDX", "SimdFloatCmpOp", smallFloatTypes, 138810037SARM gem5 Developers 2, fminnmCode) 138910037SARM gem5 Developers threeEqualRegInstX("fminnm", "FminnmQX", "SimdFloatCmpOp", floatTypes, 4, 139010037SARM gem5 Developers fminnmCode) 139110037SARM gem5 Developers # FMINNMP (scalar) 139210037SARM gem5 Developers twoRegPairwiseScInstX("fminnmp", "FminnmpScDX", "SimdFloatCmpOp", 139310037SARM gem5 Developers ("uint32_t",), 2, fminnmCode) 139410037SARM gem5 Developers twoRegPairwiseScInstX("fminnmp", "FminnmpScQX", "SimdFloatCmpOp", 139510037SARM gem5 Developers ("uint64_t",), 4, fminnmCode) 139610037SARM gem5 Developers # FMINNMP (vector) 139710037SARM gem5 Developers threeEqualRegInstX("fminnmp", "FminnmpDX", "SimdFloatCmpOp", 139810037SARM gem5 Developers smallFloatTypes, 2, fminnmCode, pairwise=True) 139910037SARM gem5 Developers threeEqualRegInstX("fminnmp", "FminnmpQX", "SimdFloatCmpOp", floatTypes, 4, 140010037SARM gem5 Developers fminnmCode, pairwise=True) 140110037SARM gem5 Developers # FMINNMV 140210037SARM gem5 Developers # Note: SimdFloatCmpOp can be a bit optimistic here 140310037SARM gem5 Developers fminnmAcrossCode = fpAcrossOp % "MinNum" 140410037SARM gem5 Developers twoRegAcrossInstX("fminnmv", "FminnmvQX", "SimdFloatCmpOp", ("uint32_t",), 140510037SARM gem5 Developers 4, fminnmAcrossCode) 140610037SARM gem5 Developers # FMINP (scalar) 140710037SARM gem5 Developers twoRegPairwiseScInstX("fminp", "FminpScDX", "SimdFloatCmpOp", 140810037SARM gem5 Developers ("uint32_t",), 2, fminCode) 140910037SARM gem5 Developers twoRegPairwiseScInstX("fminp", "FminpScQX", "SimdFloatCmpOp", 141010037SARM gem5 Developers ("uint64_t",), 4, fminCode) 141110037SARM gem5 Developers # FMINP (vector) 141210037SARM gem5 Developers threeEqualRegInstX("fminp", "FminpDX", "SimdFloatCmpOp", smallFloatTypes, 141310037SARM gem5 Developers 2, fminCode, pairwise=True) 141410037SARM gem5 Developers threeEqualRegInstX("fminp", "FminpQX", "SimdFloatCmpOp", floatTypes, 4, 141510037SARM gem5 Developers fminCode, pairwise=True) 141610037SARM gem5 Developers # FMINV 141710037SARM gem5 Developers # Note: SimdFloatCmpOp can be a bit optimistic here 141810037SARM gem5 Developers fminAcrossCode = fpAcrossOp % "Min" 141910037SARM gem5 Developers twoRegAcrossInstX("fminv", "FminvQX", "SimdFloatCmpOp", ("uint32_t",), 4, 142010037SARM gem5 Developers fminAcrossCode) 142110037SARM gem5 Developers # FMLA (by element) 142210037SARM gem5 Developers fmlaCode = fpOp % ("fplibMulAdd<Element>(" 142310037SARM gem5 Developers "destElem, srcElem1, srcElem2, fpscr)") 142410037SARM gem5 Developers threeEqualRegInstX("fmla", "FmlaElemDX", "SimdFloatMultAccOp", 142510037SARM gem5 Developers smallFloatTypes, 2, fmlaCode, True, byElem=True) 142610037SARM gem5 Developers threeEqualRegInstX("fmla", "FmlaElemQX", "SimdFloatMultAccOp", floatTypes, 142710037SARM gem5 Developers 4, fmlaCode, True, byElem=True) 142810037SARM gem5 Developers threeEqualRegInstX("fmla", "FmlaElemScX", "SimdFloatMultAccOp", floatTypes, 142910037SARM gem5 Developers 4, fmlaCode, True, byElem=True, scalar=True) 143010037SARM gem5 Developers # FMLA (vector) 143110037SARM gem5 Developers threeEqualRegInstX("fmla", "FmlaDX", "SimdFloatMultAccOp", smallFloatTypes, 143210037SARM gem5 Developers 2, fmlaCode, True) 143310037SARM gem5 Developers threeEqualRegInstX("fmla", "FmlaQX", "SimdFloatMultAccOp", floatTypes, 4, 143410037SARM gem5 Developers fmlaCode, True) 143510037SARM gem5 Developers # FMLS (by element) 143610037SARM gem5 Developers fmlsCode = fpOp % ("fplibMulAdd<Element>(destElem," 143710037SARM gem5 Developers " fplibNeg<Element>(srcElem1), srcElem2, fpscr)") 143810037SARM gem5 Developers threeEqualRegInstX("fmls", "FmlsElemDX", "SimdFloatMultAccOp", 143910037SARM gem5 Developers smallFloatTypes, 2, fmlsCode, True, byElem=True) 144010037SARM gem5 Developers threeEqualRegInstX("fmls", "FmlsElemQX", "SimdFloatMultAccOp", floatTypes, 144110037SARM gem5 Developers 4, fmlsCode, True, byElem=True) 144210037SARM gem5 Developers threeEqualRegInstX("fmls", "FmlsElemScX", "SimdFloatMultAccOp", floatTypes, 144310037SARM gem5 Developers 4, fmlsCode, True, byElem=True, scalar=True) 144410037SARM gem5 Developers # FMLS (vector) 144510037SARM gem5 Developers threeEqualRegInstX("fmls", "FmlsDX", "SimdFloatMultAccOp", smallFloatTypes, 144610037SARM gem5 Developers 2, fmlsCode, True) 144710037SARM gem5 Developers threeEqualRegInstX("fmls", "FmlsQX", "SimdFloatMultAccOp", floatTypes, 4, 144810037SARM gem5 Developers fmlsCode, True) 144910037SARM gem5 Developers # FMOV 145010037SARM gem5 Developers fmovCode = 'destElem = imm;' 145110037SARM gem5 Developers oneRegImmInstX("fmov", "FmovDX", "SimdMiscOp", smallFloatTypes, 2, 145210037SARM gem5 Developers fmovCode) 145310037SARM gem5 Developers oneRegImmInstX("fmov", "FmovQX", "SimdMiscOp", floatTypes, 4, fmovCode) 145410037SARM gem5 Developers # FMUL (by element) 145510037SARM gem5 Developers fmulCode = fpBinOp % "Mul" 145610037SARM gem5 Developers threeEqualRegInstX("fmul", "FmulElemDX", "SimdFloatMultOp", 145710037SARM gem5 Developers smallFloatTypes, 2, fmulCode, byElem=True) 145810037SARM gem5 Developers threeEqualRegInstX("fmul", "FmulElemQX", "SimdFloatMultOp", floatTypes, 4, 145910037SARM gem5 Developers fmulCode, byElem=True) 146010037SARM gem5 Developers threeEqualRegInstX("fmul", "FmulElemScX", "SimdFloatMultOp", floatTypes, 4, 146110037SARM gem5 Developers fmulCode, byElem=True, scalar=True) 146210037SARM gem5 Developers # FMUL (vector) 146310037SARM gem5 Developers threeEqualRegInstX("fmul", "FmulDX", "SimdFloatMultOp", smallFloatTypes, 2, 146410037SARM gem5 Developers fmulCode) 146510037SARM gem5 Developers threeEqualRegInstX("fmul", "FmulQX", "SimdFloatMultOp", floatTypes, 4, 146610037SARM gem5 Developers fmulCode) 146710037SARM gem5 Developers # FMULX 146810037SARM gem5 Developers fmulxCode = fpBinOp % "MulX" 146910037SARM gem5 Developers threeEqualRegInstX("fmulx", "FmulxDX", "SimdFloatMultOp", smallFloatTypes, 147010037SARM gem5 Developers 2, fmulxCode) 147110037SARM gem5 Developers threeEqualRegInstX("fmulx", "FmulxQX", "SimdFloatMultOp", floatTypes, 4, 147210037SARM gem5 Developers fmulxCode) 147310037SARM gem5 Developers threeEqualRegInstX("fmulx", "FmulxScX", "SimdFloatMultOp", floatTypes, 4, 147410037SARM gem5 Developers fmulxCode, scalar=True) 147510037SARM gem5 Developers # FMULX (by element) 147610037SARM gem5 Developers threeEqualRegInstX("fmulx", "FmulxElemDX", "SimdFloatMultOp", 147710037SARM gem5 Developers smallFloatTypes, 2, fmulxCode, byElem=True) 147810037SARM gem5 Developers threeEqualRegInstX("fmulx", "FmulxElemQX", "SimdFloatMultOp", floatTypes, 147910037SARM gem5 Developers 4, fmulxCode, byElem=True) 148010037SARM gem5 Developers threeEqualRegInstX("fmulx", "FmulxElemScX", "SimdFloatMultOp", floatTypes, 148110037SARM gem5 Developers 4, fmulxCode, byElem=True, scalar=True) 148210037SARM gem5 Developers # FNEG 148310037SARM gem5 Developers fnegCode = fpOp % "fplibNeg<Element>(srcElem1)" 148410037SARM gem5 Developers twoEqualRegInstX("Neg", "FnegDX", "SimdFloatAluOp", smallFloatTypes, 2, 148510037SARM gem5 Developers fnegCode) 148610037SARM gem5 Developers twoEqualRegInstX("Neg", "FnegQX", "SimdFloatAluOp", floatTypes, 4, 148710037SARM gem5 Developers fnegCode) 148810037SARM gem5 Developers # FRECPE 148910037SARM gem5 Developers frecpeCode = fpOp % "fplibRecipEstimate<Element>(srcElem1, fpscr)" 149010037SARM gem5 Developers twoEqualRegInstX("frecpe", "FrecpeDX", "SimdFloatMultAccOp", 149110037SARM gem5 Developers smallFloatTypes, 2, frecpeCode) 149210037SARM gem5 Developers twoEqualRegInstX("frecpe", "FrecpeQX", "SimdFloatMultAccOp", floatTypes, 4, 149310037SARM gem5 Developers frecpeCode) 149410037SARM gem5 Developers twoEqualRegInstX("frecpe", "FrecpeScX", "SimdFloatMultAccOp", floatTypes, 149510037SARM gem5 Developers 4, frecpeCode, scalar=True) 149610037SARM gem5 Developers # FRECPS 149710037SARM gem5 Developers frecpsCode = fpBinOp % "RecipStepFused" 149810037SARM gem5 Developers threeEqualRegInstX("frecps", "FrecpsDX", "SimdFloatMultAccOp", 149910037SARM gem5 Developers smallFloatTypes, 2, frecpsCode) 150010037SARM gem5 Developers threeEqualRegInstX("frecps", "FrecpsQX", "SimdFloatMultAccOp", floatTypes, 150110037SARM gem5 Developers 4, frecpsCode) 150210037SARM gem5 Developers threeEqualRegInstX("frecps", "FrecpsScX", "SimdFloatMultAccOp", floatTypes, 150310037SARM gem5 Developers 4, frecpsCode, scalar=True) 150410037SARM gem5 Developers # FRECPX 150510037SARM gem5 Developers frecpxCode = fpOp % "fplibRecpX<Element>(srcElem1, fpscr)" 150610037SARM gem5 Developers twoEqualRegInstX("frecpx", "FrecpxX", "SimdFloatMultAccOp", floatTypes, 4, 150710037SARM gem5 Developers frecpxCode, scalar=True) 150810037SARM gem5 Developers # FRINTA 150910037SARM gem5 Developers frintCode = fpOp % "fplibRoundInt<Element>(srcElem1, %s, %s, fpscr)" 151010037SARM gem5 Developers frintaCode = frintCode % ("FPRounding_TIEAWAY", "false") 151110037SARM gem5 Developers twoEqualRegInstX("frinta", "FrintaDX", "SimdCvtOp", smallFloatTypes, 2, 151210037SARM gem5 Developers frintaCode) 151310037SARM gem5 Developers twoEqualRegInstX("frinta", "FrintaQX", "SimdCvtOp", floatTypes, 4, 151410037SARM gem5 Developers frintaCode) 151510037SARM gem5 Developers # FRINTI 151610037SARM gem5 Developers frintiCode = frintCode % ("FPCRRounding(fpscr)", "false") 151710037SARM gem5 Developers twoEqualRegInstX("frinti", "FrintiDX", "SimdCvtOp", smallFloatTypes, 2, 151810037SARM gem5 Developers frintiCode) 151910037SARM gem5 Developers twoEqualRegInstX("frinti", "FrintiQX", "SimdCvtOp", floatTypes, 4, 152010037SARM gem5 Developers frintiCode) 152110037SARM gem5 Developers # FRINTM 152210037SARM gem5 Developers frintmCode = frintCode % ("FPRounding_NEGINF", "false") 152310037SARM gem5 Developers twoEqualRegInstX("frintm", "FrintmDX", "SimdCvtOp", smallFloatTypes, 2, 152410037SARM gem5 Developers frintmCode) 152510037SARM gem5 Developers twoEqualRegInstX("frintm", "FrintmQX", "SimdCvtOp", floatTypes, 4, 152610037SARM gem5 Developers frintmCode) 152710037SARM gem5 Developers # FRINTN 152810037SARM gem5 Developers frintnCode = frintCode % ("FPRounding_TIEEVEN", "false") 152910037SARM gem5 Developers twoEqualRegInstX("frintn", "FrintnDX", "SimdCvtOp", smallFloatTypes, 2, 153010037SARM gem5 Developers frintnCode) 153110037SARM gem5 Developers twoEqualRegInstX("frintn", "FrintnQX", "SimdCvtOp", floatTypes, 4, 153210037SARM gem5 Developers frintnCode) 153310037SARM gem5 Developers # FRINTP 153410037SARM gem5 Developers frintpCode = frintCode % ("FPRounding_POSINF", "false") 153510037SARM gem5 Developers twoEqualRegInstX("frintp", "FrintpDX", "SimdCvtOp", smallFloatTypes, 2, 153610037SARM gem5 Developers frintpCode) 153710037SARM gem5 Developers twoEqualRegInstX("frintp", "FrintpQX", "SimdCvtOp", floatTypes, 4, 153810037SARM gem5 Developers frintpCode) 153910037SARM gem5 Developers # FRINTX 154010037SARM gem5 Developers frintxCode = frintCode % ("FPCRRounding(fpscr)", "true") 154110037SARM gem5 Developers twoEqualRegInstX("frintx", "FrintxDX", "SimdCvtOp", smallFloatTypes, 2, 154210037SARM gem5 Developers frintxCode) 154310037SARM gem5 Developers twoEqualRegInstX("frintx", "FrintxQX", "SimdCvtOp", floatTypes, 4, 154410037SARM gem5 Developers frintxCode) 154510037SARM gem5 Developers # FRINTZ 154610037SARM gem5 Developers frintzCode = frintCode % ("FPRounding_ZERO", "false") 154710037SARM gem5 Developers twoEqualRegInstX("frintz", "FrintzDX", "SimdCvtOp", smallFloatTypes, 2, 154810037SARM gem5 Developers frintzCode) 154910037SARM gem5 Developers twoEqualRegInstX("frintz", "FrintzQX", "SimdCvtOp", floatTypes, 4, 155010037SARM gem5 Developers frintzCode) 155110037SARM gem5 Developers # FRSQRTE 155210037SARM gem5 Developers frsqrteCode = fpOp % "fplibRSqrtEstimate<Element>(srcElem1, fpscr)" 155310037SARM gem5 Developers twoEqualRegInstX("frsqrte", "FrsqrteDX", "SimdFloatSqrtOp", 155410037SARM gem5 Developers smallFloatTypes, 2, frsqrteCode) 155510037SARM gem5 Developers twoEqualRegInstX("frsqrte", "FrsqrteQX", "SimdFloatSqrtOp", floatTypes, 4, 155610037SARM gem5 Developers frsqrteCode) 155710037SARM gem5 Developers twoEqualRegInstX("frsqrte", "FrsqrteScX", "SimdFloatSqrtOp", floatTypes, 4, 155810037SARM gem5 Developers frsqrteCode, scalar=True) 155910037SARM gem5 Developers # FRSQRTS 156010037SARM gem5 Developers frsqrtsCode = fpBinOp % "RSqrtStepFused" 156110037SARM gem5 Developers threeEqualRegInstX("frsqrts", "FrsqrtsDX", "SimdFloatMiscOp", 156210037SARM gem5 Developers smallFloatTypes, 2, frsqrtsCode) 156310037SARM gem5 Developers threeEqualRegInstX("frsqrts", "FrsqrtsQX", "SimdFloatMiscOp", floatTypes, 156410037SARM gem5 Developers 4, frsqrtsCode) 156510037SARM gem5 Developers threeEqualRegInstX("frsqrts", "FrsqrtsScX", "SimdFloatMiscOp", floatTypes, 156610037SARM gem5 Developers 4, frsqrtsCode, scalar=True) 156710037SARM gem5 Developers # FSQRT 156810037SARM gem5 Developers fsqrtCode = fpOp % "fplibSqrt<Element>(srcElem1, fpscr)" 156910037SARM gem5 Developers twoEqualRegInstX("fsqrt", "FsqrtDX", "SimdFloatSqrtOp", smallFloatTypes, 2, 157010037SARM gem5 Developers fsqrtCode) 157110037SARM gem5 Developers twoEqualRegInstX("fsqrt", "FsqrtQX", "SimdFloatSqrtOp", floatTypes, 4, 157210037SARM gem5 Developers fsqrtCode) 157310037SARM gem5 Developers # FSUB 157410037SARM gem5 Developers fsubCode = fpBinOp % "Sub" 157510037SARM gem5 Developers threeEqualRegInstX("fsub", "FsubDX", "SimdFloatAddOp", smallFloatTypes, 2, 157610037SARM gem5 Developers fsubCode) 157710037SARM gem5 Developers threeEqualRegInstX("fsub", "FsubQX", "SimdFloatAddOp", floatTypes, 4, 157810037SARM gem5 Developers fsubCode) 157910037SARM gem5 Developers # INS (element) 158010037SARM gem5 Developers insFromVecElemInstX("ins", "InsElemX", "SimdMiscOp", unsignedTypes, 4) 158110037SARM gem5 Developers # INS (general register) 158210037SARM gem5 Developers insFromGprInstX("ins", "InsGprWX", "SimdMiscOp", smallUnsignedTypes, 4, 158310037SARM gem5 Developers 'W') 158410037SARM gem5 Developers insFromGprInstX("ins", "InsGprXX", "SimdMiscOp", unsignedTypes, 4, 'X') 158510037SARM gem5 Developers # MLA (by element) 158610037SARM gem5 Developers mlaCode = "destElem += srcElem1 * srcElem2;" 158710037SARM gem5 Developers threeEqualRegInstX("mla", "MlaElemDX", "SimdMultAccOp", 158810037SARM gem5 Developers ("uint16_t", "uint32_t"), 2, mlaCode, True, byElem=True) 158910037SARM gem5 Developers threeEqualRegInstX("mla", "MlaElemQX", "SimdMultAccOp", 159010037SARM gem5 Developers ("uint16_t", "uint32_t"), 4, mlaCode, True, byElem=True) 159110037SARM gem5 Developers # MLA (vector) 159210037SARM gem5 Developers threeEqualRegInstX("mla", "MlaDX", "SimdMultAccOp", smallUnsignedTypes, 2, 159310037SARM gem5 Developers mlaCode, True) 159410037SARM gem5 Developers threeEqualRegInstX("mla", "MlaQX", "SimdMultAccOp", smallUnsignedTypes, 4, 159510037SARM gem5 Developers mlaCode, True) 159610037SARM gem5 Developers # MLS (by element) 159710037SARM gem5 Developers mlsCode = "destElem -= srcElem1 * srcElem2;" 159810037SARM gem5 Developers threeEqualRegInstX("mls", "MlsElemDX", "SimdMultAccOp", 159910037SARM gem5 Developers ("uint16_t", "uint32_t"), 2, mlsCode, True, byElem=True) 160010037SARM gem5 Developers threeEqualRegInstX("mls", "MlsElemQX", "SimdMultAccOp", 160110037SARM gem5 Developers ("uint16_t", "uint32_t"), 4, mlsCode, True, byElem=True) 160210037SARM gem5 Developers # MLS (vector) 160310037SARM gem5 Developers threeEqualRegInstX("mls", "MlsDX", "SimdMultAccOp", smallUnsignedTypes, 2, 160410037SARM gem5 Developers mlsCode, True) 160510037SARM gem5 Developers threeEqualRegInstX("mls", "MlsQX", "SimdMultAccOp", smallUnsignedTypes, 4, 160610037SARM gem5 Developers mlsCode, True) 160710037SARM gem5 Developers # MOV (element) -> alias to INS (element) 160810037SARM gem5 Developers # MOV (from general) -> alias to INS (general register) 160910037SARM gem5 Developers # MOV (scalar) -> alias to DUP (element) 161010037SARM gem5 Developers # MOV (to general) -> alias to UMOV 161110037SARM gem5 Developers # MOV (vector) -> alias to ORR (register) 161210037SARM gem5 Developers # MOVI 161310037SARM gem5 Developers movImmCode = "destElem = imm;" 161410037SARM gem5 Developers oneRegImmInstX("movi", "MoviDX", "SimdMiscOp", ("uint64_t",), 2, 161510037SARM gem5 Developers movImmCode) 161610037SARM gem5 Developers oneRegImmInstX("movi", "MoviQX", "SimdMiscOp", ("uint64_t",), 4, 161710037SARM gem5 Developers movImmCode) 161810037SARM gem5 Developers # MUL (by element) 161910037SARM gem5 Developers mulCode = "destElem = srcElem1 * srcElem2;" 162010037SARM gem5 Developers threeEqualRegInstX("mul", "MulElemDX", "SimdMultOp", 162110037SARM gem5 Developers ("uint16_t", "uint32_t"), 2, mulCode, byElem=True) 162210037SARM gem5 Developers threeEqualRegInstX("mul", "MulElemQX", "SimdMultOp", 162310037SARM gem5 Developers ("uint16_t", "uint32_t"), 4, mulCode, byElem=True) 162410037SARM gem5 Developers # MUL (vector) 162510037SARM gem5 Developers threeEqualRegInstX("mul", "MulDX", "SimdMultOp", smallUnsignedTypes, 2, 162610037SARM gem5 Developers mulCode) 162710037SARM gem5 Developers threeEqualRegInstX("mul", "MulQX", "SimdMultOp", smallUnsignedTypes, 4, 162810037SARM gem5 Developers mulCode) 162910037SARM gem5 Developers # MVN 163010037SARM gem5 Developers mvnCode = "destElem = ~srcElem1;" 163110037SARM gem5 Developers twoEqualRegInstX("mvn", "MvnDX", "SimdAluOp", ("uint64_t",), 2, mvnCode) 163210037SARM gem5 Developers twoEqualRegInstX("mvn", "MvnQX", "SimdAluOp", ("uint64_t",), 4, mvnCode) 163310037SARM gem5 Developers # MVNI 163410037SARM gem5 Developers mvniCode = "destElem = ~imm;" 163510037SARM gem5 Developers oneRegImmInstX("mvni", "MvniDX", "SimdAluOp", ("uint64_t",), 2, mvniCode) 163610037SARM gem5 Developers oneRegImmInstX("mvni", "MvniQX", "SimdAluOp", ("uint64_t",), 4, mvniCode) 163710037SARM gem5 Developers # NEG 163810037SARM gem5 Developers negCode = "destElem = -srcElem1;" 163910037SARM gem5 Developers twoEqualRegInstX("neg", "NegDX", "SimdAluOp", signedTypes, 2, negCode) 164010037SARM gem5 Developers twoEqualRegInstX("neg", "NegQX", "SimdAluOp", signedTypes, 4, negCode) 164110037SARM gem5 Developers # NOT -> alias to MVN 164210037SARM gem5 Developers # ORN 164310037SARM gem5 Developers ornCode = "destElem = srcElem1 | ~srcElem2;" 164410037SARM gem5 Developers threeEqualRegInstX("orn", "OrnDX", "SimdAluOp", ("uint64_t",), 2, ornCode) 164510037SARM gem5 Developers threeEqualRegInstX("orn", "OrnQX", "SimdAluOp", ("uint64_t",), 4, ornCode) 164610037SARM gem5 Developers # ORR (immediate) 164710037SARM gem5 Developers orrImmCode = "destElem |= imm;" 164810037SARM gem5 Developers oneRegImmInstX("orr", "OrrImmDX", "SimdAluOp", ("uint64_t",), 2, 164910037SARM gem5 Developers orrImmCode, True) 165010037SARM gem5 Developers oneRegImmInstX("orr", "OrrImmQX", "SimdAluOp", ("uint64_t",), 4, 165110037SARM gem5 Developers orrImmCode, True) 165210037SARM gem5 Developers # ORR (register) 165310037SARM gem5 Developers orrCode = "destElem = srcElem1 | srcElem2;" 165410037SARM gem5 Developers threeEqualRegInstX("orr", "OrrDX", "SimdAluOp", ("uint64_t",), 2, orrCode) 165510037SARM gem5 Developers threeEqualRegInstX("orr", "OrrQX", "SimdAluOp", ("uint64_t",), 4, orrCode) 165610037SARM gem5 Developers # PMUL 165710037SARM gem5 Developers pmulCode = ''' 165810037SARM gem5 Developers destElem = 0; 165910037SARM gem5 Developers for (unsigned j = 0; j < sizeof(Element) * 8; j++) { 166010037SARM gem5 Developers if (bits(srcElem2, j)) 166110037SARM gem5 Developers destElem ^= srcElem1 << j; 166210037SARM gem5 Developers } 166310037SARM gem5 Developers ''' 166410037SARM gem5 Developers threeEqualRegInstX("pmul", "PmulDX", "SimdMultOp", ("uint8_t",), 2, 166510037SARM gem5 Developers pmulCode) 166610037SARM gem5 Developers threeEqualRegInstX("pmul", "PmulQX", "SimdMultOp", ("uint8_t",), 4, 166710037SARM gem5 Developers pmulCode) 166810037SARM gem5 Developers # PMULL, PMULL2 166910037SARM gem5 Developers # Note: 64-bit PMULL is not available (Crypto. Extension) 167010037SARM gem5 Developers pmullCode = ''' 167110037SARM gem5 Developers destElem = 0; 167210037SARM gem5 Developers for (unsigned j = 0; j < sizeof(Element) * 8; j++) { 167310037SARM gem5 Developers if (bits(srcElem2, j)) 167410037SARM gem5 Developers destElem ^= (BigElement)srcElem1 << j; 167510037SARM gem5 Developers } 167610037SARM gem5 Developers ''' 167710037SARM gem5 Developers threeRegLongInstX("pmull", "PmullX", "SimdMultOp", ("uint8_t",), pmullCode) 167810037SARM gem5 Developers threeRegLongInstX("pmull", "Pmull2X", "SimdMultOp", ("uint8_t",), 167910037SARM gem5 Developers pmullCode, hi=True) 168010037SARM gem5 Developers # RADDHN, RADDHN2 168110037SARM gem5 Developers raddhnCode = ''' 168210037SARM gem5 Developers destElem = ((BigElement)srcElem1 + (BigElement)srcElem2 + 168310037SARM gem5 Developers ((BigElement)1 << (sizeof(Element) * 8 - 1))) >> 168410037SARM gem5 Developers (sizeof(Element) * 8); 168510037SARM gem5 Developers ''' 168610037SARM gem5 Developers threeRegNarrowInstX("raddhn", "RaddhnX", "SimdAddOp", smallUnsignedTypes, 168710037SARM gem5 Developers raddhnCode) 168810037SARM gem5 Developers threeRegNarrowInstX("raddhn2", "Raddhn2X", "SimdAddOp", smallUnsignedTypes, 168910037SARM gem5 Developers raddhnCode, hi=True) 169010037SARM gem5 Developers # RBIT 169110037SARM gem5 Developers rbitCode = ''' 169210037SARM gem5 Developers destElem = 0; 169310037SARM gem5 Developers Element temp = srcElem1; 169410037SARM gem5 Developers for (int i = 0; i < 8 * sizeof(Element); i++) { 169510037SARM gem5 Developers destElem = destElem | ((temp & 0x1) << 169610037SARM gem5 Developers (8 * sizeof(Element) - 1 - i)); 169710037SARM gem5 Developers temp >>= 1; 169810037SARM gem5 Developers } 169910037SARM gem5 Developers ''' 170010037SARM gem5 Developers twoEqualRegInstX("rbit", "RbitDX", "SimdAluOp", ("uint8_t",), 2, rbitCode) 170110037SARM gem5 Developers twoEqualRegInstX("rbit", "RbitQX", "SimdAluOp", ("uint8_t",), 4, rbitCode) 170210037SARM gem5 Developers # REV16 170310037SARM gem5 Developers rev16Code = ''' 170410037SARM gem5 Developers destElem = srcElem1; 170510037SARM gem5 Developers unsigned groupSize = ((1 << 1) / sizeof(Element)); 170610037SARM gem5 Developers unsigned reverseMask = (groupSize - 1); 170710037SARM gem5 Developers j = i ^ reverseMask; 170810037SARM gem5 Developers ''' 170910037SARM gem5 Developers twoEqualRegInstX("rev16", "Rev16DX", "SimdAluOp", ("uint8_t",), 2, 171010037SARM gem5 Developers rev16Code) 171110037SARM gem5 Developers twoEqualRegInstX("rev16", "Rev16QX", "SimdAluOp", ("uint8_t",), 4, 171210037SARM gem5 Developers rev16Code) 171310037SARM gem5 Developers # REV32 171410037SARM gem5 Developers rev32Code = ''' 171510037SARM gem5 Developers destElem = srcElem1; 171610037SARM gem5 Developers unsigned groupSize = ((1 << 2) / sizeof(Element)); 171710037SARM gem5 Developers unsigned reverseMask = (groupSize - 1); 171810037SARM gem5 Developers j = i ^ reverseMask; 171910037SARM gem5 Developers ''' 172010037SARM gem5 Developers twoEqualRegInstX("rev32", "Rev32DX", "SimdAluOp", ("uint8_t", "uint16_t"), 172110037SARM gem5 Developers 2, rev32Code) 172210037SARM gem5 Developers twoEqualRegInstX("rev32", "Rev32QX", "SimdAluOp", ("uint8_t", "uint16_t"), 172310037SARM gem5 Developers 4, rev32Code) 172410037SARM gem5 Developers # REV64 172510037SARM gem5 Developers rev64Code = ''' 172610037SARM gem5 Developers destElem = srcElem1; 172710037SARM gem5 Developers unsigned groupSize = ((1 << 3) / sizeof(Element)); 172810037SARM gem5 Developers unsigned reverseMask = (groupSize - 1); 172910037SARM gem5 Developers j = i ^ reverseMask; 173010037SARM gem5 Developers ''' 173110037SARM gem5 Developers twoEqualRegInstX("rev64", "Rev64DX", "SimdAluOp", smallUnsignedTypes, 2, 173210037SARM gem5 Developers rev64Code) 173310037SARM gem5 Developers twoEqualRegInstX("rev64", "Rev64QX", "SimdAluOp", smallUnsignedTypes, 4, 173410037SARM gem5 Developers rev64Code) 173510037SARM gem5 Developers # RSHRN, RSHRN2 173610037SARM gem5 Developers rshrnCode = ''' 173710037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 173810037SARM gem5 Developers destElem = 0; 173910037SARM gem5 Developers } else if (imm) { 174010037SARM gem5 Developers Element rBit = bits(srcElem1, imm - 1); 174110037SARM gem5 Developers destElem = ((srcElem1 >> (imm - 1)) >> 1) + rBit; 174210037SARM gem5 Developers } else { 174310037SARM gem5 Developers destElem = srcElem1; 174410037SARM gem5 Developers } 174510037SARM gem5 Developers ''' 174610037SARM gem5 Developers twoRegNarrowInstX("rshrn", "RshrnX", "SimdShiftOp", smallUnsignedTypes, 174710037SARM gem5 Developers rshrnCode, hasImm=True) 174810037SARM gem5 Developers twoRegNarrowInstX("rshrn2", "Rshrn2X", "SimdShiftOp", smallUnsignedTypes, 174910037SARM gem5 Developers rshrnCode, hasImm=True, hi=True) 175010037SARM gem5 Developers # RSUBHN, RSUBHN2 175110037SARM gem5 Developers rsubhnCode = ''' 175210037SARM gem5 Developers destElem = ((BigElement)srcElem1 - (BigElement)srcElem2 + 175310037SARM gem5 Developers ((BigElement)1 << (sizeof(Element) * 8 - 1))) >> 175410037SARM gem5 Developers (sizeof(Element) * 8); 175510037SARM gem5 Developers ''' 175610037SARM gem5 Developers threeRegNarrowInstX("rsubhn", "RsubhnX", "SimdAddOp", smallTypes, 175710037SARM gem5 Developers rsubhnCode) 175810037SARM gem5 Developers threeRegNarrowInstX("rsubhn2", "Rsubhn2X", "SimdAddOp", smallTypes, 175910037SARM gem5 Developers rsubhnCode, hi=True) 176010037SARM gem5 Developers # SABA 176110037SARM gem5 Developers abaCode = ''' 176210037SARM gem5 Developers destElem += (srcElem1 > srcElem2) ? (srcElem1 - srcElem2) : 176310037SARM gem5 Developers (srcElem2 - srcElem1); 176410037SARM gem5 Developers ''' 176510037SARM gem5 Developers threeEqualRegInstX("saba", "SabaDX", "SimdAddAccOp", smallSignedTypes, 2, 176610037SARM gem5 Developers abaCode, True) 176710037SARM gem5 Developers threeEqualRegInstX("saba", "SabaQX", "SimdAddAccOp", smallSignedTypes, 4, 176810037SARM gem5 Developers abaCode, True) 176910037SARM gem5 Developers # SABAL, SABAL2 177010037SARM gem5 Developers abalCode = ''' 177110037SARM gem5 Developers destElem += (srcElem1 > srcElem2) ? 177210037SARM gem5 Developers ((BigElement)srcElem1 - (BigElement)srcElem2) : 177310037SARM gem5 Developers ((BigElement)srcElem2 - (BigElement)srcElem1); 177410037SARM gem5 Developers ''' 177510037SARM gem5 Developers threeRegLongInstX("sabal", "SabalX", "SimdAddAccOp", smallSignedTypes, 177610037SARM gem5 Developers abalCode, True) 177710037SARM gem5 Developers threeRegLongInstX("sabal2", "Sabal2X", "SimdAddAccOp", smallSignedTypes, 177810037SARM gem5 Developers abalCode, True, hi=True) 177910037SARM gem5 Developers # SABD 178010037SARM gem5 Developers abdCode = ''' 178110037SARM gem5 Developers destElem = (srcElem1 > srcElem2) ? (srcElem1 - srcElem2) : 178210037SARM gem5 Developers (srcElem2 - srcElem1); 178310037SARM gem5 Developers ''' 178410037SARM gem5 Developers threeEqualRegInstX("sabd", "SabdDX", "SimdAddOp", smallSignedTypes, 2, 178510037SARM gem5 Developers abdCode) 178610037SARM gem5 Developers threeEqualRegInstX("sabd", "SabdQX", "SimdAddOp", smallSignedTypes, 4, 178710037SARM gem5 Developers abdCode) 178810037SARM gem5 Developers # SABDL, SABDL2 178910037SARM gem5 Developers abdlCode = ''' 179010037SARM gem5 Developers destElem = (srcElem1 > srcElem2) ? 179110037SARM gem5 Developers ((BigElement)srcElem1 - (BigElement)srcElem2) : 179210037SARM gem5 Developers ((BigElement)srcElem2 - (BigElement)srcElem1); 179310037SARM gem5 Developers ''' 179410037SARM gem5 Developers threeRegLongInstX("sabdl", "SabdlX", "SimdAddAccOp", smallSignedTypes, 179510037SARM gem5 Developers abdlCode, True) 179610037SARM gem5 Developers threeRegLongInstX("sabdl2", "Sabdl2X", "SimdAddAccOp", smallSignedTypes, 179710037SARM gem5 Developers abdlCode, True, hi=True) 179810037SARM gem5 Developers # SADALP 179910037SARM gem5 Developers adalpCode = "destElem += (BigElement)srcElem1 + (BigElement)srcElem2;" 180010037SARM gem5 Developers twoRegCondenseInstX("sadalp", "SadalpDX", "SimdAddOp", smallSignedTypes, 2, 180110037SARM gem5 Developers adalpCode, True) 180210037SARM gem5 Developers twoRegCondenseInstX("sadalp", "SadalpQX", "SimdAddOp", smallSignedTypes, 4, 180310037SARM gem5 Developers adalpCode, True) 180410037SARM gem5 Developers # SADDL, SADDL2 180510037SARM gem5 Developers addlwCode = "destElem = (BigElement)srcElem1 + (BigElement)srcElem2;" 180610037SARM gem5 Developers threeRegLongInstX("saddl", "SaddlX", "SimdAddAccOp", smallSignedTypes, 180710037SARM gem5 Developers addlwCode) 180810037SARM gem5 Developers threeRegLongInstX("saddl2", "Saddl2X", "SimdAddAccOp", smallSignedTypes, 180910037SARM gem5 Developers addlwCode, hi=True) 181010037SARM gem5 Developers # SADDLP 181110037SARM gem5 Developers twoRegCondenseInstX("saddlp", "SaddlpDX", "SimdAddOp", smallSignedTypes, 2, 181210037SARM gem5 Developers addlwCode) 181310037SARM gem5 Developers twoRegCondenseInstX("saddlp", "SaddlpQX", "SimdAddOp", smallSignedTypes, 4, 181410037SARM gem5 Developers addlwCode) 181510037SARM gem5 Developers # SADDLV 181610037SARM gem5 Developers # Note: SimdAddOp can be a bit optimistic here 181710037SARM gem5 Developers addAcrossLongCode = "destElem += (BigElement)srcElem1;" 181810037SARM gem5 Developers twoRegAcrossInstX("saddlv", "SaddlvDX", "SimdAddOp", ("int8_t", "int16_t"), 181910037SARM gem5 Developers 2, addAcrossLongCode, long=True) 182010037SARM gem5 Developers twoRegAcrossInstX("saddlv", "SaddlvQX", "SimdAddOp", ("int8_t", "int16_t"), 182110037SARM gem5 Developers 4, addAcrossLongCode, long=True) 182210037SARM gem5 Developers twoRegAcrossInstX("saddlv", "SaddlvBQX", "SimdAddOp", ("int32_t",), 4, 182310037SARM gem5 Developers addAcrossLongCode, doubleDest=True, long=True) 182410037SARM gem5 Developers # SADDW, SADDW2 182510037SARM gem5 Developers threeRegWideInstX("saddw", "SaddwX", "SimdAddAccOp", smallSignedTypes, 182610037SARM gem5 Developers addlwCode) 182710037SARM gem5 Developers threeRegWideInstX("saddw2", "Saddw2X", "SimdAddAccOp", smallSignedTypes, 182810037SARM gem5 Developers addlwCode, hi=True) 182910037SARM gem5 Developers # SCVTF (fixed-point) 183010037SARM gem5 Developers scvtfFixedCode = fpOp % ("fplibFixedToFP<Element>((int%d_t) srcElem1, imm," 183110037SARM gem5 Developers " false, FPCRRounding(fpscr), fpscr)") 183210037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfFixedDX", "SimdCvtOp", smallFloatTypes, 2, 183310037SARM gem5 Developers scvtfFixedCode % 32, hasImm=True) 183410037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfFixedSQX", "SimdCvtOp", smallFloatTypes, 4, 183510037SARM gem5 Developers scvtfFixedCode % 32, hasImm=True) 183610037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfFixedDQX", "SimdCvtOp", ("uint64_t",), 4, 183710037SARM gem5 Developers scvtfFixedCode % 64, hasImm=True) 183810037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfFixedScSX", "SimdCvtOp", smallFloatTypes, 183910037SARM gem5 Developers 4, scvtfFixedCode % 32, hasImm=True, scalar=True) 184010037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfFixedScDX", "SimdCvtOp", ("uint64_t",), 4, 184110037SARM gem5 Developers scvtfFixedCode % 64, hasImm=True, scalar=True) 184210037SARM gem5 Developers # SCVTF (integer) 184310037SARM gem5 Developers scvtfIntCode = fpOp % ("fplibFixedToFP<Element>((int%d_t) srcElem1, 0," 184410037SARM gem5 Developers " false, FPCRRounding(fpscr), fpscr)") 184510037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfIntDX", "SimdCvtOp", smallFloatTypes, 2, 184610037SARM gem5 Developers scvtfIntCode % 32) 184710037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfIntSQX", "SimdCvtOp", smallFloatTypes, 4, 184810037SARM gem5 Developers scvtfIntCode % 32) 184910037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfIntDQX", "SimdCvtOp", ("uint64_t",), 4, 185010037SARM gem5 Developers scvtfIntCode % 64) 185110037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfIntScSX", "SimdCvtOp", smallFloatTypes, 4, 185210037SARM gem5 Developers scvtfIntCode % 32, scalar=True) 185310037SARM gem5 Developers twoEqualRegInstX("scvtf", "ScvtfIntScDX", "SimdCvtOp", ("uint64_t",), 4, 185410037SARM gem5 Developers scvtfIntCode % 64, scalar=True) 185510037SARM gem5 Developers # SHADD 185610037SARM gem5 Developers haddCode = ''' 185710037SARM gem5 Developers Element carryBit = 185810037SARM gem5 Developers (((unsigned)srcElem1 & 0x1) + 185910037SARM gem5 Developers ((unsigned)srcElem2 & 0x1)) >> 1; 186010037SARM gem5 Developers // Use division instead of a shift to ensure the sign extension works 186110037SARM gem5 Developers // right. The compiler will figure out if it can be a shift. Mask the 186210037SARM gem5 Developers // inputs so they get truncated correctly. 186310037SARM gem5 Developers destElem = (((srcElem1 & ~(Element)1) / 2) + 186410037SARM gem5 Developers ((srcElem2 & ~(Element)1) / 2)) + carryBit; 186510037SARM gem5 Developers ''' 186610037SARM gem5 Developers threeEqualRegInstX("shadd", "ShaddDX", "SimdAddOp", smallSignedTypes, 2, 186710037SARM gem5 Developers haddCode) 186810037SARM gem5 Developers threeEqualRegInstX("shadd", "ShaddQX", "SimdAddOp", smallSignedTypes, 4, 186910037SARM gem5 Developers haddCode) 187010037SARM gem5 Developers # SHL 187110037SARM gem5 Developers shlCode = ''' 187210037SARM gem5 Developers if (imm >= sizeof(Element) * 8) 187310037SARM gem5 Developers destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1; 187410037SARM gem5 Developers else 187510037SARM gem5 Developers destElem = srcElem1 << imm; 187610037SARM gem5 Developers ''' 187710037SARM gem5 Developers twoEqualRegInstX("shl", "ShlDX", "SimdShiftOp", unsignedTypes, 2, shlCode, 187810037SARM gem5 Developers hasImm=True) 187910037SARM gem5 Developers twoEqualRegInstX("shl", "ShlQX", "SimdShiftOp", unsignedTypes, 4, shlCode, 188010037SARM gem5 Developers hasImm=True) 188110037SARM gem5 Developers # SHLL, SHLL2 188210037SARM gem5 Developers shllCode = "destElem = ((BigElement)srcElem1) << (sizeof(Element) * 8);" 188310037SARM gem5 Developers twoRegLongInstX("shll", "ShllX", "SimdShiftOp", smallTypes, shllCode) 188410037SARM gem5 Developers twoRegLongInstX("shll", "Shll2X", "SimdShiftOp", smallTypes, shllCode, 188510037SARM gem5 Developers hi=True) 188610037SARM gem5 Developers # SHRN, SHRN2 188710037SARM gem5 Developers shrnCode = ''' 188810037SARM gem5 Developers if (imm >= sizeof(srcElem1) * 8) { 188910037SARM gem5 Developers destElem = 0; 189010037SARM gem5 Developers } else { 189110037SARM gem5 Developers destElem = srcElem1 >> imm; 189210037SARM gem5 Developers } 189310037SARM gem5 Developers ''' 189410037SARM gem5 Developers twoRegNarrowInstX("shrn", "ShrnX", "SimdShiftOp", smallUnsignedTypes, 189510037SARM gem5 Developers shrnCode, hasImm=True) 189610037SARM gem5 Developers twoRegNarrowInstX("shrn2", "Shrn2X", "SimdShiftOp", smallUnsignedTypes, 189710037SARM gem5 Developers shrnCode, hasImm=True, hi=True) 189810037SARM gem5 Developers # SHSUB 189910037SARM gem5 Developers hsubCode = ''' 190010037SARM gem5 Developers Element borrowBit = 190110037SARM gem5 Developers (((srcElem1 & 0x1) - (srcElem2 & 0x1)) >> 1) & 0x1; 190210037SARM gem5 Developers // Use division instead of a shift to ensure the sign extension works 190310037SARM gem5 Developers // right. The compiler will figure out if it can be a shift. Mask the 190410037SARM gem5 Developers // inputs so they get truncated correctly. 190510037SARM gem5 Developers destElem = (((srcElem1 & ~(Element)1) / 2) - 190610037SARM gem5 Developers ((srcElem2 & ~(Element)1) / 2)) - borrowBit; 190710037SARM gem5 Developers ''' 190810037SARM gem5 Developers threeEqualRegInstX("shsub", "ShsubDX", "SimdAddOp", smallSignedTypes, 2, 190910037SARM gem5 Developers hsubCode) 191010037SARM gem5 Developers threeEqualRegInstX("shsub", "ShsubQX", "SimdAddOp", smallSignedTypes, 4, 191110037SARM gem5 Developers hsubCode) 191210037SARM gem5 Developers # SLI 191310037SARM gem5 Developers sliCode = ''' 191410037SARM gem5 Developers if (imm >= sizeof(Element) * 8) 191510037SARM gem5 Developers destElem = destElem; 191610037SARM gem5 Developers else 191710037SARM gem5 Developers destElem = (srcElem1 << imm) | (destElem & mask(imm)); 191810037SARM gem5 Developers ''' 191910037SARM gem5 Developers twoEqualRegInstX("sli", "SliDX", "SimdShiftOp", unsignedTypes, 2, sliCode, 192010037SARM gem5 Developers True, hasImm=True) 192110037SARM gem5 Developers twoEqualRegInstX("sli", "SliQX", "SimdShiftOp", unsignedTypes, 4, sliCode, 192210037SARM gem5 Developers True, hasImm=True) 192310037SARM gem5 Developers # SMAX 192410037SARM gem5 Developers maxCode = "destElem = (srcElem1 > srcElem2) ? srcElem1 : srcElem2;" 192510037SARM gem5 Developers threeEqualRegInstX("smax", "SmaxDX", "SimdCmpOp", smallSignedTypes, 2, 192610037SARM gem5 Developers maxCode) 192710037SARM gem5 Developers threeEqualRegInstX("smax", "SmaxQX", "SimdCmpOp", smallSignedTypes, 4, 192810037SARM gem5 Developers maxCode) 192910037SARM gem5 Developers # SMAXP 193010037SARM gem5 Developers threeEqualRegInstX("smaxp", "SmaxpDX", "SimdCmpOp", smallSignedTypes, 2, 193110037SARM gem5 Developers maxCode, pairwise=True) 193210037SARM gem5 Developers threeEqualRegInstX("smaxp", "SmaxpQX", "SimdCmpOp", smallSignedTypes, 4, 193310037SARM gem5 Developers maxCode, pairwise=True) 193410037SARM gem5 Developers # SMAXV 193510037SARM gem5 Developers maxAcrossCode = ''' 193610037SARM gem5 Developers if (i == 0 || srcElem1 > destElem) 193710037SARM gem5 Developers destElem = srcElem1; 193810037SARM gem5 Developers ''' 193910037SARM gem5 Developers twoRegAcrossInstX("smaxv", "SmaxvDX", "SimdCmpOp", ("int8_t", "int16_t"), 194010037SARM gem5 Developers 2, maxAcrossCode) 194110037SARM gem5 Developers twoRegAcrossInstX("smaxv", "SmaxvQX", "SimdCmpOp", smallSignedTypes, 4, 194210037SARM gem5 Developers maxAcrossCode) 194310037SARM gem5 Developers # SMIN 194410037SARM gem5 Developers minCode = "destElem = (srcElem1 < srcElem2) ? srcElem1 : srcElem2;" 194510037SARM gem5 Developers threeEqualRegInstX("smin", "SminDX", "SimdCmpOp", smallSignedTypes, 2, 194610037SARM gem5 Developers minCode) 194710037SARM gem5 Developers threeEqualRegInstX("smin", "SminQX", "SimdCmpOp", smallSignedTypes, 4, 194810037SARM gem5 Developers minCode) 194910037SARM gem5 Developers # SMINP 195010037SARM gem5 Developers threeEqualRegInstX("sminp", "SminpDX", "SimdCmpOp", smallSignedTypes, 2, 195110037SARM gem5 Developers minCode, pairwise=True) 195210037SARM gem5 Developers threeEqualRegInstX("sminp", "SminpQX", "SimdCmpOp", smallSignedTypes, 4, 195310037SARM gem5 Developers minCode, pairwise=True) 195410037SARM gem5 Developers # SMINV 195510037SARM gem5 Developers minAcrossCode = ''' 195610037SARM gem5 Developers if (i == 0 || srcElem1 < destElem) 195710037SARM gem5 Developers destElem = srcElem1; 195810037SARM gem5 Developers ''' 195910037SARM gem5 Developers twoRegAcrossInstX("sminv", "SminvDX", "SimdCmpOp", ("int8_t", "int16_t"), 196010037SARM gem5 Developers 2, minAcrossCode) 196110037SARM gem5 Developers twoRegAcrossInstX("sminv", "SminvQX", "SimdCmpOp", smallSignedTypes, 4, 196210037SARM gem5 Developers minAcrossCode) 196310197SCurtis.Dunham@arm.com 196410197SCurtis.Dunham@arm.com split('exec') 196510197SCurtis.Dunham@arm.com 196610037SARM gem5 Developers # SMLAL, SMLAL2 (by element) 196710037SARM gem5 Developers mlalCode = "destElem += (BigElement)srcElem1 * (BigElement)srcElem2;" 196810037SARM gem5 Developers threeRegLongInstX("smlal", "SmlalElemX", "SimdMultAccOp", 196910037SARM gem5 Developers ("int16_t", "int32_t"), mlalCode, True, byElem=True) 197010037SARM gem5 Developers threeRegLongInstX("smlal", "SmlalElem2X", "SimdMultAccOp", 197110037SARM gem5 Developers ("int16_t", "int32_t"), mlalCode, True, byElem=True, 197210037SARM gem5 Developers hi=True) 197310037SARM gem5 Developers # SMLAL, SMLAL2 (vector) 197410037SARM gem5 Developers threeRegLongInstX("smlal", "SmlalX", "SimdMultAccOp", smallSignedTypes, 197510037SARM gem5 Developers mlalCode, True) 197610037SARM gem5 Developers threeRegLongInstX("smlal", "Smlal2X", "SimdMultAccOp", smallSignedTypes, 197710037SARM gem5 Developers mlalCode, True, hi=True) 197810037SARM gem5 Developers # SMLSL, SMLSL2 (by element) 197910037SARM gem5 Developers mlslCode = "destElem -= (BigElement)srcElem1 * (BigElement)srcElem2;" 198010037SARM gem5 Developers threeRegLongInstX("smlsl", "SmlslElemX", "SimdMultAccOp", smallSignedTypes, 198110037SARM gem5 Developers mlslCode, True, byElem=True) 198210037SARM gem5 Developers threeRegLongInstX("smlsl", "SmlslElem2X", "SimdMultAccOp", 198310037SARM gem5 Developers smallSignedTypes, mlslCode, True, byElem=True, hi=True) 198410037SARM gem5 Developers # SMLSL, SMLSL2 (vector) 198510037SARM gem5 Developers threeRegLongInstX("smlsl", "SmlslX", "SimdMultAccOp", smallSignedTypes, 198610037SARM gem5 Developers mlslCode, True) 198710037SARM gem5 Developers threeRegLongInstX("smlsl", "Smlsl2X", "SimdMultAccOp", smallSignedTypes, 198810037SARM gem5 Developers mlslCode, True, hi=True) 198910037SARM gem5 Developers # SMOV 199010037SARM gem5 Developers insToGprInstX("smov", "SmovWX", "SimdMiscOp", ("int8_t", "int16_t"), 4, 199110037SARM gem5 Developers 'W', True) 199210037SARM gem5 Developers insToGprInstX("smov", "SmovXX", "SimdMiscOp", smallSignedTypes, 4, 'X', 199310037SARM gem5 Developers True) 199410037SARM gem5 Developers # SMULL, SMULL2 (by element) 199510037SARM gem5 Developers mullCode = "destElem = (BigElement)srcElem1 * (BigElement)srcElem2;" 199610037SARM gem5 Developers threeRegLongInstX("smull", "SmullElemX", "SimdMultOp", smallSignedTypes, 199710037SARM gem5 Developers mullCode, byElem=True) 199810037SARM gem5 Developers threeRegLongInstX("smull", "SmullElem2X", "SimdMultOp", smallSignedTypes, 199910037SARM gem5 Developers mullCode, byElem=True, hi=True) 200010037SARM gem5 Developers # SMULL, SMULL2 (vector) 200110037SARM gem5 Developers threeRegLongInstX("smull", "SmullX", "SimdMultOp", smallSignedTypes, 200210037SARM gem5 Developers mullCode) 200310037SARM gem5 Developers threeRegLongInstX("smull", "Smull2X", "SimdMultOp", smallSignedTypes, 200410037SARM gem5 Developers mullCode, hi=True) 200510037SARM gem5 Developers # SQABS 200610037SARM gem5 Developers sqabsCode = ''' 200710037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 200810037SARM gem5 Developers if (srcElem1 == (Element)((Element)1 << (sizeof(Element) * 8 - 1))) { 200910037SARM gem5 Developers fpscr.qc = 1; 201010037SARM gem5 Developers destElem = ~srcElem1; 201110037SARM gem5 Developers } else if (srcElem1 < 0) { 201210037SARM gem5 Developers destElem = -srcElem1; 201310037SARM gem5 Developers } else { 201410037SARM gem5 Developers destElem = srcElem1; 201510037SARM gem5 Developers } 201610037SARM gem5 Developers FpscrQc = fpscr; 201710037SARM gem5 Developers ''' 201810037SARM gem5 Developers twoEqualRegInstX("sqabs", "SqabsDX", "SimdAluOp", smallSignedTypes, 2, 201910037SARM gem5 Developers sqabsCode) 202010037SARM gem5 Developers twoEqualRegInstX("sqabs", "SqabsQX", "SimdAluOp", signedTypes, 4, 202110037SARM gem5 Developers sqabsCode) 202210037SARM gem5 Developers twoEqualRegInstX("sqabs", "SqabsScX", "SimdAluOp", signedTypes, 4, 202310037SARM gem5 Developers sqabsCode, scalar=True) 202410037SARM gem5 Developers # SQADD 202510037SARM gem5 Developers sqaddCode = ''' 202610037SARM gem5 Developers destElem = srcElem1 + srcElem2; 202710037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 202810037SARM gem5 Developers bool negDest = (destElem < 0); 202910037SARM gem5 Developers bool negSrc1 = (srcElem1 < 0); 203010037SARM gem5 Developers bool negSrc2 = (srcElem2 < 0); 203110037SARM gem5 Developers if ((negDest != negSrc1) && (negSrc1 == negSrc2)) { 203210037SARM gem5 Developers destElem = (Element)1 << (sizeof(Element) * 8 - 1); 203310037SARM gem5 Developers if (negDest) 203410037SARM gem5 Developers destElem -= 1; 203510037SARM gem5 Developers fpscr.qc = 1; 203610037SARM gem5 Developers } 203710037SARM gem5 Developers FpscrQc = fpscr; 203810037SARM gem5 Developers ''' 203910037SARM gem5 Developers threeEqualRegInstX("sqadd", "SqaddDX", "SimdAddOp", smallSignedTypes, 2, 204010037SARM gem5 Developers sqaddCode) 204110037SARM gem5 Developers threeEqualRegInstX("sqadd", "SqaddQX", "SimdAddOp", signedTypes, 4, 204210037SARM gem5 Developers sqaddCode) 204310037SARM gem5 Developers threeEqualRegInstX("sqadd", "SqaddScX", "SimdAddOp", signedTypes, 4, 204410037SARM gem5 Developers sqaddCode, scalar=True) 204510037SARM gem5 Developers # SQDMLAL, SQDMLAL2 (by element) 204610037SARM gem5 Developers qdmlalCode = ''' 204710037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 204810037SARM gem5 Developers BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 204910037SARM gem5 Developers Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 205010037SARM gem5 Developers Element halfNeg = maxNeg / 2; 205110037SARM gem5 Developers if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 205210037SARM gem5 Developers (srcElem1 == halfNeg && srcElem2 == maxNeg) || 205310037SARM gem5 Developers (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 205410037SARM gem5 Developers midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 205510037SARM gem5 Developers fpscr.qc = 1; 205610037SARM gem5 Developers } 205710037SARM gem5 Developers bool negPreDest = ltz(destElem); 205810037SARM gem5 Developers destElem += midElem; 205910037SARM gem5 Developers bool negDest = ltz(destElem); 206010037SARM gem5 Developers bool negMid = ltz(midElem); 206110037SARM gem5 Developers if (negPreDest == negMid && negMid != negDest) { 206210037SARM gem5 Developers destElem = mask(sizeof(BigElement) * 8 - 1); 206310037SARM gem5 Developers if (negPreDest) 206410037SARM gem5 Developers destElem = ~destElem; 206510037SARM gem5 Developers fpscr.qc = 1; 206610037SARM gem5 Developers } 206710037SARM gem5 Developers FpscrQc = fpscr; 206810037SARM gem5 Developers ''' 206910037SARM gem5 Developers threeRegLongInstX("sqdmlal", "SqdmlalElemX", "SimdMultAccOp", 207010037SARM gem5 Developers ("int16_t", "int32_t"), qdmlalCode, True, byElem=True) 207110037SARM gem5 Developers threeRegLongInstX("sqdmlal", "SqdmlalElem2X", "SimdMultAccOp", 207210037SARM gem5 Developers ("int16_t", "int32_t"), qdmlalCode, True, byElem=True, 207310037SARM gem5 Developers hi=True) 207410037SARM gem5 Developers threeRegLongInstX("sqdmlal", "SqdmlalElemScX", "SimdMultAccOp", 207510037SARM gem5 Developers ("int16_t", "int32_t"), qdmlalCode, True, byElem=True, 207610037SARM gem5 Developers scalar=True) 207710037SARM gem5 Developers # SQDMLAL, SQDMLAL2 (vector) 207810037SARM gem5 Developers threeRegLongInstX("sqdmlal", "SqdmlalX", "SimdMultAccOp", 207910037SARM gem5 Developers ("int16_t", "int32_t"), qdmlalCode, True) 208010037SARM gem5 Developers threeRegLongInstX("sqdmlal", "Sqdmlal2X", "SimdMultAccOp", 208110037SARM gem5 Developers ("int16_t", "int32_t"), qdmlalCode, True, hi=True) 208210037SARM gem5 Developers threeRegLongInstX("sqdmlal", "SqdmlalScX", "SimdMultAccOp", 208310037SARM gem5 Developers ("int16_t", "int32_t"), qdmlalCode, True, scalar=True) 208410037SARM gem5 Developers # SQDMLSL, SQDMLSL2 (by element) 208510037SARM gem5 Developers qdmlslCode = ''' 208610037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 208710037SARM gem5 Developers BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 208810037SARM gem5 Developers Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 208910037SARM gem5 Developers Element halfNeg = maxNeg / 2; 209010037SARM gem5 Developers if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 209110037SARM gem5 Developers (srcElem1 == halfNeg && srcElem2 == maxNeg) || 209210037SARM gem5 Developers (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 209310037SARM gem5 Developers midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 209410037SARM gem5 Developers fpscr.qc = 1; 209510037SARM gem5 Developers } 209610037SARM gem5 Developers bool negPreDest = ltz(destElem); 209710037SARM gem5 Developers destElem -= midElem; 209810037SARM gem5 Developers bool negDest = ltz(destElem); 209910037SARM gem5 Developers bool posMid = ltz((BigElement)-midElem); 210010037SARM gem5 Developers if (negPreDest == posMid && posMid != negDest) { 210110037SARM gem5 Developers destElem = mask(sizeof(BigElement) * 8 - 1); 210210037SARM gem5 Developers if (negPreDest) 210310037SARM gem5 Developers destElem = ~destElem; 210410037SARM gem5 Developers fpscr.qc = 1; 210510037SARM gem5 Developers } 210610037SARM gem5 Developers FpscrQc = fpscr; 210710037SARM gem5 Developers ''' 210810037SARM gem5 Developers threeRegLongInstX("sqdmlsl", "SqdmlslElemX", "SimdMultAccOp", 210910037SARM gem5 Developers ("int16_t", "int32_t"), qdmlslCode, True, byElem=True) 211010037SARM gem5 Developers threeRegLongInstX("sqdmlsl", "SqdmlslElem2X", "SimdMultAccOp", 211110037SARM gem5 Developers ("int16_t", "int32_t"), qdmlslCode, True, byElem=True, 211210037SARM gem5 Developers hi=True) 211310037SARM gem5 Developers threeRegLongInstX("sqdmlsl", "SqdmlslElemScX", "SimdMultAccOp", 211410037SARM gem5 Developers ("int16_t", "int32_t"), qdmlslCode, True, byElem=True, 211510037SARM gem5 Developers scalar=True) 211610037SARM gem5 Developers # SQDMLSL, SQDMLSL2 (vector) 211710037SARM gem5 Developers threeRegLongInstX("sqdmlsl", "SqdmlslX", "SimdMultAccOp", 211810037SARM gem5 Developers ("int16_t", "int32_t"), qdmlslCode, True) 211910037SARM gem5 Developers threeRegLongInstX("sqdmlsl", "Sqdmlsl2X", "SimdMultAccOp", 212010037SARM gem5 Developers ("int16_t", "int32_t"), qdmlslCode, True, hi=True) 212110037SARM gem5 Developers threeRegLongInstX("sqdmlsl", "SqdmlslScX", "SimdMultAccOp", 212210037SARM gem5 Developers ("int16_t", "int32_t"), qdmlslCode, True, scalar=True) 212310037SARM gem5 Developers # SQDMULH (by element) 212410037SARM gem5 Developers sqdmulhCode = ''' 212510037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 212610037SARM gem5 Developers destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2) >> 212710037SARM gem5 Developers (sizeof(Element) * 8); 212810037SARM gem5 Developers if (srcElem1 == srcElem2 && 212910037SARM gem5 Developers srcElem1 == (Element)((Element)1 << 213010037SARM gem5 Developers (sizeof(Element) * 8 - 1))) { 213110037SARM gem5 Developers destElem = ~srcElem1; 213210037SARM gem5 Developers fpscr.qc = 1; 213310037SARM gem5 Developers } 213410037SARM gem5 Developers FpscrQc = fpscr; 213510037SARM gem5 Developers ''' 213610037SARM gem5 Developers threeEqualRegInstX("sqdmulh", "SqdmulhElemDX", "SimdMultOp", 213710037SARM gem5 Developers ("int16_t", "int32_t"), 2, sqdmulhCode, byElem=True) 213810037SARM gem5 Developers threeEqualRegInstX("sqdmulh", "SqdmulhElemQX", "SimdMultOp", 213910037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqdmulhCode, byElem=True) 214010037SARM gem5 Developers threeEqualRegInstX("sqdmulh", "SqdmulhElemScX", "SimdMultOp", 214110037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqdmulhCode, byElem=True, 214210037SARM gem5 Developers scalar=True) 214310037SARM gem5 Developers # SQDMULH (vector) 214410037SARM gem5 Developers threeEqualRegInstX("sqdmulh", "SqdmulhDX", "SimdMultOp", 214510037SARM gem5 Developers ("int16_t", "int32_t"), 2, sqdmulhCode) 214610037SARM gem5 Developers threeEqualRegInstX("sqdmulh", "SqdmulhQX", "SimdMultOp", 214710037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqdmulhCode) 214810037SARM gem5 Developers threeEqualRegInstX("sqdmulh", "SqdmulhScX", "SimdMultOp", 214910037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqdmulhCode, scalar=True) 215010037SARM gem5 Developers # SQDMULL, SQDMULL2 (by element) 215110037SARM gem5 Developers qdmullCode = ''' 215210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 215310037SARM gem5 Developers destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 215410037SARM gem5 Developers if (srcElem1 == srcElem2 && 215510037SARM gem5 Developers srcElem1 == (Element)((Element)1 << 215610037SARM gem5 Developers (Element)(sizeof(Element) * 8 - 1))) { 215710037SARM gem5 Developers destElem = ~((BigElement)srcElem1 << (sizeof(Element) * 8)); 215810037SARM gem5 Developers fpscr.qc = 1; 215910037SARM gem5 Developers } 216010037SARM gem5 Developers FpscrQc = fpscr; 216110037SARM gem5 Developers ''' 216210037SARM gem5 Developers threeRegLongInstX("sqdmull", "SqdmullElemX", "SimdMultOp", 216310037SARM gem5 Developers ("int16_t", "int32_t"), qdmullCode, True, byElem=True) 216410037SARM gem5 Developers threeRegLongInstX("sqdmull", "SqdmullElem2X", "SimdMultOp", 216510037SARM gem5 Developers ("int16_t", "int32_t"), qdmullCode, True, byElem=True, 216610037SARM gem5 Developers hi=True) 216710037SARM gem5 Developers threeRegLongInstX("sqdmull", "SqdmullElemScX", "SimdMultOp", 216810037SARM gem5 Developers ("int16_t", "int32_t"), qdmullCode, True, byElem=True, 216910037SARM gem5 Developers scalar=True) 217010037SARM gem5 Developers # SQDMULL, SQDMULL2 (vector) 217110037SARM gem5 Developers threeRegLongInstX("sqdmull", "SqdmullX", "SimdMultOp", 217210037SARM gem5 Developers ("int16_t", "int32_t"), qdmullCode, True) 217310037SARM gem5 Developers threeRegLongInstX("sqdmull", "Sqdmull2X", "SimdMultOp", 217410037SARM gem5 Developers ("int16_t", "int32_t"), qdmullCode, True, hi=True) 217510037SARM gem5 Developers threeRegLongInstX("sqdmull", "SqdmullScX", "SimdMultOp", 217610037SARM gem5 Developers ("int16_t", "int32_t"), qdmullCode, True, scalar=True) 217710037SARM gem5 Developers # SQNEG 217810037SARM gem5 Developers sqnegCode = ''' 217910037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 218010037SARM gem5 Developers if (srcElem1 == (Element)((Element)1 << (sizeof(Element) * 8 - 1))) { 218110037SARM gem5 Developers fpscr.qc = 1; 218210037SARM gem5 Developers destElem = ~srcElem1; 218310037SARM gem5 Developers } else { 218410037SARM gem5 Developers destElem = -srcElem1; 218510037SARM gem5 Developers } 218610037SARM gem5 Developers FpscrQc = fpscr; 218710037SARM gem5 Developers ''' 218810037SARM gem5 Developers twoEqualRegInstX("sqneg", "SqnegDX", "SimdAluOp", smallSignedTypes, 2, 218910037SARM gem5 Developers sqnegCode) 219010037SARM gem5 Developers twoEqualRegInstX("sqneg", "SqnegQX", "SimdAluOp", signedTypes, 4, 219110037SARM gem5 Developers sqnegCode) 219210037SARM gem5 Developers twoEqualRegInstX("sqneg", "SqnegScX", "SimdAluOp", signedTypes, 4, 219310037SARM gem5 Developers sqnegCode, scalar=True) 219410037SARM gem5 Developers # SQRDMULH (by element) 219510037SARM gem5 Developers sqrdmulhCode = ''' 219610037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 219710037SARM gem5 Developers destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2 + 219810037SARM gem5 Developers ((int64_t)1 << (sizeof(Element) * 8 - 1))) >> 219910037SARM gem5 Developers (sizeof(Element) * 8); 220010037SARM gem5 Developers Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 220110037SARM gem5 Developers Element halfNeg = maxNeg / 2; 220210037SARM gem5 Developers if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 220310037SARM gem5 Developers (srcElem1 == halfNeg && srcElem2 == maxNeg) || 220410037SARM gem5 Developers (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 220510037SARM gem5 Developers if (destElem < 0) { 220610037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 220710037SARM gem5 Developers } else { 220810037SARM gem5 Developers destElem = (Element)1 << (sizeof(Element) * 8 - 1); 220910037SARM gem5 Developers } 221010037SARM gem5 Developers fpscr.qc = 1; 221110037SARM gem5 Developers } 221210037SARM gem5 Developers FpscrQc = fpscr; 221310037SARM gem5 Developers ''' 221410037SARM gem5 Developers threeEqualRegInstX("sqrdmulh", "SqrdmulhElemDX", "SimdMultOp", 221510037SARM gem5 Developers ("int16_t", "int32_t"), 2, sqrdmulhCode, byElem=True) 221610037SARM gem5 Developers threeEqualRegInstX("sqrdmulh", "SqrdmulhElemQX", "SimdMultOp", 221710037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqrdmulhCode, byElem=True) 221810037SARM gem5 Developers threeEqualRegInstX("sqrdmulh", "SqrdmulhElemScX", "SimdMultOp", 221910037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqrdmulhCode, byElem=True, 222010037SARM gem5 Developers scalar=True) 222110037SARM gem5 Developers # SQRDMULH (vector) 222210037SARM gem5 Developers threeEqualRegInstX("sqrdmulh", "SqrdmulhDX", "SimdMultOp", 222310037SARM gem5 Developers ("int16_t", "int32_t"), 2, sqrdmulhCode) 222410037SARM gem5 Developers threeEqualRegInstX("sqrdmulh", "SqrdmulhQX", "SimdMultOp", 222510037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqrdmulhCode) 222610037SARM gem5 Developers threeEqualRegInstX("sqrdmulh", "SqrdmulhScX", "SimdMultOp", 222710037SARM gem5 Developers ("int16_t", "int32_t"), 4, sqrdmulhCode, scalar=True) 222810037SARM gem5 Developers # SQRSHL 222910037SARM gem5 Developers sqrshlCode = ''' 223010037SARM gem5 Developers int16_t shiftAmt = (int8_t)srcElem2; 223110037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 223210037SARM gem5 Developers if (shiftAmt < 0) { 223310037SARM gem5 Developers shiftAmt = -shiftAmt; 223410037SARM gem5 Developers Element rBit = 0; 223510037SARM gem5 Developers if (shiftAmt <= sizeof(Element) * 8) 223610037SARM gem5 Developers rBit = bits(srcElem1, shiftAmt - 1); 223710037SARM gem5 Developers if (shiftAmt > sizeof(Element) * 8 && srcElem1 < 0) 223810037SARM gem5 Developers rBit = 1; 223910037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 224010037SARM gem5 Developers shiftAmt = sizeof(Element) * 8 - 1; 224110037SARM gem5 Developers destElem = 0; 224210037SARM gem5 Developers } else { 224310037SARM gem5 Developers destElem = (srcElem1 >> shiftAmt); 224410037SARM gem5 Developers } 224510037SARM gem5 Developers // Make sure the right shift sign extended when it should. 224610037SARM gem5 Developers if (srcElem1 < 0 && destElem >= 0) { 224710037SARM gem5 Developers destElem |= -((Element)1 << (sizeof(Element) * 8 - 224810037SARM gem5 Developers 1 - shiftAmt)); 224910037SARM gem5 Developers } 225010037SARM gem5 Developers destElem += rBit; 225110037SARM gem5 Developers } else if (shiftAmt > 0) { 225210037SARM gem5 Developers bool sat = false; 225310037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 225410037SARM gem5 Developers if (srcElem1 != 0) 225510037SARM gem5 Developers sat = true; 225610037SARM gem5 Developers else 225710037SARM gem5 Developers destElem = 0; 225810037SARM gem5 Developers } else { 225910037SARM gem5 Developers if (bits((uint64_t) srcElem1, sizeof(Element) * 8 - 1, 226010037SARM gem5 Developers sizeof(Element) * 8 - 1 - shiftAmt) != 226110037SARM gem5 Developers ((srcElem1 < 0) ? mask(shiftAmt + 1) : 0)) { 226210037SARM gem5 Developers sat = true; 226310037SARM gem5 Developers } else { 226410037SARM gem5 Developers destElem = srcElem1 << shiftAmt; 226510037SARM gem5 Developers } 226610037SARM gem5 Developers } 226710037SARM gem5 Developers if (sat) { 226810037SARM gem5 Developers fpscr.qc = 1; 226910037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 227010037SARM gem5 Developers if (srcElem1 < 0) 227110037SARM gem5 Developers destElem = ~destElem; 227210037SARM gem5 Developers } 227310037SARM gem5 Developers } else { 227410037SARM gem5 Developers destElem = srcElem1; 227510037SARM gem5 Developers } 227610037SARM gem5 Developers FpscrQc = fpscr; 227710037SARM gem5 Developers ''' 227810037SARM gem5 Developers threeEqualRegInstX("sqrshl", "SqrshlDX", "SimdCmpOp", smallSignedTypes, 2, 227910037SARM gem5 Developers sqrshlCode) 228010037SARM gem5 Developers threeEqualRegInstX("sqrshl", "SqrshlQX", "SimdCmpOp", signedTypes, 4, 228110037SARM gem5 Developers sqrshlCode) 228210037SARM gem5 Developers threeEqualRegInstX("sqrshl", "SqrshlScX", "SimdCmpOp", signedTypes, 4, 228310037SARM gem5 Developers sqrshlCode, scalar=True) 228410037SARM gem5 Developers # SQRSHRN, SQRSHRN2 228510037SARM gem5 Developers sqrshrnCode = ''' 228610037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 228710037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 228810037SARM gem5 Developers if (srcElem1 != 0 && srcElem1 != -1) 228910037SARM gem5 Developers fpscr.qc = 1; 229010037SARM gem5 Developers destElem = 0; 229110037SARM gem5 Developers } else if (imm) { 229210037SARM gem5 Developers BigElement mid = (srcElem1 >> (imm - 1)); 229310037SARM gem5 Developers uint64_t rBit = mid & 0x1; 229410037SARM gem5 Developers mid >>= 1; 229510037SARM gem5 Developers mid |= -(mid & ((BigElement)1 << 229610037SARM gem5 Developers (sizeof(BigElement) * 8 - 1 - imm))); 229710037SARM gem5 Developers mid += rBit; 229810037SARM gem5 Developers if (mid != (Element)mid) { 229910037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 230010037SARM gem5 Developers if (srcElem1 < 0) 230110037SARM gem5 Developers destElem = ~destElem; 230210037SARM gem5 Developers fpscr.qc = 1; 230310037SARM gem5 Developers } else { 230410037SARM gem5 Developers destElem = mid; 230510037SARM gem5 Developers } 230610037SARM gem5 Developers } else { 230710037SARM gem5 Developers if (srcElem1 != (Element)srcElem1) { 230810037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 230910037SARM gem5 Developers if (srcElem1 < 0) 231010037SARM gem5 Developers destElem = ~destElem; 231110037SARM gem5 Developers fpscr.qc = 1; 231210037SARM gem5 Developers } else { 231310037SARM gem5 Developers destElem = srcElem1; 231410037SARM gem5 Developers } 231510037SARM gem5 Developers } 231610037SARM gem5 Developers FpscrQc = fpscr; 231710037SARM gem5 Developers ''' 231810037SARM gem5 Developers twoRegNarrowInstX("sqrshrn", "SqrshrnX", "SimdShiftOp", smallSignedTypes, 231910037SARM gem5 Developers sqrshrnCode, hasImm=True) 232010037SARM gem5 Developers twoRegNarrowInstX("sqrshrn2", "Sqrshrn2X", "SimdShiftOp", smallSignedTypes, 232110037SARM gem5 Developers sqrshrnCode, hasImm=True, hi=True) 232210037SARM gem5 Developers twoRegNarrowInstX("sqrshrn", "SqrshrnScX", "SimdShiftOp", smallSignedTypes, 232310037SARM gem5 Developers sqrshrnCode, hasImm=True, scalar=True) 232410037SARM gem5 Developers # SQRSHRUN, SQRSHRUN2 232510037SARM gem5 Developers sqrshrunCode = ''' 232610037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 232710037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 232810037SARM gem5 Developers if (srcElem1 != 0) 232910037SARM gem5 Developers fpscr.qc = 1; 233010037SARM gem5 Developers destElem = 0; 233110037SARM gem5 Developers } else if (imm) { 233210037SARM gem5 Developers BigElement mid = (srcElem1 >> (imm - 1)); 233310037SARM gem5 Developers uint64_t rBit = mid & 0x1; 233410037SARM gem5 Developers mid >>= 1; 233510037SARM gem5 Developers mid |= -(mid & ((BigElement)1 << 233610037SARM gem5 Developers (sizeof(BigElement) * 8 - 1 - imm))); 233710037SARM gem5 Developers mid += rBit; 233810037SARM gem5 Developers if (bits(mid, sizeof(BigElement) * 8 - 1, 233910037SARM gem5 Developers sizeof(Element) * 8) != 0) { 234010037SARM gem5 Developers if (srcElem1 < 0) { 234110037SARM gem5 Developers destElem = 0; 234210037SARM gem5 Developers } else { 234310037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 234410037SARM gem5 Developers } 234510037SARM gem5 Developers fpscr.qc = 1; 234610037SARM gem5 Developers } else { 234710037SARM gem5 Developers destElem = mid; 234810037SARM gem5 Developers } 234910037SARM gem5 Developers } else { 235010037SARM gem5 Developers if (srcElem1 < 0) { 235110037SARM gem5 Developers fpscr.qc = 1; 235210037SARM gem5 Developers destElem = 0; 235310037SARM gem5 Developers } else { 235410037SARM gem5 Developers destElem = srcElem1; 235510037SARM gem5 Developers } 235610037SARM gem5 Developers } 235710037SARM gem5 Developers FpscrQc = fpscr; 235810037SARM gem5 Developers ''' 235910037SARM gem5 Developers twoRegNarrowInstX("sqrshrun", "SqrshrunX", "SimdShiftOp", smallSignedTypes, 236010037SARM gem5 Developers sqrshrunCode, hasImm=True) 236110037SARM gem5 Developers twoRegNarrowInstX("sqrshrun", "Sqrshrun2X", "SimdShiftOp", 236210037SARM gem5 Developers smallSignedTypes, sqrshrunCode, hasImm=True, hi=True) 236310037SARM gem5 Developers twoRegNarrowInstX("sqrshrun", "SqrshrunScX", "SimdShiftOp", 236410037SARM gem5 Developers smallSignedTypes, sqrshrunCode, hasImm=True, scalar=True) 236510037SARM gem5 Developers # SQSHL (immediate) 236610037SARM gem5 Developers sqshlImmCode = ''' 236710037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 236810037SARM gem5 Developers if (imm >= sizeof(Element) * 8) { 236910037SARM gem5 Developers if (srcElem1 != 0) { 237010037SARM gem5 Developers destElem = (Element)1 << (sizeof(Element) * 8 - 1); 237110037SARM gem5 Developers if (srcElem1 > 0) 237210037SARM gem5 Developers destElem = ~destElem; 237310037SARM gem5 Developers fpscr.qc = 1; 237410037SARM gem5 Developers } else { 237510037SARM gem5 Developers destElem = 0; 237610037SARM gem5 Developers } 237710037SARM gem5 Developers } else if (imm) { 237810037SARM gem5 Developers destElem = (srcElem1 << imm); 237910037SARM gem5 Developers uint64_t topBits = bits((uint64_t)srcElem1, 238010037SARM gem5 Developers sizeof(Element) * 8 - 1, 238110037SARM gem5 Developers sizeof(Element) * 8 - 1 - imm); 238210037SARM gem5 Developers if (topBits != 0 && topBits != mask(imm + 1)) { 238310037SARM gem5 Developers destElem = (Element)1 << (sizeof(Element) * 8 - 1); 238410037SARM gem5 Developers if (srcElem1 > 0) 238510037SARM gem5 Developers destElem = ~destElem; 238610037SARM gem5 Developers fpscr.qc = 1; 238710037SARM gem5 Developers } 238810037SARM gem5 Developers } else { 238910037SARM gem5 Developers destElem = srcElem1; 239010037SARM gem5 Developers } 239110037SARM gem5 Developers FpscrQc = fpscr; 239210037SARM gem5 Developers ''' 239310037SARM gem5 Developers twoEqualRegInstX("sqshl", "SqshlImmDX", "SimdAluOp", smallSignedTypes, 2, 239410037SARM gem5 Developers sqshlImmCode, hasImm=True) 239510037SARM gem5 Developers twoEqualRegInstX("sqshl", "SqshlImmQX", "SimdAluOp", signedTypes, 4, 239610037SARM gem5 Developers sqshlImmCode, hasImm=True) 239710037SARM gem5 Developers twoEqualRegInstX("sqshl", "SqshlImmScX", "SimdAluOp", signedTypes, 4, 239810037SARM gem5 Developers sqshlImmCode, hasImm=True, scalar=True) 239910037SARM gem5 Developers # SQSHL (register) 240010037SARM gem5 Developers sqshlCode = ''' 240110037SARM gem5 Developers int16_t shiftAmt = (int8_t)srcElem2; 240210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 240310037SARM gem5 Developers if (shiftAmt < 0) { 240410037SARM gem5 Developers shiftAmt = -shiftAmt; 240510037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 240610037SARM gem5 Developers shiftAmt = sizeof(Element) * 8 - 1; 240710037SARM gem5 Developers destElem = 0; 240810037SARM gem5 Developers } else { 240910037SARM gem5 Developers destElem = (srcElem1 >> shiftAmt); 241010037SARM gem5 Developers } 241110037SARM gem5 Developers // Make sure the right shift sign extended when it should. 241210037SARM gem5 Developers if (srcElem1 < 0 && destElem >= 0) { 241310037SARM gem5 Developers destElem |= -((Element)1 << (sizeof(Element) * 8 - 241410037SARM gem5 Developers 1 - shiftAmt)); 241510037SARM gem5 Developers } 241610037SARM gem5 Developers } else if (shiftAmt > 0) { 241710037SARM gem5 Developers bool sat = false; 241810037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 241910037SARM gem5 Developers if (srcElem1 != 0) 242010037SARM gem5 Developers sat = true; 242110037SARM gem5 Developers else 242210037SARM gem5 Developers destElem = 0; 242310037SARM gem5 Developers } else { 242410037SARM gem5 Developers if (bits((uint64_t) srcElem1, sizeof(Element) * 8 - 1, 242510037SARM gem5 Developers sizeof(Element) * 8 - 1 - shiftAmt) != 242610037SARM gem5 Developers ((srcElem1 < 0) ? mask(shiftAmt + 1) : 0)) { 242710037SARM gem5 Developers sat = true; 242810037SARM gem5 Developers } else { 242910037SARM gem5 Developers destElem = srcElem1 << shiftAmt; 243010037SARM gem5 Developers } 243110037SARM gem5 Developers } 243210037SARM gem5 Developers if (sat) { 243310037SARM gem5 Developers fpscr.qc = 1; 243410037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 243510037SARM gem5 Developers if (srcElem1 < 0) 243610037SARM gem5 Developers destElem = ~destElem; 243710037SARM gem5 Developers } 243810037SARM gem5 Developers } else { 243910037SARM gem5 Developers destElem = srcElem1; 244010037SARM gem5 Developers } 244110037SARM gem5 Developers FpscrQc = fpscr; 244210037SARM gem5 Developers ''' 244310037SARM gem5 Developers threeEqualRegInstX("sqshl", "SqshlDX", "SimdAluOp", smallSignedTypes, 2, 244410037SARM gem5 Developers sqshlCode) 244510037SARM gem5 Developers threeEqualRegInstX("sqshl", "SqshlQX", "SimdAluOp", signedTypes, 4, 244610037SARM gem5 Developers sqshlCode) 244710037SARM gem5 Developers threeEqualRegInstX("sqshl", "SqshlScX", "SimdAluOp", signedTypes, 4, 244810037SARM gem5 Developers sqshlCode, scalar=True) 244910037SARM gem5 Developers # SQSHLU 245010037SARM gem5 Developers sqshluCode = ''' 245110037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 245210037SARM gem5 Developers if (imm >= sizeof(Element) * 8) { 245310037SARM gem5 Developers if (srcElem1 < 0) { 245410037SARM gem5 Developers destElem = 0; 245510037SARM gem5 Developers fpscr.qc = 1; 245610037SARM gem5 Developers } else if (srcElem1 > 0) { 245710037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 245810037SARM gem5 Developers fpscr.qc = 1; 245910037SARM gem5 Developers } else { 246010037SARM gem5 Developers destElem = 0; 246110037SARM gem5 Developers } 246210037SARM gem5 Developers } else if (imm) { 246310037SARM gem5 Developers destElem = (srcElem1 << imm); 246410037SARM gem5 Developers uint64_t topBits = bits((uint64_t)srcElem1, 246510037SARM gem5 Developers sizeof(Element) * 8 - 1, 246610037SARM gem5 Developers sizeof(Element) * 8 - imm); 246710037SARM gem5 Developers if (srcElem1 < 0) { 246810037SARM gem5 Developers destElem = 0; 246910037SARM gem5 Developers fpscr.qc = 1; 247010037SARM gem5 Developers } else if (topBits != 0) { 247110037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 247210037SARM gem5 Developers fpscr.qc = 1; 247310037SARM gem5 Developers } 247410037SARM gem5 Developers } else { 247510037SARM gem5 Developers if (srcElem1 < 0) { 247610037SARM gem5 Developers fpscr.qc = 1; 247710037SARM gem5 Developers destElem = 0; 247810037SARM gem5 Developers } else { 247910037SARM gem5 Developers destElem = srcElem1; 248010037SARM gem5 Developers } 248110037SARM gem5 Developers } 248210037SARM gem5 Developers FpscrQc = fpscr; 248310037SARM gem5 Developers ''' 248410037SARM gem5 Developers twoEqualRegInstX("sqshlu", "SqshluDX", "SimdAluOp", smallSignedTypes, 2, 248510037SARM gem5 Developers sqshluCode, hasImm=True) 248610037SARM gem5 Developers twoEqualRegInstX("sqshlu", "SqshluQX", "SimdAluOp", signedTypes, 4, 248710037SARM gem5 Developers sqshluCode, hasImm=True) 248810037SARM gem5 Developers twoEqualRegInstX("sqshlu", "SqshluScX", "SimdAluOp", signedTypes, 4, 248910037SARM gem5 Developers sqshluCode, hasImm=True, scalar=True) 249010037SARM gem5 Developers # SQSHRN, SQSHRN2 249110037SARM gem5 Developers sqshrnCode = ''' 249210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 249310037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 249410037SARM gem5 Developers if (srcElem1 != 0 && srcElem1 != -1) 249510037SARM gem5 Developers fpscr.qc = 1; 249610037SARM gem5 Developers destElem = 0; 249710037SARM gem5 Developers } else if (imm) { 249810037SARM gem5 Developers BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 249910037SARM gem5 Developers mid |= -(mid & ((BigElement)1 << 250010037SARM gem5 Developers (sizeof(BigElement) * 8 - 1 - imm))); 250110037SARM gem5 Developers if (mid != (Element)mid) { 250210037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 250310037SARM gem5 Developers if (srcElem1 < 0) 250410037SARM gem5 Developers destElem = ~destElem; 250510037SARM gem5 Developers fpscr.qc = 1; 250610037SARM gem5 Developers } else { 250710037SARM gem5 Developers destElem = mid; 250810037SARM gem5 Developers } 250910037SARM gem5 Developers } else { 251010037SARM gem5 Developers destElem = srcElem1; 251110037SARM gem5 Developers } 251210037SARM gem5 Developers FpscrQc = fpscr; 251310037SARM gem5 Developers ''' 251410037SARM gem5 Developers twoRegNarrowInstX("sqshrn", "SqshrnX", "SimdShiftOp", smallSignedTypes, 251510037SARM gem5 Developers sqshrnCode, hasImm=True) 251610037SARM gem5 Developers twoRegNarrowInstX("sqshrn2", "Sqshrn2X", "SimdShiftOp", smallSignedTypes, 251710037SARM gem5 Developers sqshrnCode, hasImm=True, hi=True) 251810037SARM gem5 Developers twoRegNarrowInstX("sqshrn", "SqshrnScX", "SimdShiftOp", smallSignedTypes, 251910037SARM gem5 Developers sqshrnCode, hasImm=True, scalar=True) 252010037SARM gem5 Developers # SQSHRUN, SQSHRUN2 252110037SARM gem5 Developers sqshrunCode = ''' 252210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 252310037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 252410037SARM gem5 Developers if (srcElem1 != 0) 252510037SARM gem5 Developers fpscr.qc = 1; 252610037SARM gem5 Developers destElem = 0; 252710037SARM gem5 Developers } else if (imm) { 252810037SARM gem5 Developers BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 252910037SARM gem5 Developers if (bits(mid, sizeof(BigElement) * 8 - 1, 253010037SARM gem5 Developers sizeof(Element) * 8) != 0) { 253110037SARM gem5 Developers if (srcElem1 < 0) { 253210037SARM gem5 Developers destElem = 0; 253310037SARM gem5 Developers } else { 253410037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 253510037SARM gem5 Developers } 253610037SARM gem5 Developers fpscr.qc = 1; 253710037SARM gem5 Developers } else { 253810037SARM gem5 Developers destElem = mid; 253910037SARM gem5 Developers } 254010037SARM gem5 Developers } else { 254110037SARM gem5 Developers destElem = srcElem1; 254210037SARM gem5 Developers } 254310037SARM gem5 Developers FpscrQc = fpscr; 254410037SARM gem5 Developers ''' 254510037SARM gem5 Developers twoRegNarrowInstX("sqshrun", "SqshrunX", "SimdShiftOp", smallSignedTypes, 254610037SARM gem5 Developers sqshrunCode, hasImm=True) 254710037SARM gem5 Developers twoRegNarrowInstX("sqshrun", "Sqshrun2X", "SimdShiftOp", smallSignedTypes, 254810037SARM gem5 Developers sqshrunCode, hasImm=True, hi=True) 254910037SARM gem5 Developers twoRegNarrowInstX("sqshrun", "SqshrunScX", "SimdShiftOp", smallSignedTypes, 255010037SARM gem5 Developers sqshrunCode, hasImm=True, scalar=True) 255110037SARM gem5 Developers # SQSUB 255210037SARM gem5 Developers sqsubCode = ''' 255310037SARM gem5 Developers destElem = srcElem1 - srcElem2; 255410037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 255510037SARM gem5 Developers bool negDest = (destElem < 0); 255610037SARM gem5 Developers bool negSrc1 = (srcElem1 < 0); 255710037SARM gem5 Developers bool posSrc2 = (srcElem2 >= 0); 255810037SARM gem5 Developers if ((negDest != negSrc1) && (negSrc1 == posSrc2)) { 255910037SARM gem5 Developers destElem = (Element)1 << (sizeof(Element) * 8 - 1); 256010037SARM gem5 Developers if (negDest) 256110037SARM gem5 Developers destElem -= 1; 256210037SARM gem5 Developers fpscr.qc = 1; 256310037SARM gem5 Developers } 256410037SARM gem5 Developers FpscrQc = fpscr; 256510037SARM gem5 Developers ''' 256610037SARM gem5 Developers threeEqualRegInstX("sqsub", "SqsubDX", "SimdAddOp", smallSignedTypes, 2, 256710037SARM gem5 Developers sqsubCode) 256810037SARM gem5 Developers threeEqualRegInstX("sqsub", "SqsubQX", "SimdAddOp", signedTypes, 4, 256910037SARM gem5 Developers sqsubCode) 257010037SARM gem5 Developers threeEqualRegInstX("sqsub", "SqsubScX", "SimdAddOp", signedTypes, 4, 257110037SARM gem5 Developers sqsubCode, scalar=True) 257210037SARM gem5 Developers # SQXTN, SQXTN2 257310037SARM gem5 Developers sqxtnCode = ''' 257410037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 257510037SARM gem5 Developers destElem = srcElem1; 257610037SARM gem5 Developers if ((BigElement)destElem != srcElem1) { 257710037SARM gem5 Developers fpscr.qc = 1; 257810037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 257910037SARM gem5 Developers if (srcElem1 < 0) 258010037SARM gem5 Developers destElem = ~destElem; 258110037SARM gem5 Developers } 258210037SARM gem5 Developers FpscrQc = fpscr; 258310037SARM gem5 Developers ''' 258410037SARM gem5 Developers twoRegNarrowInstX("sqxtn", "SqxtnX", "SimdMiscOp", smallSignedTypes, 258510037SARM gem5 Developers sqxtnCode) 258610037SARM gem5 Developers twoRegNarrowInstX("sqxtn", "Sqxtn2X", "SimdMiscOp", smallSignedTypes, 258710037SARM gem5 Developers sqxtnCode, hi=True) 258810037SARM gem5 Developers twoRegNarrowInstX("sqxtn", "SqxtnScX", "SimdMiscOp", smallSignedTypes, 258910037SARM gem5 Developers sqxtnCode, scalar=True) 259010037SARM gem5 Developers # SQXTUN, SQXTUN2 259110037SARM gem5 Developers sqxtunCode = ''' 259210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 259310037SARM gem5 Developers destElem = srcElem1; 259410037SARM gem5 Developers if (srcElem1 < 0 || 259510037SARM gem5 Developers ((BigElement)destElem & mask(sizeof(Element) * 8)) != srcElem1) { 259610037SARM gem5 Developers fpscr.qc = 1; 259710037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 259810037SARM gem5 Developers if (srcElem1 < 0) 259910037SARM gem5 Developers destElem = ~destElem; 260010037SARM gem5 Developers } 260110037SARM gem5 Developers FpscrQc = fpscr; 260210037SARM gem5 Developers ''' 260310037SARM gem5 Developers twoRegNarrowInstX("sqxtun", "SqxtunX", "SimdMiscOp", smallSignedTypes, 260410037SARM gem5 Developers sqxtunCode) 260510037SARM gem5 Developers twoRegNarrowInstX("sqxtun", "Sqxtun2X", "SimdMiscOp", smallSignedTypes, 260610037SARM gem5 Developers sqxtunCode, hi=True) 260710037SARM gem5 Developers twoRegNarrowInstX("sqxtun", "SqxtunScX", "SimdMiscOp", smallSignedTypes, 260810037SARM gem5 Developers sqxtunCode, scalar=True) 260910037SARM gem5 Developers # SRHADD 261010037SARM gem5 Developers rhaddCode = ''' 261110037SARM gem5 Developers Element carryBit = 261210037SARM gem5 Developers (((unsigned)srcElem1 & 0x1) + 261310037SARM gem5 Developers ((unsigned)srcElem2 & 0x1) + 1) >> 1; 261410037SARM gem5 Developers // Use division instead of a shift to ensure the sign extension works 261510037SARM gem5 Developers // right. The compiler will figure out if it can be a shift. Mask the 261610037SARM gem5 Developers // inputs so they get truncated correctly. 261710037SARM gem5 Developers destElem = (((srcElem1 & ~(Element)1) / 2) + 261810037SARM gem5 Developers ((srcElem2 & ~(Element)1) / 2)) + carryBit; 261910037SARM gem5 Developers ''' 262010037SARM gem5 Developers threeEqualRegInstX("srhadd", "SrhaddDX", "SimdAddOp", smallSignedTypes, 2, 262110037SARM gem5 Developers rhaddCode) 262210037SARM gem5 Developers threeEqualRegInstX("srhadd", "SrhaddQX", "SimdAddOp", smallSignedTypes, 4, 262310037SARM gem5 Developers rhaddCode) 262410037SARM gem5 Developers # SRI 262510037SARM gem5 Developers sriCode = ''' 262610037SARM gem5 Developers if (imm >= sizeof(Element) * 8) 262710037SARM gem5 Developers destElem = destElem; 262810037SARM gem5 Developers else 262910037SARM gem5 Developers destElem = (srcElem1 >> imm) | 263010037SARM gem5 Developers (destElem & ~mask(sizeof(Element) * 8 - imm)); 263110037SARM gem5 Developers ''' 263210037SARM gem5 Developers twoEqualRegInstX("sri", "SriDX", "SimdShiftOp", unsignedTypes, 2, sriCode, 263310037SARM gem5 Developers True, hasImm=True) 263410037SARM gem5 Developers twoEqualRegInstX("sri", "SriQX", "SimdShiftOp", unsignedTypes, 4, sriCode, 263510037SARM gem5 Developers True, hasImm=True) 263610037SARM gem5 Developers # SRSHL 263710037SARM gem5 Developers rshlCode = ''' 263810037SARM gem5 Developers int16_t shiftAmt = (int8_t)srcElem2; 263910037SARM gem5 Developers if (shiftAmt < 0) { 264010037SARM gem5 Developers shiftAmt = -shiftAmt; 264110037SARM gem5 Developers Element rBit = 0; 264210037SARM gem5 Developers if (shiftAmt <= sizeof(Element) * 8) 264310037SARM gem5 Developers rBit = bits(srcElem1, shiftAmt - 1); 264410037SARM gem5 Developers if (shiftAmt > sizeof(Element) * 8 && ltz(srcElem1)) 264510037SARM gem5 Developers rBit = 1; 264610037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 264710037SARM gem5 Developers shiftAmt = sizeof(Element) * 8 - 1; 264810037SARM gem5 Developers destElem = 0; 264910037SARM gem5 Developers } else { 265010037SARM gem5 Developers destElem = (srcElem1 >> shiftAmt); 265110037SARM gem5 Developers } 265210037SARM gem5 Developers // Make sure the right shift sign extended when it should. 265310037SARM gem5 Developers if (ltz(srcElem1) && !ltz(destElem)) { 265410037SARM gem5 Developers destElem |= -((Element)1 << (sizeof(Element) * 8 - 265510037SARM gem5 Developers 1 - shiftAmt)); 265610037SARM gem5 Developers } 265710037SARM gem5 Developers destElem += rBit; 265810037SARM gem5 Developers } else if (shiftAmt > 0) { 265910037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 266010037SARM gem5 Developers destElem = 0; 266110037SARM gem5 Developers } else { 266210037SARM gem5 Developers destElem = srcElem1 << shiftAmt; 266310037SARM gem5 Developers } 266410037SARM gem5 Developers } else { 266510037SARM gem5 Developers destElem = srcElem1; 266610037SARM gem5 Developers } 266710037SARM gem5 Developers ''' 266810037SARM gem5 Developers threeEqualRegInstX("srshl", "SrshlDX", "SimdShiftOp", signedTypes, 2, 266910037SARM gem5 Developers rshlCode) 267010037SARM gem5 Developers threeEqualRegInstX("srshl", "SrshlQX", "SimdShiftOp", signedTypes, 4, 267110037SARM gem5 Developers rshlCode) 267210037SARM gem5 Developers # SRSHR 267310037SARM gem5 Developers rshrCode = ''' 267410037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 267510037SARM gem5 Developers destElem = 0; 267610037SARM gem5 Developers } else if (imm) { 267710037SARM gem5 Developers Element rBit = bits(srcElem1, imm - 1); 267810037SARM gem5 Developers destElem = ((srcElem1 >> (imm - 1)) >> 1) + rBit; 267910037SARM gem5 Developers } else { 268010037SARM gem5 Developers destElem = srcElem1; 268110037SARM gem5 Developers } 268210037SARM gem5 Developers ''' 268310037SARM gem5 Developers twoEqualRegInstX("srshr", "SrshrDX", "SimdShiftOp", signedTypes, 2, 268410037SARM gem5 Developers rshrCode, hasImm=True) 268510037SARM gem5 Developers twoEqualRegInstX("srshr", "SrshrQX", "SimdShiftOp", signedTypes, 4, 268610037SARM gem5 Developers rshrCode, hasImm=True) 268710037SARM gem5 Developers # SRSRA 268810037SARM gem5 Developers rsraCode = ''' 268910037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 269010037SARM gem5 Developers destElem += 0; 269110037SARM gem5 Developers } else if (imm) { 269210037SARM gem5 Developers Element rBit = bits(srcElem1, imm - 1); 269310037SARM gem5 Developers destElem += ((srcElem1 >> (imm - 1)) >> 1) + rBit; 269410037SARM gem5 Developers } else { 269510037SARM gem5 Developers destElem += srcElem1; 269610037SARM gem5 Developers } 269710037SARM gem5 Developers ''' 269810037SARM gem5 Developers twoEqualRegInstX("srsra", "SrsraDX", "SimdShiftOp", signedTypes, 2, 269910037SARM gem5 Developers rsraCode, True, hasImm=True) 270010037SARM gem5 Developers twoEqualRegInstX("srsra", "SrsraQX", "SimdShiftOp", signedTypes, 4, 270110037SARM gem5 Developers rsraCode, True, hasImm=True) 270210037SARM gem5 Developers # SSHL 270310037SARM gem5 Developers shlCode = ''' 270410037SARM gem5 Developers int16_t shiftAmt = (int8_t)srcElem2; 270510037SARM gem5 Developers if (shiftAmt < 0) { 270610037SARM gem5 Developers shiftAmt = -shiftAmt; 270710037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 270810037SARM gem5 Developers shiftAmt = sizeof(Element) * 8 - 1; 270910037SARM gem5 Developers destElem = 0; 271010037SARM gem5 Developers } else { 271110037SARM gem5 Developers destElem = (srcElem1 >> shiftAmt); 271210037SARM gem5 Developers } 271310037SARM gem5 Developers // Make sure the right shift sign extended when it should. 271410037SARM gem5 Developers if (ltz(srcElem1) && !ltz(destElem)) { 271510037SARM gem5 Developers destElem |= -((Element)1 << (sizeof(Element) * 8 - 271610037SARM gem5 Developers 1 - shiftAmt)); 271710037SARM gem5 Developers } 271810037SARM gem5 Developers } else { 271910037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 272010037SARM gem5 Developers destElem = 0; 272110037SARM gem5 Developers } else { 272210037SARM gem5 Developers destElem = srcElem1 << shiftAmt; 272310037SARM gem5 Developers } 272410037SARM gem5 Developers } 272510037SARM gem5 Developers ''' 272610037SARM gem5 Developers threeEqualRegInstX("sshl", "SshlDX", "SimdShiftOp", signedTypes, 2, 272710037SARM gem5 Developers shlCode) 272810037SARM gem5 Developers threeEqualRegInstX("sshl", "SshlQX", "SimdShiftOp", signedTypes, 4, 272910037SARM gem5 Developers shlCode) 273010037SARM gem5 Developers # SSHLL, SSHLL2 273110037SARM gem5 Developers shllCode = ''' 273210037SARM gem5 Developers if (imm >= sizeof(destElem) * 8) { 273310037SARM gem5 Developers destElem = 0; 273410037SARM gem5 Developers } else { 273510037SARM gem5 Developers destElem = (BigElement)srcElem1 << imm; 273610037SARM gem5 Developers } 273710037SARM gem5 Developers ''' 273810037SARM gem5 Developers twoRegLongInstX("sshll", "SshllX", "SimdShiftOp", smallSignedTypes, 273910037SARM gem5 Developers shllCode, hasImm=True) 274010037SARM gem5 Developers twoRegLongInstX("sshll", "Sshll2X", "SimdShiftOp", smallSignedTypes, 274110037SARM gem5 Developers shllCode, hasImm=True, hi=True) 274210037SARM gem5 Developers # SSHR 274310037SARM gem5 Developers shrCode = ''' 274410037SARM gem5 Developers if (imm >= sizeof(srcElem1) * 8) { 274510037SARM gem5 Developers if (ltz(srcElem1)) 274610037SARM gem5 Developers destElem = -1; 274710037SARM gem5 Developers else 274810037SARM gem5 Developers destElem = 0; 274910037SARM gem5 Developers } else { 275010037SARM gem5 Developers destElem = srcElem1 >> imm; 275110037SARM gem5 Developers } 275210037SARM gem5 Developers ''' 275310037SARM gem5 Developers twoEqualRegInstX("sshr", "SshrDX", "SimdShiftOp", signedTypes, 2, shrCode, 275410037SARM gem5 Developers hasImm=True) 275510037SARM gem5 Developers twoEqualRegInstX("sshr", "SshrQX", "SimdShiftOp", signedTypes, 4, shrCode, 275610037SARM gem5 Developers hasImm=True) 275710037SARM gem5 Developers # SSRA 275810037SARM gem5 Developers sraCode = ''' 275910037SARM gem5 Developers Element mid;; 276010037SARM gem5 Developers if (imm >= sizeof(srcElem1) * 8) { 276110037SARM gem5 Developers mid = ltz(srcElem1) ? -1 : 0; 276210037SARM gem5 Developers } else { 276310037SARM gem5 Developers mid = srcElem1 >> imm; 276410037SARM gem5 Developers if (ltz(srcElem1) && !ltz(mid)) { 276510037SARM gem5 Developers mid |= -(mid & ((Element)1 << 276610037SARM gem5 Developers (sizeof(Element) * 8 - 1 - imm))); 276710037SARM gem5 Developers } 276810037SARM gem5 Developers } 276910037SARM gem5 Developers destElem += mid; 277010037SARM gem5 Developers ''' 277110037SARM gem5 Developers twoEqualRegInstX("ssra", "SsraDX", "SimdShiftOp", signedTypes, 2, sraCode, 277210037SARM gem5 Developers True, hasImm=True) 277310037SARM gem5 Developers twoEqualRegInstX("ssra", "SsraQX", "SimdShiftOp", signedTypes, 4, sraCode, 277410037SARM gem5 Developers True, hasImm=True) 277510037SARM gem5 Developers # SSUBL 277610037SARM gem5 Developers sublwCode = "destElem = (BigElement)srcElem1 - (BigElement)srcElem2;" 277710037SARM gem5 Developers threeRegLongInstX("ssubl", "SsublX", "SimdAddOp", smallSignedTypes, 277810037SARM gem5 Developers sublwCode) 277910037SARM gem5 Developers threeRegLongInstX("ssubl2", "Ssubl2X", "SimdAddOp", smallSignedTypes, 278010037SARM gem5 Developers sublwCode, hi=True) 278110037SARM gem5 Developers # SSUBW 278210037SARM gem5 Developers threeRegWideInstX("ssubw", "SsubwX", "SimdAddOp", smallSignedTypes, 278310037SARM gem5 Developers sublwCode) 278410037SARM gem5 Developers threeRegWideInstX("ssubw2", "Ssubw2X", "SimdAddOp", smallSignedTypes, 278510037SARM gem5 Developers sublwCode, hi=True) 278610037SARM gem5 Developers # SUB 278710037SARM gem5 Developers subCode = "destElem = srcElem1 - srcElem2;" 278810037SARM gem5 Developers threeEqualRegInstX("sub", "SubDX", "SimdAddOp", unsignedTypes, 2, subCode) 278910037SARM gem5 Developers threeEqualRegInstX("sub", "SubQX", "SimdAddOp", unsignedTypes, 4, subCode) 279010037SARM gem5 Developers # SUBHN, SUBHN2 279110037SARM gem5 Developers subhnCode = ''' 279210037SARM gem5 Developers destElem = ((BigElement)srcElem1 - (BigElement)srcElem2) >> 279310037SARM gem5 Developers (sizeof(Element) * 8); 279410037SARM gem5 Developers ''' 279510037SARM gem5 Developers threeRegNarrowInstX("subhn", "SubhnX", "SimdAddOp", smallUnsignedTypes, 279610037SARM gem5 Developers subhnCode) 279710037SARM gem5 Developers threeRegNarrowInstX("subhn2", "Subhn2X", "SimdAddOp", smallUnsignedTypes, 279810037SARM gem5 Developers subhnCode, hi=True) 279910037SARM gem5 Developers # SUQADD 280010037SARM gem5 Developers suqaddCode = ''' 280110037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 280210037SARM gem5 Developers Element tmp = destElem + srcElem1; 280310037SARM gem5 Developers if (bits(destElem, sizeof(Element) * 8 - 1) == 0) { 280410037SARM gem5 Developers if (bits(tmp, sizeof(Element) * 8 - 1) == 1 || 280510037SARM gem5 Developers tmp < srcElem1 || tmp < destElem) { 280610037SARM gem5 Developers destElem = (((Element) 1) << (sizeof(Element) * 8 - 1)) - 1; 280710037SARM gem5 Developers fpscr.qc = 1; 280810037SARM gem5 Developers } else { 280910037SARM gem5 Developers destElem = tmp; 281010037SARM gem5 Developers } 281110037SARM gem5 Developers } else { 281210037SARM gem5 Developers Element absDestElem = (~destElem) + 1; 281310037SARM gem5 Developers if (absDestElem < srcElem1) { 281410037SARM gem5 Developers // Still check for positive sat., no need to check for negative sat. 281510037SARM gem5 Developers if (bits(tmp, sizeof(Element) * 8 - 1) == 1) { 281610037SARM gem5 Developers destElem = (((Element) 1) << (sizeof(Element) * 8 - 1)) - 1; 281710037SARM gem5 Developers fpscr.qc = 1; 281810037SARM gem5 Developers } else { 281910037SARM gem5 Developers destElem = tmp; 282010037SARM gem5 Developers } 282110037SARM gem5 Developers } else { 282210037SARM gem5 Developers destElem = tmp; 282310037SARM gem5 Developers } 282410037SARM gem5 Developers } 282510037SARM gem5 Developers FpscrQc = fpscr; 282610037SARM gem5 Developers ''' 282710037SARM gem5 Developers twoEqualRegInstX("suqadd", "SuqaddDX", "SimdAddOp", smallUnsignedTypes, 2, 282810037SARM gem5 Developers suqaddCode, True) 282910037SARM gem5 Developers twoEqualRegInstX("suqadd", "SuqaddQX", "SimdAddOp", unsignedTypes, 4, 283010037SARM gem5 Developers suqaddCode, True) 283110037SARM gem5 Developers twoEqualRegInstX("suqadd", "SuqaddScX", "SimdAddOp", unsignedTypes, 4, 283210037SARM gem5 Developers suqaddCode, True, scalar=True) 283310037SARM gem5 Developers # SXTL -> alias to SSHLL 283410037SARM gem5 Developers # TBL 283510037SARM gem5 Developers tbxTblInstX("tbl", "Tbl1DX", "SimdMiscOp", ("uint8_t",), 1, "true", 2) 283610037SARM gem5 Developers tbxTblInstX("tbl", "Tbl1QX", "SimdMiscOp", ("uint8_t",), 1, "true", 4) 283710037SARM gem5 Developers tbxTblInstX("tbl", "Tbl2DX", "SimdMiscOp", ("uint8_t",), 2, "true", 2) 283810037SARM gem5 Developers tbxTblInstX("tbl", "Tbl2QX", "SimdMiscOp", ("uint8_t",), 2, "true", 4) 283910037SARM gem5 Developers tbxTblInstX("tbl", "Tbl3DX", "SimdMiscOp", ("uint8_t",), 3, "true", 2) 284010037SARM gem5 Developers tbxTblInstX("tbl", "Tbl3QX", "SimdMiscOp", ("uint8_t",), 3, "true", 4) 284110037SARM gem5 Developers tbxTblInstX("tbl", "Tbl4DX", "SimdMiscOp", ("uint8_t",), 4, "true", 2) 284210037SARM gem5 Developers tbxTblInstX("tbl", "Tbl4QX", "SimdMiscOp", ("uint8_t",), 4, "true", 4) 284310037SARM gem5 Developers # TBX 284410037SARM gem5 Developers tbxTblInstX("tbx", "Tbx1DX", "SimdMiscOp", ("uint8_t",), 1, "false", 2) 284510037SARM gem5 Developers tbxTblInstX("tbx", "Tbx1QX", "SimdMiscOp", ("uint8_t",), 1, "false", 4) 284610037SARM gem5 Developers tbxTblInstX("tbx", "Tbx2DX", "SimdMiscOp", ("uint8_t",), 2, "false", 2) 284710037SARM gem5 Developers tbxTblInstX("tbx", "Tbx2QX", "SimdMiscOp", ("uint8_t",), 2, "false", 4) 284810037SARM gem5 Developers tbxTblInstX("tbx", "Tbx3DX", "SimdMiscOp", ("uint8_t",), 3, "false", 2) 284910037SARM gem5 Developers tbxTblInstX("tbx", "Tbx3QX", "SimdMiscOp", ("uint8_t",), 3, "false", 4) 285010037SARM gem5 Developers tbxTblInstX("tbx", "Tbx4DX", "SimdMiscOp", ("uint8_t",), 4, "false", 2) 285110037SARM gem5 Developers tbxTblInstX("tbx", "Tbx4QX", "SimdMiscOp", ("uint8_t",), 4, "false", 4) 285210037SARM gem5 Developers # TRN1 285310037SARM gem5 Developers trnCode = ''' 285410037SARM gem5 Developers unsigned part = %s; 285510037SARM gem5 Developers for (unsigned i = 0; i < eCount / 2; i++) { 285610037SARM gem5 Developers destReg.elements[2 * i] = srcReg1.elements[2 * i + part]; 285710037SARM gem5 Developers destReg.elements[2 * i + 1] = srcReg2.elements[2 * i + part]; 285810037SARM gem5 Developers } 285910037SARM gem5 Developers ''' 286010037SARM gem5 Developers threeRegScrambleInstX("trn1", "Trn1DX", "SimdAluOp", smallUnsignedTypes, 2, 286110037SARM gem5 Developers trnCode % "0") 286210037SARM gem5 Developers threeRegScrambleInstX("trn1", "Trn1QX", "SimdAluOp", unsignedTypes, 4, 286310037SARM gem5 Developers trnCode % "0") 286410037SARM gem5 Developers # TRN2 286510037SARM gem5 Developers threeRegScrambleInstX("trn2", "Trn2DX", "SimdAluOp", smallUnsignedTypes, 2, 286610037SARM gem5 Developers trnCode % "1") 286710037SARM gem5 Developers threeRegScrambleInstX("trn2", "Trn2QX", "SimdAluOp", unsignedTypes, 4, 286810037SARM gem5 Developers trnCode % "1") 286910037SARM gem5 Developers # UABA 287010037SARM gem5 Developers threeEqualRegInstX("uaba", "UabaDX", "SimdAddAccOp", smallUnsignedTypes, 2, 287110037SARM gem5 Developers abaCode, True) 287210037SARM gem5 Developers threeEqualRegInstX("uaba", "UabaQX", "SimdAddAccOp", smallUnsignedTypes, 4, 287310037SARM gem5 Developers abaCode, True) 287410037SARM gem5 Developers # UABAL, UABAL2 287510037SARM gem5 Developers threeRegLongInstX("uabal", "UabalX", "SimdAddAccOp", smallUnsignedTypes, 287610037SARM gem5 Developers abalCode, True) 287710037SARM gem5 Developers threeRegLongInstX("uabal2", "Uabal2X", "SimdAddAccOp", smallUnsignedTypes, 287810037SARM gem5 Developers abalCode, True, hi=True) 287910037SARM gem5 Developers # UABD 288010037SARM gem5 Developers threeEqualRegInstX("uabd", "UabdDX", "SimdAddOp", smallUnsignedTypes, 2, 288110037SARM gem5 Developers abdCode) 288210037SARM gem5 Developers threeEqualRegInstX("uabd", "UabdQX", "SimdAddOp", smallUnsignedTypes, 4, 288310037SARM gem5 Developers abdCode) 288410037SARM gem5 Developers # UABDL, UABDL2 288510037SARM gem5 Developers threeRegLongInstX("uabdl", "UabdlX", "SimdAddAccOp", smallUnsignedTypes, 288610037SARM gem5 Developers abdlCode, True) 288710037SARM gem5 Developers threeRegLongInstX("uabdl2", "Uabdl2X", "SimdAddAccOp", smallUnsignedTypes, 288810037SARM gem5 Developers abdlCode, True, hi=True) 288910037SARM gem5 Developers # UADALP 289010037SARM gem5 Developers twoRegCondenseInstX("uadalp", "UadalpDX", "SimdAddOp", smallUnsignedTypes, 289110037SARM gem5 Developers 2, adalpCode, True) 289210037SARM gem5 Developers twoRegCondenseInstX("uadalp", "UadalpQX", "SimdAddOp", smallUnsignedTypes, 289310037SARM gem5 Developers 4, adalpCode, True) 289410037SARM gem5 Developers # UADDL, UADDL2 289510037SARM gem5 Developers threeRegLongInstX("uaddl", "UaddlX", "SimdAddAccOp", smallUnsignedTypes, 289610037SARM gem5 Developers addlwCode) 289710037SARM gem5 Developers threeRegLongInstX("uaddl2", "Uaddl2X", "SimdAddAccOp", smallUnsignedTypes, 289810037SARM gem5 Developers addlwCode, hi=True) 289910037SARM gem5 Developers # UADDLP 290010037SARM gem5 Developers twoRegCondenseInstX("uaddlp", "UaddlpDX", "SimdAddOp", smallUnsignedTypes, 290110037SARM gem5 Developers 2, addlwCode) 290210037SARM gem5 Developers twoRegCondenseInstX("uaddlp", "UaddlpQX", "SimdAddOp", smallUnsignedTypes, 290310037SARM gem5 Developers 4, addlwCode) 290410037SARM gem5 Developers # UADDLV 290510037SARM gem5 Developers twoRegAcrossInstX("uaddlv", "UaddlvDX", "SimdAddOp", 290610037SARM gem5 Developers ("uint8_t", "uint16_t"), 2, addAcrossLongCode, long=True) 290710037SARM gem5 Developers twoRegAcrossInstX("uaddlv", "UaddlvQX", "SimdAddOp", 290810037SARM gem5 Developers ("uint8_t", "uint16_t"), 4, addAcrossLongCode, long=True) 290910037SARM gem5 Developers twoRegAcrossInstX("uaddlv", "UaddlvBQX", "SimdAddOp", ("uint32_t",), 4, 291010037SARM gem5 Developers addAcrossLongCode, doubleDest=True, long=True) 291110037SARM gem5 Developers # UADDW 291210037SARM gem5 Developers threeRegWideInstX("uaddw", "UaddwX", "SimdAddAccOp", smallUnsignedTypes, 291310037SARM gem5 Developers addlwCode) 291410037SARM gem5 Developers threeRegWideInstX("uaddw2", "Uaddw2X", "SimdAddAccOp", smallUnsignedTypes, 291510037SARM gem5 Developers addlwCode, hi=True) 291610037SARM gem5 Developers # UCVTF (fixed-point) 291710037SARM gem5 Developers ucvtfFixedCode = fpOp % ("fplibFixedToFP<Element>(srcElem1, imm, true," 291810037SARM gem5 Developers " FPCRRounding(fpscr), fpscr)") 291910037SARM gem5 Developers twoEqualRegInstX("ucvtf", "UcvtfFixedDX", "SimdCvtOp", smallFloatTypes, 2, 292010037SARM gem5 Developers ucvtfFixedCode, hasImm=True) 292110037SARM gem5 Developers twoEqualRegInstX("ucvtf", "UcvtfFixedQX", "SimdCvtOp", floatTypes, 4, 292210037SARM gem5 Developers ucvtfFixedCode, hasImm=True) 292310037SARM gem5 Developers twoEqualRegInstX("ucvtf", "UcvtfFixedScX", "SimdCvtOp", floatTypes, 4, 292410037SARM gem5 Developers ucvtfFixedCode, hasImm=True, scalar=True) 292510037SARM gem5 Developers # UCVTF (integer) 292610037SARM gem5 Developers ucvtfIntCode = fpOp % ("fplibFixedToFP<Element>(srcElem1, 0, true," 292710037SARM gem5 Developers " FPCRRounding(fpscr), fpscr)") 292810037SARM gem5 Developers twoEqualRegInstX("ucvtf", "UcvtfIntDX", "SimdCvtOp", smallFloatTypes, 2, 292910037SARM gem5 Developers ucvtfIntCode) 293010037SARM gem5 Developers twoEqualRegInstX("ucvtf", "UcvtfIntQX", "SimdCvtOp", floatTypes, 4, 293110037SARM gem5 Developers ucvtfIntCode) 293210037SARM gem5 Developers twoEqualRegInstX("ucvtf", "UcvtfIntScX", "SimdCvtOp", floatTypes, 4, 293310037SARM gem5 Developers ucvtfIntCode, scalar=True) 293410037SARM gem5 Developers # UHADD 293510037SARM gem5 Developers threeEqualRegInstX("uhadd", "UhaddDX", "SimdAddOp", smallUnsignedTypes, 2, 293610037SARM gem5 Developers haddCode) 293710037SARM gem5 Developers threeEqualRegInstX("uhadd", "UhaddQX", "SimdAddOp", smallUnsignedTypes, 4, 293810037SARM gem5 Developers haddCode) 293910037SARM gem5 Developers # UHSUB 294010037SARM gem5 Developers threeEqualRegInstX("uhsub", "UhsubDX", "SimdAddOp", smallUnsignedTypes, 2, 294110037SARM gem5 Developers hsubCode) 294210037SARM gem5 Developers threeEqualRegInstX("uhsub", "UhsubQX", "SimdAddOp", smallUnsignedTypes, 4, 294310037SARM gem5 Developers hsubCode) 294410037SARM gem5 Developers # UMAX 294510037SARM gem5 Developers threeEqualRegInstX("umax", "UmaxDX", "SimdCmpOp", smallUnsignedTypes, 2, 294610037SARM gem5 Developers maxCode) 294710037SARM gem5 Developers threeEqualRegInstX("umax", "UmaxQX", "SimdCmpOp", smallUnsignedTypes, 4, 294810037SARM gem5 Developers maxCode) 294910037SARM gem5 Developers # UMAXP 295010037SARM gem5 Developers threeEqualRegInstX("umaxp", "UmaxpDX", "SimdCmpOp", smallUnsignedTypes, 2, 295110037SARM gem5 Developers maxCode, pairwise=True) 295210037SARM gem5 Developers threeEqualRegInstX("umaxp", "UmaxpQX", "SimdCmpOp", smallUnsignedTypes, 4, 295310037SARM gem5 Developers maxCode, pairwise=True) 295410037SARM gem5 Developers # UMAXV 295510037SARM gem5 Developers twoRegAcrossInstX("umaxv", "UmaxvDX", "SimdCmpOp", ("uint8_t", "uint16_t"), 295610037SARM gem5 Developers 2, maxAcrossCode) 295710037SARM gem5 Developers twoRegAcrossInstX("umaxv", "UmaxvQX", "SimdCmpOp", smallUnsignedTypes, 4, 295810037SARM gem5 Developers maxAcrossCode) 295910037SARM gem5 Developers # UMIN 296010037SARM gem5 Developers threeEqualRegInstX("umin", "UminDX", "SimdCmpOp", smallUnsignedTypes, 2, 296110037SARM gem5 Developers minCode) 296210037SARM gem5 Developers threeEqualRegInstX("umin", "UminQX", "SimdCmpOp", smallUnsignedTypes, 4, 296310037SARM gem5 Developers minCode) 296410037SARM gem5 Developers # UMINP 296510037SARM gem5 Developers threeEqualRegInstX("uminp", "UminpDX", "SimdCmpOp", smallUnsignedTypes, 2, 296610037SARM gem5 Developers minCode, pairwise=True) 296710037SARM gem5 Developers threeEqualRegInstX("uminp", "UminpQX", "SimdCmpOp", smallUnsignedTypes, 4, 296810037SARM gem5 Developers minCode, pairwise=True) 296910037SARM gem5 Developers # UMINV 297010037SARM gem5 Developers twoRegAcrossInstX("uminv", "UminvDX", "SimdCmpOp", ("uint8_t", "uint16_t"), 297110037SARM gem5 Developers 2, minAcrossCode) 297210037SARM gem5 Developers twoRegAcrossInstX("uminv", "UminvQX", "SimdCmpOp", smallUnsignedTypes, 4, 297310037SARM gem5 Developers minAcrossCode) 297410037SARM gem5 Developers # UMLAL (by element) 297510037SARM gem5 Developers threeRegLongInstX("umlal", "UmlalElemX", "SimdMultAccOp", 297610037SARM gem5 Developers smallUnsignedTypes, mlalCode, True, byElem=True) 297710037SARM gem5 Developers threeRegLongInstX("umlal", "UmlalElem2X", "SimdMultAccOp", 297810037SARM gem5 Developers smallUnsignedTypes, mlalCode, True, byElem=True, hi=True) 297910037SARM gem5 Developers # UMLAL (vector) 298010037SARM gem5 Developers threeRegLongInstX("umlal", "UmlalX", "SimdMultAccOp", smallUnsignedTypes, 298110037SARM gem5 Developers mlalCode, True) 298210037SARM gem5 Developers threeRegLongInstX("umlal", "Umlal2X", "SimdMultAccOp", smallUnsignedTypes, 298310037SARM gem5 Developers mlalCode, True, hi=True) 298410037SARM gem5 Developers # UMLSL (by element) 298510037SARM gem5 Developers threeRegLongInstX("umlsl", "UmlslElemX", "SimdMultAccOp", 298610037SARM gem5 Developers smallUnsignedTypes, mlslCode, True, byElem=True) 298710037SARM gem5 Developers threeRegLongInstX("umlsl", "UmlslElem2X", "SimdMultAccOp", 298810037SARM gem5 Developers smallUnsignedTypes, mlslCode, True, byElem=True, hi=True) 298910037SARM gem5 Developers # UMLSL (vector) 299010037SARM gem5 Developers threeRegLongInstX("umlsl", "UmlslX", "SimdMultAccOp", smallUnsignedTypes, 299110037SARM gem5 Developers mlslCode, True) 299210037SARM gem5 Developers threeRegLongInstX("umlsl", "Umlsl2X", "SimdMultAccOp", smallUnsignedTypes, 299310037SARM gem5 Developers mlslCode, True, hi=True) 299410037SARM gem5 Developers # UMOV 299510037SARM gem5 Developers insToGprInstX("umov", "UmovWX", "SimdMiscOp", smallUnsignedTypes, 4, 'W') 299610037SARM gem5 Developers insToGprInstX("umov", "UmovXX", "SimdMiscOp", ("uint64_t",), 4, 'X') 299710037SARM gem5 Developers # UMULL, UMULL2 (by element) 299810037SARM gem5 Developers threeRegLongInstX("umull", "UmullElemX", "SimdMultOp", smallUnsignedTypes, 299910037SARM gem5 Developers mullCode, byElem=True) 300010037SARM gem5 Developers threeRegLongInstX("umull", "UmullElem2X", "SimdMultOp", smallUnsignedTypes, 300110037SARM gem5 Developers mullCode, byElem=True, hi=True) 300210037SARM gem5 Developers # UMULL, UMULL2 (vector) 300310037SARM gem5 Developers threeRegLongInstX("umull", "UmullX", "SimdMultOp", smallUnsignedTypes, 300410037SARM gem5 Developers mullCode) 300510037SARM gem5 Developers threeRegLongInstX("umull", "Umull2X", "SimdMultOp", smallUnsignedTypes, 300610037SARM gem5 Developers mullCode, hi=True) 300710037SARM gem5 Developers # UQADD 300810037SARM gem5 Developers uqaddCode = ''' 300910037SARM gem5 Developers destElem = srcElem1 + srcElem2; 301010037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 301110037SARM gem5 Developers if (destElem < srcElem1 || destElem < srcElem2) { 301210037SARM gem5 Developers destElem = (Element)(-1); 301310037SARM gem5 Developers fpscr.qc = 1; 301410037SARM gem5 Developers } 301510037SARM gem5 Developers FpscrQc = fpscr; 301610037SARM gem5 Developers ''' 301710037SARM gem5 Developers threeEqualRegInstX("uqadd", "UqaddDX", "SimdAddOp", smallUnsignedTypes, 2, 301810037SARM gem5 Developers uqaddCode) 301910037SARM gem5 Developers threeEqualRegInstX("uqadd", "UqaddQX", "SimdAddOp", unsignedTypes, 4, 302010037SARM gem5 Developers uqaddCode) 302110037SARM gem5 Developers threeEqualRegInstX("uqadd", "UqaddScX", "SimdAddOp", unsignedTypes, 4, 302210037SARM gem5 Developers uqaddCode, scalar=True) 302310037SARM gem5 Developers # UQRSHL 302410037SARM gem5 Developers uqrshlCode = ''' 302510037SARM gem5 Developers int16_t shiftAmt = (int8_t)srcElem2; 302610037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 302710037SARM gem5 Developers if (shiftAmt < 0) { 302810037SARM gem5 Developers shiftAmt = -shiftAmt; 302910037SARM gem5 Developers Element rBit = 0; 303010037SARM gem5 Developers if (shiftAmt <= sizeof(Element) * 8) 303110037SARM gem5 Developers rBit = bits(srcElem1, shiftAmt - 1); 303210037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 303310037SARM gem5 Developers shiftAmt = sizeof(Element) * 8 - 1; 303410037SARM gem5 Developers destElem = 0; 303510037SARM gem5 Developers } else { 303610037SARM gem5 Developers destElem = (srcElem1 >> shiftAmt); 303710037SARM gem5 Developers } 303810037SARM gem5 Developers destElem += rBit; 303910037SARM gem5 Developers } else { 304010037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 304110037SARM gem5 Developers if (srcElem1 != 0) { 304210037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 304310037SARM gem5 Developers fpscr.qc = 1; 304410037SARM gem5 Developers } else { 304510037SARM gem5 Developers destElem = 0; 304610037SARM gem5 Developers } 304710037SARM gem5 Developers } else { 304810037SARM gem5 Developers if (bits(srcElem1, sizeof(Element) * 8 - 1, 304910037SARM gem5 Developers sizeof(Element) * 8 - shiftAmt)) { 305010037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 305110037SARM gem5 Developers fpscr.qc = 1; 305210037SARM gem5 Developers } else { 305310037SARM gem5 Developers destElem = srcElem1 << shiftAmt; 305410037SARM gem5 Developers } 305510037SARM gem5 Developers } 305610037SARM gem5 Developers } 305710037SARM gem5 Developers FpscrQc = fpscr; 305810037SARM gem5 Developers ''' 305910037SARM gem5 Developers threeEqualRegInstX("uqrshl", "UqrshlDX", "SimdCmpOp", smallUnsignedTypes, 306010037SARM gem5 Developers 2, uqrshlCode) 306110037SARM gem5 Developers threeEqualRegInstX("uqrshl", "UqrshlQX", "SimdCmpOp", unsignedTypes, 4, 306210037SARM gem5 Developers uqrshlCode) 306310037SARM gem5 Developers threeEqualRegInstX("uqrshl", "UqrshlScX", "SimdCmpOp", unsignedTypes, 4, 306410037SARM gem5 Developers uqrshlCode, scalar=True) 306510037SARM gem5 Developers # UQRSHRN 306610037SARM gem5 Developers uqrshrnCode = ''' 306710037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 306810037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 306910037SARM gem5 Developers if (srcElem1 != 0) 307010037SARM gem5 Developers fpscr.qc = 1; 307110037SARM gem5 Developers destElem = 0; 307210037SARM gem5 Developers } else if (imm) { 307310037SARM gem5 Developers BigElement mid = (srcElem1 >> (imm - 1)); 307410037SARM gem5 Developers uint64_t rBit = mid & 0x1; 307510037SARM gem5 Developers mid >>= 1; 307610037SARM gem5 Developers mid += rBit; 307710037SARM gem5 Developers if (mid != (Element)mid) { 307810037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 307910037SARM gem5 Developers fpscr.qc = 1; 308010037SARM gem5 Developers } else { 308110037SARM gem5 Developers destElem = mid; 308210037SARM gem5 Developers } 308310037SARM gem5 Developers } else { 308410037SARM gem5 Developers if (srcElem1 != (Element)srcElem1) { 308510037SARM gem5 Developers destElem = mask(sizeof(Element) * 8 - 1); 308610037SARM gem5 Developers fpscr.qc = 1; 308710037SARM gem5 Developers } else { 308810037SARM gem5 Developers destElem = srcElem1; 308910037SARM gem5 Developers } 309010037SARM gem5 Developers } 309110037SARM gem5 Developers FpscrQc = fpscr; 309210037SARM gem5 Developers ''' 309310037SARM gem5 Developers twoRegNarrowInstX("uqrshrn", "UqrshrnX", "SimdShiftOp", smallUnsignedTypes, 309410037SARM gem5 Developers uqrshrnCode, hasImm=True) 309510037SARM gem5 Developers twoRegNarrowInstX("uqrshrn2", "Uqrshrn2X", "SimdShiftOp", 309610037SARM gem5 Developers smallUnsignedTypes, uqrshrnCode, hasImm=True, hi=True) 309710037SARM gem5 Developers twoRegNarrowInstX("uqrshrn", "UqrshrnScX", "SimdShiftOp", 309810037SARM gem5 Developers smallUnsignedTypes, uqrshrnCode, hasImm=True, 309910037SARM gem5 Developers scalar=True) 310010037SARM gem5 Developers # UQSHL (immediate) 310110037SARM gem5 Developers uqshlImmCode = ''' 310210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 310310037SARM gem5 Developers if (imm >= sizeof(Element) * 8) { 310410037SARM gem5 Developers if (srcElem1 != 0) { 310510037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 310610037SARM gem5 Developers fpscr.qc = 1; 310710037SARM gem5 Developers } else { 310810037SARM gem5 Developers destElem = 0; 310910037SARM gem5 Developers } 311010037SARM gem5 Developers } else if (imm) { 311110037SARM gem5 Developers destElem = (srcElem1 << imm); 311210037SARM gem5 Developers uint64_t topBits = bits((uint64_t)srcElem1, 311310037SARM gem5 Developers sizeof(Element) * 8 - 1, 311410037SARM gem5 Developers sizeof(Element) * 8 - imm); 311510037SARM gem5 Developers if (topBits != 0) { 311610037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 311710037SARM gem5 Developers fpscr.qc = 1; 311810037SARM gem5 Developers } 311910037SARM gem5 Developers } else { 312010037SARM gem5 Developers destElem = srcElem1; 312110037SARM gem5 Developers } 312210037SARM gem5 Developers FpscrQc = fpscr; 312310037SARM gem5 Developers ''' 312410037SARM gem5 Developers twoEqualRegInstX("uqshl", "UqshlImmDX", "SimdAluOp", smallUnsignedTypes, 2, 312510037SARM gem5 Developers uqshlImmCode, hasImm=True) 312610037SARM gem5 Developers twoEqualRegInstX("uqshl", "UqshlImmQX", "SimdAluOp", unsignedTypes, 4, 312710037SARM gem5 Developers uqshlImmCode, hasImm=True) 312810037SARM gem5 Developers twoEqualRegInstX("uqshl", "UqshlImmScX", "SimdAluOp", unsignedTypes, 4, 312910037SARM gem5 Developers uqshlImmCode, hasImm=True, scalar=True) 313010037SARM gem5 Developers # UQSHL (register) 313110037SARM gem5 Developers uqshlCode = ''' 313210037SARM gem5 Developers int16_t shiftAmt = (int8_t)srcElem2; 313310037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 313410037SARM gem5 Developers if (shiftAmt < 0) { 313510037SARM gem5 Developers shiftAmt = -shiftAmt; 313610037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 313710037SARM gem5 Developers shiftAmt = sizeof(Element) * 8 - 1; 313810037SARM gem5 Developers destElem = 0; 313910037SARM gem5 Developers } else { 314010037SARM gem5 Developers destElem = (srcElem1 >> shiftAmt); 314110037SARM gem5 Developers } 314210037SARM gem5 Developers } else if (shiftAmt > 0) { 314310037SARM gem5 Developers if (shiftAmt >= sizeof(Element) * 8) { 314410037SARM gem5 Developers if (srcElem1 != 0) { 314510037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 314610037SARM gem5 Developers fpscr.qc = 1; 314710037SARM gem5 Developers } else { 314810037SARM gem5 Developers destElem = 0; 314910037SARM gem5 Developers } 315010037SARM gem5 Developers } else { 315110037SARM gem5 Developers if (bits(srcElem1, sizeof(Element) * 8 - 1, 315210037SARM gem5 Developers sizeof(Element) * 8 - shiftAmt)) { 315310037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 315410037SARM gem5 Developers fpscr.qc = 1; 315510037SARM gem5 Developers } else { 315610037SARM gem5 Developers destElem = srcElem1 << shiftAmt; 315710037SARM gem5 Developers } 315810037SARM gem5 Developers } 315910037SARM gem5 Developers } else { 316010037SARM gem5 Developers destElem = srcElem1; 316110037SARM gem5 Developers } 316210037SARM gem5 Developers FpscrQc = fpscr; 316310037SARM gem5 Developers ''' 316410037SARM gem5 Developers threeEqualRegInstX("uqshl", "UqshlDX", "SimdAluOp", smallUnsignedTypes, 2, 316510037SARM gem5 Developers uqshlCode) 316610037SARM gem5 Developers threeEqualRegInstX("uqshl", "UqshlQX", "SimdAluOp", unsignedTypes, 4, 316710037SARM gem5 Developers uqshlCode) 316810037SARM gem5 Developers threeEqualRegInstX("uqshl", "UqshlScX", "SimdAluOp", unsignedTypes, 4, 316910037SARM gem5 Developers uqshlCode, scalar=True) 317010037SARM gem5 Developers # UQSHRN, UQSHRN2 317110037SARM gem5 Developers uqshrnCode = ''' 317210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 317310037SARM gem5 Developers if (imm > sizeof(srcElem1) * 8) { 317410037SARM gem5 Developers if (srcElem1 != 0) 317510037SARM gem5 Developers fpscr.qc = 1; 317610037SARM gem5 Developers destElem = 0; 317710037SARM gem5 Developers } else if (imm) { 317810037SARM gem5 Developers BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 317910037SARM gem5 Developers if (mid != (Element)mid) { 318010037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 318110037SARM gem5 Developers fpscr.qc = 1; 318210037SARM gem5 Developers } else { 318310037SARM gem5 Developers destElem = mid; 318410037SARM gem5 Developers } 318510037SARM gem5 Developers } else { 318610037SARM gem5 Developers destElem = srcElem1; 318710037SARM gem5 Developers } 318810037SARM gem5 Developers FpscrQc = fpscr; 318910037SARM gem5 Developers ''' 319010037SARM gem5 Developers twoRegNarrowInstX("uqshrn", "UqshrnX", "SimdShiftOp", smallUnsignedTypes, 319110037SARM gem5 Developers uqshrnCode, hasImm=True) 319210037SARM gem5 Developers twoRegNarrowInstX("uqshrn2", "Uqshrn2X", "SimdShiftOp", smallUnsignedTypes, 319310037SARM gem5 Developers uqshrnCode, hasImm=True, hi=True) 319410037SARM gem5 Developers twoRegNarrowInstX("uqshrn", "UqshrnScX", "SimdShiftOp", smallUnsignedTypes, 319510037SARM gem5 Developers uqshrnCode, hasImm=True, scalar=True) 319610037SARM gem5 Developers # UQSUB 319710037SARM gem5 Developers uqsubCode = ''' 319810037SARM gem5 Developers destElem = srcElem1 - srcElem2; 319910037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 320010037SARM gem5 Developers if (destElem > srcElem1) { 320110037SARM gem5 Developers destElem = 0; 320210037SARM gem5 Developers fpscr.qc = 1; 320310037SARM gem5 Developers } 320410037SARM gem5 Developers FpscrQc = fpscr; 320510037SARM gem5 Developers ''' 320610037SARM gem5 Developers threeEqualRegInstX("uqsub", "UqsubDX", "SimdAddOp", smallUnsignedTypes, 2, 320710037SARM gem5 Developers uqsubCode) 320810037SARM gem5 Developers threeEqualRegInstX("uqsub", "UqsubQX", "SimdAddOp", unsignedTypes, 4, 320910037SARM gem5 Developers uqsubCode) 321010037SARM gem5 Developers threeEqualRegInstX("uqsub", "UqsubScX", "SimdAddOp", unsignedTypes, 4, 321110037SARM gem5 Developers uqsubCode, scalar=True) 321210037SARM gem5 Developers # UQXTN 321310037SARM gem5 Developers uqxtnCode = ''' 321410037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 321510037SARM gem5 Developers destElem = srcElem1; 321610037SARM gem5 Developers if ((BigElement)destElem != srcElem1) { 321710037SARM gem5 Developers fpscr.qc = 1; 321810037SARM gem5 Developers destElem = mask(sizeof(Element) * 8); 321910037SARM gem5 Developers } 322010037SARM gem5 Developers FpscrQc = fpscr; 322110037SARM gem5 Developers ''' 322210037SARM gem5 Developers twoRegNarrowInstX("uqxtn", "UqxtnX", "SimdMiscOp", smallUnsignedTypes, 322310037SARM gem5 Developers uqxtnCode) 322410037SARM gem5 Developers twoRegNarrowInstX("uqxtn", "Uqxtn2X", "SimdMiscOp", smallUnsignedTypes, 322510037SARM gem5 Developers uqxtnCode, hi=True) 322610037SARM gem5 Developers twoRegNarrowInstX("uqxtn", "UqxtnScX", "SimdMiscOp", smallUnsignedTypes, 322710037SARM gem5 Developers uqxtnCode, scalar=True) 322810037SARM gem5 Developers # URECPE 322910037SARM gem5 Developers urecpeCode = "destElem = unsignedRecipEstimate(srcElem1);" 323010037SARM gem5 Developers twoEqualRegInstX("urecpe", "UrecpeDX", "SimdMultAccOp", ("uint32_t",), 2, 323110037SARM gem5 Developers urecpeCode) 323210037SARM gem5 Developers twoEqualRegInstX("urecpe", "UrecpeQX", "SimdMultAccOp", ("uint32_t",), 4, 323310037SARM gem5 Developers urecpeCode) 323410037SARM gem5 Developers # URHADD 323510037SARM gem5 Developers threeEqualRegInstX("urhadd", "UrhaddDX", "SimdAddOp", smallUnsignedTypes, 323610037SARM gem5 Developers 2, rhaddCode) 323710037SARM gem5 Developers threeEqualRegInstX("urhadd", "UrhaddQX", "SimdAddOp", smallUnsignedTypes, 323810037SARM gem5 Developers 4, rhaddCode) 323910037SARM gem5 Developers # URSHL 324010037SARM gem5 Developers threeEqualRegInstX("urshl", "UrshlDX", "SimdShiftOp", unsignedTypes, 2, 324110037SARM gem5 Developers rshlCode) 324210037SARM gem5 Developers threeEqualRegInstX("urshl", "UrshlQX", "SimdShiftOp", unsignedTypes, 4, 324310037SARM gem5 Developers rshlCode) 324410037SARM gem5 Developers # URSHR 324510037SARM gem5 Developers twoEqualRegInstX("urshr", "UrshrDX", "SimdShiftOp", unsignedTypes, 2, 324610037SARM gem5 Developers rshrCode, hasImm=True) 324710037SARM gem5 Developers twoEqualRegInstX("urshr", "UrshrQX", "SimdShiftOp", unsignedTypes, 4, 324810037SARM gem5 Developers rshrCode, hasImm=True) 324910037SARM gem5 Developers # URSQRTE 325010037SARM gem5 Developers ursqrteCode = "destElem = unsignedRSqrtEstimate(srcElem1);" 325110037SARM gem5 Developers twoEqualRegInstX("ursqrte", "UrsqrteDX", "SimdSqrtOp", ("uint32_t",), 2, 325210037SARM gem5 Developers ursqrteCode) 325310037SARM gem5 Developers twoEqualRegInstX("ursqrte", "UrsqrteQX", "SimdSqrtOp", ("uint32_t",), 4, 325410037SARM gem5 Developers ursqrteCode) 325510037SARM gem5 Developers # URSRA 325610037SARM gem5 Developers twoEqualRegInstX("ursra", "UrsraDX", "SimdShiftOp", unsignedTypes, 2, 325710037SARM gem5 Developers rsraCode, True, hasImm=True) 325810037SARM gem5 Developers twoEqualRegInstX("ursra", "UrsraQX", "SimdShiftOp", unsignedTypes, 4, 325910037SARM gem5 Developers rsraCode, True, hasImm=True) 326010037SARM gem5 Developers # USHL 326110037SARM gem5 Developers threeEqualRegInstX("ushl", "UshlDX", "SimdShiftOp", unsignedTypes, 2, 326210037SARM gem5 Developers shlCode) 326310037SARM gem5 Developers threeEqualRegInstX("ushl", "UshlQX", "SimdShiftOp", unsignedTypes, 4, 326410037SARM gem5 Developers shlCode) 326510037SARM gem5 Developers # USHLL, USHLL2 326610037SARM gem5 Developers twoRegLongInstX("ushll", "UshllX", "SimdShiftOp", smallUnsignedTypes, 326710037SARM gem5 Developers shllCode, hasImm=True) 326810037SARM gem5 Developers twoRegLongInstX("ushll", "Ushll2X", "SimdShiftOp", smallUnsignedTypes, 326910037SARM gem5 Developers shllCode, hi=True, hasImm=True) 327010037SARM gem5 Developers # USHR 327110037SARM gem5 Developers twoEqualRegInstX("ushr", "UshrDX", "SimdShiftOp", unsignedTypes, 2, 327210037SARM gem5 Developers shrCode, hasImm=True) 327310037SARM gem5 Developers twoEqualRegInstX("ushr", "UshrQX", "SimdShiftOp", unsignedTypes, 4, 327410037SARM gem5 Developers shrCode, hasImm=True) 327510037SARM gem5 Developers # USQADD 327610037SARM gem5 Developers usqaddCode = ''' 327710037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrQc; 327810037SARM gem5 Developers Element tmp = destElem + srcElem1; 327910037SARM gem5 Developers if (bits(srcElem1, sizeof(Element) * 8 - 1) == 0) { 328010037SARM gem5 Developers if (tmp < srcElem1 || tmp < destElem) { 328110037SARM gem5 Developers destElem = (Element)(-1); 328210037SARM gem5 Developers fpscr.qc = 1; 328310037SARM gem5 Developers } else { 328410037SARM gem5 Developers destElem = tmp; 328510037SARM gem5 Developers } 328610037SARM gem5 Developers } else { 328710037SARM gem5 Developers Element absSrcElem1 = (~srcElem1) + 1; 328810037SARM gem5 Developers if (absSrcElem1 > destElem) { 328910037SARM gem5 Developers destElem = 0; 329010037SARM gem5 Developers fpscr.qc = 1; 329110037SARM gem5 Developers } else { 329210037SARM gem5 Developers destElem = tmp; 329310037SARM gem5 Developers } 329410037SARM gem5 Developers } 329510037SARM gem5 Developers FpscrQc = fpscr; 329610037SARM gem5 Developers ''' 329710037SARM gem5 Developers twoEqualRegInstX("usqadd", "UsqaddDX", "SimdAddOp", smallUnsignedTypes, 2, 329810037SARM gem5 Developers usqaddCode, True) 329910037SARM gem5 Developers twoEqualRegInstX("usqadd", "UsqaddQX", "SimdAddOp", unsignedTypes, 4, 330010037SARM gem5 Developers usqaddCode, True) 330110037SARM gem5 Developers twoEqualRegInstX("usqadd", "UsqaddScX", "SimdAddOp", unsignedTypes, 4, 330210037SARM gem5 Developers usqaddCode, True, scalar=True) 330310037SARM gem5 Developers # USRA 330410037SARM gem5 Developers twoEqualRegInstX("usra", "UsraDX", "SimdShiftOp", unsignedTypes, 2, 330510037SARM gem5 Developers sraCode, True, hasImm=True) 330610037SARM gem5 Developers twoEqualRegInstX("usra", "UsraQX", "SimdShiftOp", unsignedTypes, 4, 330710037SARM gem5 Developers sraCode, True, hasImm=True) 330810037SARM gem5 Developers # USUBL 330910037SARM gem5 Developers threeRegLongInstX("usubl", "UsublX", "SimdAddOp", smallUnsignedTypes, 331010037SARM gem5 Developers sublwCode) 331110037SARM gem5 Developers threeRegLongInstX("usubl2", "Usubl2X", "SimdAddOp", smallUnsignedTypes, 331210037SARM gem5 Developers sublwCode, hi=True) 331310037SARM gem5 Developers # USUBW 331410037SARM gem5 Developers threeRegWideInstX("usubw", "UsubwX", "SimdAddOp", smallUnsignedTypes, 331510037SARM gem5 Developers sublwCode) 331610037SARM gem5 Developers threeRegWideInstX("usubw2", "Usubw2X", "SimdAddOp", smallUnsignedTypes, 331710037SARM gem5 Developers sublwCode, hi=True) 331810037SARM gem5 Developers # UXTL -> alias to USHLL 331910037SARM gem5 Developers # UZP1 332010037SARM gem5 Developers uzpCode = ''' 332110037SARM gem5 Developers unsigned part = %s; 332210037SARM gem5 Developers for (unsigned i = 0; i < eCount / 2; i++) { 332310037SARM gem5 Developers destReg.elements[i] = srcReg1.elements[2 * i + part]; 332410037SARM gem5 Developers destReg.elements[eCount / 2 + i] = srcReg2.elements[2 * i + part]; 332510037SARM gem5 Developers } 332610037SARM gem5 Developers ''' 332710037SARM gem5 Developers threeRegScrambleInstX("Uzp1", "Uzp1DX", "SimdAluOp", smallUnsignedTypes, 2, 332810037SARM gem5 Developers uzpCode % "0") 332910037SARM gem5 Developers threeRegScrambleInstX("Uzp1", "Uzp1QX", "SimdAluOp", unsignedTypes, 4, 333010037SARM gem5 Developers uzpCode % "0") 333110037SARM gem5 Developers # UZP2 333210037SARM gem5 Developers threeRegScrambleInstX("Uzp2", "Uzp2DX", "SimdAluOp", smallUnsignedTypes, 2, 333310037SARM gem5 Developers uzpCode % "1") 333410037SARM gem5 Developers threeRegScrambleInstX("Uzp2", "Uzp2QX", "SimdAluOp", unsignedTypes, 4, 333510037SARM gem5 Developers uzpCode % "1") 333610037SARM gem5 Developers # XTN, XTN2 333710037SARM gem5 Developers xtnCode = "destElem = srcElem1;" 333810037SARM gem5 Developers twoRegNarrowInstX("Xtn", "XtnX", "SimdMiscOp", smallUnsignedTypes, xtnCode) 333910037SARM gem5 Developers twoRegNarrowInstX("Xtn", "Xtn2X", "SimdMiscOp", smallUnsignedTypes, 334010037SARM gem5 Developers xtnCode, hi=True) 334110037SARM gem5 Developers # ZIP1 334210037SARM gem5 Developers zipCode = ''' 334310037SARM gem5 Developers unsigned base = %s; 334410037SARM gem5 Developers for (unsigned i = 0; i < eCount / 2; i++) { 334510037SARM gem5 Developers destReg.elements[2 * i] = srcReg1.elements[base + i]; 334610037SARM gem5 Developers destReg.elements[2 * i + 1] = srcReg2.elements[base + i]; 334710037SARM gem5 Developers } 334810037SARM gem5 Developers ''' 334910037SARM gem5 Developers threeRegScrambleInstX("zip1", "Zip1DX", "SimdAluOp", smallUnsignedTypes, 2, 335010037SARM gem5 Developers zipCode % "0") 335110037SARM gem5 Developers threeRegScrambleInstX("zip1", "Zip1QX", "SimdAluOp", unsignedTypes, 4, 335210037SARM gem5 Developers zipCode % "0") 335310037SARM gem5 Developers # ZIP2 335410037SARM gem5 Developers threeRegScrambleInstX("zip2", "Zip2DX", "SimdAluOp", smallUnsignedTypes, 2, 335510037SARM gem5 Developers zipCode % "eCount / 2") 335610037SARM gem5 Developers threeRegScrambleInstX("zip2", "Zip2QX", "SimdAluOp", unsignedTypes, 4, 335710037SARM gem5 Developers zipCode % "eCount / 2") 335810037SARM gem5 Developers 335910037SARM gem5 Developers}}; 3360