neon.isa revision 8607
17639Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27639Sgblack@eecs.umich.edu 37639Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47639Sgblack@eecs.umich.edu// All rights reserved 57639Sgblack@eecs.umich.edu// 67639Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77639Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87639Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97639Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107639Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117639Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127639Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137639Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147639Sgblack@eecs.umich.edu// 157639Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167639Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177639Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187639Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197639Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207639Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217639Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227639Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237639Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247639Sgblack@eecs.umich.edu// this software without specific prior written permission. 257639Sgblack@eecs.umich.edu// 267639Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277639Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287639Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297639Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307639Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317639Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327639Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337639Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347639Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357639Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367639Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377639Sgblack@eecs.umich.edu// 387639Sgblack@eecs.umich.edu// Authors: Gabe Black 397639Sgblack@eecs.umich.edu 407639Sgblack@eecs.umich.eduoutput header {{ 417639Sgblack@eecs.umich.edu template <template <typename T> class Base> 427639Sgblack@eecs.umich.edu StaticInstPtr 437639Sgblack@eecs.umich.edu decodeNeonUThreeUReg(unsigned size, 447639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 457639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 467639Sgblack@eecs.umich.edu { 477639Sgblack@eecs.umich.edu switch (size) { 487639Sgblack@eecs.umich.edu case 0: 497639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1, op2); 507639Sgblack@eecs.umich.edu case 1: 517639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1, op2); 527639Sgblack@eecs.umich.edu case 2: 537639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1, op2); 547639Sgblack@eecs.umich.edu case 3: 557639Sgblack@eecs.umich.edu return new Base<uint64_t>(machInst, dest, op1, op2); 567639Sgblack@eecs.umich.edu default: 577639Sgblack@eecs.umich.edu return new Unknown(machInst); 587639Sgblack@eecs.umich.edu } 597639Sgblack@eecs.umich.edu } 607639Sgblack@eecs.umich.edu 617639Sgblack@eecs.umich.edu template <template <typename T> class Base> 627639Sgblack@eecs.umich.edu StaticInstPtr 637639Sgblack@eecs.umich.edu decodeNeonSThreeUReg(unsigned size, 647639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 657639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 667639Sgblack@eecs.umich.edu { 677639Sgblack@eecs.umich.edu switch (size) { 687639Sgblack@eecs.umich.edu case 0: 697639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1, op2); 707639Sgblack@eecs.umich.edu case 1: 717639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1, op2); 727639Sgblack@eecs.umich.edu case 2: 737639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1, op2); 747639Sgblack@eecs.umich.edu case 3: 757639Sgblack@eecs.umich.edu return new Base<int64_t>(machInst, dest, op1, op2); 767639Sgblack@eecs.umich.edu default: 777639Sgblack@eecs.umich.edu return new Unknown(machInst); 787639Sgblack@eecs.umich.edu } 797639Sgblack@eecs.umich.edu } 807639Sgblack@eecs.umich.edu 817639Sgblack@eecs.umich.edu template <template <typename T> class Base> 827639Sgblack@eecs.umich.edu StaticInstPtr 837639Sgblack@eecs.umich.edu decodeNeonUSThreeUReg(bool notSigned, unsigned size, 847639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 857639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 867639Sgblack@eecs.umich.edu { 877639Sgblack@eecs.umich.edu if (notSigned) { 887639Sgblack@eecs.umich.edu return decodeNeonUThreeUReg<Base>(size, machInst, dest, op1, op2); 897639Sgblack@eecs.umich.edu } else { 907639Sgblack@eecs.umich.edu return decodeNeonSThreeUReg<Base>(size, machInst, dest, op1, op2); 917639Sgblack@eecs.umich.edu } 927639Sgblack@eecs.umich.edu } 937639Sgblack@eecs.umich.edu 947639Sgblack@eecs.umich.edu template <template <typename T> class Base> 957639Sgblack@eecs.umich.edu StaticInstPtr 967639Sgblack@eecs.umich.edu decodeNeonUThreeUSReg(unsigned size, 977639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 987639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 997639Sgblack@eecs.umich.edu { 1007639Sgblack@eecs.umich.edu switch (size) { 1017639Sgblack@eecs.umich.edu case 0: 1027639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1, op2); 1037639Sgblack@eecs.umich.edu case 1: 1047639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1, op2); 1057639Sgblack@eecs.umich.edu case 2: 1067639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1, op2); 1077639Sgblack@eecs.umich.edu default: 1087639Sgblack@eecs.umich.edu return new Unknown(machInst); 1097639Sgblack@eecs.umich.edu } 1107639Sgblack@eecs.umich.edu } 1117639Sgblack@eecs.umich.edu 1127639Sgblack@eecs.umich.edu template <template <typename T> class Base> 1137639Sgblack@eecs.umich.edu StaticInstPtr 1147639Sgblack@eecs.umich.edu decodeNeonSThreeUSReg(unsigned size, 1157639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1167639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1177639Sgblack@eecs.umich.edu { 1187639Sgblack@eecs.umich.edu switch (size) { 1197639Sgblack@eecs.umich.edu case 0: 1207639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1, op2); 1217639Sgblack@eecs.umich.edu case 1: 1227639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1, op2); 1237639Sgblack@eecs.umich.edu case 2: 1247639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1, op2); 1257639Sgblack@eecs.umich.edu default: 1267639Sgblack@eecs.umich.edu return new Unknown(machInst); 1277639Sgblack@eecs.umich.edu } 1287639Sgblack@eecs.umich.edu } 1297639Sgblack@eecs.umich.edu 1307639Sgblack@eecs.umich.edu template <template <typename T> class Base> 1317639Sgblack@eecs.umich.edu StaticInstPtr 1327639Sgblack@eecs.umich.edu decodeNeonUSThreeUSReg(bool notSigned, unsigned size, 1337639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1347639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1357639Sgblack@eecs.umich.edu { 1367639Sgblack@eecs.umich.edu if (notSigned) { 1377639Sgblack@eecs.umich.edu return decodeNeonUThreeUSReg<Base>( 1387639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1397639Sgblack@eecs.umich.edu } else { 1407639Sgblack@eecs.umich.edu return decodeNeonSThreeUSReg<Base>( 1417639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1427639Sgblack@eecs.umich.edu } 1437639Sgblack@eecs.umich.edu } 1447639Sgblack@eecs.umich.edu 1457639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 1467639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 1477639Sgblack@eecs.umich.edu StaticInstPtr 1487639Sgblack@eecs.umich.edu decodeNeonUThreeSReg(bool q, unsigned size, 1497639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1507639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1517639Sgblack@eecs.umich.edu { 1527639Sgblack@eecs.umich.edu if (q) { 1537639Sgblack@eecs.umich.edu return decodeNeonUThreeUSReg<BaseQ>( 1547639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1557639Sgblack@eecs.umich.edu } else { 1567639Sgblack@eecs.umich.edu return decodeNeonUThreeUSReg<BaseD>( 1577639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1587639Sgblack@eecs.umich.edu } 1597639Sgblack@eecs.umich.edu } 1607639Sgblack@eecs.umich.edu 1617639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 1627639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 1637639Sgblack@eecs.umich.edu StaticInstPtr 1647639Sgblack@eecs.umich.edu decodeNeonSThreeSReg(bool q, unsigned size, 1657639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1667639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1677639Sgblack@eecs.umich.edu { 1687639Sgblack@eecs.umich.edu if (q) { 1697639Sgblack@eecs.umich.edu return decodeNeonSThreeUSReg<BaseQ>( 1707639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1717639Sgblack@eecs.umich.edu } else { 1727639Sgblack@eecs.umich.edu return decodeNeonSThreeUSReg<BaseD>( 1737639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1747639Sgblack@eecs.umich.edu } 1757639Sgblack@eecs.umich.edu } 1767639Sgblack@eecs.umich.edu 1777639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 1787639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 1797639Sgblack@eecs.umich.edu StaticInstPtr 1807639Sgblack@eecs.umich.edu decodeNeonUSThreeSReg(bool q, bool notSigned, unsigned size, 1817639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1827639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1837639Sgblack@eecs.umich.edu { 1847639Sgblack@eecs.umich.edu if (notSigned) { 1857639Sgblack@eecs.umich.edu return decodeNeonUThreeSReg<BaseD, BaseQ>( 1867639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 1877639Sgblack@eecs.umich.edu } else { 1887639Sgblack@eecs.umich.edu return decodeNeonSThreeSReg<BaseD, BaseQ>( 1897639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 1907639Sgblack@eecs.umich.edu } 1917639Sgblack@eecs.umich.edu } 1927639Sgblack@eecs.umich.edu 1937639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 1947639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 1957639Sgblack@eecs.umich.edu StaticInstPtr 1967639Sgblack@eecs.umich.edu decodeNeonUThreeReg(bool q, unsigned size, 1977639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1987639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1997639Sgblack@eecs.umich.edu { 2007639Sgblack@eecs.umich.edu if (q) { 2017639Sgblack@eecs.umich.edu return decodeNeonUThreeUReg<BaseQ>( 2027639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2037639Sgblack@eecs.umich.edu } else { 2047639Sgblack@eecs.umich.edu return decodeNeonUThreeUReg<BaseD>( 2057639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2067639Sgblack@eecs.umich.edu } 2077639Sgblack@eecs.umich.edu } 2087639Sgblack@eecs.umich.edu 2097639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2107639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2117639Sgblack@eecs.umich.edu StaticInstPtr 2127639Sgblack@eecs.umich.edu decodeNeonSThreeReg(bool q, unsigned size, 2137639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2147639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 2157639Sgblack@eecs.umich.edu { 2167639Sgblack@eecs.umich.edu if (q) { 2177639Sgblack@eecs.umich.edu return decodeNeonSThreeUReg<BaseQ>( 2187639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2197639Sgblack@eecs.umich.edu } else { 2207639Sgblack@eecs.umich.edu return decodeNeonSThreeUReg<BaseD>( 2217639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2227639Sgblack@eecs.umich.edu } 2237639Sgblack@eecs.umich.edu } 2247639Sgblack@eecs.umich.edu 2257639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2267639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2277639Sgblack@eecs.umich.edu StaticInstPtr 2287639Sgblack@eecs.umich.edu decodeNeonUSThreeReg(bool q, bool notSigned, unsigned size, 2297639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2307639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 2317639Sgblack@eecs.umich.edu { 2327639Sgblack@eecs.umich.edu if (notSigned) { 2337639Sgblack@eecs.umich.edu return decodeNeonUThreeReg<BaseD, BaseQ>( 2347639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 2357639Sgblack@eecs.umich.edu } else { 2367639Sgblack@eecs.umich.edu return decodeNeonSThreeReg<BaseD, BaseQ>( 2377639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 2387639Sgblack@eecs.umich.edu } 2397639Sgblack@eecs.umich.edu } 2407639Sgblack@eecs.umich.edu 2417639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2427639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2437639Sgblack@eecs.umich.edu StaticInstPtr 2447639Sgblack@eecs.umich.edu decodeNeonUTwoShiftReg(bool q, unsigned size, 2457639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2467639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 2477639Sgblack@eecs.umich.edu { 2487639Sgblack@eecs.umich.edu if (q) { 2497639Sgblack@eecs.umich.edu switch (size) { 2507639Sgblack@eecs.umich.edu case 0: 2517639Sgblack@eecs.umich.edu return new BaseQ<uint8_t>(machInst, dest, op1, imm); 2527639Sgblack@eecs.umich.edu case 1: 2537639Sgblack@eecs.umich.edu return new BaseQ<uint16_t>(machInst, dest, op1, imm); 2547639Sgblack@eecs.umich.edu case 2: 2557639Sgblack@eecs.umich.edu return new BaseQ<uint32_t>(machInst, dest, op1, imm); 2567639Sgblack@eecs.umich.edu case 3: 2577639Sgblack@eecs.umich.edu return new BaseQ<uint64_t>(machInst, dest, op1, imm); 2587639Sgblack@eecs.umich.edu default: 2597639Sgblack@eecs.umich.edu return new Unknown(machInst); 2607639Sgblack@eecs.umich.edu } 2617639Sgblack@eecs.umich.edu } else { 2627639Sgblack@eecs.umich.edu switch (size) { 2637639Sgblack@eecs.umich.edu case 0: 2647639Sgblack@eecs.umich.edu return new BaseD<uint8_t>(machInst, dest, op1, imm); 2657639Sgblack@eecs.umich.edu case 1: 2667639Sgblack@eecs.umich.edu return new BaseD<uint16_t>(machInst, dest, op1, imm); 2677639Sgblack@eecs.umich.edu case 2: 2687639Sgblack@eecs.umich.edu return new BaseD<uint32_t>(machInst, dest, op1, imm); 2697639Sgblack@eecs.umich.edu case 3: 2707639Sgblack@eecs.umich.edu return new BaseD<uint64_t>(machInst, dest, op1, imm); 2717639Sgblack@eecs.umich.edu default: 2727639Sgblack@eecs.umich.edu return new Unknown(machInst); 2737639Sgblack@eecs.umich.edu } 2747639Sgblack@eecs.umich.edu } 2757639Sgblack@eecs.umich.edu } 2767639Sgblack@eecs.umich.edu 2777639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2787639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2797639Sgblack@eecs.umich.edu StaticInstPtr 2807639Sgblack@eecs.umich.edu decodeNeonSTwoShiftReg(bool q, unsigned size, 2817639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2827639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 2837639Sgblack@eecs.umich.edu { 2847639Sgblack@eecs.umich.edu if (q) { 2857639Sgblack@eecs.umich.edu switch (size) { 2867639Sgblack@eecs.umich.edu case 0: 2877639Sgblack@eecs.umich.edu return new BaseQ<int8_t>(machInst, dest, op1, imm); 2887639Sgblack@eecs.umich.edu case 1: 2897639Sgblack@eecs.umich.edu return new BaseQ<int16_t>(machInst, dest, op1, imm); 2907639Sgblack@eecs.umich.edu case 2: 2917639Sgblack@eecs.umich.edu return new BaseQ<int32_t>(machInst, dest, op1, imm); 2927639Sgblack@eecs.umich.edu case 3: 2937639Sgblack@eecs.umich.edu return new BaseQ<int64_t>(machInst, dest, op1, imm); 2947639Sgblack@eecs.umich.edu default: 2957639Sgblack@eecs.umich.edu return new Unknown(machInst); 2967639Sgblack@eecs.umich.edu } 2977639Sgblack@eecs.umich.edu } else { 2987639Sgblack@eecs.umich.edu switch (size) { 2997639Sgblack@eecs.umich.edu case 0: 3007639Sgblack@eecs.umich.edu return new BaseD<int8_t>(machInst, dest, op1, imm); 3017639Sgblack@eecs.umich.edu case 1: 3027639Sgblack@eecs.umich.edu return new BaseD<int16_t>(machInst, dest, op1, imm); 3037639Sgblack@eecs.umich.edu case 2: 3047639Sgblack@eecs.umich.edu return new BaseD<int32_t>(machInst, dest, op1, imm); 3057639Sgblack@eecs.umich.edu case 3: 3067639Sgblack@eecs.umich.edu return new BaseD<int64_t>(machInst, dest, op1, imm); 3077639Sgblack@eecs.umich.edu default: 3087639Sgblack@eecs.umich.edu return new Unknown(machInst); 3097639Sgblack@eecs.umich.edu } 3107639Sgblack@eecs.umich.edu } 3117639Sgblack@eecs.umich.edu } 3127639Sgblack@eecs.umich.edu 3137639Sgblack@eecs.umich.edu 3147639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 3157639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 3167639Sgblack@eecs.umich.edu StaticInstPtr 3177639Sgblack@eecs.umich.edu decodeNeonUSTwoShiftReg(bool q, bool notSigned, unsigned size, 3187639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 3197639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 3207639Sgblack@eecs.umich.edu { 3217639Sgblack@eecs.umich.edu if (notSigned) { 3227639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftReg<BaseD, BaseQ>( 3237639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 3247639Sgblack@eecs.umich.edu } else { 3257639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftReg<BaseD, BaseQ>( 3267639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 3277639Sgblack@eecs.umich.edu } 3287639Sgblack@eecs.umich.edu } 3297639Sgblack@eecs.umich.edu 3307639Sgblack@eecs.umich.edu template <template <typename T> class Base> 3317639Sgblack@eecs.umich.edu StaticInstPtr 3327639Sgblack@eecs.umich.edu decodeNeonUTwoShiftUSReg(unsigned size, 3337639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 3347639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 3357639Sgblack@eecs.umich.edu { 3367639Sgblack@eecs.umich.edu switch (size) { 3377639Sgblack@eecs.umich.edu case 0: 3387639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1, imm); 3397639Sgblack@eecs.umich.edu case 1: 3407639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1, imm); 3417639Sgblack@eecs.umich.edu case 2: 3427639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1, imm); 3437639Sgblack@eecs.umich.edu default: 3447639Sgblack@eecs.umich.edu return new Unknown(machInst); 3457639Sgblack@eecs.umich.edu } 3467639Sgblack@eecs.umich.edu } 3477639Sgblack@eecs.umich.edu 3487639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 3497639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 3507639Sgblack@eecs.umich.edu StaticInstPtr 3517639Sgblack@eecs.umich.edu decodeNeonUTwoShiftSReg(bool q, unsigned size, 3527639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 3537639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 3547639Sgblack@eecs.umich.edu { 3557639Sgblack@eecs.umich.edu if (q) { 3567639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftUSReg<BaseQ>( 3577639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 3587639Sgblack@eecs.umich.edu } else { 3597639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftUSReg<BaseD>( 3607639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 3617639Sgblack@eecs.umich.edu } 3627639Sgblack@eecs.umich.edu } 3637639Sgblack@eecs.umich.edu 3647639Sgblack@eecs.umich.edu template <template <typename T> class Base> 3657639Sgblack@eecs.umich.edu StaticInstPtr 3667639Sgblack@eecs.umich.edu decodeNeonSTwoShiftUSReg(unsigned size, 3677639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 3687639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 3697639Sgblack@eecs.umich.edu { 3707639Sgblack@eecs.umich.edu switch (size) { 3717639Sgblack@eecs.umich.edu case 0: 3727639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1, imm); 3737639Sgblack@eecs.umich.edu case 1: 3747639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1, imm); 3757639Sgblack@eecs.umich.edu case 2: 3767639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1, imm); 3777639Sgblack@eecs.umich.edu default: 3787639Sgblack@eecs.umich.edu return new Unknown(machInst); 3797639Sgblack@eecs.umich.edu } 3807639Sgblack@eecs.umich.edu } 3817639Sgblack@eecs.umich.edu 3827639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 3837639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 3847639Sgblack@eecs.umich.edu StaticInstPtr 3857639Sgblack@eecs.umich.edu decodeNeonSTwoShiftSReg(bool q, unsigned size, 3867639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 3877639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 3887639Sgblack@eecs.umich.edu { 3897639Sgblack@eecs.umich.edu if (q) { 3907639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftUSReg<BaseQ>( 3917639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 3927639Sgblack@eecs.umich.edu } else { 3937639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftUSReg<BaseD>( 3947639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 3957639Sgblack@eecs.umich.edu } 3967639Sgblack@eecs.umich.edu } 3977639Sgblack@eecs.umich.edu 3987639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 3997639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 4007639Sgblack@eecs.umich.edu StaticInstPtr 4017639Sgblack@eecs.umich.edu decodeNeonUSTwoShiftSReg(bool q, bool notSigned, unsigned size, 4027639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4037639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 4047639Sgblack@eecs.umich.edu { 4057639Sgblack@eecs.umich.edu if (notSigned) { 4067639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftSReg<BaseD, BaseQ>( 4077639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 4087639Sgblack@eecs.umich.edu } else { 4097639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftSReg<BaseD, BaseQ>( 4107639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 4117639Sgblack@eecs.umich.edu } 4127639Sgblack@eecs.umich.edu } 4137639Sgblack@eecs.umich.edu 4147639Sgblack@eecs.umich.edu template <template <typename T> class Base> 4157639Sgblack@eecs.umich.edu StaticInstPtr 4167639Sgblack@eecs.umich.edu decodeNeonUTwoMiscUSReg(unsigned size, 4177639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4187639Sgblack@eecs.umich.edu IntRegIndex op1) 4197639Sgblack@eecs.umich.edu { 4207639Sgblack@eecs.umich.edu switch (size) { 4217639Sgblack@eecs.umich.edu case 0: 4227639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1); 4237639Sgblack@eecs.umich.edu case 1: 4247639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1); 4257639Sgblack@eecs.umich.edu case 2: 4267639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1); 4277639Sgblack@eecs.umich.edu default: 4287639Sgblack@eecs.umich.edu return new Unknown(machInst); 4297639Sgblack@eecs.umich.edu } 4307639Sgblack@eecs.umich.edu } 4317639Sgblack@eecs.umich.edu 4327639Sgblack@eecs.umich.edu template <template <typename T> class Base> 4337639Sgblack@eecs.umich.edu StaticInstPtr 4347639Sgblack@eecs.umich.edu decodeNeonSTwoMiscUSReg(unsigned size, 4357639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4367639Sgblack@eecs.umich.edu IntRegIndex op1) 4377639Sgblack@eecs.umich.edu { 4387639Sgblack@eecs.umich.edu switch (size) { 4397639Sgblack@eecs.umich.edu case 0: 4407639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1); 4417639Sgblack@eecs.umich.edu case 1: 4427639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1); 4437639Sgblack@eecs.umich.edu case 2: 4447639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1); 4457639Sgblack@eecs.umich.edu default: 4467639Sgblack@eecs.umich.edu return new Unknown(machInst); 4477639Sgblack@eecs.umich.edu } 4487639Sgblack@eecs.umich.edu } 4497639Sgblack@eecs.umich.edu 4507639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 4517639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 4527639Sgblack@eecs.umich.edu StaticInstPtr 4537639Sgblack@eecs.umich.edu decodeNeonUTwoMiscSReg(bool q, unsigned size, 4547639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4557639Sgblack@eecs.umich.edu IntRegIndex op1) 4567639Sgblack@eecs.umich.edu { 4577639Sgblack@eecs.umich.edu if (q) { 4587639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUSReg<BaseQ>(size, machInst, dest, op1); 4597639Sgblack@eecs.umich.edu } else { 4607639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUSReg<BaseD>(size, machInst, dest, op1); 4617639Sgblack@eecs.umich.edu } 4627639Sgblack@eecs.umich.edu } 4637639Sgblack@eecs.umich.edu 4647639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 4657639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 4667639Sgblack@eecs.umich.edu StaticInstPtr 4677639Sgblack@eecs.umich.edu decodeNeonSTwoMiscSReg(bool q, unsigned size, 4687639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4697639Sgblack@eecs.umich.edu IntRegIndex op1) 4707639Sgblack@eecs.umich.edu { 4717639Sgblack@eecs.umich.edu if (q) { 4727639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUSReg<BaseQ>(size, machInst, dest, op1); 4737639Sgblack@eecs.umich.edu } else { 4747639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUSReg<BaseD>(size, machInst, dest, op1); 4757639Sgblack@eecs.umich.edu } 4767639Sgblack@eecs.umich.edu } 4777639Sgblack@eecs.umich.edu 4787639Sgblack@eecs.umich.edu template <template <typename T> class Base> 4797639Sgblack@eecs.umich.edu StaticInstPtr 4807639Sgblack@eecs.umich.edu decodeNeonUTwoMiscUReg(unsigned size, 4817639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4827639Sgblack@eecs.umich.edu IntRegIndex op1) 4837639Sgblack@eecs.umich.edu { 4847639Sgblack@eecs.umich.edu switch (size) { 4857639Sgblack@eecs.umich.edu case 0: 4867639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1); 4877639Sgblack@eecs.umich.edu case 1: 4887639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1); 4897639Sgblack@eecs.umich.edu case 2: 4907639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1); 4917639Sgblack@eecs.umich.edu case 3: 4927639Sgblack@eecs.umich.edu return new Base<uint64_t>(machInst, dest, op1); 4937639Sgblack@eecs.umich.edu default: 4947639Sgblack@eecs.umich.edu return new Unknown(machInst); 4957639Sgblack@eecs.umich.edu } 4967639Sgblack@eecs.umich.edu } 4977639Sgblack@eecs.umich.edu 4987639Sgblack@eecs.umich.edu template <template <typename T> class Base> 4997639Sgblack@eecs.umich.edu StaticInstPtr 5007639Sgblack@eecs.umich.edu decodeNeonSTwoMiscUReg(unsigned size, 5017639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 5027639Sgblack@eecs.umich.edu IntRegIndex op1) 5037639Sgblack@eecs.umich.edu { 5047639Sgblack@eecs.umich.edu switch (size) { 5057639Sgblack@eecs.umich.edu case 0: 5067639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1); 5077639Sgblack@eecs.umich.edu case 1: 5087639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1); 5097639Sgblack@eecs.umich.edu case 2: 5107639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1); 5117639Sgblack@eecs.umich.edu case 3: 5127639Sgblack@eecs.umich.edu return new Base<int64_t>(machInst, dest, op1); 5137639Sgblack@eecs.umich.edu default: 5147639Sgblack@eecs.umich.edu return new Unknown(machInst); 5157639Sgblack@eecs.umich.edu } 5167639Sgblack@eecs.umich.edu } 5177639Sgblack@eecs.umich.edu 5187639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 5197639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 5207639Sgblack@eecs.umich.edu StaticInstPtr 5217639Sgblack@eecs.umich.edu decodeNeonSTwoMiscReg(bool q, unsigned size, 5227639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 5237639Sgblack@eecs.umich.edu IntRegIndex op1) 5247639Sgblack@eecs.umich.edu { 5257639Sgblack@eecs.umich.edu if (q) { 5267639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUReg<BaseQ>(size, machInst, dest, op1); 5277639Sgblack@eecs.umich.edu } else { 5287639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUReg<BaseD>(size, machInst, dest, op1); 5297639Sgblack@eecs.umich.edu } 5307639Sgblack@eecs.umich.edu } 5317639Sgblack@eecs.umich.edu 5327639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 5337639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 5347639Sgblack@eecs.umich.edu StaticInstPtr 5357639Sgblack@eecs.umich.edu decodeNeonUTwoMiscReg(bool q, unsigned size, 5367639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 5377639Sgblack@eecs.umich.edu IntRegIndex op1) 5387639Sgblack@eecs.umich.edu { 5397639Sgblack@eecs.umich.edu if (q) { 5407639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUReg<BaseQ>(size, machInst, dest, op1); 5417639Sgblack@eecs.umich.edu } else { 5427639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUReg<BaseD>(size, machInst, dest, op1); 5437639Sgblack@eecs.umich.edu } 5447639Sgblack@eecs.umich.edu } 5457639Sgblack@eecs.umich.edu 5467639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 5477639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 5487639Sgblack@eecs.umich.edu StaticInstPtr 5497639Sgblack@eecs.umich.edu decodeNeonUSTwoMiscSReg(bool q, bool notSigned, unsigned size, 5507639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 5517639Sgblack@eecs.umich.edu IntRegIndex op1) 5527639Sgblack@eecs.umich.edu { 5537639Sgblack@eecs.umich.edu if (notSigned) { 5547639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftSReg<BaseD, BaseQ>( 5557639Sgblack@eecs.umich.edu q, size, machInst, dest, op1); 5567639Sgblack@eecs.umich.edu } else { 5577639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftSReg<BaseD, BaseQ>( 5587639Sgblack@eecs.umich.edu q, size, machInst, dest, op1); 5597639Sgblack@eecs.umich.edu } 5607639Sgblack@eecs.umich.edu } 5617639Sgblack@eecs.umich.edu 5627639Sgblack@eecs.umich.edu}}; 5637639Sgblack@eecs.umich.edu 5647639Sgblack@eecs.umich.eduoutput exec {{ 5657639Sgblack@eecs.umich.edu static float 5667639Sgblack@eecs.umich.edu vcgtFunc(float op1, float op2) 5677639Sgblack@eecs.umich.edu { 5687639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 5697639Sgblack@eecs.umich.edu return 2.0; 5707639Sgblack@eecs.umich.edu return (op1 > op2) ? 0.0 : 1.0; 5717639Sgblack@eecs.umich.edu } 5727639Sgblack@eecs.umich.edu 5737639Sgblack@eecs.umich.edu static float 5747639Sgblack@eecs.umich.edu vcgeFunc(float op1, float op2) 5757639Sgblack@eecs.umich.edu { 5767639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 5777639Sgblack@eecs.umich.edu return 2.0; 5787639Sgblack@eecs.umich.edu return (op1 >= op2) ? 0.0 : 1.0; 5797639Sgblack@eecs.umich.edu } 5807639Sgblack@eecs.umich.edu 5817639Sgblack@eecs.umich.edu static float 5827639Sgblack@eecs.umich.edu vceqFunc(float op1, float op2) 5837639Sgblack@eecs.umich.edu { 5847639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 5857639Sgblack@eecs.umich.edu return 2.0; 5867639Sgblack@eecs.umich.edu return (op1 == op2) ? 0.0 : 1.0; 5877639Sgblack@eecs.umich.edu } 5887639Sgblack@eecs.umich.edu 5897639Sgblack@eecs.umich.edu static float 5907639Sgblack@eecs.umich.edu vcleFunc(float op1, float op2) 5917639Sgblack@eecs.umich.edu { 5927639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 5937639Sgblack@eecs.umich.edu return 2.0; 5947639Sgblack@eecs.umich.edu return (op1 <= op2) ? 0.0 : 1.0; 5957639Sgblack@eecs.umich.edu } 5967639Sgblack@eecs.umich.edu 5977639Sgblack@eecs.umich.edu static float 5987639Sgblack@eecs.umich.edu vcltFunc(float op1, float op2) 5997639Sgblack@eecs.umich.edu { 6007639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 6017639Sgblack@eecs.umich.edu return 2.0; 6027639Sgblack@eecs.umich.edu return (op1 < op2) ? 0.0 : 1.0; 6037639Sgblack@eecs.umich.edu } 6047639Sgblack@eecs.umich.edu 6057639Sgblack@eecs.umich.edu static float 6067639Sgblack@eecs.umich.edu vacgtFunc(float op1, float op2) 6077639Sgblack@eecs.umich.edu { 6087639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 6097639Sgblack@eecs.umich.edu return 2.0; 6107639Sgblack@eecs.umich.edu return (fabsf(op1) > fabsf(op2)) ? 0.0 : 1.0; 6117639Sgblack@eecs.umich.edu } 6127639Sgblack@eecs.umich.edu 6137639Sgblack@eecs.umich.edu static float 6147639Sgblack@eecs.umich.edu vacgeFunc(float op1, float op2) 6157639Sgblack@eecs.umich.edu { 6167639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 6177639Sgblack@eecs.umich.edu return 2.0; 6187639Sgblack@eecs.umich.edu return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0; 6197639Sgblack@eecs.umich.edu } 6207639Sgblack@eecs.umich.edu}}; 6217639Sgblack@eecs.umich.edu 6227639Sgblack@eecs.umich.edulet {{ 6237639Sgblack@eecs.umich.edu 6247639Sgblack@eecs.umich.edu header_output = "" 6257639Sgblack@eecs.umich.edu exec_output = "" 6267639Sgblack@eecs.umich.edu 6277639Sgblack@eecs.umich.edu smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t") 6287639Sgblack@eecs.umich.edu unsignedTypes = smallUnsignedTypes + ("uint64_t",) 6297639Sgblack@eecs.umich.edu smallSignedTypes = ("int8_t", "int16_t", "int32_t") 6307639Sgblack@eecs.umich.edu signedTypes = smallSignedTypes + ("int64_t",) 6317639Sgblack@eecs.umich.edu smallTypes = smallUnsignedTypes + smallSignedTypes 6327639Sgblack@eecs.umich.edu allTypes = unsignedTypes + signedTypes 6337639Sgblack@eecs.umich.edu 6347760SGiacomo.Gabrielli@arm.com def threeEqualRegInst(name, Name, opClass, types, rCount, op, 6357639Sgblack@eecs.umich.edu readDest=False, pairwise=False): 6367639Sgblack@eecs.umich.edu global header_output, exec_output 6377640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 6387639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2, destReg; 6397639Sgblack@eecs.umich.edu ''' 6407639Sgblack@eecs.umich.edu for reg in range(rCount): 6417639Sgblack@eecs.umich.edu eWalkCode += ''' 6428588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 6438588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 6447639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 6457639Sgblack@eecs.umich.edu if readDest: 6467639Sgblack@eecs.umich.edu eWalkCode += ''' 6478588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 6487639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 6497639Sgblack@eecs.umich.edu readDestCode = '' 6507639Sgblack@eecs.umich.edu if readDest: 6517639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 6527639Sgblack@eecs.umich.edu if pairwise: 6537639Sgblack@eecs.umich.edu eWalkCode += ''' 6547639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 6557639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(2 * i < eCount ? 6567639Sgblack@eecs.umich.edu srcReg1.elements[2 * i] : 6577639Sgblack@eecs.umich.edu srcReg2.elements[2 * i - eCount]); 6587639Sgblack@eecs.umich.edu Element srcElem2 = gtoh(2 * i < eCount ? 6597639Sgblack@eecs.umich.edu srcReg1.elements[2 * i + 1] : 6607639Sgblack@eecs.umich.edu srcReg2.elements[2 * i + 1 - eCount]); 6617639Sgblack@eecs.umich.edu Element destElem; 6627639Sgblack@eecs.umich.edu %(readDest)s 6637639Sgblack@eecs.umich.edu %(op)s 6647639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 6657639Sgblack@eecs.umich.edu } 6667639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 6677639Sgblack@eecs.umich.edu else: 6687639Sgblack@eecs.umich.edu eWalkCode += ''' 6697639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 6707639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 6717639Sgblack@eecs.umich.edu Element srcElem2 = gtoh(srcReg2.elements[i]); 6727639Sgblack@eecs.umich.edu Element destElem; 6737639Sgblack@eecs.umich.edu %(readDest)s 6747639Sgblack@eecs.umich.edu %(op)s 6757639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 6767639Sgblack@eecs.umich.edu } 6777639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 6787639Sgblack@eecs.umich.edu for reg in range(rCount): 6797639Sgblack@eecs.umich.edu eWalkCode += ''' 6808588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 6817639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 6827639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 6837639Sgblack@eecs.umich.edu "RegRegRegOp", 6847639Sgblack@eecs.umich.edu { "code": eWalkCode, 6857639Sgblack@eecs.umich.edu "r_count": rCount, 6867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6877760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6887639Sgblack@eecs.umich.edu header_output += NeonRegRegRegOpDeclare.subst(iop) 6897639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 6907639Sgblack@eecs.umich.edu for type in types: 6917639Sgblack@eecs.umich.edu substDict = { "targs" : type, 6927639Sgblack@eecs.umich.edu "class_name" : Name } 6937639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 6947639Sgblack@eecs.umich.edu 6957760SGiacomo.Gabrielli@arm.com def threeEqualRegInstFp(name, Name, opClass, types, rCount, op, 6967639Sgblack@eecs.umich.edu readDest=False, pairwise=False, toInt=False): 6977639Sgblack@eecs.umich.edu global header_output, exec_output 6987640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 6997639Sgblack@eecs.umich.edu typedef FloatReg FloatVect[rCount]; 7007639Sgblack@eecs.umich.edu FloatVect srcRegs1, srcRegs2; 7017639Sgblack@eecs.umich.edu ''' 7027639Sgblack@eecs.umich.edu if toInt: 7037639Sgblack@eecs.umich.edu eWalkCode += 'RegVect destRegs;\n' 7047639Sgblack@eecs.umich.edu else: 7057639Sgblack@eecs.umich.edu eWalkCode += 'FloatVect destRegs;\n' 7067639Sgblack@eecs.umich.edu for reg in range(rCount): 7077639Sgblack@eecs.umich.edu eWalkCode += ''' 7087639Sgblack@eecs.umich.edu srcRegs1[%(reg)d] = FpOp1P%(reg)d; 7097639Sgblack@eecs.umich.edu srcRegs2[%(reg)d] = FpOp2P%(reg)d; 7107639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 7117639Sgblack@eecs.umich.edu if readDest: 7127639Sgblack@eecs.umich.edu if toInt: 7137639Sgblack@eecs.umich.edu eWalkCode += ''' 7147639Sgblack@eecs.umich.edu destRegs.regs[%(reg)d] = FpDestP%(reg)d.bits; 7157639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 7167639Sgblack@eecs.umich.edu else: 7177639Sgblack@eecs.umich.edu eWalkCode += ''' 7187639Sgblack@eecs.umich.edu destRegs[%(reg)d] = FpDestP%(reg)d; 7197639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 7207639Sgblack@eecs.umich.edu readDestCode = '' 7217639Sgblack@eecs.umich.edu if readDest: 7227639Sgblack@eecs.umich.edu readDestCode = 'destReg = destRegs[r];' 7237639Sgblack@eecs.umich.edu destType = 'FloatReg' 7247639Sgblack@eecs.umich.edu writeDest = 'destRegs[r] = destReg;' 7257639Sgblack@eecs.umich.edu if toInt: 7267639Sgblack@eecs.umich.edu destType = 'FloatRegBits' 7277639Sgblack@eecs.umich.edu writeDest = 'destRegs.regs[r] = destReg;' 7287639Sgblack@eecs.umich.edu if pairwise: 7297639Sgblack@eecs.umich.edu eWalkCode += ''' 7307639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 7317639Sgblack@eecs.umich.edu FloatReg srcReg1 = (2 * r < rCount) ? 7327639Sgblack@eecs.umich.edu srcRegs1[2 * r] : srcRegs2[2 * r - rCount]; 7337639Sgblack@eecs.umich.edu FloatReg srcReg2 = (2 * r < rCount) ? 7347639Sgblack@eecs.umich.edu srcRegs1[2 * r + 1] : srcRegs2[2 * r + 1 - rCount]; 7357639Sgblack@eecs.umich.edu %(destType)s destReg; 7367639Sgblack@eecs.umich.edu %(readDest)s 7377639Sgblack@eecs.umich.edu %(op)s 7387639Sgblack@eecs.umich.edu %(writeDest)s 7397639Sgblack@eecs.umich.edu } 7407639Sgblack@eecs.umich.edu ''' % { "op" : op, 7417639Sgblack@eecs.umich.edu "readDest" : readDestCode, 7427639Sgblack@eecs.umich.edu "destType" : destType, 7437639Sgblack@eecs.umich.edu "writeDest" : writeDest } 7447639Sgblack@eecs.umich.edu else: 7457639Sgblack@eecs.umich.edu eWalkCode += ''' 7467639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 7477639Sgblack@eecs.umich.edu FloatReg srcReg1 = srcRegs1[r]; 7487639Sgblack@eecs.umich.edu FloatReg srcReg2 = srcRegs2[r]; 7497639Sgblack@eecs.umich.edu %(destType)s destReg; 7507639Sgblack@eecs.umich.edu %(readDest)s 7517639Sgblack@eecs.umich.edu %(op)s 7527639Sgblack@eecs.umich.edu %(writeDest)s 7537639Sgblack@eecs.umich.edu } 7547639Sgblack@eecs.umich.edu ''' % { "op" : op, 7557639Sgblack@eecs.umich.edu "readDest" : readDestCode, 7567639Sgblack@eecs.umich.edu "destType" : destType, 7577639Sgblack@eecs.umich.edu "writeDest" : writeDest } 7587639Sgblack@eecs.umich.edu for reg in range(rCount): 7597639Sgblack@eecs.umich.edu if toInt: 7607639Sgblack@eecs.umich.edu eWalkCode += ''' 7618588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = destRegs.regs[%(reg)d]; 7627639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 7637639Sgblack@eecs.umich.edu else: 7647639Sgblack@eecs.umich.edu eWalkCode += ''' 7657639Sgblack@eecs.umich.edu FpDestP%(reg)d = destRegs[%(reg)d]; 7667639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 7677639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 7687639Sgblack@eecs.umich.edu "FpRegRegRegOp", 7697639Sgblack@eecs.umich.edu { "code": eWalkCode, 7707639Sgblack@eecs.umich.edu "r_count": rCount, 7717760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7727760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 7737639Sgblack@eecs.umich.edu header_output += NeonRegRegRegOpDeclare.subst(iop) 7747639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 7757639Sgblack@eecs.umich.edu for type in types: 7767639Sgblack@eecs.umich.edu substDict = { "targs" : type, 7777639Sgblack@eecs.umich.edu "class_name" : Name } 7787639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 7797639Sgblack@eecs.umich.edu 7807760SGiacomo.Gabrielli@arm.com def threeUnequalRegInst(name, Name, opClass, types, op, 7817639Sgblack@eecs.umich.edu bigSrc1, bigSrc2, bigDest, readDest): 7827639Sgblack@eecs.umich.edu global header_output, exec_output 7837639Sgblack@eecs.umich.edu src1Cnt = src2Cnt = destCnt = 2 7847639Sgblack@eecs.umich.edu src1Prefix = src2Prefix = destPrefix = '' 7857639Sgblack@eecs.umich.edu if bigSrc1: 7867639Sgblack@eecs.umich.edu src1Cnt = 4 7877639Sgblack@eecs.umich.edu src1Prefix = 'Big' 7887639Sgblack@eecs.umich.edu if bigSrc2: 7897639Sgblack@eecs.umich.edu src2Cnt = 4 7907639Sgblack@eecs.umich.edu src2Prefix = 'Big' 7917639Sgblack@eecs.umich.edu if bigDest: 7927639Sgblack@eecs.umich.edu destCnt = 4 7937639Sgblack@eecs.umich.edu destPrefix = 'Big' 7947640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 7957639Sgblack@eecs.umich.edu %sRegVect srcReg1; 7967639Sgblack@eecs.umich.edu %sRegVect srcReg2; 7977639Sgblack@eecs.umich.edu %sRegVect destReg; 7987639Sgblack@eecs.umich.edu ''' % (src1Prefix, src2Prefix, destPrefix) 7997639Sgblack@eecs.umich.edu for reg in range(src1Cnt): 8007639Sgblack@eecs.umich.edu eWalkCode += ''' 8018588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 8027639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 8037639Sgblack@eecs.umich.edu for reg in range(src2Cnt): 8047639Sgblack@eecs.umich.edu eWalkCode += ''' 8058588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 8067639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 8077639Sgblack@eecs.umich.edu if readDest: 8087639Sgblack@eecs.umich.edu for reg in range(destCnt): 8097639Sgblack@eecs.umich.edu eWalkCode += ''' 8108588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 8117639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 8127639Sgblack@eecs.umich.edu readDestCode = '' 8137639Sgblack@eecs.umich.edu if readDest: 8147639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 8157639Sgblack@eecs.umich.edu eWalkCode += ''' 8167639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 8177639Sgblack@eecs.umich.edu %(src1Prefix)sElement srcElem1 = gtoh(srcReg1.elements[i]); 8187639Sgblack@eecs.umich.edu %(src1Prefix)sElement srcElem2 = gtoh(srcReg2.elements[i]); 8197639Sgblack@eecs.umich.edu %(destPrefix)sElement destElem; 8207639Sgblack@eecs.umich.edu %(readDest)s 8217639Sgblack@eecs.umich.edu %(op)s 8227639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 8237639Sgblack@eecs.umich.edu } 8247639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode, 8257639Sgblack@eecs.umich.edu "src1Prefix" : src1Prefix, "src2Prefix" : src2Prefix, 8267639Sgblack@eecs.umich.edu "destPrefix" : destPrefix } 8277639Sgblack@eecs.umich.edu for reg in range(destCnt): 8287639Sgblack@eecs.umich.edu eWalkCode += ''' 8298588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 8307639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 8317639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 8327639Sgblack@eecs.umich.edu "RegRegRegOp", 8337639Sgblack@eecs.umich.edu { "code": eWalkCode, 8347639Sgblack@eecs.umich.edu "r_count": 2, 8357760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8367760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 8377639Sgblack@eecs.umich.edu header_output += NeonRegRegRegOpDeclare.subst(iop) 8387639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 8397639Sgblack@eecs.umich.edu for type in types: 8407639Sgblack@eecs.umich.edu substDict = { "targs" : type, 8417639Sgblack@eecs.umich.edu "class_name" : Name } 8427639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 8437639Sgblack@eecs.umich.edu 8447760SGiacomo.Gabrielli@arm.com def threeRegNarrowInst(name, Name, opClass, types, op, readDest=False): 8457760SGiacomo.Gabrielli@arm.com threeUnequalRegInst(name, Name, opClass, types, op, 8467639Sgblack@eecs.umich.edu True, True, False, readDest) 8477639Sgblack@eecs.umich.edu 8487760SGiacomo.Gabrielli@arm.com def threeRegLongInst(name, Name, opClass, types, op, readDest=False): 8497760SGiacomo.Gabrielli@arm.com threeUnequalRegInst(name, Name, opClass, types, op, 8507639Sgblack@eecs.umich.edu False, False, True, readDest) 8517639Sgblack@eecs.umich.edu 8527760SGiacomo.Gabrielli@arm.com def threeRegWideInst(name, Name, opClass, types, op, readDest=False): 8537760SGiacomo.Gabrielli@arm.com threeUnequalRegInst(name, Name, opClass, types, op, 8547639Sgblack@eecs.umich.edu True, False, True, readDest) 8557639Sgblack@eecs.umich.edu 8567760SGiacomo.Gabrielli@arm.com def twoEqualRegInst(name, Name, opClass, types, rCount, op, readDest=False): 8577639Sgblack@eecs.umich.edu global header_output, exec_output 8587640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 8597639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2, destReg; 8607639Sgblack@eecs.umich.edu ''' 8617639Sgblack@eecs.umich.edu for reg in range(rCount): 8627639Sgblack@eecs.umich.edu eWalkCode += ''' 8638588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 8648588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 8657639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 8667639Sgblack@eecs.umich.edu if readDest: 8677639Sgblack@eecs.umich.edu eWalkCode += ''' 8688588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 8697639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 8707639Sgblack@eecs.umich.edu readDestCode = '' 8717639Sgblack@eecs.umich.edu if readDest: 8727639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 8737639Sgblack@eecs.umich.edu eWalkCode += ''' 8747853SMatt.Horsnell@ARM.com if (imm < 0 && imm >= eCount) { 8757853SMatt.Horsnell@ARM.com#if FULL_SYSTEM 8767853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction; 8777853SMatt.Horsnell@ARM.com#else 8787853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction(false, mnemonic); 8797853SMatt.Horsnell@ARM.com#endif 8807853SMatt.Horsnell@ARM.com } else { 8817853SMatt.Horsnell@ARM.com for (unsigned i = 0; i < eCount; i++) { 8827853SMatt.Horsnell@ARM.com Element srcElem1 = gtoh(srcReg1.elements[i]); 8837853SMatt.Horsnell@ARM.com Element srcElem2 = gtoh(srcReg2.elements[imm]); 8847853SMatt.Horsnell@ARM.com Element destElem; 8857853SMatt.Horsnell@ARM.com %(readDest)s 8867853SMatt.Horsnell@ARM.com %(op)s 8877853SMatt.Horsnell@ARM.com destReg.elements[i] = htog(destElem); 8887853SMatt.Horsnell@ARM.com } 8897639Sgblack@eecs.umich.edu } 8907639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 8917639Sgblack@eecs.umich.edu for reg in range(rCount): 8927639Sgblack@eecs.umich.edu eWalkCode += ''' 8938588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 8947639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 8957639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 8967639Sgblack@eecs.umich.edu "RegRegRegImmOp", 8977639Sgblack@eecs.umich.edu { "code": eWalkCode, 8987639Sgblack@eecs.umich.edu "r_count": rCount, 8997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9007760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 9017639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 9027639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 9037639Sgblack@eecs.umich.edu for type in types: 9047639Sgblack@eecs.umich.edu substDict = { "targs" : type, 9057639Sgblack@eecs.umich.edu "class_name" : Name } 9067639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 9077639Sgblack@eecs.umich.edu 9087760SGiacomo.Gabrielli@arm.com def twoRegLongInst(name, Name, opClass, types, op, readDest=False): 9097639Sgblack@eecs.umich.edu global header_output, exec_output 9107639Sgblack@eecs.umich.edu rCount = 2 9117640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 9127639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2; 9137639Sgblack@eecs.umich.edu BigRegVect destReg; 9147639Sgblack@eecs.umich.edu ''' 9157639Sgblack@eecs.umich.edu for reg in range(rCount): 9167639Sgblack@eecs.umich.edu eWalkCode += ''' 9178588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 9188588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);; 9197639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 9207639Sgblack@eecs.umich.edu if readDest: 9217639Sgblack@eecs.umich.edu for reg in range(2 * rCount): 9227639Sgblack@eecs.umich.edu eWalkCode += ''' 9238588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 9247639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 9257639Sgblack@eecs.umich.edu readDestCode = '' 9267639Sgblack@eecs.umich.edu if readDest: 9277639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 9287639Sgblack@eecs.umich.edu eWalkCode += ''' 9297853SMatt.Horsnell@ARM.com if (imm < 0 && imm >= eCount) { 9307853SMatt.Horsnell@ARM.com#if FULL_SYSTEM 9317853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction; 9327853SMatt.Horsnell@ARM.com#else 9337853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction(false, mnemonic); 9347853SMatt.Horsnell@ARM.com#endif 9357853SMatt.Horsnell@ARM.com } else { 9367853SMatt.Horsnell@ARM.com for (unsigned i = 0; i < eCount; i++) { 9377853SMatt.Horsnell@ARM.com Element srcElem1 = gtoh(srcReg1.elements[i]); 9387853SMatt.Horsnell@ARM.com Element srcElem2 = gtoh(srcReg2.elements[imm]); 9397853SMatt.Horsnell@ARM.com BigElement destElem; 9407853SMatt.Horsnell@ARM.com %(readDest)s 9417853SMatt.Horsnell@ARM.com %(op)s 9427853SMatt.Horsnell@ARM.com destReg.elements[i] = htog(destElem); 9437853SMatt.Horsnell@ARM.com } 9447639Sgblack@eecs.umich.edu } 9457639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 9467639Sgblack@eecs.umich.edu for reg in range(2 * rCount): 9477639Sgblack@eecs.umich.edu eWalkCode += ''' 9488588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 9497639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 9507639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 9517639Sgblack@eecs.umich.edu "RegRegRegImmOp", 9527639Sgblack@eecs.umich.edu { "code": eWalkCode, 9537639Sgblack@eecs.umich.edu "r_count": rCount, 9547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9557760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 9567639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 9577639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 9587639Sgblack@eecs.umich.edu for type in types: 9597639Sgblack@eecs.umich.edu substDict = { "targs" : type, 9607639Sgblack@eecs.umich.edu "class_name" : Name } 9617639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 9627639Sgblack@eecs.umich.edu 9637760SGiacomo.Gabrielli@arm.com def twoEqualRegInstFp(name, Name, opClass, types, rCount, op, readDest=False): 9647639Sgblack@eecs.umich.edu global header_output, exec_output 9657640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 9667639Sgblack@eecs.umich.edu typedef FloatReg FloatVect[rCount]; 9677639Sgblack@eecs.umich.edu FloatVect srcRegs1, srcRegs2, destRegs; 9687639Sgblack@eecs.umich.edu ''' 9697639Sgblack@eecs.umich.edu for reg in range(rCount): 9707639Sgblack@eecs.umich.edu eWalkCode += ''' 9717639Sgblack@eecs.umich.edu srcRegs1[%(reg)d] = FpOp1P%(reg)d; 9727639Sgblack@eecs.umich.edu srcRegs2[%(reg)d] = FpOp2P%(reg)d; 9737639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 9747639Sgblack@eecs.umich.edu if readDest: 9757639Sgblack@eecs.umich.edu eWalkCode += ''' 9767639Sgblack@eecs.umich.edu destRegs[%(reg)d] = FpDestP%(reg)d; 9777639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 9787639Sgblack@eecs.umich.edu readDestCode = '' 9797639Sgblack@eecs.umich.edu if readDest: 9807639Sgblack@eecs.umich.edu readDestCode = 'destReg = destRegs[i];' 9817639Sgblack@eecs.umich.edu eWalkCode += ''' 9827853SMatt.Horsnell@ARM.com if (imm < 0 && imm >= eCount) { 9837853SMatt.Horsnell@ARM.com#if FULL_SYSTEM 9847853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction; 9857853SMatt.Horsnell@ARM.com#else 9867853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction(false, mnemonic); 9877853SMatt.Horsnell@ARM.com#endif 9887853SMatt.Horsnell@ARM.com } else { 9897853SMatt.Horsnell@ARM.com for (unsigned i = 0; i < rCount; i++) { 9907853SMatt.Horsnell@ARM.com FloatReg srcReg1 = srcRegs1[i]; 9917853SMatt.Horsnell@ARM.com FloatReg srcReg2 = srcRegs2[imm]; 9927853SMatt.Horsnell@ARM.com FloatReg destReg; 9937853SMatt.Horsnell@ARM.com %(readDest)s 9947853SMatt.Horsnell@ARM.com %(op)s 9957853SMatt.Horsnell@ARM.com destRegs[i] = destReg; 9967853SMatt.Horsnell@ARM.com } 9977639Sgblack@eecs.umich.edu } 9987639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 9997639Sgblack@eecs.umich.edu for reg in range(rCount): 10007639Sgblack@eecs.umich.edu eWalkCode += ''' 10017639Sgblack@eecs.umich.edu FpDestP%(reg)d = destRegs[%(reg)d]; 10027639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 10037639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 10047639Sgblack@eecs.umich.edu "FpRegRegRegImmOp", 10057639Sgblack@eecs.umich.edu { "code": eWalkCode, 10067639Sgblack@eecs.umich.edu "r_count": rCount, 10077760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10087760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 10097639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 10107639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 10117639Sgblack@eecs.umich.edu for type in types: 10127639Sgblack@eecs.umich.edu substDict = { "targs" : type, 10137639Sgblack@eecs.umich.edu "class_name" : Name } 10147639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 10157639Sgblack@eecs.umich.edu 10167760SGiacomo.Gabrielli@arm.com def twoRegShiftInst(name, Name, opClass, types, rCount, op, 10177639Sgblack@eecs.umich.edu readDest=False, toInt=False, fromInt=False): 10187639Sgblack@eecs.umich.edu global header_output, exec_output 10197640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 10207639Sgblack@eecs.umich.edu RegVect srcRegs1, destRegs; 10217639Sgblack@eecs.umich.edu ''' 10227639Sgblack@eecs.umich.edu for reg in range(rCount): 10237639Sgblack@eecs.umich.edu eWalkCode += ''' 10248588Sgblack@eecs.umich.edu srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 10257639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 10267639Sgblack@eecs.umich.edu if readDest: 10277639Sgblack@eecs.umich.edu eWalkCode += ''' 10288588Sgblack@eecs.umich.edu destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 10297639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 10307639Sgblack@eecs.umich.edu readDestCode = '' 10317639Sgblack@eecs.umich.edu if readDest: 10327639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destRegs.elements[i]);' 10337639Sgblack@eecs.umich.edu if toInt: 10347639Sgblack@eecs.umich.edu readDestCode = 'destReg = gtoh(destRegs.regs[i]);' 10357639Sgblack@eecs.umich.edu readOpCode = 'Element srcElem1 = gtoh(srcRegs1.elements[i]);' 10367639Sgblack@eecs.umich.edu if fromInt: 10377639Sgblack@eecs.umich.edu readOpCode = 'FloatRegBits srcReg1 = gtoh(srcRegs1.regs[i]);' 10387639Sgblack@eecs.umich.edu declDest = 'Element destElem;' 10397639Sgblack@eecs.umich.edu writeDestCode = 'destRegs.elements[i] = htog(destElem);' 10407639Sgblack@eecs.umich.edu if toInt: 10417639Sgblack@eecs.umich.edu declDest = 'FloatRegBits destReg;' 10427639Sgblack@eecs.umich.edu writeDestCode = 'destRegs.regs[i] = htog(destReg);' 10437639Sgblack@eecs.umich.edu eWalkCode += ''' 10447639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 10457639Sgblack@eecs.umich.edu %(readOp)s 10467639Sgblack@eecs.umich.edu %(declDest)s 10477639Sgblack@eecs.umich.edu %(readDest)s 10487639Sgblack@eecs.umich.edu %(op)s 10497639Sgblack@eecs.umich.edu %(writeDest)s 10507639Sgblack@eecs.umich.edu } 10517639Sgblack@eecs.umich.edu ''' % { "readOp" : readOpCode, 10527639Sgblack@eecs.umich.edu "declDest" : declDest, 10537639Sgblack@eecs.umich.edu "readDest" : readDestCode, 10547639Sgblack@eecs.umich.edu "op" : op, 10557639Sgblack@eecs.umich.edu "writeDest" : writeDestCode } 10567639Sgblack@eecs.umich.edu for reg in range(rCount): 10577639Sgblack@eecs.umich.edu eWalkCode += ''' 10588588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destRegs.regs[%(reg)d]); 10597639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 10607639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 10617639Sgblack@eecs.umich.edu "RegRegImmOp", 10627639Sgblack@eecs.umich.edu { "code": eWalkCode, 10637639Sgblack@eecs.umich.edu "r_count": rCount, 10647760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10657760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 10667639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 10677639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 10687639Sgblack@eecs.umich.edu for type in types: 10697639Sgblack@eecs.umich.edu substDict = { "targs" : type, 10707639Sgblack@eecs.umich.edu "class_name" : Name } 10717639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 10727639Sgblack@eecs.umich.edu 10737760SGiacomo.Gabrielli@arm.com def twoRegNarrowShiftInst(name, Name, opClass, types, op, readDest=False): 10747639Sgblack@eecs.umich.edu global header_output, exec_output 10757640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 10767639Sgblack@eecs.umich.edu BigRegVect srcReg1; 10777639Sgblack@eecs.umich.edu RegVect destReg; 10787639Sgblack@eecs.umich.edu ''' 10797639Sgblack@eecs.umich.edu for reg in range(4): 10807639Sgblack@eecs.umich.edu eWalkCode += ''' 10818588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 10827639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 10837639Sgblack@eecs.umich.edu if readDest: 10847639Sgblack@eecs.umich.edu for reg in range(2): 10857639Sgblack@eecs.umich.edu eWalkCode += ''' 10868588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 10877639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 10887639Sgblack@eecs.umich.edu readDestCode = '' 10897639Sgblack@eecs.umich.edu if readDest: 10907639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 10917639Sgblack@eecs.umich.edu eWalkCode += ''' 10927639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 10937639Sgblack@eecs.umich.edu BigElement srcElem1 = gtoh(srcReg1.elements[i]); 10947639Sgblack@eecs.umich.edu Element destElem; 10957639Sgblack@eecs.umich.edu %(readDest)s 10967639Sgblack@eecs.umich.edu %(op)s 10977639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 10987639Sgblack@eecs.umich.edu } 10997639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 11007639Sgblack@eecs.umich.edu for reg in range(2): 11017639Sgblack@eecs.umich.edu eWalkCode += ''' 11028588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 11037639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11047639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 11057639Sgblack@eecs.umich.edu "RegRegImmOp", 11067639Sgblack@eecs.umich.edu { "code": eWalkCode, 11077639Sgblack@eecs.umich.edu "r_count": 2, 11087760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11097760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 11107639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 11117639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 11127639Sgblack@eecs.umich.edu for type in types: 11137639Sgblack@eecs.umich.edu substDict = { "targs" : type, 11147639Sgblack@eecs.umich.edu "class_name" : Name } 11157639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 11167639Sgblack@eecs.umich.edu 11177760SGiacomo.Gabrielli@arm.com def twoRegLongShiftInst(name, Name, opClass, types, op, readDest=False): 11187639Sgblack@eecs.umich.edu global header_output, exec_output 11197640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 11207639Sgblack@eecs.umich.edu RegVect srcReg1; 11217639Sgblack@eecs.umich.edu BigRegVect destReg; 11227639Sgblack@eecs.umich.edu ''' 11237639Sgblack@eecs.umich.edu for reg in range(2): 11247639Sgblack@eecs.umich.edu eWalkCode += ''' 11258588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 11267639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11277639Sgblack@eecs.umich.edu if readDest: 11287639Sgblack@eecs.umich.edu for reg in range(4): 11297639Sgblack@eecs.umich.edu eWalkCode += ''' 11308588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 11317639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11327639Sgblack@eecs.umich.edu readDestCode = '' 11337639Sgblack@eecs.umich.edu if readDest: 11347639Sgblack@eecs.umich.edu readDestCode = 'destReg = gtoh(destReg.elements[i]);' 11357639Sgblack@eecs.umich.edu eWalkCode += ''' 11367639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 11377639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 11387639Sgblack@eecs.umich.edu BigElement destElem; 11397639Sgblack@eecs.umich.edu %(readDest)s 11407639Sgblack@eecs.umich.edu %(op)s 11417639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 11427639Sgblack@eecs.umich.edu } 11437639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 11447639Sgblack@eecs.umich.edu for reg in range(4): 11457639Sgblack@eecs.umich.edu eWalkCode += ''' 11468588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 11477639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11487639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 11497639Sgblack@eecs.umich.edu "RegRegImmOp", 11507639Sgblack@eecs.umich.edu { "code": eWalkCode, 11517639Sgblack@eecs.umich.edu "r_count": 2, 11527760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11537760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 11547639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 11557639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 11567639Sgblack@eecs.umich.edu for type in types: 11577639Sgblack@eecs.umich.edu substDict = { "targs" : type, 11587639Sgblack@eecs.umich.edu "class_name" : Name } 11597639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 11607639Sgblack@eecs.umich.edu 11617760SGiacomo.Gabrielli@arm.com def twoRegMiscInst(name, Name, opClass, types, rCount, op, readDest=False): 11627639Sgblack@eecs.umich.edu global header_output, exec_output 11637640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 11647639Sgblack@eecs.umich.edu RegVect srcReg1, destReg; 11657639Sgblack@eecs.umich.edu ''' 11667639Sgblack@eecs.umich.edu for reg in range(rCount): 11677639Sgblack@eecs.umich.edu eWalkCode += ''' 11688588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 11697639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11707639Sgblack@eecs.umich.edu if readDest: 11717639Sgblack@eecs.umich.edu eWalkCode += ''' 11728588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 11737639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11747639Sgblack@eecs.umich.edu readDestCode = '' 11757639Sgblack@eecs.umich.edu if readDest: 11767639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 11777639Sgblack@eecs.umich.edu eWalkCode += ''' 11787639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 11797639Sgblack@eecs.umich.edu unsigned j = i; 11807639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 11817639Sgblack@eecs.umich.edu Element destElem; 11827639Sgblack@eecs.umich.edu %(readDest)s 11837639Sgblack@eecs.umich.edu %(op)s 11847639Sgblack@eecs.umich.edu destReg.elements[j] = htog(destElem); 11857639Sgblack@eecs.umich.edu } 11867639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 11877639Sgblack@eecs.umich.edu for reg in range(rCount): 11887639Sgblack@eecs.umich.edu eWalkCode += ''' 11898588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 11907639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11917639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 11927639Sgblack@eecs.umich.edu "RegRegOp", 11937639Sgblack@eecs.umich.edu { "code": eWalkCode, 11947639Sgblack@eecs.umich.edu "r_count": rCount, 11957760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11967760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 11977639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 11987639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 11997639Sgblack@eecs.umich.edu for type in types: 12007639Sgblack@eecs.umich.edu substDict = { "targs" : type, 12017639Sgblack@eecs.umich.edu "class_name" : Name } 12027639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 12037639Sgblack@eecs.umich.edu 12047760SGiacomo.Gabrielli@arm.com def twoRegMiscScInst(name, Name, opClass, types, rCount, op, readDest=False): 12057639Sgblack@eecs.umich.edu global header_output, exec_output 12067640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 12077639Sgblack@eecs.umich.edu RegVect srcReg1, destReg; 12087639Sgblack@eecs.umich.edu ''' 12097639Sgblack@eecs.umich.edu for reg in range(rCount): 12107639Sgblack@eecs.umich.edu eWalkCode += ''' 12118588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 12127639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12137639Sgblack@eecs.umich.edu if readDest: 12147639Sgblack@eecs.umich.edu eWalkCode += ''' 12158588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 12167639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12177639Sgblack@eecs.umich.edu readDestCode = '' 12187639Sgblack@eecs.umich.edu if readDest: 12197639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 12207639Sgblack@eecs.umich.edu eWalkCode += ''' 12217639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 12227639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[imm]); 12237639Sgblack@eecs.umich.edu Element destElem; 12247639Sgblack@eecs.umich.edu %(readDest)s 12257639Sgblack@eecs.umich.edu %(op)s 12267639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 12277639Sgblack@eecs.umich.edu } 12287639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 12297639Sgblack@eecs.umich.edu for reg in range(rCount): 12307639Sgblack@eecs.umich.edu eWalkCode += ''' 12318588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 12327639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12337639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 12347639Sgblack@eecs.umich.edu "RegRegImmOp", 12357639Sgblack@eecs.umich.edu { "code": eWalkCode, 12367639Sgblack@eecs.umich.edu "r_count": rCount, 12377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12387760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 12397639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 12407639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 12417639Sgblack@eecs.umich.edu for type in types: 12427639Sgblack@eecs.umich.edu substDict = { "targs" : type, 12437639Sgblack@eecs.umich.edu "class_name" : Name } 12447639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 12457639Sgblack@eecs.umich.edu 12467760SGiacomo.Gabrielli@arm.com def twoRegMiscScramble(name, Name, opClass, types, rCount, op, readDest=False): 12477639Sgblack@eecs.umich.edu global header_output, exec_output 12487640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 12497639Sgblack@eecs.umich.edu RegVect srcReg1, destReg; 12507639Sgblack@eecs.umich.edu ''' 12517639Sgblack@eecs.umich.edu for reg in range(rCount): 12527639Sgblack@eecs.umich.edu eWalkCode += ''' 12538588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 12548588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 12557639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12567639Sgblack@eecs.umich.edu if readDest: 12577639Sgblack@eecs.umich.edu eWalkCode += ''' 12587639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12597639Sgblack@eecs.umich.edu readDestCode = '' 12607639Sgblack@eecs.umich.edu if readDest: 12617639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 12627639Sgblack@eecs.umich.edu eWalkCode += op 12637639Sgblack@eecs.umich.edu for reg in range(rCount): 12647639Sgblack@eecs.umich.edu eWalkCode += ''' 12658588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 12668588Sgblack@eecs.umich.edu FpOp1P%(reg)d_uw = gtoh(srcReg1.regs[%(reg)d]); 12677639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12687639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 12697639Sgblack@eecs.umich.edu "RegRegOp", 12707639Sgblack@eecs.umich.edu { "code": eWalkCode, 12717639Sgblack@eecs.umich.edu "r_count": rCount, 12727760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12737760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 12747639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 12757639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 12767639Sgblack@eecs.umich.edu for type in types: 12777639Sgblack@eecs.umich.edu substDict = { "targs" : type, 12787639Sgblack@eecs.umich.edu "class_name" : Name } 12797639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 12807639Sgblack@eecs.umich.edu 12817760SGiacomo.Gabrielli@arm.com def twoRegMiscInstFp(name, Name, opClass, types, rCount, op, 12827639Sgblack@eecs.umich.edu readDest=False, toInt=False): 12837639Sgblack@eecs.umich.edu global header_output, exec_output 12847640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 12857639Sgblack@eecs.umich.edu typedef FloatReg FloatVect[rCount]; 12867639Sgblack@eecs.umich.edu FloatVect srcRegs1; 12877639Sgblack@eecs.umich.edu ''' 12887639Sgblack@eecs.umich.edu if toInt: 12897639Sgblack@eecs.umich.edu eWalkCode += 'RegVect destRegs;\n' 12907639Sgblack@eecs.umich.edu else: 12917639Sgblack@eecs.umich.edu eWalkCode += 'FloatVect destRegs;\n' 12927639Sgblack@eecs.umich.edu for reg in range(rCount): 12937639Sgblack@eecs.umich.edu eWalkCode += ''' 12947639Sgblack@eecs.umich.edu srcRegs1[%(reg)d] = FpOp1P%(reg)d; 12957639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12967639Sgblack@eecs.umich.edu if readDest: 12977639Sgblack@eecs.umich.edu if toInt: 12987639Sgblack@eecs.umich.edu eWalkCode += ''' 12997639Sgblack@eecs.umich.edu destRegs.regs[%(reg)d] = FpDestP%(reg)d.bits; 13007639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13017639Sgblack@eecs.umich.edu else: 13027639Sgblack@eecs.umich.edu eWalkCode += ''' 13037639Sgblack@eecs.umich.edu destRegs[%(reg)d] = FpDestP%(reg)d; 13047639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13057639Sgblack@eecs.umich.edu readDestCode = '' 13067639Sgblack@eecs.umich.edu if readDest: 13077639Sgblack@eecs.umich.edu readDestCode = 'destReg = destRegs[i];' 13087639Sgblack@eecs.umich.edu destType = 'FloatReg' 13097639Sgblack@eecs.umich.edu writeDest = 'destRegs[r] = destReg;' 13107639Sgblack@eecs.umich.edu if toInt: 13117639Sgblack@eecs.umich.edu destType = 'FloatRegBits' 13127639Sgblack@eecs.umich.edu writeDest = 'destRegs.regs[r] = destReg;' 13137639Sgblack@eecs.umich.edu eWalkCode += ''' 13147639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 13157639Sgblack@eecs.umich.edu FloatReg srcReg1 = srcRegs1[r]; 13167639Sgblack@eecs.umich.edu %(destType)s destReg; 13177639Sgblack@eecs.umich.edu %(readDest)s 13187639Sgblack@eecs.umich.edu %(op)s 13197639Sgblack@eecs.umich.edu %(writeDest)s 13207639Sgblack@eecs.umich.edu } 13217639Sgblack@eecs.umich.edu ''' % { "op" : op, 13227639Sgblack@eecs.umich.edu "readDest" : readDestCode, 13237639Sgblack@eecs.umich.edu "destType" : destType, 13247639Sgblack@eecs.umich.edu "writeDest" : writeDest } 13257639Sgblack@eecs.umich.edu for reg in range(rCount): 13267639Sgblack@eecs.umich.edu if toInt: 13277639Sgblack@eecs.umich.edu eWalkCode += ''' 13288588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = destRegs.regs[%(reg)d]; 13297639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13307639Sgblack@eecs.umich.edu else: 13317639Sgblack@eecs.umich.edu eWalkCode += ''' 13327639Sgblack@eecs.umich.edu FpDestP%(reg)d = destRegs[%(reg)d]; 13337639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13347639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 13357639Sgblack@eecs.umich.edu "FpRegRegOp", 13367639Sgblack@eecs.umich.edu { "code": eWalkCode, 13377639Sgblack@eecs.umich.edu "r_count": rCount, 13387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13397760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 13407639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 13417639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 13427639Sgblack@eecs.umich.edu for type in types: 13437639Sgblack@eecs.umich.edu substDict = { "targs" : type, 13447639Sgblack@eecs.umich.edu "class_name" : Name } 13457639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 13467639Sgblack@eecs.umich.edu 13477760SGiacomo.Gabrielli@arm.com def twoRegCondenseInst(name, Name, opClass, types, rCount, op, readDest=False): 13487639Sgblack@eecs.umich.edu global header_output, exec_output 13497640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 13507639Sgblack@eecs.umich.edu RegVect srcRegs; 13517639Sgblack@eecs.umich.edu BigRegVect destReg; 13527639Sgblack@eecs.umich.edu ''' 13537639Sgblack@eecs.umich.edu for reg in range(rCount): 13547639Sgblack@eecs.umich.edu eWalkCode += ''' 13558588Sgblack@eecs.umich.edu srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 13567639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13577639Sgblack@eecs.umich.edu if readDest: 13587639Sgblack@eecs.umich.edu eWalkCode += ''' 13598588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 13607639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13617639Sgblack@eecs.umich.edu readDestCode = '' 13627639Sgblack@eecs.umich.edu if readDest: 13637639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 13647639Sgblack@eecs.umich.edu eWalkCode += ''' 13657639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 13667639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcRegs.elements[2 * i]); 13677639Sgblack@eecs.umich.edu Element srcElem2 = gtoh(srcRegs.elements[2 * i + 1]); 13687639Sgblack@eecs.umich.edu BigElement destElem; 13697639Sgblack@eecs.umich.edu %(readDest)s 13707639Sgblack@eecs.umich.edu %(op)s 13717639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 13727639Sgblack@eecs.umich.edu } 13737639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 13747639Sgblack@eecs.umich.edu for reg in range(rCount): 13757639Sgblack@eecs.umich.edu eWalkCode += ''' 13768588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 13777639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13787639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 13797639Sgblack@eecs.umich.edu "RegRegOp", 13807639Sgblack@eecs.umich.edu { "code": eWalkCode, 13817639Sgblack@eecs.umich.edu "r_count": rCount, 13827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13837760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 13847639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 13857639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 13867639Sgblack@eecs.umich.edu for type in types: 13877639Sgblack@eecs.umich.edu substDict = { "targs" : type, 13887639Sgblack@eecs.umich.edu "class_name" : Name } 13897639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 13907639Sgblack@eecs.umich.edu 13917760SGiacomo.Gabrielli@arm.com def twoRegNarrowMiscInst(name, Name, opClass, types, op, readDest=False): 13927639Sgblack@eecs.umich.edu global header_output, exec_output 13937640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 13947639Sgblack@eecs.umich.edu BigRegVect srcReg1; 13957639Sgblack@eecs.umich.edu RegVect destReg; 13967639Sgblack@eecs.umich.edu ''' 13977639Sgblack@eecs.umich.edu for reg in range(4): 13987639Sgblack@eecs.umich.edu eWalkCode += ''' 13998588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 14007639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14017639Sgblack@eecs.umich.edu if readDest: 14027639Sgblack@eecs.umich.edu for reg in range(2): 14037639Sgblack@eecs.umich.edu eWalkCode += ''' 14048588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 14057639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14067639Sgblack@eecs.umich.edu readDestCode = '' 14077639Sgblack@eecs.umich.edu if readDest: 14087639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 14097639Sgblack@eecs.umich.edu eWalkCode += ''' 14107639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 14117639Sgblack@eecs.umich.edu BigElement srcElem1 = gtoh(srcReg1.elements[i]); 14127639Sgblack@eecs.umich.edu Element destElem; 14137639Sgblack@eecs.umich.edu %(readDest)s 14147639Sgblack@eecs.umich.edu %(op)s 14157639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 14167639Sgblack@eecs.umich.edu } 14177639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 14187639Sgblack@eecs.umich.edu for reg in range(2): 14197639Sgblack@eecs.umich.edu eWalkCode += ''' 14208588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 14217639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14227639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 14237639Sgblack@eecs.umich.edu "RegRegOp", 14247639Sgblack@eecs.umich.edu { "code": eWalkCode, 14257639Sgblack@eecs.umich.edu "r_count": 2, 14267760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14277760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 14287639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 14297639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 14307639Sgblack@eecs.umich.edu for type in types: 14317639Sgblack@eecs.umich.edu substDict = { "targs" : type, 14327639Sgblack@eecs.umich.edu "class_name" : Name } 14337639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 14347639Sgblack@eecs.umich.edu 14357760SGiacomo.Gabrielli@arm.com def oneRegImmInst(name, Name, opClass, types, rCount, op, readDest=False): 14367639Sgblack@eecs.umich.edu global header_output, exec_output 14377640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 14387639Sgblack@eecs.umich.edu RegVect destReg; 14397639Sgblack@eecs.umich.edu ''' 14407639Sgblack@eecs.umich.edu if readDest: 14417639Sgblack@eecs.umich.edu for reg in range(rCount): 14427639Sgblack@eecs.umich.edu eWalkCode += ''' 14438588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 14447639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14457639Sgblack@eecs.umich.edu readDestCode = '' 14467639Sgblack@eecs.umich.edu if readDest: 14477639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 14487639Sgblack@eecs.umich.edu eWalkCode += ''' 14497639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 14507639Sgblack@eecs.umich.edu Element destElem; 14517639Sgblack@eecs.umich.edu %(readDest)s 14527639Sgblack@eecs.umich.edu %(op)s 14537639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 14547639Sgblack@eecs.umich.edu } 14557639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 14567639Sgblack@eecs.umich.edu for reg in range(rCount): 14577639Sgblack@eecs.umich.edu eWalkCode += ''' 14588588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 14597639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14607639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 14617639Sgblack@eecs.umich.edu "RegImmOp", 14627639Sgblack@eecs.umich.edu { "code": eWalkCode, 14637639Sgblack@eecs.umich.edu "r_count": rCount, 14647760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14657760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 14667639Sgblack@eecs.umich.edu header_output += NeonRegImmOpDeclare.subst(iop) 14677639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 14687639Sgblack@eecs.umich.edu for type in types: 14697639Sgblack@eecs.umich.edu substDict = { "targs" : type, 14707639Sgblack@eecs.umich.edu "class_name" : Name } 14717639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 14727639Sgblack@eecs.umich.edu 14737760SGiacomo.Gabrielli@arm.com def twoRegLongMiscInst(name, Name, opClass, types, op, readDest=False): 14747639Sgblack@eecs.umich.edu global header_output, exec_output 14757640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 14767639Sgblack@eecs.umich.edu RegVect srcReg1; 14777639Sgblack@eecs.umich.edu BigRegVect destReg; 14787639Sgblack@eecs.umich.edu ''' 14797639Sgblack@eecs.umich.edu for reg in range(2): 14807639Sgblack@eecs.umich.edu eWalkCode += ''' 14818588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 14827639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14837639Sgblack@eecs.umich.edu if readDest: 14847639Sgblack@eecs.umich.edu for reg in range(4): 14857639Sgblack@eecs.umich.edu eWalkCode += ''' 14868588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 14877639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14887639Sgblack@eecs.umich.edu readDestCode = '' 14897639Sgblack@eecs.umich.edu if readDest: 14907639Sgblack@eecs.umich.edu readDestCode = 'destReg = gtoh(destReg.elements[i]);' 14917639Sgblack@eecs.umich.edu eWalkCode += ''' 14927639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 14937639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 14947639Sgblack@eecs.umich.edu BigElement destElem; 14957639Sgblack@eecs.umich.edu %(readDest)s 14967639Sgblack@eecs.umich.edu %(op)s 14977639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 14987639Sgblack@eecs.umich.edu } 14997639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 15007639Sgblack@eecs.umich.edu for reg in range(4): 15017639Sgblack@eecs.umich.edu eWalkCode += ''' 15028588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 15037639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 15047639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 15057639Sgblack@eecs.umich.edu "RegRegOp", 15067639Sgblack@eecs.umich.edu { "code": eWalkCode, 15077639Sgblack@eecs.umich.edu "r_count": 2, 15087760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15097760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 15107639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 15117639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 15127639Sgblack@eecs.umich.edu for type in types: 15137639Sgblack@eecs.umich.edu substDict = { "targs" : type, 15147639Sgblack@eecs.umich.edu "class_name" : Name } 15157639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 15167639Sgblack@eecs.umich.edu 15177639Sgblack@eecs.umich.edu vhaddCode = ''' 15187639Sgblack@eecs.umich.edu Element carryBit = 15197639Sgblack@eecs.umich.edu (((unsigned)srcElem1 & 0x1) + 15207639Sgblack@eecs.umich.edu ((unsigned)srcElem2 & 0x1)) >> 1; 15217639Sgblack@eecs.umich.edu // Use division instead of a shift to ensure the sign extension works 15227639Sgblack@eecs.umich.edu // right. The compiler will figure out if it can be a shift. Mask the 15237639Sgblack@eecs.umich.edu // inputs so they get truncated correctly. 15247639Sgblack@eecs.umich.edu destElem = (((srcElem1 & ~(Element)1) / 2) + 15257639Sgblack@eecs.umich.edu ((srcElem2 & ~(Element)1) / 2)) + carryBit; 15267639Sgblack@eecs.umich.edu ''' 15277760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhadd", "VhaddD", "SimdAddOp", allTypes, 2, vhaddCode) 15287760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhadd", "VhaddQ", "SimdAddOp", allTypes, 4, vhaddCode) 15297639Sgblack@eecs.umich.edu 15307639Sgblack@eecs.umich.edu vrhaddCode = ''' 15317639Sgblack@eecs.umich.edu Element carryBit = 15327639Sgblack@eecs.umich.edu (((unsigned)srcElem1 & 0x1) + 15337639Sgblack@eecs.umich.edu ((unsigned)srcElem2 & 0x1) + 1) >> 1; 15347639Sgblack@eecs.umich.edu // Use division instead of a shift to ensure the sign extension works 15357639Sgblack@eecs.umich.edu // right. The compiler will figure out if it can be a shift. Mask the 15367639Sgblack@eecs.umich.edu // inputs so they get truncated correctly. 15377639Sgblack@eecs.umich.edu destElem = (((srcElem1 & ~(Element)1) / 2) + 15387639Sgblack@eecs.umich.edu ((srcElem2 & ~(Element)1) / 2)) + carryBit; 15397639Sgblack@eecs.umich.edu ''' 15407760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrhadd", "VrhaddD", "SimdAddOp", allTypes, 2, vrhaddCode) 15417760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrhadd", "VrhaddQ", "SimdAddOp", allTypes, 4, vrhaddCode) 15427639Sgblack@eecs.umich.edu 15437639Sgblack@eecs.umich.edu vhsubCode = ''' 15447639Sgblack@eecs.umich.edu Element barrowBit = 15457639Sgblack@eecs.umich.edu (((srcElem1 & 0x1) - (srcElem2 & 0x1)) >> 1) & 0x1; 15467639Sgblack@eecs.umich.edu // Use division instead of a shift to ensure the sign extension works 15477639Sgblack@eecs.umich.edu // right. The compiler will figure out if it can be a shift. Mask the 15487639Sgblack@eecs.umich.edu // inputs so they get truncated correctly. 15497639Sgblack@eecs.umich.edu destElem = (((srcElem1 & ~(Element)1) / 2) - 15507639Sgblack@eecs.umich.edu ((srcElem2 & ~(Element)1) / 2)) - barrowBit; 15517639Sgblack@eecs.umich.edu ''' 15527760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhsub", "VhsubD", "SimdAddOp", allTypes, 2, vhsubCode) 15537760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhsub", "VhsubQ", "SimdAddOp", allTypes, 4, vhsubCode) 15547639Sgblack@eecs.umich.edu 15557639Sgblack@eecs.umich.edu vandCode = ''' 15567639Sgblack@eecs.umich.edu destElem = srcElem1 & srcElem2; 15577639Sgblack@eecs.umich.edu ''' 15587760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vand", "VandD", "SimdAluOp", unsignedTypes, 2, vandCode) 15597760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vand", "VandQ", "SimdAluOp", unsignedTypes, 4, vandCode) 15607639Sgblack@eecs.umich.edu 15617639Sgblack@eecs.umich.edu vbicCode = ''' 15627639Sgblack@eecs.umich.edu destElem = srcElem1 & ~srcElem2; 15637639Sgblack@eecs.umich.edu ''' 15647760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbic", "VbicD", "SimdAluOp", unsignedTypes, 2, vbicCode) 15657760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbic", "VbicQ", "SimdAluOp", unsignedTypes, 4, vbicCode) 15667639Sgblack@eecs.umich.edu 15677639Sgblack@eecs.umich.edu vorrCode = ''' 15687639Sgblack@eecs.umich.edu destElem = srcElem1 | srcElem2; 15697639Sgblack@eecs.umich.edu ''' 15707760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorr", "VorrD", "SimdAluOp", unsignedTypes, 2, vorrCode) 15717760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorr", "VorrQ", "SimdAluOp", unsignedTypes, 4, vorrCode) 15727639Sgblack@eecs.umich.edu 15737760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmov", "VmovD", "SimdMiscOp", unsignedTypes, 2, vorrCode) 15747760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmov", "VmovQ", "SimdMiscOp", unsignedTypes, 4, vorrCode) 15757639Sgblack@eecs.umich.edu 15767639Sgblack@eecs.umich.edu vornCode = ''' 15777639Sgblack@eecs.umich.edu destElem = srcElem1 | ~srcElem2; 15787639Sgblack@eecs.umich.edu ''' 15797760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorn", "VornD", "SimdAluOp", unsignedTypes, 2, vornCode) 15807760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorn", "VornQ", "SimdAluOp", unsignedTypes, 4, vornCode) 15817639Sgblack@eecs.umich.edu 15827639Sgblack@eecs.umich.edu veorCode = ''' 15837639Sgblack@eecs.umich.edu destElem = srcElem1 ^ srcElem2; 15847639Sgblack@eecs.umich.edu ''' 15857760SGiacomo.Gabrielli@arm.com threeEqualRegInst("veor", "VeorD", "SimdAluOp", unsignedTypes, 2, veorCode) 15867760SGiacomo.Gabrielli@arm.com threeEqualRegInst("veor", "VeorQ", "SimdAluOp", unsignedTypes, 4, veorCode) 15877639Sgblack@eecs.umich.edu 15887639Sgblack@eecs.umich.edu vbifCode = ''' 15897639Sgblack@eecs.umich.edu destElem = (destElem & srcElem2) | (srcElem1 & ~srcElem2); 15907639Sgblack@eecs.umich.edu ''' 15917760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbif", "VbifD", "SimdAluOp", unsignedTypes, 2, vbifCode, True) 15927760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbif", "VbifQ", "SimdAluOp", unsignedTypes, 4, vbifCode, True) 15937639Sgblack@eecs.umich.edu vbitCode = ''' 15947639Sgblack@eecs.umich.edu destElem = (srcElem1 & srcElem2) | (destElem & ~srcElem2); 15957639Sgblack@eecs.umich.edu ''' 15967760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbit", "VbitD", "SimdAluOp", unsignedTypes, 2, vbitCode, True) 15977760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbit", "VbitQ", "SimdAluOp", unsignedTypes, 4, vbitCode, True) 15987639Sgblack@eecs.umich.edu vbslCode = ''' 15997639Sgblack@eecs.umich.edu destElem = (srcElem1 & destElem) | (srcElem2 & ~destElem); 16007639Sgblack@eecs.umich.edu ''' 16017760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbsl", "VbslD", "SimdAluOp", unsignedTypes, 2, vbslCode, True) 16027760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbsl", "VbslQ", "SimdAluOp", unsignedTypes, 4, vbslCode, True) 16037639Sgblack@eecs.umich.edu 16047639Sgblack@eecs.umich.edu vmaxCode = ''' 16057639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? srcElem1 : srcElem2; 16067639Sgblack@eecs.umich.edu ''' 16077760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmax", "VmaxD", "SimdCmpOp", allTypes, 2, vmaxCode) 16087760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmax", "VmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode) 16097639Sgblack@eecs.umich.edu 16107639Sgblack@eecs.umich.edu vminCode = ''' 16117639Sgblack@eecs.umich.edu destElem = (srcElem1 < srcElem2) ? srcElem1 : srcElem2; 16127639Sgblack@eecs.umich.edu ''' 16137760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmin", "VminD", "SimdCmpOp", allTypes, 2, vminCode) 16147760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmin", "VminQ", "SimdCmpOp", allTypes, 4, vminCode) 16157639Sgblack@eecs.umich.edu 16167639Sgblack@eecs.umich.edu vaddCode = ''' 16177639Sgblack@eecs.umich.edu destElem = srcElem1 + srcElem2; 16187639Sgblack@eecs.umich.edu ''' 16197760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode) 16207760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode) 16217639Sgblack@eecs.umich.edu 16228607Sgblack@eecs.umich.edu threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes, 16237639Sgblack@eecs.umich.edu 2, vaddCode, pairwise=True) 16247639Sgblack@eecs.umich.edu vaddlwCode = ''' 16257639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 + (BigElement)srcElem2; 16267639Sgblack@eecs.umich.edu ''' 16277760SGiacomo.Gabrielli@arm.com threeRegLongInst("vaddl", "Vaddl", "SimdAddOp", smallTypes, vaddlwCode) 16287760SGiacomo.Gabrielli@arm.com threeRegWideInst("vaddw", "Vaddw", "SimdAddOp", smallTypes, vaddlwCode) 16297639Sgblack@eecs.umich.edu vaddhnCode = ''' 16307639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 + (BigElement)srcElem2) >> 16317639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 16327639Sgblack@eecs.umich.edu ''' 16337760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vaddhn", "Vaddhn", "SimdAddOp", smallTypes, vaddhnCode) 16347639Sgblack@eecs.umich.edu vraddhnCode = ''' 16357639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 + (BigElement)srcElem2 + 16367639Sgblack@eecs.umich.edu ((BigElement)1 << (sizeof(Element) * 8 - 1))) >> 16377639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 16387639Sgblack@eecs.umich.edu ''' 16397760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vraddhn", "Vraddhn", "SimdAddOp", smallTypes, vraddhnCode) 16407639Sgblack@eecs.umich.edu 16417639Sgblack@eecs.umich.edu vsubCode = ''' 16427639Sgblack@eecs.umich.edu destElem = srcElem1 - srcElem2; 16437639Sgblack@eecs.umich.edu ''' 16447760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vsub", "NVsubD", "SimdAddOp", unsignedTypes, 2, vsubCode) 16457760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vsub", "NVsubQ", "SimdAddOp", unsignedTypes, 4, vsubCode) 16467639Sgblack@eecs.umich.edu vsublwCode = ''' 16477639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 - (BigElement)srcElem2; 16487639Sgblack@eecs.umich.edu ''' 16497760SGiacomo.Gabrielli@arm.com threeRegLongInst("vsubl", "Vsubl", "SimdAddOp", smallTypes, vsublwCode) 16507760SGiacomo.Gabrielli@arm.com threeRegWideInst("vsubw", "Vsubw", "SimdAddOp", smallTypes, vsublwCode) 16517639Sgblack@eecs.umich.edu 16527639Sgblack@eecs.umich.edu vqaddUCode = ''' 16537639Sgblack@eecs.umich.edu destElem = srcElem1 + srcElem2; 16547783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 16557639Sgblack@eecs.umich.edu if (destElem < srcElem1 || destElem < srcElem2) { 16567639Sgblack@eecs.umich.edu destElem = (Element)(-1); 16577639Sgblack@eecs.umich.edu fpscr.qc = 1; 16587639Sgblack@eecs.umich.edu } 16597783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 16607639Sgblack@eecs.umich.edu ''' 16617760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddUD", "SimdAddOp", unsignedTypes, 2, vqaddUCode) 16627760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddUQ", "SimdAddOp", unsignedTypes, 4, vqaddUCode) 16637639Sgblack@eecs.umich.edu vsubhnCode = ''' 16647639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 - (BigElement)srcElem2) >> 16657639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 16667639Sgblack@eecs.umich.edu ''' 16677760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vsubhn", "Vsubhn", "SimdAddOp", smallTypes, vsubhnCode) 16687639Sgblack@eecs.umich.edu vrsubhnCode = ''' 16697639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 - (BigElement)srcElem2 + 16707639Sgblack@eecs.umich.edu ((BigElement)1 << (sizeof(Element) * 8 - 1))) >> 16717639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 16727639Sgblack@eecs.umich.edu ''' 16737760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vrsubhn", "Vrsubhn", "SimdAddOp", smallTypes, vrsubhnCode) 16747639Sgblack@eecs.umich.edu 16757639Sgblack@eecs.umich.edu vqaddSCode = ''' 16767639Sgblack@eecs.umich.edu destElem = srcElem1 + srcElem2; 16777783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 16787639Sgblack@eecs.umich.edu bool negDest = (destElem < 0); 16797639Sgblack@eecs.umich.edu bool negSrc1 = (srcElem1 < 0); 16807639Sgblack@eecs.umich.edu bool negSrc2 = (srcElem2 < 0); 16817639Sgblack@eecs.umich.edu if ((negDest != negSrc1) && (negSrc1 == negSrc2)) { 16827639Sgblack@eecs.umich.edu destElem = (Element)1 << (sizeof(Element) * 8 - 1); 16837639Sgblack@eecs.umich.edu if (negDest) 16847639Sgblack@eecs.umich.edu destElem -= 1; 16857639Sgblack@eecs.umich.edu fpscr.qc = 1; 16867639Sgblack@eecs.umich.edu } 16877783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 16887639Sgblack@eecs.umich.edu ''' 16897760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddSD", "SimdAddOp", signedTypes, 2, vqaddSCode) 16907760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddSQ", "SimdAddOp", signedTypes, 4, vqaddSCode) 16917639Sgblack@eecs.umich.edu 16927639Sgblack@eecs.umich.edu vqsubUCode = ''' 16937639Sgblack@eecs.umich.edu destElem = srcElem1 - srcElem2; 16947783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 16957639Sgblack@eecs.umich.edu if (destElem > srcElem1) { 16967639Sgblack@eecs.umich.edu destElem = 0; 16977639Sgblack@eecs.umich.edu fpscr.qc = 1; 16987639Sgblack@eecs.umich.edu } 16997783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 17007639Sgblack@eecs.umich.edu ''' 17017760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubUD", "SimdAddOp", unsignedTypes, 2, vqsubUCode) 17027760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubUQ", "SimdAddOp", unsignedTypes, 4, vqsubUCode) 17037639Sgblack@eecs.umich.edu 17047639Sgblack@eecs.umich.edu vqsubSCode = ''' 17057639Sgblack@eecs.umich.edu destElem = srcElem1 - srcElem2; 17067783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 17077639Sgblack@eecs.umich.edu bool negDest = (destElem < 0); 17087639Sgblack@eecs.umich.edu bool negSrc1 = (srcElem1 < 0); 17097639Sgblack@eecs.umich.edu bool posSrc2 = (srcElem2 >= 0); 17107639Sgblack@eecs.umich.edu if ((negDest != negSrc1) && (negSrc1 == posSrc2)) { 17117639Sgblack@eecs.umich.edu destElem = (Element)1 << (sizeof(Element) * 8 - 1); 17127639Sgblack@eecs.umich.edu if (negDest) 17137639Sgblack@eecs.umich.edu destElem -= 1; 17147639Sgblack@eecs.umich.edu fpscr.qc = 1; 17157639Sgblack@eecs.umich.edu } 17167783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 17177639Sgblack@eecs.umich.edu ''' 17187760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubSD", "SimdAddOp", signedTypes, 2, vqsubSCode) 17197760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubSQ", "SimdAddOp", signedTypes, 4, vqsubSCode) 17207639Sgblack@eecs.umich.edu 17217639Sgblack@eecs.umich.edu vcgtCode = ''' 17227639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? (Element)(-1) : 0; 17237639Sgblack@eecs.umich.edu ''' 17247760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcgt", "VcgtD", "SimdCmpOp", allTypes, 2, vcgtCode) 17257760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcgt", "VcgtQ", "SimdCmpOp", allTypes, 4, vcgtCode) 17267639Sgblack@eecs.umich.edu 17277639Sgblack@eecs.umich.edu vcgeCode = ''' 17287639Sgblack@eecs.umich.edu destElem = (srcElem1 >= srcElem2) ? (Element)(-1) : 0; 17297639Sgblack@eecs.umich.edu ''' 17307760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcge", "VcgeD", "SimdCmpOp", allTypes, 2, vcgeCode) 17317760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcge", "VcgeQ", "SimdCmpOp", allTypes, 4, vcgeCode) 17327639Sgblack@eecs.umich.edu 17337639Sgblack@eecs.umich.edu vceqCode = ''' 17347639Sgblack@eecs.umich.edu destElem = (srcElem1 == srcElem2) ? (Element)(-1) : 0; 17357639Sgblack@eecs.umich.edu ''' 17367760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vceq", "VceqD", "SimdCmpOp", unsignedTypes, 2, vceqCode) 17377760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vceq", "VceqQ", "SimdCmpOp", unsignedTypes, 4, vceqCode) 17387639Sgblack@eecs.umich.edu 17397639Sgblack@eecs.umich.edu vshlCode = ''' 17407639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 17417639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 17427639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 17437639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 17447639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 17457639Sgblack@eecs.umich.edu destElem = 0; 17467639Sgblack@eecs.umich.edu } else { 17477639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 17487639Sgblack@eecs.umich.edu } 17497639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 17507641Sgblack@eecs.umich.edu if (ltz(srcElem1) && !ltz(destElem)) { 17517639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 17527639Sgblack@eecs.umich.edu 1 - shiftAmt)); 17537639Sgblack@eecs.umich.edu } 17547639Sgblack@eecs.umich.edu } else { 17557639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 17567639Sgblack@eecs.umich.edu destElem = 0; 17577639Sgblack@eecs.umich.edu } else { 17587639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 17597639Sgblack@eecs.umich.edu } 17607639Sgblack@eecs.umich.edu } 17617639Sgblack@eecs.umich.edu ''' 17628206SWilliam.Wang@arm.com threeEqualRegInst("vshl", "VshlD", "SimdShiftOp", allTypes, 2, vshlCode) 17638206SWilliam.Wang@arm.com threeEqualRegInst("vshl", "VshlQ", "SimdShiftOp", allTypes, 4, vshlCode) 17647639Sgblack@eecs.umich.edu 17657639Sgblack@eecs.umich.edu vrshlCode = ''' 17667639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 17677639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 17687639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 17697639Sgblack@eecs.umich.edu Element rBit = 0; 17707639Sgblack@eecs.umich.edu if (shiftAmt <= sizeof(Element) * 8) 17717639Sgblack@eecs.umich.edu rBit = bits(srcElem1, shiftAmt - 1); 17727641Sgblack@eecs.umich.edu if (shiftAmt > sizeof(Element) * 8 && ltz(srcElem1)) 17737639Sgblack@eecs.umich.edu rBit = 1; 17747639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 17757639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 17767639Sgblack@eecs.umich.edu destElem = 0; 17777639Sgblack@eecs.umich.edu } else { 17787639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 17797639Sgblack@eecs.umich.edu } 17807639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 17817641Sgblack@eecs.umich.edu if (ltz(srcElem1) && !ltz(destElem)) { 17827639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 17837639Sgblack@eecs.umich.edu 1 - shiftAmt)); 17847639Sgblack@eecs.umich.edu } 17857639Sgblack@eecs.umich.edu destElem += rBit; 17867639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 17877639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 17887639Sgblack@eecs.umich.edu destElem = 0; 17897639Sgblack@eecs.umich.edu } else { 17907639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 17917639Sgblack@eecs.umich.edu } 17927639Sgblack@eecs.umich.edu } else { 17937639Sgblack@eecs.umich.edu destElem = srcElem1; 17947639Sgblack@eecs.umich.edu } 17957639Sgblack@eecs.umich.edu ''' 17967760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrshl", "VrshlD", "SimdAluOp", allTypes, 2, vrshlCode) 17977760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrshl", "VrshlQ", "SimdAluOp", allTypes, 4, vrshlCode) 17987639Sgblack@eecs.umich.edu 17997639Sgblack@eecs.umich.edu vqshlUCode = ''' 18007639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 18017783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 18027639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 18037639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 18047639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 18057639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 18067639Sgblack@eecs.umich.edu destElem = 0; 18077639Sgblack@eecs.umich.edu } else { 18087639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 18097639Sgblack@eecs.umich.edu } 18107639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 18117639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 18127639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 18137639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 18147639Sgblack@eecs.umich.edu fpscr.qc = 1; 18157639Sgblack@eecs.umich.edu } else { 18167639Sgblack@eecs.umich.edu destElem = 0; 18177639Sgblack@eecs.umich.edu } 18187639Sgblack@eecs.umich.edu } else { 18197639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 18207639Sgblack@eecs.umich.edu sizeof(Element) * 8 - shiftAmt)) { 18217639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 18227639Sgblack@eecs.umich.edu fpscr.qc = 1; 18237639Sgblack@eecs.umich.edu } else { 18247639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 18257639Sgblack@eecs.umich.edu } 18267639Sgblack@eecs.umich.edu } 18277639Sgblack@eecs.umich.edu } else { 18287639Sgblack@eecs.umich.edu destElem = srcElem1; 18297639Sgblack@eecs.umich.edu } 18307783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 18317639Sgblack@eecs.umich.edu ''' 18327760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlUD", "SimdAluOp", unsignedTypes, 2, vqshlUCode) 18337760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlUQ", "SimdAluOp", unsignedTypes, 4, vqshlUCode) 18347639Sgblack@eecs.umich.edu 18357639Sgblack@eecs.umich.edu vqshlSCode = ''' 18367639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 18377783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 18387639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 18397639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 18407639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 18417639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 18427639Sgblack@eecs.umich.edu destElem = 0; 18437639Sgblack@eecs.umich.edu } else { 18447639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 18457639Sgblack@eecs.umich.edu } 18467639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 18477639Sgblack@eecs.umich.edu if (srcElem1 < 0 && destElem >= 0) { 18487639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 18497639Sgblack@eecs.umich.edu 1 - shiftAmt)); 18507639Sgblack@eecs.umich.edu } 18517639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 18527639Sgblack@eecs.umich.edu bool sat = false; 18537639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 18547639Sgblack@eecs.umich.edu if (srcElem1 != 0) 18557639Sgblack@eecs.umich.edu sat = true; 18567639Sgblack@eecs.umich.edu else 18577639Sgblack@eecs.umich.edu destElem = 0; 18587639Sgblack@eecs.umich.edu } else { 18597639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 18607639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1 - shiftAmt) != 18617639Sgblack@eecs.umich.edu ((srcElem1 < 0) ? mask(shiftAmt + 1) : 0)) { 18627639Sgblack@eecs.umich.edu sat = true; 18637639Sgblack@eecs.umich.edu } else { 18647639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 18657639Sgblack@eecs.umich.edu } 18667639Sgblack@eecs.umich.edu } 18677639Sgblack@eecs.umich.edu if (sat) { 18687639Sgblack@eecs.umich.edu fpscr.qc = 1; 18697639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 18707639Sgblack@eecs.umich.edu if (srcElem1 < 0) 18717639Sgblack@eecs.umich.edu destElem = ~destElem; 18727639Sgblack@eecs.umich.edu } 18737639Sgblack@eecs.umich.edu } else { 18747639Sgblack@eecs.umich.edu destElem = srcElem1; 18757639Sgblack@eecs.umich.edu } 18767783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 18777639Sgblack@eecs.umich.edu ''' 18787760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlSD", "SimdCmpOp", signedTypes, 2, vqshlSCode) 18797760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlSQ", "SimdCmpOp", signedTypes, 4, vqshlSCode) 18807639Sgblack@eecs.umich.edu 18817639Sgblack@eecs.umich.edu vqrshlUCode = ''' 18827639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 18837783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 18847639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 18857639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 18867639Sgblack@eecs.umich.edu Element rBit = 0; 18877639Sgblack@eecs.umich.edu if (shiftAmt <= sizeof(Element) * 8) 18887639Sgblack@eecs.umich.edu rBit = bits(srcElem1, shiftAmt - 1); 18897639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 18907639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 18917639Sgblack@eecs.umich.edu destElem = 0; 18927639Sgblack@eecs.umich.edu } else { 18937639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 18947639Sgblack@eecs.umich.edu } 18957639Sgblack@eecs.umich.edu destElem += rBit; 18967639Sgblack@eecs.umich.edu } else { 18977639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 18987639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 18997639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 19007639Sgblack@eecs.umich.edu fpscr.qc = 1; 19017639Sgblack@eecs.umich.edu } else { 19027639Sgblack@eecs.umich.edu destElem = 0; 19037639Sgblack@eecs.umich.edu } 19047639Sgblack@eecs.umich.edu } else { 19057639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 19067639Sgblack@eecs.umich.edu sizeof(Element) * 8 - shiftAmt)) { 19077639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 19087639Sgblack@eecs.umich.edu fpscr.qc = 1; 19097639Sgblack@eecs.umich.edu } else { 19107639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 19117639Sgblack@eecs.umich.edu } 19127639Sgblack@eecs.umich.edu } 19137639Sgblack@eecs.umich.edu } 19147783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 19157639Sgblack@eecs.umich.edu ''' 19167760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlUD", "SimdCmpOp", unsignedTypes, 2, vqrshlUCode) 19177760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlUQ", "SimdCmpOp", unsignedTypes, 4, vqrshlUCode) 19187639Sgblack@eecs.umich.edu 19197639Sgblack@eecs.umich.edu vqrshlSCode = ''' 19207639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 19217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 19227639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 19237639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 19247639Sgblack@eecs.umich.edu Element rBit = 0; 19257639Sgblack@eecs.umich.edu if (shiftAmt <= sizeof(Element) * 8) 19267639Sgblack@eecs.umich.edu rBit = bits(srcElem1, shiftAmt - 1); 19277639Sgblack@eecs.umich.edu if (shiftAmt > sizeof(Element) * 8 && srcElem1 < 0) 19287639Sgblack@eecs.umich.edu rBit = 1; 19297639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 19307639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 19317639Sgblack@eecs.umich.edu destElem = 0; 19327639Sgblack@eecs.umich.edu } else { 19337639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 19347639Sgblack@eecs.umich.edu } 19357639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 19367639Sgblack@eecs.umich.edu if (srcElem1 < 0 && destElem >= 0) { 19377639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 19387639Sgblack@eecs.umich.edu 1 - shiftAmt)); 19397639Sgblack@eecs.umich.edu } 19407639Sgblack@eecs.umich.edu destElem += rBit; 19417639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 19427639Sgblack@eecs.umich.edu bool sat = false; 19437639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 19447639Sgblack@eecs.umich.edu if (srcElem1 != 0) 19457639Sgblack@eecs.umich.edu sat = true; 19467639Sgblack@eecs.umich.edu else 19477639Sgblack@eecs.umich.edu destElem = 0; 19487639Sgblack@eecs.umich.edu } else { 19497639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 19507639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1 - shiftAmt) != 19517639Sgblack@eecs.umich.edu ((srcElem1 < 0) ? mask(shiftAmt + 1) : 0)) { 19527639Sgblack@eecs.umich.edu sat = true; 19537639Sgblack@eecs.umich.edu } else { 19547639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 19557639Sgblack@eecs.umich.edu } 19567639Sgblack@eecs.umich.edu } 19577639Sgblack@eecs.umich.edu if (sat) { 19587639Sgblack@eecs.umich.edu fpscr.qc = 1; 19597639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 19607639Sgblack@eecs.umich.edu if (srcElem1 < 0) 19617639Sgblack@eecs.umich.edu destElem = ~destElem; 19627639Sgblack@eecs.umich.edu } 19637639Sgblack@eecs.umich.edu } else { 19647639Sgblack@eecs.umich.edu destElem = srcElem1; 19657639Sgblack@eecs.umich.edu } 19667783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 19677639Sgblack@eecs.umich.edu ''' 19687760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlSD", "SimdCmpOp", signedTypes, 2, vqrshlSCode) 19697760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlSQ", "SimdCmpOp", signedTypes, 4, vqrshlSCode) 19707639Sgblack@eecs.umich.edu 19717639Sgblack@eecs.umich.edu vabaCode = ''' 19727639Sgblack@eecs.umich.edu destElem += (srcElem1 > srcElem2) ? (srcElem1 - srcElem2) : 19737639Sgblack@eecs.umich.edu (srcElem2 - srcElem1); 19747639Sgblack@eecs.umich.edu ''' 19757760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vaba", "VabaD", "SimdAddAccOp", allTypes, 2, vabaCode, True) 19767760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vaba", "VabaQ", "SimdAddAccOp", allTypes, 4, vabaCode, True) 19777639Sgblack@eecs.umich.edu vabalCode = ''' 19787639Sgblack@eecs.umich.edu destElem += (srcElem1 > srcElem2) ? 19797639Sgblack@eecs.umich.edu ((BigElement)srcElem1 - (BigElement)srcElem2) : 19807639Sgblack@eecs.umich.edu ((BigElement)srcElem2 - (BigElement)srcElem1); 19817639Sgblack@eecs.umich.edu ''' 19827760SGiacomo.Gabrielli@arm.com threeRegLongInst("vabal", "Vabal", "SimdAddAccOp", smallTypes, vabalCode, True) 19837639Sgblack@eecs.umich.edu 19847639Sgblack@eecs.umich.edu vabdCode = ''' 19857639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? (srcElem1 - srcElem2) : 19867639Sgblack@eecs.umich.edu (srcElem2 - srcElem1); 19877639Sgblack@eecs.umich.edu ''' 19887760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vabd", "VabdD", "SimdAddOp", allTypes, 2, vabdCode) 19897760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vabd", "VabdQ", "SimdAddOp", allTypes, 4, vabdCode) 19907639Sgblack@eecs.umich.edu vabdlCode = ''' 19917639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? 19927639Sgblack@eecs.umich.edu ((BigElement)srcElem1 - (BigElement)srcElem2) : 19937639Sgblack@eecs.umich.edu ((BigElement)srcElem2 - (BigElement)srcElem1); 19947639Sgblack@eecs.umich.edu ''' 19957760SGiacomo.Gabrielli@arm.com threeRegLongInst("vabdl", "Vabdl", "SimdAddOp", smallTypes, vabdlCode) 19967639Sgblack@eecs.umich.edu 19977639Sgblack@eecs.umich.edu vtstCode = ''' 19987639Sgblack@eecs.umich.edu destElem = (srcElem1 & srcElem2) ? (Element)(-1) : 0; 19997639Sgblack@eecs.umich.edu ''' 20007760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vtst", "VtstD", "SimdAluOp", unsignedTypes, 2, vtstCode) 20017760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vtst", "VtstQ", "SimdAluOp", unsignedTypes, 4, vtstCode) 20027639Sgblack@eecs.umich.edu 20037639Sgblack@eecs.umich.edu vmulCode = ''' 20047639Sgblack@eecs.umich.edu destElem = srcElem1 * srcElem2; 20057639Sgblack@eecs.umich.edu ''' 20067760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulD", "SimdMultOp", allTypes, 2, vmulCode) 20077760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulQ", "SimdMultOp", allTypes, 4, vmulCode) 20087639Sgblack@eecs.umich.edu vmullCode = ''' 20097639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 * (BigElement)srcElem2; 20107639Sgblack@eecs.umich.edu ''' 20117760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmull", "Vmull", "SimdMultOp", smallTypes, vmullCode) 20127639Sgblack@eecs.umich.edu 20137639Sgblack@eecs.umich.edu vmlaCode = ''' 20147639Sgblack@eecs.umich.edu destElem = destElem + srcElem1 * srcElem2; 20157639Sgblack@eecs.umich.edu ''' 20167760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmla", "NVmlaD", "SimdMultAccOp", allTypes, 2, vmlaCode, True) 20177760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmla", "NVmlaQ", "SimdMultAccOp", allTypes, 4, vmlaCode, True) 20187639Sgblack@eecs.umich.edu vmlalCode = ''' 20197639Sgblack@eecs.umich.edu destElem = destElem + (BigElement)srcElem1 * (BigElement)srcElem2; 20207639Sgblack@eecs.umich.edu ''' 20217760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmlal", "Vmlal", "SimdMultAccOp", smallTypes, vmlalCode, True) 20227639Sgblack@eecs.umich.edu 20237639Sgblack@eecs.umich.edu vqdmlalCode = ''' 20247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 20257639Sgblack@eecs.umich.edu BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 20267639Sgblack@eecs.umich.edu Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 20277639Sgblack@eecs.umich.edu Element halfNeg = maxNeg / 2; 20287639Sgblack@eecs.umich.edu if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 20297639Sgblack@eecs.umich.edu (srcElem1 == halfNeg && srcElem2 == maxNeg) || 20307639Sgblack@eecs.umich.edu (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 20317639Sgblack@eecs.umich.edu midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 20327639Sgblack@eecs.umich.edu fpscr.qc = 1; 20337639Sgblack@eecs.umich.edu } 20347641Sgblack@eecs.umich.edu bool negPreDest = ltz(destElem); 20357639Sgblack@eecs.umich.edu destElem += midElem; 20367641Sgblack@eecs.umich.edu bool negDest = ltz(destElem); 20377641Sgblack@eecs.umich.edu bool negMid = ltz(midElem); 20387639Sgblack@eecs.umich.edu if (negPreDest == negMid && negMid != negDest) { 20397639Sgblack@eecs.umich.edu destElem = mask(sizeof(BigElement) * 8 - 1); 20407639Sgblack@eecs.umich.edu if (negPreDest) 20417639Sgblack@eecs.umich.edu destElem = ~destElem; 20427639Sgblack@eecs.umich.edu fpscr.qc = 1; 20437639Sgblack@eecs.umich.edu } 20447783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 20457639Sgblack@eecs.umich.edu ''' 20467760SGiacomo.Gabrielli@arm.com threeRegLongInst("vqdmlal", "Vqdmlal", "SimdMultAccOp", smallTypes, vqdmlalCode, True) 20477639Sgblack@eecs.umich.edu 20487639Sgblack@eecs.umich.edu vqdmlslCode = ''' 20497783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 20507639Sgblack@eecs.umich.edu BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 20517639Sgblack@eecs.umich.edu Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 20527639Sgblack@eecs.umich.edu Element halfNeg = maxNeg / 2; 20537639Sgblack@eecs.umich.edu if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 20547639Sgblack@eecs.umich.edu (srcElem1 == halfNeg && srcElem2 == maxNeg) || 20557639Sgblack@eecs.umich.edu (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 20567639Sgblack@eecs.umich.edu midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 20577639Sgblack@eecs.umich.edu fpscr.qc = 1; 20587639Sgblack@eecs.umich.edu } 20597641Sgblack@eecs.umich.edu bool negPreDest = ltz(destElem); 20607639Sgblack@eecs.umich.edu destElem -= midElem; 20617641Sgblack@eecs.umich.edu bool negDest = ltz(destElem); 20627641Sgblack@eecs.umich.edu bool posMid = ltz((BigElement)-midElem); 20637639Sgblack@eecs.umich.edu if (negPreDest == posMid && posMid != negDest) { 20647639Sgblack@eecs.umich.edu destElem = mask(sizeof(BigElement) * 8 - 1); 20657639Sgblack@eecs.umich.edu if (negPreDest) 20667639Sgblack@eecs.umich.edu destElem = ~destElem; 20677639Sgblack@eecs.umich.edu fpscr.qc = 1; 20687639Sgblack@eecs.umich.edu } 20697783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 20707639Sgblack@eecs.umich.edu ''' 20717760SGiacomo.Gabrielli@arm.com threeRegLongInst("vqdmlsl", "Vqdmlsl", "SimdMultAccOp", smallTypes, vqdmlslCode, True) 20727639Sgblack@eecs.umich.edu 20737639Sgblack@eecs.umich.edu vqdmullCode = ''' 20747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 20757639Sgblack@eecs.umich.edu destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 20767639Sgblack@eecs.umich.edu if (srcElem1 == srcElem2 && 20777639Sgblack@eecs.umich.edu srcElem1 == (Element)((Element)1 << 20787639Sgblack@eecs.umich.edu (Element)(sizeof(Element) * 8 - 1))) { 20797639Sgblack@eecs.umich.edu destElem = ~((BigElement)srcElem1 << (sizeof(Element) * 8)); 20807639Sgblack@eecs.umich.edu fpscr.qc = 1; 20817639Sgblack@eecs.umich.edu } 20827783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 20837639Sgblack@eecs.umich.edu ''' 20847760SGiacomo.Gabrielli@arm.com threeRegLongInst("vqdmull", "Vqdmull", "SimdMultAccOp", smallTypes, vqdmullCode) 20857639Sgblack@eecs.umich.edu 20867639Sgblack@eecs.umich.edu vmlsCode = ''' 20877639Sgblack@eecs.umich.edu destElem = destElem - srcElem1 * srcElem2; 20887639Sgblack@eecs.umich.edu ''' 20897760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmls", "NVmlsD", "SimdMultAccOp", allTypes, 2, vmlsCode, True) 20907760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmls", "NVmlsQ", "SimdMultAccOp", allTypes, 4, vmlsCode, True) 20917639Sgblack@eecs.umich.edu vmlslCode = ''' 20927639Sgblack@eecs.umich.edu destElem = destElem - (BigElement)srcElem1 * (BigElement)srcElem2; 20937639Sgblack@eecs.umich.edu ''' 20947760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmlsl", "Vmlsl", "SimdMultAccOp", smallTypes, vmlslCode, True) 20957639Sgblack@eecs.umich.edu 20967639Sgblack@eecs.umich.edu vmulpCode = ''' 20977639Sgblack@eecs.umich.edu destElem = 0; 20987639Sgblack@eecs.umich.edu for (unsigned j = 0; j < sizeof(Element) * 8; j++) { 20997639Sgblack@eecs.umich.edu if (bits(srcElem2, j)) 21007639Sgblack@eecs.umich.edu destElem ^= srcElem1 << j; 21017639Sgblack@eecs.umich.edu } 21027639Sgblack@eecs.umich.edu ''' 21037760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulpD", "SimdMultOp", unsignedTypes, 2, vmulpCode) 21047760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulpQ", "SimdMultOp", unsignedTypes, 4, vmulpCode) 21057639Sgblack@eecs.umich.edu vmullpCode = ''' 21067639Sgblack@eecs.umich.edu destElem = 0; 21077639Sgblack@eecs.umich.edu for (unsigned j = 0; j < sizeof(Element) * 8; j++) { 21087639Sgblack@eecs.umich.edu if (bits(srcElem2, j)) 21097639Sgblack@eecs.umich.edu destElem ^= (BigElement)srcElem1 << j; 21107639Sgblack@eecs.umich.edu } 21117639Sgblack@eecs.umich.edu ''' 21127760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode) 21137639Sgblack@eecs.umich.edu 21148607Sgblack@eecs.umich.edu threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True) 21157639Sgblack@eecs.umich.edu 21168607Sgblack@eecs.umich.edu threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True) 21177639Sgblack@eecs.umich.edu 21187639Sgblack@eecs.umich.edu vqdmulhCode = ''' 21197783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 21207639Sgblack@eecs.umich.edu destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2) >> 21217639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 21227639Sgblack@eecs.umich.edu if (srcElem1 == srcElem2 && 21237639Sgblack@eecs.umich.edu srcElem1 == (Element)((Element)1 << 21247639Sgblack@eecs.umich.edu (sizeof(Element) * 8 - 1))) { 21257639Sgblack@eecs.umich.edu destElem = ~srcElem1; 21267639Sgblack@eecs.umich.edu fpscr.qc = 1; 21277639Sgblack@eecs.umich.edu } 21287783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 21297639Sgblack@eecs.umich.edu ''' 21307760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqdmulh", "VqdmulhD", "SimdMultOp", smallSignedTypes, 2, vqdmulhCode) 21317760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqdmulh", "VqdmulhQ", "SimdMultOp", smallSignedTypes, 4, vqdmulhCode) 21327639Sgblack@eecs.umich.edu 21337639Sgblack@eecs.umich.edu vqrdmulhCode = ''' 21347783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 21357639Sgblack@eecs.umich.edu destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2 + 21367639Sgblack@eecs.umich.edu ((int64_t)1 << (sizeof(Element) * 8 - 1))) >> 21377639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 21387639Sgblack@eecs.umich.edu Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1); 21397639Sgblack@eecs.umich.edu Element halfNeg = maxNeg / 2; 21407639Sgblack@eecs.umich.edu if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 21417639Sgblack@eecs.umich.edu (srcElem1 == halfNeg && srcElem2 == maxNeg) || 21427639Sgblack@eecs.umich.edu (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 21437639Sgblack@eecs.umich.edu if (destElem < 0) { 21447639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 21457639Sgblack@eecs.umich.edu } else { 21467639Sgblack@eecs.umich.edu destElem = (Element)1 << (sizeof(Element) * 8 - 1); 21477639Sgblack@eecs.umich.edu } 21487639Sgblack@eecs.umich.edu fpscr.qc = 1; 21497639Sgblack@eecs.umich.edu } 21507783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 21517639Sgblack@eecs.umich.edu ''' 21527639Sgblack@eecs.umich.edu threeEqualRegInst("vqrdmulh", "VqrdmulhD", 21537760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 2, vqrdmulhCode) 21547639Sgblack@eecs.umich.edu threeEqualRegInst("vqrdmulh", "VqrdmulhQ", 21557760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 4, vqrdmulhCode) 21567639Sgblack@eecs.umich.edu 21577639Sgblack@eecs.umich.edu vmaxfpCode = ''' 21587783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 21597639Sgblack@eecs.umich.edu bool done; 21607639Sgblack@eecs.umich.edu destReg = processNans(fpscr, done, true, srcReg1, srcReg2); 21617639Sgblack@eecs.umich.edu if (!done) { 21627639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpMaxS, 21637639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 21647639Sgblack@eecs.umich.edu } else if (flushToZero(srcReg1, srcReg2)) { 21657639Sgblack@eecs.umich.edu fpscr.idc = 1; 21667639Sgblack@eecs.umich.edu } 21677783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 21687639Sgblack@eecs.umich.edu ''' 21697760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmax", "VmaxDFp", "SimdFloatCmpOp", ("float",), 2, vmaxfpCode) 21707760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmax", "VmaxQFp", "SimdFloatCmpOp", ("float",), 4, vmaxfpCode) 21717639Sgblack@eecs.umich.edu 21727639Sgblack@eecs.umich.edu vminfpCode = ''' 21737783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 21747639Sgblack@eecs.umich.edu bool done; 21757639Sgblack@eecs.umich.edu destReg = processNans(fpscr, done, true, srcReg1, srcReg2); 21767639Sgblack@eecs.umich.edu if (!done) { 21777639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpMinS, 21787639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 21797639Sgblack@eecs.umich.edu } else if (flushToZero(srcReg1, srcReg2)) { 21807639Sgblack@eecs.umich.edu fpscr.idc = 1; 21817639Sgblack@eecs.umich.edu } 21827783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 21837639Sgblack@eecs.umich.edu ''' 21847760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmin", "VminDFp", "SimdFloatCmpOp", ("float",), 2, vminfpCode) 21857760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmin", "VminQFp", "SimdFloatCmpOp", ("float",), 4, vminfpCode) 21867639Sgblack@eecs.umich.edu 21877760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpmax", "VpmaxDFp", "SimdFloatCmpOp", ("float",), 21887639Sgblack@eecs.umich.edu 2, vmaxfpCode, pairwise=True) 21897760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpmax", "VpmaxQFp", "SimdFloatCmpOp", ("float",), 21907639Sgblack@eecs.umich.edu 4, vmaxfpCode, pairwise=True) 21917639Sgblack@eecs.umich.edu 21927760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpmin", "VpminDFp", "SimdFloatCmpOp", ("float",), 21937639Sgblack@eecs.umich.edu 2, vminfpCode, pairwise=True) 21947760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpmin", "VpminQFp", "SimdFloatCmpOp", ("float",), 21957639Sgblack@eecs.umich.edu 4, vminfpCode, pairwise=True) 21967639Sgblack@eecs.umich.edu 21977639Sgblack@eecs.umich.edu vaddfpCode = ''' 21987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 21997639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpAddS, 22007639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22017783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22027639Sgblack@eecs.umich.edu ''' 22037760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vadd", "VaddDFp", "SimdFloatAddOp", ("float",), 2, vaddfpCode) 22047760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vadd", "VaddQFp", "SimdFloatAddOp", ("float",), 4, vaddfpCode) 22057639Sgblack@eecs.umich.edu 22067760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpadd", "VpaddDFp", "SimdFloatAddOp", ("float",), 22077639Sgblack@eecs.umich.edu 2, vaddfpCode, pairwise=True) 22087760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpadd", "VpaddQFp", "SimdFloatAddOp", ("float",), 22097639Sgblack@eecs.umich.edu 4, vaddfpCode, pairwise=True) 22107639Sgblack@eecs.umich.edu 22117639Sgblack@eecs.umich.edu vsubfpCode = ''' 22127783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22137639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpSubS, 22147639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22167639Sgblack@eecs.umich.edu ''' 22177760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vsub", "VsubDFp", "SimdFloatAddOp", ("float",), 2, vsubfpCode) 22187760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vsub", "VsubQFp", "SimdFloatAddOp", ("float",), 4, vsubfpCode) 22197639Sgblack@eecs.umich.edu 22207639Sgblack@eecs.umich.edu vmulfpCode = ''' 22217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22227639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpMulS, 22237639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22247783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22257639Sgblack@eecs.umich.edu ''' 22267760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmul", "NVmulDFp", "SimdFloatMultOp", ("float",), 2, vmulfpCode) 22277760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmul", "NVmulQFp", "SimdFloatMultOp", ("float",), 4, vmulfpCode) 22287639Sgblack@eecs.umich.edu 22297639Sgblack@eecs.umich.edu vmlafpCode = ''' 22307783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22317639Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, srcReg1, srcReg2, fpMulS, 22327639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22337639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, mid, destReg, fpAddS, 22347639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22357783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22367639Sgblack@eecs.umich.edu ''' 22377760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmla", "NVmlaDFp", "SimdFloatMultAccOp", ("float",), 2, vmlafpCode, True) 22387760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmla", "NVmlaQFp", "SimdFloatMultAccOp", ("float",), 4, vmlafpCode, True) 22397639Sgblack@eecs.umich.edu 22407639Sgblack@eecs.umich.edu vmlsfpCode = ''' 22417783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22427639Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, srcReg1, srcReg2, fpMulS, 22437639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22447639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, destReg, mid, fpSubS, 22457639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22467783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22477639Sgblack@eecs.umich.edu ''' 22487760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmls", "NVmlsDFp", "SimdFloatMultAccOp", ("float",), 2, vmlsfpCode, True) 22497760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmls", "NVmlsQFp", "SimdFloatMultAccOp", ("float",), 4, vmlsfpCode, True) 22507639Sgblack@eecs.umich.edu 22517639Sgblack@eecs.umich.edu vcgtfpCode = ''' 22527783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22537639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vcgtFunc, 22547639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22557639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 22567639Sgblack@eecs.umich.edu if (res == 2.0) 22577639Sgblack@eecs.umich.edu fpscr.ioc = 1; 22587783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22597639Sgblack@eecs.umich.edu ''' 22607760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcgt", "VcgtDFp", "SimdFloatCmpOp", ("float",), 22617639Sgblack@eecs.umich.edu 2, vcgtfpCode, toInt = True) 22627760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcgt", "VcgtQFp", "SimdFloatCmpOp", ("float",), 22637639Sgblack@eecs.umich.edu 4, vcgtfpCode, toInt = True) 22647639Sgblack@eecs.umich.edu 22657639Sgblack@eecs.umich.edu vcgefpCode = ''' 22667783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22677639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vcgeFunc, 22687639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22697639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 22707639Sgblack@eecs.umich.edu if (res == 2.0) 22717639Sgblack@eecs.umich.edu fpscr.ioc = 1; 22727783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22737639Sgblack@eecs.umich.edu ''' 22747760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcge", "VcgeDFp", "SimdFloatCmpOp", ("float",), 22757639Sgblack@eecs.umich.edu 2, vcgefpCode, toInt = True) 22767760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcge", "VcgeQFp", "SimdFloatCmpOp", ("float",), 22777639Sgblack@eecs.umich.edu 4, vcgefpCode, toInt = True) 22787639Sgblack@eecs.umich.edu 22797639Sgblack@eecs.umich.edu vacgtfpCode = ''' 22807783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22817639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vacgtFunc, 22827639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22837639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 22847639Sgblack@eecs.umich.edu if (res == 2.0) 22857639Sgblack@eecs.umich.edu fpscr.ioc = 1; 22867783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 22877639Sgblack@eecs.umich.edu ''' 22887760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacgt", "VacgtDFp", "SimdFloatCmpOp", ("float",), 22897639Sgblack@eecs.umich.edu 2, vacgtfpCode, toInt = True) 22907760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacgt", "VacgtQFp", "SimdFloatCmpOp", ("float",), 22917639Sgblack@eecs.umich.edu 4, vacgtfpCode, toInt = True) 22927639Sgblack@eecs.umich.edu 22937639Sgblack@eecs.umich.edu vacgefpCode = ''' 22947783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 22957639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vacgeFunc, 22967639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 22977639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 22987639Sgblack@eecs.umich.edu if (res == 2.0) 22997639Sgblack@eecs.umich.edu fpscr.ioc = 1; 23007783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 23017639Sgblack@eecs.umich.edu ''' 23027760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacge", "VacgeDFp", "SimdFloatCmpOp", ("float",), 23037639Sgblack@eecs.umich.edu 2, vacgefpCode, toInt = True) 23047760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacge", "VacgeQFp", "SimdFloatCmpOp", ("float",), 23057639Sgblack@eecs.umich.edu 4, vacgefpCode, toInt = True) 23067639Sgblack@eecs.umich.edu 23077639Sgblack@eecs.umich.edu vceqfpCode = ''' 23087783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 23097639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vceqFunc, 23107639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 23117639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 23127639Sgblack@eecs.umich.edu if (res == 2.0) 23137639Sgblack@eecs.umich.edu fpscr.ioc = 1; 23147783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 23157639Sgblack@eecs.umich.edu ''' 23167760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vceq", "VceqDFp", "SimdFloatCmpOp", ("float",), 23177639Sgblack@eecs.umich.edu 2, vceqfpCode, toInt = True) 23187760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vceq", "VceqQFp", "SimdFloatCmpOp", ("float",), 23197639Sgblack@eecs.umich.edu 4, vceqfpCode, toInt = True) 23207639Sgblack@eecs.umich.edu 23217639Sgblack@eecs.umich.edu vrecpsCode = ''' 23227783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 23237639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpRecpsS, 23247639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 23257783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 23267639Sgblack@eecs.umich.edu ''' 23277760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrecps", "VrecpsDFp", "SimdFloatMultAccOp", ("float",), 2, vrecpsCode) 23287760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrecps", "VrecpsQFp", "SimdFloatMultAccOp", ("float",), 4, vrecpsCode) 23297639Sgblack@eecs.umich.edu 23307639Sgblack@eecs.umich.edu vrsqrtsCode = ''' 23317783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 23327639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpRSqrtsS, 23337639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 23347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 23357639Sgblack@eecs.umich.edu ''' 23367760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrsqrts", "VrsqrtsDFp", "SimdFloatMiscOp", ("float",), 2, vrsqrtsCode) 23377760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrsqrts", "VrsqrtsQFp", "SimdFloatMiscOp", ("float",), 4, vrsqrtsCode) 23387639Sgblack@eecs.umich.edu 23397639Sgblack@eecs.umich.edu vabdfpCode = ''' 23407783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 23417639Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, srcReg1, srcReg2, fpSubS, 23427639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 23437639Sgblack@eecs.umich.edu destReg = fabs(mid); 23447783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 23457639Sgblack@eecs.umich.edu ''' 23467760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vabd", "VabdDFp", "SimdFloatAddOp", ("float",), 2, vabdfpCode) 23477760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vabd", "VabdQFp", "SimdFloatAddOp", ("float",), 4, vabdfpCode) 23487639Sgblack@eecs.umich.edu 23497760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmla", "VmlasD", "SimdMultAccOp", unsignedTypes, 2, vmlaCode, True) 23507760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmla", "VmlasQ", "SimdMultAccOp", unsignedTypes, 4, vmlaCode, True) 23517760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmla", "VmlasDFp", "SimdFloatMultAccOp", ("float",), 2, vmlafpCode, True) 23527760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmla", "VmlasQFp", "SimdFloatMultAccOp", ("float",), 4, vmlafpCode, True) 23537760SGiacomo.Gabrielli@arm.com twoRegLongInst("vmlal", "Vmlals", "SimdMultAccOp", smallTypes, vmlalCode, True) 23547639Sgblack@eecs.umich.edu 23557760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmls", "VmlssD", "SimdMultAccOp", allTypes, 2, vmlsCode, True) 23567760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmls", "VmlssQ", "SimdMultAccOp", allTypes, 4, vmlsCode, True) 23577760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmls", "VmlssDFp", "SimdFloatMultAccOp", ("float",), 2, vmlsfpCode, True) 23587760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmls", "VmlssQFp", "SimdFloatMultAccOp", ("float",), 4, vmlsfpCode, True) 23597760SGiacomo.Gabrielli@arm.com twoRegLongInst("vmlsl", "Vmlsls", "SimdMultAccOp", smallTypes, vmlslCode, True) 23607639Sgblack@eecs.umich.edu 23617760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmul", "VmulsD", "SimdMultOp", allTypes, 2, vmulCode) 23627760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmul", "VmulsQ", "SimdMultOp", allTypes, 4, vmulCode) 23637760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmul", "VmulsDFp", "SimdFloatMultOp", ("float",), 2, vmulfpCode) 23647760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmul", "VmulsQFp", "SimdFloatMultOp", ("float",), 4, vmulfpCode) 23657760SGiacomo.Gabrielli@arm.com twoRegLongInst("vmull", "Vmulls", "SimdMultOp", smallTypes, vmullCode) 23667639Sgblack@eecs.umich.edu 23677760SGiacomo.Gabrielli@arm.com twoRegLongInst("vqdmull", "Vqdmulls", "SimdMultOp", smallTypes, vqdmullCode) 23687760SGiacomo.Gabrielli@arm.com twoRegLongInst("vqdmlal", "Vqdmlals", "SimdMultAccOp", smallTypes, vqdmlalCode, True) 23697760SGiacomo.Gabrielli@arm.com twoRegLongInst("vqdmlsl", "Vqdmlsls", "SimdMultAccOp", smallTypes, vqdmlslCode, True) 23707760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vqdmulh", "VqdmulhsD", "SimdMultOp", smallSignedTypes, 2, vqdmulhCode) 23717760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vqdmulh", "VqdmulhsQ", "SimdMultOp", smallSignedTypes, 4, vqdmulhCode) 23727639Sgblack@eecs.umich.edu twoEqualRegInst("vqrdmulh", "VqrdmulhsD", 23737760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 2, vqrdmulhCode) 23747639Sgblack@eecs.umich.edu twoEqualRegInst("vqrdmulh", "VqrdmulhsQ", 23757760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 4, vqrdmulhCode) 23767639Sgblack@eecs.umich.edu 23777639Sgblack@eecs.umich.edu vshrCode = ''' 23787639Sgblack@eecs.umich.edu if (imm >= sizeof(srcElem1) * 8) { 23797641Sgblack@eecs.umich.edu if (ltz(srcElem1)) 23807639Sgblack@eecs.umich.edu destElem = -1; 23817639Sgblack@eecs.umich.edu else 23827639Sgblack@eecs.umich.edu destElem = 0; 23837639Sgblack@eecs.umich.edu } else { 23847639Sgblack@eecs.umich.edu destElem = srcElem1 >> imm; 23857639Sgblack@eecs.umich.edu } 23867639Sgblack@eecs.umich.edu ''' 23877760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshr", "NVshrD", "SimdShiftOp", allTypes, 2, vshrCode) 23887760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshr", "NVshrQ", "SimdShiftOp", allTypes, 4, vshrCode) 23897639Sgblack@eecs.umich.edu 23907639Sgblack@eecs.umich.edu vsraCode = ''' 23917639Sgblack@eecs.umich.edu Element mid;; 23927639Sgblack@eecs.umich.edu if (imm >= sizeof(srcElem1) * 8) { 23937641Sgblack@eecs.umich.edu mid = ltz(srcElem1) ? -1 : 0; 23947639Sgblack@eecs.umich.edu } else { 23957639Sgblack@eecs.umich.edu mid = srcElem1 >> imm; 23967641Sgblack@eecs.umich.edu if (ltz(srcElem1) && !ltz(mid)) { 23977639Sgblack@eecs.umich.edu mid |= -(mid & ((Element)1 << 23987639Sgblack@eecs.umich.edu (sizeof(Element) * 8 - 1 - imm))); 23997639Sgblack@eecs.umich.edu } 24007639Sgblack@eecs.umich.edu } 24017639Sgblack@eecs.umich.edu destElem += mid; 24027639Sgblack@eecs.umich.edu ''' 24037760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsra", "NVsraD", "SimdShiftAccOp", allTypes, 2, vsraCode, True) 24047760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsra", "NVsraQ", "SimdShiftAccOp", allTypes, 4, vsraCode, True) 24057639Sgblack@eecs.umich.edu 24067639Sgblack@eecs.umich.edu vrshrCode = ''' 24077639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 24087639Sgblack@eecs.umich.edu destElem = 0; 24097639Sgblack@eecs.umich.edu } else if (imm) { 24107639Sgblack@eecs.umich.edu Element rBit = bits(srcElem1, imm - 1); 24117639Sgblack@eecs.umich.edu destElem = ((srcElem1 >> (imm - 1)) >> 1) + rBit; 24127639Sgblack@eecs.umich.edu } else { 24137639Sgblack@eecs.umich.edu destElem = srcElem1; 24147639Sgblack@eecs.umich.edu } 24157639Sgblack@eecs.umich.edu ''' 24167760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrshr", "NVrshrD", "SimdShiftOp", allTypes, 2, vrshrCode) 24177760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrshr", "NVrshrQ", "SimdShiftOp", allTypes, 4, vrshrCode) 24187639Sgblack@eecs.umich.edu 24197639Sgblack@eecs.umich.edu vrsraCode = ''' 24207639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 24217639Sgblack@eecs.umich.edu destElem += 0; 24227639Sgblack@eecs.umich.edu } else if (imm) { 24237639Sgblack@eecs.umich.edu Element rBit = bits(srcElem1, imm - 1); 24247639Sgblack@eecs.umich.edu destElem += ((srcElem1 >> (imm - 1)) >> 1) + rBit; 24257639Sgblack@eecs.umich.edu } else { 24267639Sgblack@eecs.umich.edu destElem += srcElem1; 24277639Sgblack@eecs.umich.edu } 24287639Sgblack@eecs.umich.edu ''' 24297760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrsra", "NVrsraD", "SimdShiftAccOp", allTypes, 2, vrsraCode, True) 24307760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True) 24317639Sgblack@eecs.umich.edu 24327639Sgblack@eecs.umich.edu vsriCode = ''' 24337639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) 24347639Sgblack@eecs.umich.edu destElem = destElem; 24357639Sgblack@eecs.umich.edu else 24367639Sgblack@eecs.umich.edu destElem = (srcElem1 >> imm) | 24377639Sgblack@eecs.umich.edu (destElem & ~mask(sizeof(Element) * 8 - imm)); 24387639Sgblack@eecs.umich.edu ''' 24397760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True) 24407760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True) 24417639Sgblack@eecs.umich.edu 24427639Sgblack@eecs.umich.edu vshlCode = ''' 24437639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) 24447639Sgblack@eecs.umich.edu destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1; 24457639Sgblack@eecs.umich.edu else 24467639Sgblack@eecs.umich.edu destElem = srcElem1 << imm; 24477639Sgblack@eecs.umich.edu ''' 24487760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode) 24497760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode) 24507639Sgblack@eecs.umich.edu 24517639Sgblack@eecs.umich.edu vsliCode = ''' 24527639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) 24537639Sgblack@eecs.umich.edu destElem = destElem; 24547639Sgblack@eecs.umich.edu else 24557639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm) | (destElem & mask(imm)); 24567639Sgblack@eecs.umich.edu ''' 24577760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True) 24587760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True) 24597639Sgblack@eecs.umich.edu 24607639Sgblack@eecs.umich.edu vqshlCode = ''' 24617783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 24627639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) { 24637639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 24647639Sgblack@eecs.umich.edu destElem = (Element)1 << (sizeof(Element) * 8 - 1); 24657639Sgblack@eecs.umich.edu if (srcElem1 > 0) 24667639Sgblack@eecs.umich.edu destElem = ~destElem; 24677639Sgblack@eecs.umich.edu fpscr.qc = 1; 24687639Sgblack@eecs.umich.edu } else { 24697639Sgblack@eecs.umich.edu destElem = 0; 24707639Sgblack@eecs.umich.edu } 24717639Sgblack@eecs.umich.edu } else if (imm) { 24727639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm); 24737639Sgblack@eecs.umich.edu uint64_t topBits = bits((uint64_t)srcElem1, 24747639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1, 24757639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1 - imm); 24767639Sgblack@eecs.umich.edu if (topBits != 0 && topBits != mask(imm + 1)) { 24777639Sgblack@eecs.umich.edu destElem = (Element)1 << (sizeof(Element) * 8 - 1); 24787639Sgblack@eecs.umich.edu if (srcElem1 > 0) 24797639Sgblack@eecs.umich.edu destElem = ~destElem; 24807639Sgblack@eecs.umich.edu fpscr.qc = 1; 24817639Sgblack@eecs.umich.edu } 24827639Sgblack@eecs.umich.edu } else { 24837639Sgblack@eecs.umich.edu destElem = srcElem1; 24847639Sgblack@eecs.umich.edu } 24857783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 24867639Sgblack@eecs.umich.edu ''' 24877760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshl", "NVqshlD", "SimdShiftOp", signedTypes, 2, vqshlCode) 24887760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshl", "NVqshlQ", "SimdShiftOp", signedTypes, 4, vqshlCode) 24897639Sgblack@eecs.umich.edu 24907639Sgblack@eecs.umich.edu vqshluCode = ''' 24917783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 24927639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) { 24937639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 24947639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 24957639Sgblack@eecs.umich.edu fpscr.qc = 1; 24967639Sgblack@eecs.umich.edu } else { 24977639Sgblack@eecs.umich.edu destElem = 0; 24987639Sgblack@eecs.umich.edu } 24997639Sgblack@eecs.umich.edu } else if (imm) { 25007639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm); 25017639Sgblack@eecs.umich.edu uint64_t topBits = bits((uint64_t)srcElem1, 25027639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1, 25037639Sgblack@eecs.umich.edu sizeof(Element) * 8 - imm); 25047639Sgblack@eecs.umich.edu if (topBits != 0) { 25057639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 25067639Sgblack@eecs.umich.edu fpscr.qc = 1; 25077639Sgblack@eecs.umich.edu } 25087639Sgblack@eecs.umich.edu } else { 25097639Sgblack@eecs.umich.edu destElem = srcElem1; 25107639Sgblack@eecs.umich.edu } 25117783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 25127639Sgblack@eecs.umich.edu ''' 25137760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlu", "NVqshluD", "SimdShiftOp", unsignedTypes, 2, vqshluCode) 25147760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlu", "NVqshluQ", "SimdShiftOp", unsignedTypes, 4, vqshluCode) 25157639Sgblack@eecs.umich.edu 25167639Sgblack@eecs.umich.edu vqshlusCode = ''' 25177783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 25187639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) { 25197639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 25207639Sgblack@eecs.umich.edu destElem = 0; 25217639Sgblack@eecs.umich.edu fpscr.qc = 1; 25227639Sgblack@eecs.umich.edu } else if (srcElem1 > 0) { 25237639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 25247639Sgblack@eecs.umich.edu fpscr.qc = 1; 25257639Sgblack@eecs.umich.edu } else { 25267639Sgblack@eecs.umich.edu destElem = 0; 25277639Sgblack@eecs.umich.edu } 25287639Sgblack@eecs.umich.edu } else if (imm) { 25297639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm); 25307639Sgblack@eecs.umich.edu uint64_t topBits = bits((uint64_t)srcElem1, 25317639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1, 25327639Sgblack@eecs.umich.edu sizeof(Element) * 8 - imm); 25337639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 25347639Sgblack@eecs.umich.edu destElem = 0; 25357639Sgblack@eecs.umich.edu fpscr.qc = 1; 25367639Sgblack@eecs.umich.edu } else if (topBits != 0) { 25377639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 25387639Sgblack@eecs.umich.edu fpscr.qc = 1; 25397639Sgblack@eecs.umich.edu } 25407639Sgblack@eecs.umich.edu } else { 25417639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 25427639Sgblack@eecs.umich.edu fpscr.qc = 1; 25437639Sgblack@eecs.umich.edu destElem = 0; 25447639Sgblack@eecs.umich.edu } else { 25457639Sgblack@eecs.umich.edu destElem = srcElem1; 25467639Sgblack@eecs.umich.edu } 25477639Sgblack@eecs.umich.edu } 25487783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 25497639Sgblack@eecs.umich.edu ''' 25507760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlus", "NVqshlusD", "SimdShiftOp", signedTypes, 2, vqshlusCode) 25517760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlus", "NVqshlusQ", "SimdShiftOp", signedTypes, 4, vqshlusCode) 25527639Sgblack@eecs.umich.edu 25537639Sgblack@eecs.umich.edu vshrnCode = ''' 25547639Sgblack@eecs.umich.edu if (imm >= sizeof(srcElem1) * 8) { 25557639Sgblack@eecs.umich.edu destElem = 0; 25567639Sgblack@eecs.umich.edu } else { 25577639Sgblack@eecs.umich.edu destElem = srcElem1 >> imm; 25587639Sgblack@eecs.umich.edu } 25597639Sgblack@eecs.umich.edu ''' 25607760SGiacomo.Gabrielli@arm.com twoRegNarrowShiftInst("vshrn", "NVshrn", "SimdShiftOp", smallUnsignedTypes, vshrnCode) 25617639Sgblack@eecs.umich.edu 25627639Sgblack@eecs.umich.edu vrshrnCode = ''' 25637639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 25647639Sgblack@eecs.umich.edu destElem = 0; 25657639Sgblack@eecs.umich.edu } else if (imm) { 25667639Sgblack@eecs.umich.edu Element rBit = bits(srcElem1, imm - 1); 25677639Sgblack@eecs.umich.edu destElem = ((srcElem1 >> (imm - 1)) >> 1) + rBit; 25687639Sgblack@eecs.umich.edu } else { 25697639Sgblack@eecs.umich.edu destElem = srcElem1; 25707639Sgblack@eecs.umich.edu } 25717639Sgblack@eecs.umich.edu ''' 25727760SGiacomo.Gabrielli@arm.com twoRegNarrowShiftInst("vrshrn", "NVrshrn", "SimdShiftOp", smallUnsignedTypes, vrshrnCode) 25737639Sgblack@eecs.umich.edu 25747639Sgblack@eecs.umich.edu vqshrnCode = ''' 25757783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 25767639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 25777639Sgblack@eecs.umich.edu if (srcElem1 != 0 && srcElem1 != -1) 25787639Sgblack@eecs.umich.edu fpscr.qc = 1; 25797639Sgblack@eecs.umich.edu destElem = 0; 25807639Sgblack@eecs.umich.edu } else if (imm) { 25817639Sgblack@eecs.umich.edu BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 25827639Sgblack@eecs.umich.edu mid |= -(mid & ((BigElement)1 << 25837639Sgblack@eecs.umich.edu (sizeof(BigElement) * 8 - 1 - imm))); 25847639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 25857639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 25867639Sgblack@eecs.umich.edu if (srcElem1 < 0) 25877639Sgblack@eecs.umich.edu destElem = ~destElem; 25887639Sgblack@eecs.umich.edu fpscr.qc = 1; 25897639Sgblack@eecs.umich.edu } else { 25907639Sgblack@eecs.umich.edu destElem = mid; 25917639Sgblack@eecs.umich.edu } 25927639Sgblack@eecs.umich.edu } else { 25937639Sgblack@eecs.umich.edu destElem = srcElem1; 25947639Sgblack@eecs.umich.edu } 25957783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 25967639Sgblack@eecs.umich.edu ''' 25977760SGiacomo.Gabrielli@arm.com twoRegNarrowShiftInst("vqshrn", "NVqshrn", "SimdShiftOp", smallSignedTypes, vqshrnCode) 25987639Sgblack@eecs.umich.edu 25997639Sgblack@eecs.umich.edu vqshrunCode = ''' 26007783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 26017639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 26027639Sgblack@eecs.umich.edu if (srcElem1 != 0) 26037639Sgblack@eecs.umich.edu fpscr.qc = 1; 26047639Sgblack@eecs.umich.edu destElem = 0; 26057639Sgblack@eecs.umich.edu } else if (imm) { 26067639Sgblack@eecs.umich.edu BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 26077639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 26087639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 26097639Sgblack@eecs.umich.edu fpscr.qc = 1; 26107639Sgblack@eecs.umich.edu } else { 26117639Sgblack@eecs.umich.edu destElem = mid; 26127639Sgblack@eecs.umich.edu } 26137639Sgblack@eecs.umich.edu } else { 26147639Sgblack@eecs.umich.edu destElem = srcElem1; 26157639Sgblack@eecs.umich.edu } 26167783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 26177639Sgblack@eecs.umich.edu ''' 26187639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqshrun", "NVqshrun", 26197760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallUnsignedTypes, vqshrunCode) 26207639Sgblack@eecs.umich.edu 26217639Sgblack@eecs.umich.edu vqshrunsCode = ''' 26227783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 26237639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 26247639Sgblack@eecs.umich.edu if (srcElem1 != 0) 26257639Sgblack@eecs.umich.edu fpscr.qc = 1; 26267639Sgblack@eecs.umich.edu destElem = 0; 26277639Sgblack@eecs.umich.edu } else if (imm) { 26287639Sgblack@eecs.umich.edu BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 26297639Sgblack@eecs.umich.edu if (bits(mid, sizeof(BigElement) * 8 - 1, 26307639Sgblack@eecs.umich.edu sizeof(Element) * 8) != 0) { 26317639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 26327639Sgblack@eecs.umich.edu destElem = 0; 26337639Sgblack@eecs.umich.edu } else { 26347639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 26357639Sgblack@eecs.umich.edu } 26367639Sgblack@eecs.umich.edu fpscr.qc = 1; 26377639Sgblack@eecs.umich.edu } else { 26387639Sgblack@eecs.umich.edu destElem = mid; 26397639Sgblack@eecs.umich.edu } 26407639Sgblack@eecs.umich.edu } else { 26417639Sgblack@eecs.umich.edu destElem = srcElem1; 26427639Sgblack@eecs.umich.edu } 26437783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 26447639Sgblack@eecs.umich.edu ''' 26457639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqshrun", "NVqshruns", 26467760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallSignedTypes, vqshrunsCode) 26477639Sgblack@eecs.umich.edu 26487639Sgblack@eecs.umich.edu vqrshrnCode = ''' 26497783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 26507639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 26517639Sgblack@eecs.umich.edu if (srcElem1 != 0 && srcElem1 != -1) 26527639Sgblack@eecs.umich.edu fpscr.qc = 1; 26537639Sgblack@eecs.umich.edu destElem = 0; 26547639Sgblack@eecs.umich.edu } else if (imm) { 26557639Sgblack@eecs.umich.edu BigElement mid = (srcElem1 >> (imm - 1)); 26567639Sgblack@eecs.umich.edu uint64_t rBit = mid & 0x1; 26577639Sgblack@eecs.umich.edu mid >>= 1; 26587639Sgblack@eecs.umich.edu mid |= -(mid & ((BigElement)1 << 26597639Sgblack@eecs.umich.edu (sizeof(BigElement) * 8 - 1 - imm))); 26607639Sgblack@eecs.umich.edu mid += rBit; 26617639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 26627639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 26637639Sgblack@eecs.umich.edu if (srcElem1 < 0) 26647639Sgblack@eecs.umich.edu destElem = ~destElem; 26657639Sgblack@eecs.umich.edu fpscr.qc = 1; 26667639Sgblack@eecs.umich.edu } else { 26677639Sgblack@eecs.umich.edu destElem = mid; 26687639Sgblack@eecs.umich.edu } 26697639Sgblack@eecs.umich.edu } else { 26707639Sgblack@eecs.umich.edu if (srcElem1 != (Element)srcElem1) { 26717639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 26727639Sgblack@eecs.umich.edu if (srcElem1 < 0) 26737639Sgblack@eecs.umich.edu destElem = ~destElem; 26747639Sgblack@eecs.umich.edu fpscr.qc = 1; 26757639Sgblack@eecs.umich.edu } else { 26767639Sgblack@eecs.umich.edu destElem = srcElem1; 26777639Sgblack@eecs.umich.edu } 26787639Sgblack@eecs.umich.edu } 26797783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 26807639Sgblack@eecs.umich.edu ''' 26817639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqrshrn", "NVqrshrn", 26827760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallSignedTypes, vqrshrnCode) 26837639Sgblack@eecs.umich.edu 26847639Sgblack@eecs.umich.edu vqrshrunCode = ''' 26857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 26867639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 26877639Sgblack@eecs.umich.edu if (srcElem1 != 0) 26887639Sgblack@eecs.umich.edu fpscr.qc = 1; 26897639Sgblack@eecs.umich.edu destElem = 0; 26907639Sgblack@eecs.umich.edu } else if (imm) { 26917639Sgblack@eecs.umich.edu BigElement mid = (srcElem1 >> (imm - 1)); 26927639Sgblack@eecs.umich.edu uint64_t rBit = mid & 0x1; 26937639Sgblack@eecs.umich.edu mid >>= 1; 26947639Sgblack@eecs.umich.edu mid += rBit; 26957639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 26967639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 26977639Sgblack@eecs.umich.edu fpscr.qc = 1; 26987639Sgblack@eecs.umich.edu } else { 26997639Sgblack@eecs.umich.edu destElem = mid; 27007639Sgblack@eecs.umich.edu } 27017639Sgblack@eecs.umich.edu } else { 27027639Sgblack@eecs.umich.edu if (srcElem1 != (Element)srcElem1) { 27037639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 27047639Sgblack@eecs.umich.edu fpscr.qc = 1; 27057639Sgblack@eecs.umich.edu } else { 27067639Sgblack@eecs.umich.edu destElem = srcElem1; 27077639Sgblack@eecs.umich.edu } 27087639Sgblack@eecs.umich.edu } 27097783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 27107639Sgblack@eecs.umich.edu ''' 27117639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqrshrun", "NVqrshrun", 27127760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallUnsignedTypes, vqrshrunCode) 27137639Sgblack@eecs.umich.edu 27147639Sgblack@eecs.umich.edu vqrshrunsCode = ''' 27157783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 27167639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 27177639Sgblack@eecs.umich.edu if (srcElem1 != 0) 27187639Sgblack@eecs.umich.edu fpscr.qc = 1; 27197639Sgblack@eecs.umich.edu destElem = 0; 27207639Sgblack@eecs.umich.edu } else if (imm) { 27217639Sgblack@eecs.umich.edu BigElement mid = (srcElem1 >> (imm - 1)); 27227639Sgblack@eecs.umich.edu uint64_t rBit = mid & 0x1; 27237639Sgblack@eecs.umich.edu mid >>= 1; 27247639Sgblack@eecs.umich.edu mid |= -(mid & ((BigElement)1 << 27257639Sgblack@eecs.umich.edu (sizeof(BigElement) * 8 - 1 - imm))); 27267639Sgblack@eecs.umich.edu mid += rBit; 27277639Sgblack@eecs.umich.edu if (bits(mid, sizeof(BigElement) * 8 - 1, 27287639Sgblack@eecs.umich.edu sizeof(Element) * 8) != 0) { 27297639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 27307639Sgblack@eecs.umich.edu destElem = 0; 27317639Sgblack@eecs.umich.edu } else { 27327639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 27337639Sgblack@eecs.umich.edu } 27347639Sgblack@eecs.umich.edu fpscr.qc = 1; 27357639Sgblack@eecs.umich.edu } else { 27367639Sgblack@eecs.umich.edu destElem = mid; 27377639Sgblack@eecs.umich.edu } 27387639Sgblack@eecs.umich.edu } else { 27397639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 27407639Sgblack@eecs.umich.edu fpscr.qc = 1; 27417639Sgblack@eecs.umich.edu destElem = 0; 27427639Sgblack@eecs.umich.edu } else { 27437639Sgblack@eecs.umich.edu destElem = srcElem1; 27447639Sgblack@eecs.umich.edu } 27457639Sgblack@eecs.umich.edu } 27467783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 27477639Sgblack@eecs.umich.edu ''' 27487639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqrshrun", "NVqrshruns", 27497760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallSignedTypes, vqrshrunsCode) 27507639Sgblack@eecs.umich.edu 27517639Sgblack@eecs.umich.edu vshllCode = ''' 27527639Sgblack@eecs.umich.edu if (imm >= sizeof(destElem) * 8) { 27537639Sgblack@eecs.umich.edu destElem = 0; 27547639Sgblack@eecs.umich.edu } else { 27557639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 << imm; 27567639Sgblack@eecs.umich.edu } 27577639Sgblack@eecs.umich.edu ''' 27587760SGiacomo.Gabrielli@arm.com twoRegLongShiftInst("vshll", "NVshll", "SimdShiftOp", smallTypes, vshllCode) 27597639Sgblack@eecs.umich.edu 27607639Sgblack@eecs.umich.edu vmovlCode = ''' 27617639Sgblack@eecs.umich.edu destElem = srcElem1; 27627639Sgblack@eecs.umich.edu ''' 27637760SGiacomo.Gabrielli@arm.com twoRegLongShiftInst("vmovl", "NVmovl", "SimdMiscOp", smallTypes, vmovlCode) 27647639Sgblack@eecs.umich.edu 27657639Sgblack@eecs.umich.edu vcvt2ufxCode = ''' 27667783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27677639Sgblack@eecs.umich.edu if (flushToZero(srcElem1)) 27687639Sgblack@eecs.umich.edu fpscr.idc = 1; 27697639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 27707639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcElem1) : "m" (srcElem1)); 27717639Sgblack@eecs.umich.edu destReg = vfpFpSToFixed(srcElem1, false, false, imm); 27727639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destReg)); 27737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 27747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27757639Sgblack@eecs.umich.edu ''' 27767760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2ufxD", "SimdCvtOp", ("float",), 27777639Sgblack@eecs.umich.edu 2, vcvt2ufxCode, toInt = True) 27787760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2ufxQ", "SimdCvtOp", ("float",), 27797639Sgblack@eecs.umich.edu 4, vcvt2ufxCode, toInt = True) 27807639Sgblack@eecs.umich.edu 27817639Sgblack@eecs.umich.edu vcvt2sfxCode = ''' 27827783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27837639Sgblack@eecs.umich.edu if (flushToZero(srcElem1)) 27847639Sgblack@eecs.umich.edu fpscr.idc = 1; 27857639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 27867639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcElem1) : "m" (srcElem1)); 27877639Sgblack@eecs.umich.edu destReg = vfpFpSToFixed(srcElem1, true, false, imm); 27887639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destReg)); 27897639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 27907783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27917639Sgblack@eecs.umich.edu ''' 27927760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2sfxD", "SimdCvtOp", ("float",), 27937639Sgblack@eecs.umich.edu 2, vcvt2sfxCode, toInt = True) 27947760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2sfxQ", "SimdCvtOp", ("float",), 27957639Sgblack@eecs.umich.edu 4, vcvt2sfxCode, toInt = True) 27967639Sgblack@eecs.umich.edu 27977639Sgblack@eecs.umich.edu vcvtu2fpCode = ''' 27987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27997639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 28007639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcReg1) : "m" (srcReg1)); 28017639Sgblack@eecs.umich.edu destElem = vfpUFixedToFpS(true, true, srcReg1, false, imm); 28027639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 28037639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 28047783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28057639Sgblack@eecs.umich.edu ''' 28067760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvtu2fpD", "SimdCvtOp", ("float",), 28077639Sgblack@eecs.umich.edu 2, vcvtu2fpCode, fromInt = True) 28087760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvtu2fpQ", "SimdCvtOp", ("float",), 28097639Sgblack@eecs.umich.edu 4, vcvtu2fpCode, fromInt = True) 28107639Sgblack@eecs.umich.edu 28117639Sgblack@eecs.umich.edu vcvts2fpCode = ''' 28127783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28137639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 28147639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcReg1) : "m" (srcReg1)); 28157639Sgblack@eecs.umich.edu destElem = vfpSFixedToFpS(true, true, srcReg1, false, imm); 28167639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 28177639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 28187783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28197639Sgblack@eecs.umich.edu ''' 28207760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvts2fpD", "SimdCvtOp", ("float",), 28217639Sgblack@eecs.umich.edu 2, vcvts2fpCode, fromInt = True) 28227760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvts2fpQ", "SimdCvtOp", ("float",), 28237639Sgblack@eecs.umich.edu 4, vcvts2fpCode, fromInt = True) 28247639Sgblack@eecs.umich.edu 28257639Sgblack@eecs.umich.edu vcvts2hCode = ''' 28267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28277639Sgblack@eecs.umich.edu float srcFp1 = bitsToFp(srcElem1, (float)0.0); 28287639Sgblack@eecs.umich.edu if (flushToZero(srcFp1)) 28297639Sgblack@eecs.umich.edu fpscr.idc = 1; 28307639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 28317639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcFp1), "=m" (destElem) 28327639Sgblack@eecs.umich.edu : "m" (srcFp1), "m" (destElem)); 28337639Sgblack@eecs.umich.edu destElem = vcvtFpSFpH(fpscr, true, true, VfpRoundNearest, 28347639Sgblack@eecs.umich.edu fpscr.ahp, srcFp1); 28357639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 28367639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 28377783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28387639Sgblack@eecs.umich.edu ''' 28397760SGiacomo.Gabrielli@arm.com twoRegNarrowMiscInst("vcvt", "NVcvts2h", "SimdCvtOp", ("uint16_t",), vcvts2hCode) 28407639Sgblack@eecs.umich.edu 28417639Sgblack@eecs.umich.edu vcvth2sCode = ''' 28427783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28437639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 28447639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcElem1), "=m" (destElem) 28457639Sgblack@eecs.umich.edu : "m" (srcElem1), "m" (destElem)); 28467639Sgblack@eecs.umich.edu destElem = fpToBits(vcvtFpHFpS(fpscr, true, fpscr.ahp, srcElem1)); 28477639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 28487639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 28497783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28507639Sgblack@eecs.umich.edu ''' 28517760SGiacomo.Gabrielli@arm.com twoRegLongMiscInst("vcvt", "NVcvth2s", "SimdCvtOp", ("uint16_t",), vcvth2sCode) 28527639Sgblack@eecs.umich.edu 28537639Sgblack@eecs.umich.edu vrsqrteCode = ''' 28547639Sgblack@eecs.umich.edu destElem = unsignedRSqrtEstimate(srcElem1); 28557639Sgblack@eecs.umich.edu ''' 28567760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrsqrte", "NVrsqrteD", "SimdSqrtOp", ("uint32_t",), 2, vrsqrteCode) 28577760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrsqrte", "NVrsqrteQ", "SimdSqrtOp", ("uint32_t",), 4, vrsqrteCode) 28587639Sgblack@eecs.umich.edu 28597639Sgblack@eecs.umich.edu vrsqrtefpCode = ''' 28607783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28617639Sgblack@eecs.umich.edu if (flushToZero(srcReg1)) 28627639Sgblack@eecs.umich.edu fpscr.idc = 1; 28637639Sgblack@eecs.umich.edu destReg = fprSqrtEstimate(fpscr, srcReg1); 28647783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28657639Sgblack@eecs.umich.edu ''' 28667760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrsqrte", "NVrsqrteDFp", "SimdFloatSqrtOp", ("float",), 2, vrsqrtefpCode) 28677760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrsqrte", "NVrsqrteQFp", "SimdFloatSqrtOp", ("float",), 4, vrsqrtefpCode) 28687639Sgblack@eecs.umich.edu 28697639Sgblack@eecs.umich.edu vrecpeCode = ''' 28707639Sgblack@eecs.umich.edu destElem = unsignedRecipEstimate(srcElem1); 28717639Sgblack@eecs.umich.edu ''' 28727760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrecpe", "NVrecpeD", "SimdMultAccOp", ("uint32_t",), 2, vrecpeCode) 28737760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrecpe", "NVrecpeQ", "SimdMultAccOp", ("uint32_t",), 4, vrecpeCode) 28747639Sgblack@eecs.umich.edu 28757639Sgblack@eecs.umich.edu vrecpefpCode = ''' 28767783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28777639Sgblack@eecs.umich.edu if (flushToZero(srcReg1)) 28787639Sgblack@eecs.umich.edu fpscr.idc = 1; 28797639Sgblack@eecs.umich.edu destReg = fpRecipEstimate(fpscr, srcReg1); 28807783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28817639Sgblack@eecs.umich.edu ''' 28827760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrecpe", "NVrecpeDFp", "SimdFloatMultAccOp", ("float",), 2, vrecpefpCode) 28837760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrecpe", "NVrecpeQFp", "SimdFloatMultAccOp", ("float",), 4, vrecpefpCode) 28847639Sgblack@eecs.umich.edu 28857639Sgblack@eecs.umich.edu vrev16Code = ''' 28867639Sgblack@eecs.umich.edu destElem = srcElem1; 28877639Sgblack@eecs.umich.edu unsigned groupSize = ((1 << 1) / sizeof(Element)); 28887639Sgblack@eecs.umich.edu unsigned reverseMask = (groupSize - 1); 28897639Sgblack@eecs.umich.edu j = i ^ reverseMask; 28907639Sgblack@eecs.umich.edu ''' 28917760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev16", "NVrev16D", "SimdAluOp", ("uint8_t",), 2, vrev16Code) 28927760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev16", "NVrev16Q", "SimdAluOp", ("uint8_t",), 4, vrev16Code) 28937639Sgblack@eecs.umich.edu vrev32Code = ''' 28947639Sgblack@eecs.umich.edu destElem = srcElem1; 28957639Sgblack@eecs.umich.edu unsigned groupSize = ((1 << 2) / sizeof(Element)); 28967639Sgblack@eecs.umich.edu unsigned reverseMask = (groupSize - 1); 28977639Sgblack@eecs.umich.edu j = i ^ reverseMask; 28987639Sgblack@eecs.umich.edu ''' 28997639Sgblack@eecs.umich.edu twoRegMiscInst("vrev32", "NVrev32D", 29007760SGiacomo.Gabrielli@arm.com "SimdAluOp", ("uint8_t", "uint16_t"), 2, vrev32Code) 29017639Sgblack@eecs.umich.edu twoRegMiscInst("vrev32", "NVrev32Q", 29027760SGiacomo.Gabrielli@arm.com "SimdAluOp", ("uint8_t", "uint16_t"), 4, vrev32Code) 29037639Sgblack@eecs.umich.edu vrev64Code = ''' 29047639Sgblack@eecs.umich.edu destElem = srcElem1; 29057639Sgblack@eecs.umich.edu unsigned groupSize = ((1 << 3) / sizeof(Element)); 29067639Sgblack@eecs.umich.edu unsigned reverseMask = (groupSize - 1); 29077639Sgblack@eecs.umich.edu j = i ^ reverseMask; 29087639Sgblack@eecs.umich.edu ''' 29097760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev64", "NVrev64D", "SimdAluOp", smallUnsignedTypes, 2, vrev64Code) 29107760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev64", "NVrev64Q", "SimdAluOp", smallUnsignedTypes, 4, vrev64Code) 29117639Sgblack@eecs.umich.edu 29127639Sgblack@eecs.umich.edu vpaddlCode = ''' 29137639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 + (BigElement)srcElem2; 29147639Sgblack@eecs.umich.edu ''' 29157760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpaddl", "NVpaddlD", "SimdAddOp", smallTypes, 2, vpaddlCode) 29167760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpaddl", "NVpaddlQ", "SimdAddOp", smallTypes, 4, vpaddlCode) 29177639Sgblack@eecs.umich.edu 29187639Sgblack@eecs.umich.edu vpadalCode = ''' 29197639Sgblack@eecs.umich.edu destElem += (BigElement)srcElem1 + (BigElement)srcElem2; 29207639Sgblack@eecs.umich.edu ''' 29217760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpadal", "NVpadalD", "SimdAddAccOp", smallTypes, 2, vpadalCode, True) 29227760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpadal", "NVpadalQ", "SimdAddAccOp", smallTypes, 4, vpadalCode, True) 29237639Sgblack@eecs.umich.edu 29247639Sgblack@eecs.umich.edu vclsCode = ''' 29257639Sgblack@eecs.umich.edu unsigned count = 0; 29267639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 29277639Sgblack@eecs.umich.edu srcElem1 <<= 1; 29287639Sgblack@eecs.umich.edu while (srcElem1 < 0 && count < sizeof(Element) * 8 - 1) { 29297639Sgblack@eecs.umich.edu count++; 29307639Sgblack@eecs.umich.edu srcElem1 <<= 1; 29317639Sgblack@eecs.umich.edu } 29327639Sgblack@eecs.umich.edu } else { 29337639Sgblack@eecs.umich.edu srcElem1 <<= 1; 29347639Sgblack@eecs.umich.edu while (srcElem1 >= 0 && count < sizeof(Element) * 8 - 1) { 29357639Sgblack@eecs.umich.edu count++; 29367639Sgblack@eecs.umich.edu srcElem1 <<= 1; 29377639Sgblack@eecs.umich.edu } 29387639Sgblack@eecs.umich.edu } 29397639Sgblack@eecs.umich.edu destElem = count; 29407639Sgblack@eecs.umich.edu ''' 29417760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcls", "NVclsD", "SimdAluOp", signedTypes, 2, vclsCode) 29427760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcls", "NVclsQ", "SimdAluOp", signedTypes, 4, vclsCode) 29437639Sgblack@eecs.umich.edu 29447639Sgblack@eecs.umich.edu vclzCode = ''' 29457639Sgblack@eecs.umich.edu unsigned count = 0; 29467639Sgblack@eecs.umich.edu while (srcElem1 >= 0 && count < sizeof(Element) * 8) { 29477639Sgblack@eecs.umich.edu count++; 29487639Sgblack@eecs.umich.edu srcElem1 <<= 1; 29497639Sgblack@eecs.umich.edu } 29507639Sgblack@eecs.umich.edu destElem = count; 29517639Sgblack@eecs.umich.edu ''' 29527760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclz", "NVclzD", "SimdAluOp", signedTypes, 2, vclzCode) 29537760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclz", "NVclzQ", "SimdAluOp", signedTypes, 4, vclzCode) 29547639Sgblack@eecs.umich.edu 29557639Sgblack@eecs.umich.edu vcntCode = ''' 29567639Sgblack@eecs.umich.edu unsigned count = 0; 29577639Sgblack@eecs.umich.edu while (srcElem1 && count < sizeof(Element) * 8) { 29587639Sgblack@eecs.umich.edu count += srcElem1 & 0x1; 29597639Sgblack@eecs.umich.edu srcElem1 >>= 1; 29607639Sgblack@eecs.umich.edu } 29617639Sgblack@eecs.umich.edu destElem = count; 29627639Sgblack@eecs.umich.edu ''' 29637760SGiacomo.Gabrielli@arm.com 29647760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcnt", "NVcntD", "SimdAluOp", unsignedTypes, 2, vcntCode) 29657760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcnt", "NVcntQ", "SimdAluOp", unsignedTypes, 4, vcntCode) 29667639Sgblack@eecs.umich.edu 29677639Sgblack@eecs.umich.edu vmvnCode = ''' 29687639Sgblack@eecs.umich.edu destElem = ~srcElem1; 29697639Sgblack@eecs.umich.edu ''' 29707760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vmvn", "NVmvnD", "SimdAluOp", ("uint64_t",), 2, vmvnCode) 29717760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vmvn", "NVmvnQ", "SimdAluOp", ("uint64_t",), 4, vmvnCode) 29727639Sgblack@eecs.umich.edu 29737639Sgblack@eecs.umich.edu vqabsCode = ''' 29747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 29757639Sgblack@eecs.umich.edu if (srcElem1 == (Element)((Element)1 << (sizeof(Element) * 8 - 1))) { 29767639Sgblack@eecs.umich.edu fpscr.qc = 1; 29777639Sgblack@eecs.umich.edu destElem = ~srcElem1; 29787639Sgblack@eecs.umich.edu } else if (srcElem1 < 0) { 29797639Sgblack@eecs.umich.edu destElem = -srcElem1; 29807639Sgblack@eecs.umich.edu } else { 29817639Sgblack@eecs.umich.edu destElem = srcElem1; 29827639Sgblack@eecs.umich.edu } 29837783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 29847639Sgblack@eecs.umich.edu ''' 29857760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqabs", "NVqabsD", "SimdAluOp", signedTypes, 2, vqabsCode) 29867760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqabs", "NVqabsQ", "SimdAluOp", signedTypes, 4, vqabsCode) 29877639Sgblack@eecs.umich.edu 29887639Sgblack@eecs.umich.edu vqnegCode = ''' 29897783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 29907639Sgblack@eecs.umich.edu if (srcElem1 == (Element)((Element)1 << (sizeof(Element) * 8 - 1))) { 29917639Sgblack@eecs.umich.edu fpscr.qc = 1; 29927639Sgblack@eecs.umich.edu destElem = ~srcElem1; 29937639Sgblack@eecs.umich.edu } else { 29947639Sgblack@eecs.umich.edu destElem = -srcElem1; 29957639Sgblack@eecs.umich.edu } 29967783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 29977639Sgblack@eecs.umich.edu ''' 29987760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqneg", "NVqnegD", "SimdAluOp", signedTypes, 2, vqnegCode) 29997760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqneg", "NVqnegQ", "SimdAluOp", signedTypes, 4, vqnegCode) 30007639Sgblack@eecs.umich.edu 30017639Sgblack@eecs.umich.edu vabsCode = ''' 30027639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 30037639Sgblack@eecs.umich.edu destElem = -srcElem1; 30047639Sgblack@eecs.umich.edu } else { 30057639Sgblack@eecs.umich.edu destElem = srcElem1; 30067639Sgblack@eecs.umich.edu } 30077639Sgblack@eecs.umich.edu ''' 30087760SGiacomo.Gabrielli@arm.com 30097760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vabs", "NVabsD", "SimdAluOp", signedTypes, 2, vabsCode) 30107760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vabs", "NVabsQ", "SimdAluOp", signedTypes, 4, vabsCode) 30117639Sgblack@eecs.umich.edu vabsfpCode = ''' 30127639Sgblack@eecs.umich.edu union 30137639Sgblack@eecs.umich.edu { 30147639Sgblack@eecs.umich.edu uint32_t i; 30157639Sgblack@eecs.umich.edu float f; 30167639Sgblack@eecs.umich.edu } cStruct; 30177639Sgblack@eecs.umich.edu cStruct.f = srcReg1; 30187639Sgblack@eecs.umich.edu cStruct.i &= mask(sizeof(Element) * 8 - 1); 30197639Sgblack@eecs.umich.edu destReg = cStruct.f; 30207639Sgblack@eecs.umich.edu ''' 30217760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vabs", "NVabsDFp", "SimdFloatAluOp", ("float",), 2, vabsfpCode) 30227760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vabs", "NVabsQFp", "SimdFloatAluOp", ("float",), 4, vabsfpCode) 30237639Sgblack@eecs.umich.edu 30247639Sgblack@eecs.umich.edu vnegCode = ''' 30257639Sgblack@eecs.umich.edu destElem = -srcElem1; 30267639Sgblack@eecs.umich.edu ''' 30277760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vneg", "NVnegD", "SimdAluOp", signedTypes, 2, vnegCode) 30287760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vneg", "NVnegQ", "SimdAluOp", signedTypes, 4, vnegCode) 30297639Sgblack@eecs.umich.edu vnegfpCode = ''' 30307639Sgblack@eecs.umich.edu destReg = -srcReg1; 30317639Sgblack@eecs.umich.edu ''' 30327760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vneg", "NVnegDFp", "SimdFloatAluOp", ("float",), 2, vnegfpCode) 30337760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vneg", "NVnegQFp", "SimdFloatAluOp", ("float",), 4, vnegfpCode) 30347639Sgblack@eecs.umich.edu 30357639Sgblack@eecs.umich.edu vcgtCode = 'destElem = (srcElem1 > 0) ? mask(sizeof(Element) * 8) : 0;' 30367760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcgt", "NVcgtD", "SimdCmpOp", signedTypes, 2, vcgtCode) 30377760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcgt", "NVcgtQ", "SimdCmpOp", signedTypes, 4, vcgtCode) 30387639Sgblack@eecs.umich.edu vcgtfpCode = ''' 30397783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 30407639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcgtFunc, 30417639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 30427639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 30437639Sgblack@eecs.umich.edu if (res == 2.0) 30447639Sgblack@eecs.umich.edu fpscr.ioc = 1; 30457783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 30467639Sgblack@eecs.umich.edu ''' 30477760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcgt", "NVcgtDFp", "SimdFloatCmpOp", ("float",), 30487639Sgblack@eecs.umich.edu 2, vcgtfpCode, toInt = True) 30497760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcgt", "NVcgtQFp", "SimdFloatCmpOp", ("float",), 30507639Sgblack@eecs.umich.edu 4, vcgtfpCode, toInt = True) 30517639Sgblack@eecs.umich.edu 30527639Sgblack@eecs.umich.edu vcgeCode = 'destElem = (srcElem1 >= 0) ? mask(sizeof(Element) * 8) : 0;' 30537760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcge", "NVcgeD", "SimdCmpOp", signedTypes, 2, vcgeCode) 30547760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcge", "NVcgeQ", "SimdCmpOp", signedTypes, 4, vcgeCode) 30557639Sgblack@eecs.umich.edu vcgefpCode = ''' 30567783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 30577639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcgeFunc, 30587639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 30597639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 30607639Sgblack@eecs.umich.edu if (res == 2.0) 30617639Sgblack@eecs.umich.edu fpscr.ioc = 1; 30627783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 30637639Sgblack@eecs.umich.edu ''' 30647760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcge", "NVcgeDFp", "SimdFloatCmpOp", ("float",), 30657639Sgblack@eecs.umich.edu 2, vcgefpCode, toInt = True) 30667760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcge", "NVcgeQFp", "SimdFloatCmpOp", ("float",), 30677639Sgblack@eecs.umich.edu 4, vcgefpCode, toInt = True) 30687639Sgblack@eecs.umich.edu 30697639Sgblack@eecs.umich.edu vceqCode = 'destElem = (srcElem1 == 0) ? mask(sizeof(Element) * 8) : 0;' 30707760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vceq", "NVceqD", "SimdCmpOp", signedTypes, 2, vceqCode) 30717760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vceq", "NVceqQ", "SimdCmpOp", signedTypes, 4, vceqCode) 30727639Sgblack@eecs.umich.edu vceqfpCode = ''' 30737783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 30747639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vceqFunc, 30757639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 30767639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 30777639Sgblack@eecs.umich.edu if (res == 2.0) 30787639Sgblack@eecs.umich.edu fpscr.ioc = 1; 30797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 30807639Sgblack@eecs.umich.edu ''' 30817760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vceq", "NVceqDFp", "SimdFloatCmpOp", ("float",), 30827639Sgblack@eecs.umich.edu 2, vceqfpCode, toInt = True) 30837760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vceq", "NVceqQFp", "SimdFloatCmpOp", ("float",), 30847639Sgblack@eecs.umich.edu 4, vceqfpCode, toInt = True) 30857639Sgblack@eecs.umich.edu 30867639Sgblack@eecs.umich.edu vcleCode = 'destElem = (srcElem1 <= 0) ? mask(sizeof(Element) * 8) : 0;' 30877760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcle", "NVcleD", "SimdCmpOp", signedTypes, 2, vcleCode) 30887760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcle", "NVcleQ", "SimdCmpOp", signedTypes, 4, vcleCode) 30897639Sgblack@eecs.umich.edu vclefpCode = ''' 30907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 30917639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcleFunc, 30927639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 30937639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 30947639Sgblack@eecs.umich.edu if (res == 2.0) 30957639Sgblack@eecs.umich.edu fpscr.ioc = 1; 30967783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 30977639Sgblack@eecs.umich.edu ''' 30987760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcle", "NVcleDFp", "SimdFloatCmpOp", ("float",), 30997639Sgblack@eecs.umich.edu 2, vclefpCode, toInt = True) 31007760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcle", "NVcleQFp", "SimdFloatCmpOp", ("float",), 31017639Sgblack@eecs.umich.edu 4, vclefpCode, toInt = True) 31027639Sgblack@eecs.umich.edu 31037639Sgblack@eecs.umich.edu vcltCode = 'destElem = (srcElem1 < 0) ? mask(sizeof(Element) * 8) : 0;' 31047760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclt", "NVcltD", "SimdCmpOp", signedTypes, 2, vcltCode) 31057760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclt", "NVcltQ", "SimdCmpOp", signedTypes, 4, vcltCode) 31067639Sgblack@eecs.umich.edu vcltfpCode = ''' 31077783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 31087639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcltFunc, 31097639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 31107639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 31117639Sgblack@eecs.umich.edu if (res == 2.0) 31127639Sgblack@eecs.umich.edu fpscr.ioc = 1; 31137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 31147639Sgblack@eecs.umich.edu ''' 31157760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vclt", "NVcltDFp", "SimdFloatCmpOp", ("float",), 31167639Sgblack@eecs.umich.edu 2, vcltfpCode, toInt = True) 31177760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vclt", "NVcltQFp", "SimdFloatCmpOp", ("float",), 31187639Sgblack@eecs.umich.edu 4, vcltfpCode, toInt = True) 31197639Sgblack@eecs.umich.edu 31207639Sgblack@eecs.umich.edu vswpCode = ''' 31217639Sgblack@eecs.umich.edu FloatRegBits mid; 31227639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 31237639Sgblack@eecs.umich.edu mid = srcReg1.regs[r]; 31247639Sgblack@eecs.umich.edu srcReg1.regs[r] = destReg.regs[r]; 31257639Sgblack@eecs.umich.edu destReg.regs[r] = mid; 31267639Sgblack@eecs.umich.edu } 31277639Sgblack@eecs.umich.edu ''' 31287760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vswp", "NVswpD", "SimdAluOp", ("uint64_t",), 2, vswpCode) 31297760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vswp", "NVswpQ", "SimdAluOp", ("uint64_t",), 4, vswpCode) 31307639Sgblack@eecs.umich.edu 31317639Sgblack@eecs.umich.edu vtrnCode = ''' 31327639Sgblack@eecs.umich.edu Element mid; 31337639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i += 2) { 31347639Sgblack@eecs.umich.edu mid = srcReg1.elements[i]; 31357639Sgblack@eecs.umich.edu srcReg1.elements[i] = destReg.elements[i + 1]; 31367639Sgblack@eecs.umich.edu destReg.elements[i + 1] = mid; 31377639Sgblack@eecs.umich.edu } 31387639Sgblack@eecs.umich.edu ''' 31398607Sgblack@eecs.umich.edu twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", 31408607Sgblack@eecs.umich.edu smallUnsignedTypes, 2, vtrnCode) 31418607Sgblack@eecs.umich.edu twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", 31428607Sgblack@eecs.umich.edu smallUnsignedTypes, 4, vtrnCode) 31437639Sgblack@eecs.umich.edu 31447639Sgblack@eecs.umich.edu vuzpCode = ''' 31457639Sgblack@eecs.umich.edu Element mid[eCount]; 31467639Sgblack@eecs.umich.edu memcpy(&mid, &srcReg1, sizeof(srcReg1)); 31477639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 31487639Sgblack@eecs.umich.edu srcReg1.elements[i] = destReg.elements[2 * i + 1]; 31497639Sgblack@eecs.umich.edu srcReg1.elements[eCount / 2 + i] = mid[2 * i + 1]; 31507639Sgblack@eecs.umich.edu destReg.elements[i] = destReg.elements[2 * i]; 31517639Sgblack@eecs.umich.edu } 31527639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 31537639Sgblack@eecs.umich.edu destReg.elements[eCount / 2 + i] = mid[2 * i]; 31547639Sgblack@eecs.umich.edu } 31557639Sgblack@eecs.umich.edu ''' 31567760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vuzp", "NVuzpD", "SimdAluOp", unsignedTypes, 2, vuzpCode) 31577760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vuzp", "NVuzpQ", "SimdAluOp", unsignedTypes, 4, vuzpCode) 31587639Sgblack@eecs.umich.edu 31597639Sgblack@eecs.umich.edu vzipCode = ''' 31607639Sgblack@eecs.umich.edu Element mid[eCount]; 31617639Sgblack@eecs.umich.edu memcpy(&mid, &destReg, sizeof(destReg)); 31627639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 31637639Sgblack@eecs.umich.edu destReg.elements[2 * i] = mid[i]; 31647639Sgblack@eecs.umich.edu destReg.elements[2 * i + 1] = srcReg1.elements[i]; 31657639Sgblack@eecs.umich.edu } 31667639Sgblack@eecs.umich.edu for (int i = 0; i < eCount / 2; i++) { 31677639Sgblack@eecs.umich.edu srcReg1.elements[2 * i] = mid[eCount / 2 + i]; 31687639Sgblack@eecs.umich.edu srcReg1.elements[2 * i + 1] = srcReg1.elements[eCount / 2 + i]; 31697639Sgblack@eecs.umich.edu } 31707639Sgblack@eecs.umich.edu ''' 31717760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vzip", "NVzipD", "SimdAluOp", unsignedTypes, 2, vzipCode) 31727760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vzip", "NVzipQ", "SimdAluOp", unsignedTypes, 4, vzipCode) 31737639Sgblack@eecs.umich.edu 31747639Sgblack@eecs.umich.edu vmovnCode = 'destElem = srcElem1;' 31757760SGiacomo.Gabrielli@arm.com twoRegNarrowMiscInst("vmovn", "NVmovn", "SimdMiscOp", smallUnsignedTypes, vmovnCode) 31767639Sgblack@eecs.umich.edu 31777639Sgblack@eecs.umich.edu vdupCode = 'destElem = srcElem1;' 31787760SGiacomo.Gabrielli@arm.com twoRegMiscScInst("vdup", "NVdupD", "SimdAluOp", smallUnsignedTypes, 2, vdupCode) 31797760SGiacomo.Gabrielli@arm.com twoRegMiscScInst("vdup", "NVdupQ", "SimdAluOp", smallUnsignedTypes, 4, vdupCode) 31807639Sgblack@eecs.umich.edu 31817760SGiacomo.Gabrielli@arm.com def vdupGprInst(name, Name, opClass, types, rCount): 31827639Sgblack@eecs.umich.edu global header_output, exec_output 31837639Sgblack@eecs.umich.edu eWalkCode = ''' 31847639Sgblack@eecs.umich.edu RegVect destReg; 31857639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 31867639Sgblack@eecs.umich.edu destReg.elements[i] = htog((Element)Op1); 31877639Sgblack@eecs.umich.edu } 31887639Sgblack@eecs.umich.edu ''' 31897639Sgblack@eecs.umich.edu for reg in range(rCount): 31907639Sgblack@eecs.umich.edu eWalkCode += ''' 31918588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 31927639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 31937639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 31947639Sgblack@eecs.umich.edu "RegRegOp", 31957639Sgblack@eecs.umich.edu { "code": eWalkCode, 31967639Sgblack@eecs.umich.edu "r_count": rCount, 31977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 31987760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 31997639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 32007639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 32017639Sgblack@eecs.umich.edu for type in types: 32027639Sgblack@eecs.umich.edu substDict = { "targs" : type, 32037639Sgblack@eecs.umich.edu "class_name" : Name } 32047639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 32058206SWilliam.Wang@arm.com vdupGprInst("vdup", "NVdupDGpr", "SimdMiscOp", smallUnsignedTypes, 2) 32068206SWilliam.Wang@arm.com vdupGprInst("vdup", "NVdupQGpr", "SimdMiscOp", smallUnsignedTypes, 4) 32077639Sgblack@eecs.umich.edu 32087639Sgblack@eecs.umich.edu vmovCode = 'destElem = imm;' 32097760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmov", "NVmoviD", "SimdMiscOp", ("uint64_t",), 2, vmovCode) 32107760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmov", "NVmoviQ", "SimdMiscOp", ("uint64_t",), 4, vmovCode) 32117639Sgblack@eecs.umich.edu 32127639Sgblack@eecs.umich.edu vorrCode = 'destElem |= imm;' 32137760SGiacomo.Gabrielli@arm.com oneRegImmInst("vorr", "NVorriD", "SimdAluOp", ("uint64_t",), 2, vorrCode, True) 32147760SGiacomo.Gabrielli@arm.com oneRegImmInst("vorr", "NVorriQ", "SimdAluOp", ("uint64_t",), 4, vorrCode, True) 32157639Sgblack@eecs.umich.edu 32167639Sgblack@eecs.umich.edu vmvnCode = 'destElem = ~imm;' 32177760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmvn", "NVmvniD", "SimdAluOp", ("uint64_t",), 2, vmvnCode) 32187760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmvn", "NVmvniQ", "SimdAluOp", ("uint64_t",), 4, vmvnCode) 32197639Sgblack@eecs.umich.edu 32207639Sgblack@eecs.umich.edu vbicCode = 'destElem &= ~imm;' 32217760SGiacomo.Gabrielli@arm.com oneRegImmInst("vbic", "NVbiciD", "SimdAluOp", ("uint64_t",), 2, vbicCode, True) 32227760SGiacomo.Gabrielli@arm.com oneRegImmInst("vbic", "NVbiciQ", "SimdAluOp", ("uint64_t",), 4, vbicCode, True) 32237639Sgblack@eecs.umich.edu 32247639Sgblack@eecs.umich.edu vqmovnCode = ''' 32257783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 32267639Sgblack@eecs.umich.edu destElem = srcElem1; 32277639Sgblack@eecs.umich.edu if ((BigElement)destElem != srcElem1) { 32287639Sgblack@eecs.umich.edu fpscr.qc = 1; 32297639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 32307639Sgblack@eecs.umich.edu if (srcElem1 < 0) 32317639Sgblack@eecs.umich.edu destElem = ~destElem; 32327639Sgblack@eecs.umich.edu } 32337783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 32347639Sgblack@eecs.umich.edu ''' 32357760SGiacomo.Gabrielli@arm.com twoRegNarrowMiscInst("vqmovn", "NVqmovn", "SimdMiscOp", smallSignedTypes, vqmovnCode) 32367639Sgblack@eecs.umich.edu 32377639Sgblack@eecs.umich.edu vqmovunCode = ''' 32387783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 32397639Sgblack@eecs.umich.edu destElem = srcElem1; 32407639Sgblack@eecs.umich.edu if ((BigElement)destElem != srcElem1) { 32417639Sgblack@eecs.umich.edu fpscr.qc = 1; 32427639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 32437639Sgblack@eecs.umich.edu } 32447783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 32457639Sgblack@eecs.umich.edu ''' 32467639Sgblack@eecs.umich.edu twoRegNarrowMiscInst("vqmovun", "NVqmovun", 32477760SGiacomo.Gabrielli@arm.com "SimdMiscOp", smallUnsignedTypes, vqmovunCode) 32487639Sgblack@eecs.umich.edu 32497639Sgblack@eecs.umich.edu vqmovunsCode = ''' 32507783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 32517639Sgblack@eecs.umich.edu destElem = srcElem1; 32527639Sgblack@eecs.umich.edu if (srcElem1 < 0 || 32537639Sgblack@eecs.umich.edu ((BigElement)destElem & mask(sizeof(Element) * 8)) != srcElem1) { 32547639Sgblack@eecs.umich.edu fpscr.qc = 1; 32557639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 32567639Sgblack@eecs.umich.edu if (srcElem1 < 0) 32577639Sgblack@eecs.umich.edu destElem = ~destElem; 32587639Sgblack@eecs.umich.edu } 32597783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 32607639Sgblack@eecs.umich.edu ''' 32617639Sgblack@eecs.umich.edu twoRegNarrowMiscInst("vqmovun", "NVqmovuns", 32627760SGiacomo.Gabrielli@arm.com "SimdMiscOp", smallSignedTypes, vqmovunsCode) 32637639Sgblack@eecs.umich.edu 32647760SGiacomo.Gabrielli@arm.com def buildVext(name, Name, opClass, types, rCount, op): 32657639Sgblack@eecs.umich.edu global header_output, exec_output 32667639Sgblack@eecs.umich.edu eWalkCode = ''' 32677639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2, destReg; 32687639Sgblack@eecs.umich.edu ''' 32697639Sgblack@eecs.umich.edu for reg in range(rCount): 32707644Sali.saidi@arm.com eWalkCode += simdEnabledCheckCode + ''' 32718588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 32728588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 32737639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 32747639Sgblack@eecs.umich.edu eWalkCode += op 32757639Sgblack@eecs.umich.edu for reg in range(rCount): 32767639Sgblack@eecs.umich.edu eWalkCode += ''' 32778588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 32787639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 32797639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 32807639Sgblack@eecs.umich.edu "RegRegRegImmOp", 32817639Sgblack@eecs.umich.edu { "code": eWalkCode, 32827639Sgblack@eecs.umich.edu "r_count": rCount, 32837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 32847760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 32857639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 32867639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 32877639Sgblack@eecs.umich.edu for type in types: 32887639Sgblack@eecs.umich.edu substDict = { "targs" : type, 32897639Sgblack@eecs.umich.edu "class_name" : Name } 32907639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 32917639Sgblack@eecs.umich.edu 32927639Sgblack@eecs.umich.edu vextCode = ''' 32937639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 32947639Sgblack@eecs.umich.edu unsigned index = i + imm; 32957639Sgblack@eecs.umich.edu if (index < eCount) { 32967639Sgblack@eecs.umich.edu destReg.elements[i] = srcReg1.elements[index]; 32977639Sgblack@eecs.umich.edu } else { 32987639Sgblack@eecs.umich.edu index -= eCount; 32997853SMatt.Horsnell@ARM.com if (index >= eCount) 33007853SMatt.Horsnell@ARM.com#if FULL_SYSTEM 33017853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction; 33027853SMatt.Horsnell@ARM.com#else 33037853SMatt.Horsnell@ARM.com fault = new UndefinedInstruction(false, mnemonic); 33047853SMatt.Horsnell@ARM.com#endif 33057853SMatt.Horsnell@ARM.com else 33067853SMatt.Horsnell@ARM.com destReg.elements[i] = srcReg2.elements[index]; 33077639Sgblack@eecs.umich.edu } 33087639Sgblack@eecs.umich.edu } 33097639Sgblack@eecs.umich.edu ''' 33108206SWilliam.Wang@arm.com buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode) 33118206SWilliam.Wang@arm.com buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode) 33127639Sgblack@eecs.umich.edu 33137760SGiacomo.Gabrielli@arm.com def buildVtbxl(name, Name, opClass, length, isVtbl): 33147639Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 33157639Sgblack@eecs.umich.edu code = ''' 33167639Sgblack@eecs.umich.edu union 33177639Sgblack@eecs.umich.edu { 33187639Sgblack@eecs.umich.edu uint8_t bytes[32]; 33197639Sgblack@eecs.umich.edu FloatRegBits regs[8]; 33207639Sgblack@eecs.umich.edu } table; 33217639Sgblack@eecs.umich.edu 33227639Sgblack@eecs.umich.edu union 33237639Sgblack@eecs.umich.edu { 33247639Sgblack@eecs.umich.edu uint8_t bytes[8]; 33257639Sgblack@eecs.umich.edu FloatRegBits regs[2]; 33267639Sgblack@eecs.umich.edu } destReg, srcReg2; 33277639Sgblack@eecs.umich.edu 33287639Sgblack@eecs.umich.edu const unsigned length = %(length)d; 33297639Sgblack@eecs.umich.edu const bool isVtbl = %(isVtbl)s; 33307639Sgblack@eecs.umich.edu 33318588Sgblack@eecs.umich.edu srcReg2.regs[0] = htog(FpOp2P0_uw); 33328588Sgblack@eecs.umich.edu srcReg2.regs[1] = htog(FpOp2P1_uw); 33337639Sgblack@eecs.umich.edu 33348588Sgblack@eecs.umich.edu destReg.regs[0] = htog(FpDestP0_uw); 33358588Sgblack@eecs.umich.edu destReg.regs[1] = htog(FpDestP1_uw); 33367639Sgblack@eecs.umich.edu ''' % { "length" : length, "isVtbl" : isVtbl } 33377639Sgblack@eecs.umich.edu for reg in range(8): 33387639Sgblack@eecs.umich.edu if reg < length * 2: 33398588Sgblack@eecs.umich.edu code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);\n' % \ 33407639Sgblack@eecs.umich.edu { "reg" : reg } 33417639Sgblack@eecs.umich.edu else: 33427639Sgblack@eecs.umich.edu code += 'table.regs[%(reg)d] = 0;\n' % { "reg" : reg } 33437639Sgblack@eecs.umich.edu code += ''' 33447639Sgblack@eecs.umich.edu for (unsigned i = 0; i < sizeof(destReg); i++) { 33457639Sgblack@eecs.umich.edu uint8_t index = srcReg2.bytes[i]; 33467639Sgblack@eecs.umich.edu if (index < 8 * length) { 33477639Sgblack@eecs.umich.edu destReg.bytes[i] = table.bytes[index]; 33487639Sgblack@eecs.umich.edu } else { 33497639Sgblack@eecs.umich.edu if (isVtbl) 33507639Sgblack@eecs.umich.edu destReg.bytes[i] = 0; 33517639Sgblack@eecs.umich.edu // else destReg.bytes[i] unchanged 33527639Sgblack@eecs.umich.edu } 33537639Sgblack@eecs.umich.edu } 33547639Sgblack@eecs.umich.edu 33558588Sgblack@eecs.umich.edu FpDestP0_uw = gtoh(destReg.regs[0]); 33568588Sgblack@eecs.umich.edu FpDestP1_uw = gtoh(destReg.regs[1]); 33577639Sgblack@eecs.umich.edu ''' 33587639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 33597639Sgblack@eecs.umich.edu "RegRegRegOp", 33607639Sgblack@eecs.umich.edu { "code": code, 33617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 33627760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 33637639Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(iop) 33647639Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(iop) 33657639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 33667639Sgblack@eecs.umich.edu 33678206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl1", "SimdMiscOp", 1, "true") 33688206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl2", "SimdMiscOp", 2, "true") 33698206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl3", "SimdMiscOp", 3, "true") 33708206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl4", "SimdMiscOp", 4, "true") 33717639Sgblack@eecs.umich.edu 33728206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx1", "SimdMiscOp", 1, "false") 33738206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx2", "SimdMiscOp", 2, "false") 33748206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx3", "SimdMiscOp", 3, "false") 33758206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx4", "SimdMiscOp", 4, "false") 33767639Sgblack@eecs.umich.edu}}; 3377