mult.isa revision 8302
17584SN/A// -*- mode:c++ -*- 28869SAli.Saidi@ARM.com 37584SN/A// Copyright (c) 2010 ARM Limited 47584SN/A// All rights reserved 57584SN/A// 67584SN/A// The license below extends only to copyright in the software and shall 77584SN/A// not be construed as granting a license to any other intellectual 87584SN/A// property including but not limited to intellectual property relating 97584SN/A// to a hardware implementation of the functionality of the software 107584SN/A// licensed hereunder. You may use the software subject to the license 117584SN/A// terms below provided that you ensure that this notice is replicated 127584SN/A// unmodified and in its entirety in all distributions of the software, 137584SN/A// modified or unmodified, in source code or in binary form. 147584SN/A// 157584SN/A// Redistribution and use in source and binary forms, with or without 167584SN/A// modification, are permitted provided that the following conditions are 177584SN/A// met: redistributions of source code must retain the above copyright 187584SN/A// notice, this list of conditions and the following disclaimer; 197584SN/A// redistributions in binary form must reproduce the above copyright 207584SN/A// notice, this list of conditions and the following disclaimer in the 217584SN/A// documentation and/or other materials provided with the distribution; 227584SN/A// neither the name of the copyright holders nor the names of its 237584SN/A// contributors may be used to endorse or promote products derived from 247584SN/A// this software without specific prior written permission. 257584SN/A// 267584SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277584SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287584SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297584SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307584SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317584SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327584SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337584SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347584SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357584SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367584SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377584SN/A// 387584SN/A// Authors: Gabe Black 397584SN/A 407584SN/Alet {{ 418869SAli.Saidi@ARM.com 427584SN/A header_output = "" 438245SN/A decoder_output = "" 448245SN/A exec_output = "" 458869SAli.Saidi@ARM.com 468869SAli.Saidi@ARM.com calcQCode = ''' 478869SAli.Saidi@ARM.com CpsrQ = (resTemp & 1) << 27; 487584SN/A ''' 497584SN/A 507584SN/A calcCcCode = ''' 518869SAli.Saidi@ARM.com uint16_t _iz, _in; 529808Sstever@gmail.com _in = (resTemp >> %(negBit)d) & 1; 539808Sstever@gmail.com _iz = ((%(zType)s)resTemp == 0); 549808Sstever@gmail.com 557584SN/A CondCodesF = _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF); 567584SN/A 577584SN/A DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz); 587584SN/A ''' 597584SN/A 608869SAli.Saidi@ARM.com def buildMultInst(mnem, doCc, unCc, regs, code, flagType): 617584SN/A global header_output, decoder_output, exec_output 627584SN/A cCode = carryCode[flagType] 637584SN/A vCode = overflowCode[flagType] 647584SN/A zType = "uint32_t" 657584SN/A negBit = 31 668869SAli.Saidi@ARM.com if flagType == "llbit": 677584SN/A zType = "uint64_t" 688869SAli.Saidi@ARM.com negBit = 63 698869SAli.Saidi@ARM.com if flagType == "overflow": 708869SAli.Saidi@ARM.com ccCode = calcQCode 718869SAli.Saidi@ARM.com else: 728869SAli.Saidi@ARM.com ccCode = calcCcCode % { 738869SAli.Saidi@ARM.com "negBit": negBit, 748869SAli.Saidi@ARM.com "zType": zType 758869SAli.Saidi@ARM.com } 768869SAli.Saidi@ARM.com 778869SAli.Saidi@ARM.com if not regs in (3, 4): 788869SAli.Saidi@ARM.com raise Exception, "Multiplication instructions with %d " + \ 798869SAli.Saidi@ARM.com "registers are not implemented" 808869SAli.Saidi@ARM.com 818869SAli.Saidi@ARM.com if regs == 3: 828869SAli.Saidi@ARM.com base = 'Mult3' 838869SAli.Saidi@ARM.com else: 848869SAli.Saidi@ARM.com base = 'Mult4' 858869SAli.Saidi@ARM.com 868869SAli.Saidi@ARM.com Name = mnem.capitalize() 878869SAli.Saidi@ARM.com 888869SAli.Saidi@ARM.com if unCc: 898869SAli.Saidi@ARM.com iop = InstObjParams(mnem, Name, base, 908869SAli.Saidi@ARM.com {"code" : code, 918869SAli.Saidi@ARM.com "predicate_test": predicateTest, 928869SAli.Saidi@ARM.com "op_class": "IntMultOp" }) 939806Sstever@gmail.com if doCc: 948869SAli.Saidi@ARM.com iopCc = InstObjParams(mnem + "s", Name + "Cc", base, 958869SAli.Saidi@ARM.com {"code" : code + ccCode, 968869SAli.Saidi@ARM.com "predicate_test": condPredicateTest, 978869SAli.Saidi@ARM.com "op_class": "IntMultOp" }) 988869SAli.Saidi@ARM.com 998869SAli.Saidi@ARM.com if regs == 3: 1008869SAli.Saidi@ARM.com declare = Mult3Declare 1018869SAli.Saidi@ARM.com constructor = Mult3Constructor 1028869SAli.Saidi@ARM.com else: 1038869SAli.Saidi@ARM.com declare = Mult4Declare 1048869SAli.Saidi@ARM.com constructor = Mult4Constructor 1058869SAli.Saidi@ARM.com 1068869SAli.Saidi@ARM.com if unCc: 1078869SAli.Saidi@ARM.com header_output += declare.subst(iop) 1088869SAli.Saidi@ARM.com decoder_output += constructor.subst(iop) 1098869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(iop) 1108869SAli.Saidi@ARM.com if doCc: 1118869SAli.Saidi@ARM.com header_output += declare.subst(iopCc) 1128869SAli.Saidi@ARM.com decoder_output += constructor.subst(iopCc) 1138869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(iopCc) 1148869SAli.Saidi@ARM.com 1158869SAli.Saidi@ARM.com def buildMult3Inst(mnem, code, flagType = "logic"): 1168869SAli.Saidi@ARM.com buildMultInst(mnem, True, True, 3, code, flagType) 1178869SAli.Saidi@ARM.com 1187584SN/A def buildMult3InstCc(mnem, code, flagType = "logic"): 1197584SN/A buildMultInst(mnem, True, False, 3, code, flagType) 1207584SN/A 1217584SN/A def buildMult3InstUnCc(mnem, code, flagType = "logic"): 1227584SN/A buildMultInst(mnem, False, True, 3, code, flagType) 1238869SAli.Saidi@ARM.com 1247584SN/A def buildMult4Inst(mnem, code, flagType = "logic"): 1257584SN/A buildMultInst(mnem, True, True, 4, code, flagType) 1267584SN/A 1277584SN/A def buildMult4InstCc(mnem, code, flagType = "logic"): 1287584SN/A buildMultInst(mnem, True, False, 4, code, flagType) 1298869SAli.Saidi@ARM.com 1307584SN/A def buildMult4InstUnCc(mnem, code, flagType = "logic"): 1318869SAli.Saidi@ARM.com buildMultInst(mnem, False, True, 4, code, flagType) 1328869SAli.Saidi@ARM.com 1338869SAli.Saidi@ARM.com buildMult4Inst ("mla", "Reg0 = resTemp = Reg1 * Reg2 + Reg3;") 1348869SAli.Saidi@ARM.com buildMult4InstUnCc("mls", "Reg0 = resTemp = Reg3 - Reg1 * Reg2;") 1358869SAli.Saidi@ARM.com buildMult3Inst ("mul", "Reg0 = resTemp = Reg1 * Reg2;") 1368869SAli.Saidi@ARM.com buildMult4InstCc ("smlabb", '''Reg0 = resTemp = 1378869SAli.Saidi@ARM.com sext<16>(bits(Reg1, 15, 0)) * 1388869SAli.Saidi@ARM.com sext<16>(bits(Reg2.sw, 15, 0)) + 1398869SAli.Saidi@ARM.com Reg3.sw; 1408869SAli.Saidi@ARM.com resTemp = bits(resTemp, 32) != 1418869SAli.Saidi@ARM.com bits(resTemp, 31); 1428869SAli.Saidi@ARM.com ''', "overflow") 1438869SAli.Saidi@ARM.com buildMult4InstCc ("smlabt", '''Reg0 = resTemp = 1448869SAli.Saidi@ARM.com sext<16>(bits(Reg1, 15, 0)) * 1458869SAli.Saidi@ARM.com sext<16>(bits(Reg2.sw, 31, 16)) + 1468869SAli.Saidi@ARM.com Reg3.sw; 1478869SAli.Saidi@ARM.com resTemp = bits(resTemp, 32) != 1488869SAli.Saidi@ARM.com bits(resTemp, 31); 1498869SAli.Saidi@ARM.com ''', "overflow") 1508869SAli.Saidi@ARM.com buildMult4InstCc ("smlatb", '''Reg0 = resTemp = 1518869SAli.Saidi@ARM.com sext<16>(bits(Reg1, 31, 16)) * 1528869SAli.Saidi@ARM.com sext<16>(bits(Reg2.sw, 15, 0)) + 1538869SAli.Saidi@ARM.com Reg3.sw; 1548869SAli.Saidi@ARM.com resTemp = bits(resTemp, 32) != 1558869SAli.Saidi@ARM.com bits(resTemp, 31); 1569806Sstever@gmail.com ''', "overflow") 1578869SAli.Saidi@ARM.com buildMult4InstCc ("smlatt", '''Reg0 = resTemp = 1588869SAli.Saidi@ARM.com sext<16>(bits(Reg1, 31, 16)) * 1598869SAli.Saidi@ARM.com sext<16>(bits(Reg2.sw, 31, 16)) + 1608869SAli.Saidi@ARM.com Reg3.sw; 1618869SAli.Saidi@ARM.com resTemp = bits(resTemp, 32) != 1627584SN/A bits(resTemp, 31); 1637584SN/A ''', "overflow") 1647584SN/A buildMult4InstCc ("smlad", '''Reg0 = resTemp = 1657584SN/A sext<16>(bits(Reg1, 31, 16)) * 1667584SN/A sext<16>(bits(Reg2, 31, 16)) + 1678869SAli.Saidi@ARM.com sext<16>(bits(Reg1, 15, 0)) * 1687584SN/A sext<16>(bits(Reg2, 15, 0)) + 1698869SAli.Saidi@ARM.com Reg3.sw; 1708869SAli.Saidi@ARM.com resTemp = bits(resTemp, 32) != 1718869SAli.Saidi@ARM.com bits(resTemp, 31); 1728869SAli.Saidi@ARM.com ''', "overflow") 1738869SAli.Saidi@ARM.com buildMult4InstCc ("smladx", '''Reg0 = resTemp = 1748869SAli.Saidi@ARM.com sext<16>(bits(Reg1, 31, 16)) * 1758869SAli.Saidi@ARM.com sext<16>(bits(Reg2, 15, 0)) + 1768869SAli.Saidi@ARM.com sext<16>(bits(Reg1, 15, 0)) * 1778869SAli.Saidi@ARM.com sext<16>(bits(Reg2, 31, 16)) + 1788869SAli.Saidi@ARM.com Reg3.sw; 1798869SAli.Saidi@ARM.com resTemp = bits(resTemp, 32) != 1808869SAli.Saidi@ARM.com bits(resTemp, 31); 1818869SAli.Saidi@ARM.com ''', "overflow") 1828869SAli.Saidi@ARM.com buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) + 1838869SAli.Saidi@ARM.com (int64_t)((Reg1.ud << 32) | Reg0.ud); 1848869SAli.Saidi@ARM.com Reg0.ud = (uint32_t)resTemp; 1858869SAli.Saidi@ARM.com Reg1.ud = (uint32_t)(resTemp >> 32); 1868869SAli.Saidi@ARM.com ''', "llbit") 1878869SAli.Saidi@ARM.com buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) * 1888869SAli.Saidi@ARM.com sext<16>(bits(Reg3, 15, 0)) + 1898869SAli.Saidi@ARM.com (int64_t)((Reg1.ud << 32) | 1908869SAli.Saidi@ARM.com Reg0.ud); 1918993SAli.Saidi@ARM.com Reg0.ud = (uint32_t)resTemp; 1928869SAli.Saidi@ARM.com Reg1.ud = (uint32_t)(resTemp >> 32); 1938869SAli.Saidi@ARM.com ''') 1947584SN/A buildMult4InstUnCc("smlalbt", '''resTemp = sext<16>(bits(Reg2, 15, 0)) * 1957584SN/A sext<16>(bits(Reg3, 31, 16)) + 1967584SN/A (int64_t)((Reg1.ud << 32) | 1977584SN/A Reg0.ud); 1988869SAli.Saidi@ARM.com Reg0.ud = (uint32_t)resTemp; 1997584SN/A Reg1.ud = (uint32_t)(resTemp >> 32); 2008869SAli.Saidi@ARM.com ''') 2018869SAli.Saidi@ARM.com buildMult4InstUnCc("smlaltb", '''resTemp = sext<16>(bits(Reg2, 31, 16)) * 2028869SAli.Saidi@ARM.com sext<16>(bits(Reg3, 15, 0)) + 2038869SAli.Saidi@ARM.com (int64_t)((Reg1.ud << 32) | 2048869SAli.Saidi@ARM.com Reg0.ud); 2058869SAli.Saidi@ARM.com Reg0.ud = (uint32_t)resTemp; 2068869SAli.Saidi@ARM.com Reg1.ud = (uint32_t)(resTemp >> 32); 2078869SAli.Saidi@ARM.com ''') 2087584SN/A buildMult4InstUnCc("smlaltt", '''resTemp = sext<16>(bits(Reg2, 31, 16)) * 2098869SAli.Saidi@ARM.com sext<16>(bits(Reg3, 31, 16)) + 2107733SN/A (int64_t)((Reg1.ud << 32) | 2117733SN/A Reg0.ud); 2127733SN/A Reg0.ud = (uint32_t)resTemp; 2137733SN/A Reg1.ud = (uint32_t)(resTemp >> 32); 2148869SAli.Saidi@ARM.com ''') 2157733SN/A buildMult4InstUnCc("smlald", '''resTemp = 2167733SN/A sext<16>(bits(Reg2, 31, 16)) * 2177733SN/A sext<16>(bits(Reg3, 31, 16)) + 2187733SN/A sext<16>(bits(Reg2, 15, 0)) * 2197733SN/A sext<16>(bits(Reg3, 15, 0)) + 2208869SAli.Saidi@ARM.com (int64_t)((Reg1.ud << 32) | 2217733SN/A Reg0.ud); 2228869SAli.Saidi@ARM.com Reg0.ud = (uint32_t)resTemp; 2237733SN/A Reg1.ud = (uint32_t)(resTemp >> 32); 2248869SAli.Saidi@ARM.com ''') 2258869SAli.Saidi@ARM.com buildMult4InstUnCc("smlaldx", '''resTemp = 2268869SAli.Saidi@ARM.com sext<16>(bits(Reg2, 31, 16)) * 2278869SAli.Saidi@ARM.com sext<16>(bits(Reg3, 15, 0)) + 2287733SN/A sext<16>(bits(Reg2, 15, 0)) * 2298869SAli.Saidi@ARM.com sext<16>(bits(Reg3, 31, 16)) + 2307733SN/A (int64_t)((Reg1.ud << 32) | 2317733SN/A Reg0.ud); 2327733SN/A Reg0.ud = (uint32_t)resTemp; 2337733SN/A Reg1.ud = (uint32_t)(resTemp >> 32); 2347733SN/A ''') 2357733SN/A buildMult4InstCc ("smlawb", '''Reg0 = resTemp = 2367733SN/A (Reg1.sw * 2377733SN/A sext<16>(bits(Reg2, 15, 0)) + 2388869SAli.Saidi@ARM.com ((int64_t)Reg3.sw << 16)) >> 16; 2397733SN/A resTemp = bits(resTemp, 32) != 2407733SN/A bits(resTemp, 31); 2417733SN/A ''', "overflow") 2427733SN/A buildMult4InstCc ("smlawt", '''Reg0 = resTemp = 2437584SN/A (Reg1.sw * 2448869SAli.Saidi@ARM.com sext<16>(bits(Reg2, 31, 16)) + 2458869SAli.Saidi@ARM.com ((int64_t)Reg3.sw << 16)) >> 16; 2467584SN/A resTemp = bits(resTemp, 32) != 2478869SAli.Saidi@ARM.com bits(resTemp, 31); 2487584SN/A ''', "overflow") 249 buildMult4InstCc ("smlsd", '''Reg0 = resTemp = 250 sext<16>(bits(Reg1, 15, 0)) * 251 sext<16>(bits(Reg2, 15, 0)) - 252 sext<16>(bits(Reg1, 31, 16)) * 253 sext<16>(bits(Reg2, 31, 16)) + 254 Reg3.sw; 255 resTemp = bits(resTemp, 32) != 256 bits(resTemp, 31); 257 ''', "overflow") 258 buildMult4InstCc ("smlsdx", '''Reg0 = resTemp = 259 sext<16>(bits(Reg1, 15, 0)) * 260 sext<16>(bits(Reg2, 31, 16)) - 261 sext<16>(bits(Reg1, 31, 16)) * 262 sext<16>(bits(Reg2, 15, 0)) + 263 Reg3.sw; 264 resTemp = bits(resTemp, 32) != 265 bits(resTemp, 31); 266 ''', "overflow") 267 buildMult4InstUnCc("smlsld", '''resTemp = 268 sext<16>(bits(Reg2, 15, 0)) * 269 sext<16>(bits(Reg3, 15, 0)) - 270 sext<16>(bits(Reg2, 31, 16)) * 271 sext<16>(bits(Reg3, 31, 16)) + 272 (int64_t)((Reg1.ud << 32) | 273 Reg0.ud); 274 Reg0.ud = (uint32_t)resTemp; 275 Reg1.ud = (uint32_t)(resTemp >> 32); 276 ''') 277 buildMult4InstUnCc("smlsldx", '''resTemp = 278 sext<16>(bits(Reg2, 15, 0)) * 279 sext<16>(bits(Reg3, 31, 16)) - 280 sext<16>(bits(Reg2, 31, 16)) * 281 sext<16>(bits(Reg3, 15, 0)) + 282 (int64_t)((Reg1.ud << 32) | 283 Reg0.ud); 284 Reg0.ud = (uint32_t)resTemp; 285 Reg1.ud = (uint32_t)(resTemp >> 32); 286 ''') 287 buildMult4InstUnCc("smmla", '''Reg0 = resTemp = 288 ((int64_t)(Reg3.ud << 32) + 289 (int64_t)Reg1.sw * 290 (int64_t)Reg2.sw) >> 32; 291 ''') 292 buildMult4InstUnCc("smmlar", '''Reg0 = resTemp = 293 ((int64_t)(Reg3.ud << 32) + 294 (int64_t)Reg1.sw * 295 (int64_t)Reg2.sw + 296 ULL(0x80000000)) >> 32; 297 ''') 298 buildMult4InstUnCc("smmls", '''Reg0 = resTemp = 299 ((int64_t)(Reg3.ud << 32) - 300 (int64_t)Reg1.sw * 301 (int64_t)Reg2.sw) >> 32; 302 ''') 303 buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp = 304 ((int64_t)(Reg3.ud << 32) - 305 (int64_t)Reg1.sw * 306 (int64_t)Reg2.sw + 307 ULL(0x80000000)) >> 32; 308 ''') 309 buildMult3InstUnCc("smmul", '''Reg0 = resTemp = 310 ((int64_t)Reg1.sw * 311 (int64_t)Reg2.sw) >> 32; 312 ''') 313 buildMult3InstUnCc("smmulr", '''Reg0 = resTemp = 314 ((int64_t)Reg1.sw * 315 (int64_t)Reg2.sw + 316 ULL(0x80000000)) >> 32; 317 ''') 318 buildMult3InstCc ("smuad", '''Reg0 = resTemp = 319 sext<16>(bits(Reg1, 15, 0)) * 320 sext<16>(bits(Reg2, 15, 0)) + 321 sext<16>(bits(Reg1, 31, 16)) * 322 sext<16>(bits(Reg2, 31, 16)); 323 resTemp = bits(resTemp, 32) != 324 bits(resTemp, 31); 325 ''', "overflow") 326 buildMult3InstCc ("smuadx", '''Reg0 = resTemp = 327 sext<16>(bits(Reg1, 15, 0)) * 328 sext<16>(bits(Reg2, 31, 16)) + 329 sext<16>(bits(Reg1, 31, 16)) * 330 sext<16>(bits(Reg2, 15, 0)); 331 resTemp = bits(resTemp, 32) != 332 bits(resTemp, 31); 333 ''', "overflow") 334 buildMult3InstUnCc("smulbb", '''Reg0 = resTemp = 335 sext<16>(bits(Reg1, 15, 0)) * 336 sext<16>(bits(Reg2, 15, 0)); 337 ''') 338 buildMult3InstUnCc("smulbt", '''Reg0 = resTemp = 339 sext<16>(bits(Reg1, 15, 0)) * 340 sext<16>(bits(Reg2, 31, 16)); 341 ''') 342 buildMult3InstUnCc("smultb", '''Reg0 = resTemp = 343 sext<16>(bits(Reg1, 31, 16)) * 344 sext<16>(bits(Reg2, 15, 0)); 345 ''') 346 buildMult3InstUnCc("smultt", '''Reg0 = resTemp = 347 sext<16>(bits(Reg1, 31, 16)) * 348 sext<16>(bits(Reg2, 31, 16)); 349 ''') 350 buildMult4Inst ("smull", '''resTemp = (int64_t)Reg2.sw * 351 (int64_t)Reg3.sw; 352 Reg1 = (int32_t)(resTemp >> 32); 353 Reg0 = (int32_t)resTemp; 354 ''', "llbit") 355 buildMult3InstUnCc("smulwb", '''Reg0 = resTemp = 356 (Reg1.sw * 357 sext<16>(bits(Reg2, 15, 0))) >> 16; 358 ''') 359 buildMult3InstUnCc("smulwt", '''Reg0 = resTemp = 360 (Reg1.sw * 361 sext<16>(bits(Reg2, 31, 16))) >> 16; 362 ''') 363 buildMult3InstUnCc("smusd", '''Reg0 = resTemp = 364 sext<16>(bits(Reg1, 15, 0)) * 365 sext<16>(bits(Reg2, 15, 0)) - 366 sext<16>(bits(Reg1, 31, 16)) * 367 sext<16>(bits(Reg2, 31, 16)); 368 ''') 369 buildMult3InstUnCc("smusdx", '''Reg0 = resTemp = 370 sext<16>(bits(Reg1, 15, 0)) * 371 sext<16>(bits(Reg2, 31, 16)) - 372 sext<16>(bits(Reg1, 31, 16)) * 373 sext<16>(bits(Reg2, 15, 0)); 374 ''') 375 buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud + 376 Reg0.ud + Reg1.ud; 377 Reg1.ud = (uint32_t)(resTemp >> 32); 378 Reg0.ud = (uint32_t)resTemp; 379 ''') 380 buildMult4Inst ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud + 381 (Reg1.ud << 32); 382 Reg1.ud = (uint32_t)(resTemp >> 32); 383 Reg0.ud = (uint32_t)resTemp; 384 ''', "llbit") 385 buildMult4Inst ("umull", '''resTemp = Reg2.ud * Reg3.ud; 386 Reg1 = (uint32_t)(resTemp >> 32); 387 Reg0 = (uint32_t)resTemp; 388 ''', "llbit") 389}}; 390