misc64.isa revision 10474
110037SARM gem5 Developers// -*- mode:c++ -*- 210037SARM gem5 Developers 310037SARM gem5 Developers// Copyright (c) 2011-2013 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Gabe Black 3910037SARM gem5 Developers 4010037SARM gem5 Developerslet {{ 4110037SARM gem5 Developers svcCode = ''' 4210474Sandreas.hansson@arm.com fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5)); 4310037SARM gem5 Developers ''' 4410037SARM gem5 Developers 4510037SARM gem5 Developers svcIop = InstObjParams("svc", "Svc64", "ArmStaticInst", 4610037SARM gem5 Developers svcCode, ["IsSyscall", "IsNonSpeculative", 4710037SARM gem5 Developers "IsSerializeAfter"]) 4810037SARM gem5 Developers header_output = BasicDeclare.subst(svcIop) 4910037SARM gem5 Developers decoder_output = BasicConstructor64.subst(svcIop) 5010037SARM gem5 Developers exec_output = BasicExecute.subst(svcIop) 5110037SARM gem5 Developers 5210037SARM gem5 Developers # @todo: extend to take into account Virtualization. 5310037SARM gem5 Developers smcCode = ''' 5410037SARM gem5 Developers SCR scr = Scr64; 5510037SARM gem5 Developers CPSR cpsr = Cpsr; 5610037SARM gem5 Developers 5710037SARM gem5 Developers if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) { 5810037SARM gem5 Developers fault = disabledFault(); 5910037SARM gem5 Developers } else { 6010474Sandreas.hansson@arm.com fault = std::make_shared<SecureMonitorCall>(machInst); 6110037SARM gem5 Developers } 6210037SARM gem5 Developers ''' 6310037SARM gem5 Developers 6410037SARM gem5 Developers smcIop = InstObjParams("smc", "Smc64", "ArmStaticInst", 6510037SARM gem5 Developers smcCode, ["IsNonSpeculative", "IsSerializeAfter"]) 6610037SARM gem5 Developers header_output += BasicDeclare.subst(smcIop) 6710037SARM gem5 Developers decoder_output += BasicConstructor64.subst(smcIop) 6810037SARM gem5 Developers exec_output += BasicExecute.subst(smcIop) 6910037SARM gem5 Developers 7010037SARM gem5 Developers def subst(templateBase, iop): 7110037SARM gem5 Developers global header_output, decoder_output, exec_output 7210037SARM gem5 Developers header_output += eval(templateBase + "Declare").subst(iop) 7310037SARM gem5 Developers decoder_output += eval(templateBase + "Constructor").subst(iop) 7410037SARM gem5 Developers exec_output += BasicExecute.subst(iop) 7510037SARM gem5 Developers 7610037SARM gem5 Developers bfmMaskCode = ''' 7710037SARM gem5 Developers uint64_t bitMask; 7810037SARM gem5 Developers int diff = imm2 - imm1; 7910037SARM gem5 Developers if (imm1 <= imm2) { 8010037SARM gem5 Developers bitMask = mask(diff + 1); 8110037SARM gem5 Developers } else { 8210037SARM gem5 Developers bitMask = mask(imm2 + 1); 8310037SARM gem5 Developers bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1)); 8410037SARM gem5 Developers diff += intWidth; 8510037SARM gem5 Developers } 8610037SARM gem5 Developers uint64_t topBits M5_VAR_USED = ~mask(diff+1); 8710037SARM gem5 Developers uint64_t result = (Op164 >> imm1) | (Op164 << (intWidth - imm1)); 8810037SARM gem5 Developers result &= bitMask; 8910037SARM gem5 Developers ''' 9010037SARM gem5 Developers 9110037SARM gem5 Developers bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);' 9210037SARM gem5 Developers bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode); 9310037SARM gem5 Developers subst("RegRegImmImmOp64", bfmIop) 9410037SARM gem5 Developers 9510037SARM gem5 Developers ubfmCode = bfmMaskCode + 'Dest64 = result;' 9610037SARM gem5 Developers ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode); 9710037SARM gem5 Developers subst("RegRegImmImmOp64", ubfmIop) 9810037SARM gem5 Developers 9910037SARM gem5 Developers sbfmCode = bfmMaskCode + \ 10010037SARM gem5 Developers 'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);' 10110037SARM gem5 Developers sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode); 10210037SARM gem5 Developers subst("RegRegImmImmOp64", sbfmIop) 10310037SARM gem5 Developers 10410037SARM gem5 Developers extrCode = ''' 10510037SARM gem5 Developers if (imm == 0) { 10610037SARM gem5 Developers Dest64 = Op264; 10710037SARM gem5 Developers } else { 10810037SARM gem5 Developers Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm); 10910037SARM gem5 Developers } 11010037SARM gem5 Developers ''' 11110037SARM gem5 Developers extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode); 11210037SARM gem5 Developers subst("RegRegRegImmOp64", extrIop); 11310037SARM gem5 Developers 11410037SARM gem5 Developers unknownCode = ''' 11510474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, true); 11610037SARM gem5 Developers ''' 11710037SARM gem5 Developers unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64", 11810037SARM gem5 Developers unknownCode) 11910037SARM gem5 Developers header_output += BasicDeclare.subst(unknown64Iop) 12010037SARM gem5 Developers decoder_output += BasicConstructor64.subst(unknown64Iop) 12110037SARM gem5 Developers exec_output += BasicExecute.subst(unknown64Iop) 12210037SARM gem5 Developers 12310037SARM gem5 Developers isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", 12410474Sandreas.hansson@arm.com "fault = std::make_shared<FlushPipe>();", 12510474Sandreas.hansson@arm.com ['IsSerializeAfter']) 12610037SARM gem5 Developers header_output += BasicDeclare.subst(isbIop) 12710037SARM gem5 Developers decoder_output += BasicConstructor64.subst(isbIop) 12810037SARM gem5 Developers exec_output += BasicExecute.subst(isbIop) 12910037SARM gem5 Developers 13010037SARM gem5 Developers dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", 13110474Sandreas.hansson@arm.com "fault = std::make_shared<FlushPipe>();", 13210037SARM gem5 Developers ['IsMemBarrier', 'IsSerializeAfter']) 13310037SARM gem5 Developers header_output += BasicDeclare.subst(dsbIop) 13410037SARM gem5 Developers decoder_output += BasicConstructor64.subst(dsbIop) 13510037SARM gem5 Developers exec_output += BasicExecute.subst(dsbIop) 13610037SARM gem5 Developers 13710037SARM gem5 Developers dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "", 13810037SARM gem5 Developers ['IsMemBarrier']) 13910037SARM gem5 Developers header_output += BasicDeclare.subst(dmbIop) 14010037SARM gem5 Developers decoder_output += BasicConstructor64.subst(dmbIop) 14110037SARM gem5 Developers exec_output += BasicExecute.subst(dmbIop) 14210037SARM gem5 Developers 14310037SARM gem5 Developers clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst", 14410037SARM gem5 Developers "LLSCLock = 0;") 14510037SARM gem5 Developers header_output += BasicDeclare.subst(clrexIop) 14610037SARM gem5 Developers decoder_output += BasicConstructor64.subst(clrexIop) 14710037SARM gem5 Developers exec_output += BasicExecute.subst(clrexIop) 14810037SARM gem5 Developers}}; 149