misc.isa revision 7848:cc5e64f8423f
15353Svilas.sridharan@gmail.com// -*- mode:c++ -*- 23395Shsul@eecs.umich.edu 33395Shsul@eecs.umich.edu// Copyright (c) 2010 ARM Limited 43395Shsul@eecs.umich.edu// All rights reserved 53395Shsul@eecs.umich.edu// 63395Shsul@eecs.umich.edu// The license below extends only to copyright in the software and shall 73395Shsul@eecs.umich.edu// not be construed as granting a license to any other intellectual 83395Shsul@eecs.umich.edu// property including but not limited to intellectual property relating 93395Shsul@eecs.umich.edu// to a hardware implementation of the functionality of the software 103395Shsul@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 113395Shsul@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 123395Shsul@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 133395Shsul@eecs.umich.edu// modified or unmodified, in source code or in binary form. 143395Shsul@eecs.umich.edu// 153395Shsul@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 163395Shsul@eecs.umich.edu// modification, are permitted provided that the following conditions are 173395Shsul@eecs.umich.edu// met: redistributions of source code must retain the above copyright 183395Shsul@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 193395Shsul@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 203395Shsul@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 213395Shsul@eecs.umich.edu// documentation and/or other materials provided with the distribution; 223395Shsul@eecs.umich.edu// neither the name of the copyright holders nor the names of its 233395Shsul@eecs.umich.edu// contributors may be used to endorse or promote products derived from 243395Shsul@eecs.umich.edu// this software without specific prior written permission. 253395Shsul@eecs.umich.edu// 263395Shsul@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 273395Shsul@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 283395Shsul@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 293395Shsul@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 303395Shsul@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 313395Shsul@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 325869Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 335361Srstrong@cs.ucsd.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 343395Shsul@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 354455Ssaidi@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 364968Sacolyte@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 376893SBrad.Beckmann@amd.com// 386893SBrad.Beckmann@amd.com// Authors: Gabe Black 396908SBrad.Beckmann@amd.com 406893SBrad.Beckmann@amd.comlet {{ 413395Shsul@eecs.umich.edu 426892SBrad.Beckmann@amd.com svcCode = ''' 436892SBrad.Beckmann@amd.com#if FULL_SYSTEM 446892SBrad.Beckmann@amd.com fault = new SupervisorCall; 453395Shsul@eecs.umich.edu#else 466641Sksewell@umich.edu fault = new SupervisorCall(machInst); 476144Sksewell@umich.edu#endif 486144Sksewell@umich.edu ''' 493395Shsul@eecs.umich.edu 503395Shsul@eecs.umich.edu svcIop = InstObjParams("svc", "Svc", "PredOp", 513395Shsul@eecs.umich.edu { "code": svcCode, 523395Shsul@eecs.umich.edu "predicate_test": predicateTest }, ["IsSyscall"]) 535361Srstrong@cs.ucsd.edu header_output = BasicDeclare.subst(svcIop) 545361Srstrong@cs.ucsd.edu decoder_output = BasicConstructor.subst(svcIop) 555361Srstrong@cs.ucsd.edu exec_output = PredOpExecute.subst(svcIop) 565361Srstrong@cs.ucsd.edu 575361Srstrong@cs.ucsd.edu}}; 585361Srstrong@cs.ucsd.edu 595361Srstrong@cs.ucsd.edulet {{ 605361Srstrong@cs.ucsd.edu 616776SBrad.Beckmann@amd.com header_output = decoder_output = exec_output = "" 626776SBrad.Beckmann@amd.com 636776SBrad.Beckmann@amd.com mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF" 643395Shsul@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 653395Shsul@eecs.umich.edu { "code": mrsCpsrCode, 663395Shsul@eecs.umich.edu "predicate_test": condPredicateTest }, 673395Shsul@eecs.umich.edu ["IsSerializeBefore"]) 685361Srstrong@cs.ucsd.edu header_output += MrsDeclare.subst(mrsCpsrIop) 695361Srstrong@cs.ucsd.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 703445Shsul@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 715361Srstrong@cs.ucsd.edu 725361Srstrong@cs.ucsd.edu mrsSpsrCode = "Dest = Spsr" 736769SBrad.Beckmann@amd.com mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 745361Srstrong@cs.ucsd.edu { "code": mrsSpsrCode, 755361Srstrong@cs.ucsd.edu "predicate_test": predicateTest }, 765361Srstrong@cs.ucsd.edu ["IsSerializeBefore"]) 775361Srstrong@cs.ucsd.edu header_output += MrsDeclare.subst(mrsSpsrIop) 785361Srstrong@cs.ucsd.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 795361Srstrong@cs.ucsd.edu exec_output += PredOpExecute.subst(mrsSpsrIop) 805361Srstrong@cs.ucsd.edu 815361Srstrong@cs.ucsd.edu msrCpsrRegCode = ''' 825361Srstrong@cs.ucsd.edu SCTLR sctlr = Sctlr; 835361Srstrong@cs.ucsd.edu uint32_t newCpsr = 845361Srstrong@cs.ucsd.edu cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); 855361Srstrong@cs.ucsd.edu Cpsr = ~CondCodesMask & newCpsr; 865361Srstrong@cs.ucsd.edu NextThumb = ((CPSR)newCpsr).t; 875361Srstrong@cs.ucsd.edu NextJazelle = ((CPSR)newCpsr).j; 885361Srstrong@cs.ucsd.edu CondCodes = CondCodesMask & newCpsr; 895361Srstrong@cs.ucsd.edu ''' 905361Srstrong@cs.ucsd.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 915361Srstrong@cs.ucsd.edu { "code": msrCpsrRegCode, 92 "predicate_test": condPredicateTest }, 93 ["IsSerializeAfter","IsNonSpeculative"]) 94 header_output += MsrRegDeclare.subst(msrCpsrRegIop) 95 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 96 exec_output += PredOpExecute.subst(msrCpsrRegIop) 97 98 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 99 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 100 { "code": msrSpsrRegCode, 101 "predicate_test": predicateTest }, 102 ["IsSerializeAfter","IsNonSpeculative"]) 103 header_output += MsrRegDeclare.subst(msrSpsrRegIop) 104 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 105 exec_output += PredOpExecute.subst(msrSpsrRegIop) 106 107 msrCpsrImmCode = ''' 108 SCTLR sctlr = Sctlr; 109 uint32_t newCpsr = 110 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); 111 Cpsr = ~CondCodesMask & newCpsr; 112 NextThumb = ((CPSR)newCpsr).t; 113 NextJazelle = ((CPSR)newCpsr).j; 114 CondCodes = CondCodesMask & newCpsr; 115 ''' 116 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 117 { "code": msrCpsrImmCode, 118 "predicate_test": condPredicateTest }, 119 ["IsSerializeAfter","IsNonSpeculative"]) 120 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 121 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 122 exec_output += PredOpExecute.subst(msrCpsrImmIop) 123 124 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 125 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 126 { "code": msrSpsrImmCode, 127 "predicate_test": predicateTest }, 128 ["IsSerializeAfter","IsNonSpeculative"]) 129 header_output += MsrImmDeclare.subst(msrSpsrImmIop) 130 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 131 exec_output += PredOpExecute.subst(msrSpsrImmIop) 132 133 revCode = ''' 134 uint32_t val = Op1; 135 Dest = swap_byte(val); 136 ''' 137 revIop = InstObjParams("rev", "Rev", "RegRegOp", 138 { "code": revCode, 139 "predicate_test": predicateTest }, []) 140 header_output += RegRegOpDeclare.subst(revIop) 141 decoder_output += RegRegOpConstructor.subst(revIop) 142 exec_output += PredOpExecute.subst(revIop) 143 144 rev16Code = ''' 145 uint32_t val = Op1; 146 Dest = (bits(val, 15, 8) << 0) | 147 (bits(val, 7, 0) << 8) | 148 (bits(val, 31, 24) << 16) | 149 (bits(val, 23, 16) << 24); 150 ''' 151 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 152 { "code": rev16Code, 153 "predicate_test": predicateTest }, []) 154 header_output += RegRegOpDeclare.subst(rev16Iop) 155 decoder_output += RegRegOpConstructor.subst(rev16Iop) 156 exec_output += PredOpExecute.subst(rev16Iop) 157 158 revshCode = ''' 159 uint16_t val = Op1; 160 Dest = sext<16>(swap_byte(val)); 161 ''' 162 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 163 { "code": revshCode, 164 "predicate_test": predicateTest }, []) 165 header_output += RegRegOpDeclare.subst(revshIop) 166 decoder_output += RegRegOpConstructor.subst(revshIop) 167 exec_output += PredOpExecute.subst(revshIop) 168 169 rbitCode = ''' 170 uint8_t *opBytes = (uint8_t *)&Op1; 171 uint32_t resTemp; 172 uint8_t *destBytes = (uint8_t *)&resTemp; 173 // This reverses the bytes and bits of the input, or so says the 174 // internet. 175 for (int i = 0; i < 4; i++) { 176 uint32_t temp = opBytes[i]; 177 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 178 destBytes[3 - i] = (temp * 0x10101) >> 16; 179 } 180 Dest = resTemp; 181 ''' 182 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 183 { "code": rbitCode, 184 "predicate_test": predicateTest }, []) 185 header_output += RegRegOpDeclare.subst(rbitIop) 186 decoder_output += RegRegOpConstructor.subst(rbitIop) 187 exec_output += PredOpExecute.subst(rbitIop) 188 189 clzCode = ''' 190 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 191 ''' 192 clzIop = InstObjParams("clz", "Clz", "RegRegOp", 193 { "code": clzCode, 194 "predicate_test": predicateTest }, []) 195 header_output += RegRegOpDeclare.subst(clzIop) 196 decoder_output += RegRegOpConstructor.subst(clzIop) 197 exec_output += PredOpExecute.subst(clzIop) 198 199 ssatCode = ''' 200 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 201 int32_t res; 202 if (satInt(res, operand, imm)) 203 CondCodes = CondCodes | (1 << 27); 204 else 205 CondCodes = CondCodes; 206 Dest = res; 207 ''' 208 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 209 { "code": ssatCode, 210 "predicate_test": condPredicateTest }, []) 211 header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 212 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 213 exec_output += PredOpExecute.subst(ssatIop) 214 215 usatCode = ''' 216 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 217 int32_t res; 218 if (uSatInt(res, operand, imm)) 219 CondCodes = CondCodes | (1 << 27); 220 else 221 CondCodes = CondCodes; 222 Dest = res; 223 ''' 224 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 225 { "code": usatCode, 226 "predicate_test": condPredicateTest }, []) 227 header_output += RegImmRegShiftOpDeclare.subst(usatIop) 228 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 229 exec_output += PredOpExecute.subst(usatIop) 230 231 ssat16Code = ''' 232 int32_t res; 233 uint32_t resTemp = 0; 234 CondCodes = CondCodes; 235 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 236 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 237 if (satInt(res, argLow, imm)) 238 CondCodes = CondCodes | (1 << 27); 239 replaceBits(resTemp, 15, 0, res); 240 if (satInt(res, argHigh, imm)) 241 CondCodes = CondCodes | (1 << 27); 242 replaceBits(resTemp, 31, 16, res); 243 Dest = resTemp; 244 ''' 245 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 246 { "code": ssat16Code, 247 "predicate_test": condPredicateTest }, []) 248 header_output += RegImmRegOpDeclare.subst(ssat16Iop) 249 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 250 exec_output += PredOpExecute.subst(ssat16Iop) 251 252 usat16Code = ''' 253 int32_t res; 254 uint32_t resTemp = 0; 255 CondCodes = CondCodes; 256 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 257 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 258 if (uSatInt(res, argLow, imm)) 259 CondCodes = CondCodes | (1 << 27); 260 replaceBits(resTemp, 15, 0, res); 261 if (uSatInt(res, argHigh, imm)) 262 CondCodes = CondCodes | (1 << 27); 263 replaceBits(resTemp, 31, 16, res); 264 Dest = resTemp; 265 ''' 266 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 267 { "code": usat16Code, 268 "predicate_test": condPredicateTest }, []) 269 header_output += RegImmRegOpDeclare.subst(usat16Iop) 270 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 271 exec_output += PredOpExecute.subst(usat16Iop) 272 273 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 274 { "code": 275 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 276 "predicate_test": predicateTest }, []) 277 header_output += RegImmRegOpDeclare.subst(sxtbIop) 278 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 279 exec_output += PredOpExecute.subst(sxtbIop) 280 281 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 282 { "code": 283 ''' 284 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 285 Op1; 286 ''', 287 "predicate_test": predicateTest }, []) 288 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 289 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 290 exec_output += PredOpExecute.subst(sxtabIop) 291 292 sxtb16Code = ''' 293 uint32_t resTemp = 0; 294 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 295 replaceBits(resTemp, 31, 16, 296 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 297 Dest = resTemp; 298 ''' 299 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 300 { "code": sxtb16Code, 301 "predicate_test": predicateTest }, []) 302 header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 303 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 304 exec_output += PredOpExecute.subst(sxtb16Iop) 305 306 sxtab16Code = ''' 307 uint32_t resTemp = 0; 308 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 309 bits(Op1, 15, 0)); 310 replaceBits(resTemp, 31, 16, 311 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 312 bits(Op1, 31, 16)); 313 Dest = resTemp; 314 ''' 315 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 316 { "code": sxtab16Code, 317 "predicate_test": predicateTest }, []) 318 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 319 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 320 exec_output += PredOpExecute.subst(sxtab16Iop) 321 322 sxthCode = ''' 323 uint64_t rotated = (uint32_t)Op1; 324 rotated = (rotated | (rotated << 32)) >> imm; 325 Dest = sext<16>((uint16_t)rotated); 326 ''' 327 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 328 { "code": sxthCode, 329 "predicate_test": predicateTest }, []) 330 header_output += RegImmRegOpDeclare.subst(sxthIop) 331 decoder_output += RegImmRegOpConstructor.subst(sxthIop) 332 exec_output += PredOpExecute.subst(sxthIop) 333 334 sxtahCode = ''' 335 uint64_t rotated = (uint32_t)Op2; 336 rotated = (rotated | (rotated << 32)) >> imm; 337 Dest = sext<16>((uint16_t)rotated) + Op1; 338 ''' 339 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 340 { "code": sxtahCode, 341 "predicate_test": predicateTest }, []) 342 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 343 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 344 exec_output += PredOpExecute.subst(sxtahIop) 345 346 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 347 { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 348 "predicate_test": predicateTest }, []) 349 header_output += RegImmRegOpDeclare.subst(uxtbIop) 350 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 351 exec_output += PredOpExecute.subst(uxtbIop) 352 353 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 354 { "code": 355 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 356 "predicate_test": predicateTest }, []) 357 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 358 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 359 exec_output += PredOpExecute.subst(uxtabIop) 360 361 uxtb16Code = ''' 362 uint32_t resTemp = 0; 363 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 364 replaceBits(resTemp, 31, 16, 365 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 366 Dest = resTemp; 367 ''' 368 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 369 { "code": uxtb16Code, 370 "predicate_test": predicateTest }, []) 371 header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 372 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 373 exec_output += PredOpExecute.subst(uxtb16Iop) 374 375 uxtab16Code = ''' 376 uint32_t resTemp = 0; 377 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 378 bits(Op1, 15, 0)); 379 replaceBits(resTemp, 31, 16, 380 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 381 bits(Op1, 31, 16)); 382 Dest = resTemp; 383 ''' 384 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 385 { "code": uxtab16Code, 386 "predicate_test": predicateTest }, []) 387 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 388 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 389 exec_output += PredOpExecute.subst(uxtab16Iop) 390 391 uxthCode = ''' 392 uint64_t rotated = (uint32_t)Op1; 393 rotated = (rotated | (rotated << 32)) >> imm; 394 Dest = (uint16_t)rotated; 395 ''' 396 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 397 { "code": uxthCode, 398 "predicate_test": predicateTest }, []) 399 header_output += RegImmRegOpDeclare.subst(uxthIop) 400 decoder_output += RegImmRegOpConstructor.subst(uxthIop) 401 exec_output += PredOpExecute.subst(uxthIop) 402 403 uxtahCode = ''' 404 uint64_t rotated = (uint32_t)Op2; 405 rotated = (rotated | (rotated << 32)) >> imm; 406 Dest = (uint16_t)rotated + Op1; 407 ''' 408 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 409 { "code": uxtahCode, 410 "predicate_test": predicateTest }, []) 411 header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 412 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 413 exec_output += PredOpExecute.subst(uxtahIop) 414 415 selCode = ''' 416 uint32_t resTemp = 0; 417 for (unsigned i = 0; i < 4; i++) { 418 int low = i * 8; 419 int high = low + 7; 420 replaceBits(resTemp, high, low, 421 bits(CondCodes, 16 + i) ? 422 bits(Op1, high, low) : bits(Op2, high, low)); 423 } 424 Dest = resTemp; 425 ''' 426 selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 427 { "code": selCode, 428 "predicate_test": condPredicateTest }, []) 429 header_output += RegRegRegOpDeclare.subst(selIop) 430 decoder_output += RegRegRegOpConstructor.subst(selIop) 431 exec_output += PredOpExecute.subst(selIop) 432 433 usad8Code = ''' 434 uint32_t resTemp = 0; 435 for (unsigned i = 0; i < 4; i++) { 436 int low = i * 8; 437 int high = low + 7; 438 int32_t diff = bits(Op1, high, low) - 439 bits(Op2, high, low); 440 resTemp += ((diff < 0) ? -diff : diff); 441 } 442 Dest = resTemp; 443 ''' 444 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 445 { "code": usad8Code, 446 "predicate_test": predicateTest }, []) 447 header_output += RegRegRegOpDeclare.subst(usad8Iop) 448 decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 449 exec_output += PredOpExecute.subst(usad8Iop) 450 451 usada8Code = ''' 452 uint32_t resTemp = 0; 453 for (unsigned i = 0; i < 4; i++) { 454 int low = i * 8; 455 int high = low + 7; 456 int32_t diff = bits(Op1, high, low) - 457 bits(Op2, high, low); 458 resTemp += ((diff < 0) ? -diff : diff); 459 } 460 Dest = Op3 + resTemp; 461 ''' 462 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 463 { "code": usada8Code, 464 "predicate_test": predicateTest }, []) 465 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 466 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 467 exec_output += PredOpExecute.subst(usada8Iop) 468 469 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 470 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 471 header_output += BasicDeclare.subst(bkptIop) 472 decoder_output += BasicConstructor.subst(bkptIop) 473 exec_output += BasicExecute.subst(bkptIop) 474 475 nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 476 { "code" : "", "predicate_test" : predicateTest }) 477 header_output += BasicDeclare.subst(nopIop) 478 decoder_output += BasicConstructor.subst(nopIop) 479 exec_output += PredOpExecute.subst(nopIop) 480 481 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 482 { "code" : "", "predicate_test" : predicateTest }) 483 header_output += BasicDeclare.subst(yieldIop) 484 decoder_output += BasicConstructor.subst(yieldIop) 485 exec_output += PredOpExecute.subst(yieldIop) 486 487 wfeCode = ''' 488#if FULL_SYSTEM 489 if (SevMailbox) 490 SevMailbox = 0; 491 else 492 PseudoInst::quiesce(xc->tcBase()); 493#endif 494 ''' 495 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 496 { "code" : wfeCode, "predicate_test" : predicateTest }, 497 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 498 header_output += BasicDeclare.subst(wfeIop) 499 decoder_output += BasicConstructor.subst(wfeIop) 500 exec_output += PredOpExecute.subst(wfeIop) 501 502 wfiCode = ''' 503#if FULL_SYSTEM 504 PseudoInst::quiesce(xc->tcBase()); 505#endif 506 ''' 507 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 508 { "code" : wfiCode, "predicate_test" : predicateTest }, 509 ["IsNonSpeculative", "IsQuiesce"]) 510 header_output += BasicDeclare.subst(wfiIop) 511 decoder_output += BasicConstructor.subst(wfiIop) 512 exec_output += PredOpExecute.subst(wfiIop) 513 514 sevCode = ''' 515 // Need a way for O3 to not scoreboard these accesses as pipe flushes. 516 System *sys = xc->tcBase()->getSystemPtr(); 517 for (int x = 0; x < sys->numContexts(); x++) { 518 ThreadContext *oc = sys->getThreadContext(x); 519 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 520 } 521 ''' 522 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 523 { "code" : sevCode, "predicate_test" : predicateTest }, 524 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 525 header_output += BasicDeclare.subst(sevIop) 526 decoder_output += BasicConstructor.subst(sevIop) 527 exec_output += PredOpExecute.subst(sevIop) 528 529 itIop = InstObjParams("it", "ItInst", "PredOp", \ 530 { "code" : "Itstate = machInst.newItstate;", 531 "predicate_test" : predicateTest }, 532 ["IsNonSpeculative", "IsSerializeAfter"]) 533 header_output += BasicDeclare.subst(itIop) 534 decoder_output += BasicConstructor.subst(itIop) 535 exec_output += PredOpExecute.subst(itIop) 536 unknownCode = ''' 537#if FULL_SYSTEM 538 return new UndefinedInstruction; 539#else 540 return new UndefinedInstruction(machInst, true); 541#endif 542 ''' 543 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 544 { "code": unknownCode, 545 "predicate_test": predicateTest }) 546 header_output += BasicDeclare.subst(unknownIop) 547 decoder_output += BasicConstructor.subst(unknownIop) 548 exec_output += PredOpExecute.subst(unknownIop) 549 550 ubfxCode = ''' 551 Dest = bits(Op1, imm2, imm1); 552 ''' 553 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 554 { "code": ubfxCode, 555 "predicate_test": predicateTest }, []) 556 header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 557 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 558 exec_output += PredOpExecute.subst(ubfxIop) 559 560 sbfxCode = ''' 561 int32_t resTemp = bits(Op1, imm2, imm1); 562 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 563 ''' 564 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 565 { "code": sbfxCode, 566 "predicate_test": predicateTest }, []) 567 header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 568 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 569 exec_output += PredOpExecute.subst(sbfxIop) 570 571 bfcCode = ''' 572 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 573 ''' 574 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 575 { "code": bfcCode, 576 "predicate_test": predicateTest }, []) 577 header_output += RegRegImmImmOpDeclare.subst(bfcIop) 578 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 579 exec_output += PredOpExecute.subst(bfcIop) 580 581 bfiCode = ''' 582 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 583 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 584 ''' 585 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 586 { "code": bfiCode, 587 "predicate_test": predicateTest }, []) 588 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 589 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 590 exec_output += PredOpExecute.subst(bfiIop) 591 592 mrc15code = ''' 593 CPSR cpsr = Cpsr; 594 if (cpsr.mode == MODE_USER) 595#if FULL_SYSTEM 596 return new UndefinedInstruction; 597#else 598 return new UndefinedInstruction(false, mnemonic); 599#endif 600 Dest = MiscOp1; 601 ''' 602 603 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 604 { "code": mrc15code, 605 "predicate_test": predicateTest }, []) 606 header_output += RegRegOpDeclare.subst(mrc15Iop) 607 decoder_output += RegRegOpConstructor.subst(mrc15Iop) 608 exec_output += PredOpExecute.subst(mrc15Iop) 609 610 611 mcr15code = ''' 612 CPSR cpsr = Cpsr; 613 if (cpsr.mode == MODE_USER) 614#if FULL_SYSTEM 615 return new UndefinedInstruction; 616#else 617 return new UndefinedInstruction(false, mnemonic); 618#endif 619 MiscDest = Op1; 620 ''' 621 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 622 { "code": mcr15code, 623 "predicate_test": predicateTest }, 624 ["IsSerializeAfter","IsNonSpeculative"]) 625 header_output += RegRegOpDeclare.subst(mcr15Iop) 626 decoder_output += RegRegOpConstructor.subst(mcr15Iop) 627 exec_output += PredOpExecute.subst(mcr15Iop) 628 629 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 630 { "code": "Dest = MiscOp1;", 631 "predicate_test": predicateTest }, []) 632 header_output += RegRegOpDeclare.subst(mrc15UserIop) 633 decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 634 exec_output += PredOpExecute.subst(mrc15UserIop) 635 636 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 637 { "code": "MiscDest = Op1", 638 "predicate_test": predicateTest }, 639 ["IsSerializeAfter","IsNonSpeculative"]) 640 header_output += RegRegOpDeclare.subst(mcr15UserIop) 641 decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 642 exec_output += PredOpExecute.subst(mcr15UserIop) 643 644 enterxCode = ''' 645 NextThumb = true; 646 NextJazelle = true; 647 ''' 648 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 649 { "code": enterxCode, 650 "predicate_test": predicateTest }, []) 651 header_output += BasicDeclare.subst(enterxIop) 652 decoder_output += BasicConstructor.subst(enterxIop) 653 exec_output += PredOpExecute.subst(enterxIop) 654 655 leavexCode = ''' 656 NextThumb = true; 657 NextJazelle = false; 658 ''' 659 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 660 { "code": leavexCode, 661 "predicate_test": predicateTest }, []) 662 header_output += BasicDeclare.subst(leavexIop) 663 decoder_output += BasicConstructor.subst(leavexIop) 664 exec_output += PredOpExecute.subst(leavexIop) 665 666 setendCode = ''' 667 CPSR cpsr = Cpsr; 668 cpsr.e = imm; 669 Cpsr = cpsr; 670 ''' 671 setendIop = InstObjParams("setend", "Setend", "ImmOp", 672 { "code": setendCode, 673 "predicate_test": predicateTest }, 674 ["IsSerializeAfter","IsNonSpeculative"]) 675 header_output += ImmOpDeclare.subst(setendIop) 676 decoder_output += ImmOpConstructor.subst(setendIop) 677 exec_output += PredOpExecute.subst(setendIop) 678 679 clrexCode = ''' 680 unsigned memAccessFlags = Request::CLEAR_LL | 681 ArmISA::TLB::AlignWord | Request::LLSC; 682 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); 683 ''' 684 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 685 { "code": clrexCode, 686 "predicate_test": predicateTest },[]) 687 header_output += ClrexDeclare.subst(clrexIop) 688 decoder_output += BasicConstructor.subst(clrexIop) 689 exec_output += PredOpExecute.subst(clrexIop) 690 exec_output += ClrexInitiateAcc.subst(clrexIop) 691 exec_output += ClrexCompleteAcc.subst(clrexIop) 692 693 isbCode = ''' 694 ''' 695 isbIop = InstObjParams("isb", "Isb", "PredOp", 696 {"code": isbCode, 697 "predicate_test": predicateTest}, ['IsSerializing']) 698 header_output += BasicDeclare.subst(isbIop) 699 decoder_output += BasicConstructor.subst(isbIop) 700 exec_output += PredOpExecute.subst(isbIop) 701 702 dsbCode = ''' 703 ''' 704 dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 705 {"code": dsbCode, 706 "predicate_test": predicateTest},['IsMemBarrier']) 707 header_output += BasicDeclare.subst(dsbIop) 708 decoder_output += BasicConstructor.subst(dsbIop) 709 exec_output += PredOpExecute.subst(dsbIop) 710 711 dmbCode = ''' 712 ''' 713 dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 714 {"code": dmbCode, 715 "predicate_test": predicateTest},['IsMemBarrier']) 716 header_output += BasicDeclare.subst(dmbIop) 717 decoder_output += BasicConstructor.subst(dmbIop) 718 exec_output += PredOpExecute.subst(dmbIop) 719 720 dbgCode = ''' 721 ''' 722 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 723 {"code": dbgCode, 724 "predicate_test": predicateTest}) 725 header_output += BasicDeclare.subst(dbgIop) 726 decoder_output += BasicConstructor.subst(dbgIop) 727 exec_output += PredOpExecute.subst(dbgIop) 728 729 cpsCode = ''' 730 uint32_t mode = bits(imm, 4, 0); 731 uint32_t f = bits(imm, 5); 732 uint32_t i = bits(imm, 6); 733 uint32_t a = bits(imm, 7); 734 bool setMode = bits(imm, 8); 735 bool enable = bits(imm, 9); 736 CPSR cpsr = Cpsr; 737 SCTLR sctlr = Sctlr; 738 if (cpsr.mode != MODE_USER) { 739 if (enable) { 740 if (f) cpsr.f = 0; 741 if (i) cpsr.i = 0; 742 if (a) cpsr.a = 0; 743 } else { 744 if (f && !sctlr.nmfi) cpsr.f = 1; 745 if (i) cpsr.i = 1; 746 if (a) cpsr.a = 1; 747 } 748 if (setMode) { 749 cpsr.mode = mode; 750 } 751 } 752 Cpsr = cpsr; 753 ''' 754 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 755 { "code": cpsCode, 756 "predicate_test": predicateTest }, 757 ["IsSerializeAfter","IsNonSpeculative"]) 758 header_output += ImmOpDeclare.subst(cpsIop) 759 decoder_output += ImmOpConstructor.subst(cpsIop) 760 exec_output += PredOpExecute.subst(cpsIop) 761}}; 762