misc.isa revision 7202:b99579129992 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    svcCode = '''
43#if FULL_SYSTEM
44    fault = new SupervisorCall;
45#else
46    fault = new SupervisorCall(machInst);
47#endif
48    '''
49
50    svcIop = InstObjParams("svc", "Svc", "PredOp",
51                           { "code": svcCode,
52                             "predicate_test": predicateTest }, ["IsSyscall"])
53    header_output = BasicDeclare.subst(svcIop)
54    decoder_output = BasicConstructor.subst(svcIop)
55    exec_output = PredOpExecute.subst(svcIop)
56
57}};
58
59let {{
60
61    header_output = decoder_output = exec_output = ""
62
63    mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
64    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
65                               { "code": mrsCpsrCode,
66                                 "predicate_test": predicateTest }, [])
67    header_output += MrsDeclare.subst(mrsCpsrIop)
68    decoder_output += MrsConstructor.subst(mrsCpsrIop)
69    exec_output += PredOpExecute.subst(mrsCpsrIop)
70
71    mrsSpsrCode = "Dest = Spsr"
72    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
73                               { "code": mrsSpsrCode,
74                                 "predicate_test": predicateTest }, [])
75    header_output += MrsDeclare.subst(mrsSpsrIop)
76    decoder_output += MrsConstructor.subst(mrsSpsrIop)
77    exec_output += PredOpExecute.subst(mrsSpsrIop)
78
79    msrCpsrRegCode = '''
80        uint32_t newCpsr =
81            cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
82        Cpsr = ~CondCodesMask & newCpsr;
83        CondCodes = CondCodesMask & newCpsr;
84    '''
85    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
86                                  { "code": msrCpsrRegCode,
87                                    "predicate_test": predicateTest }, [])
88    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
89    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
90    exec_output += PredOpExecute.subst(msrCpsrRegIop)
91
92    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
93    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
94                                  { "code": msrSpsrRegCode,
95                                    "predicate_test": predicateTest }, [])
96    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
97    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
98    exec_output += PredOpExecute.subst(msrSpsrRegIop)
99
100    msrCpsrImmCode = '''
101        uint32_t newCpsr =
102            cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
103        Cpsr = ~CondCodesMask & newCpsr;
104        CondCodes = CondCodesMask & newCpsr;
105    '''
106    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
107                                  { "code": msrCpsrImmCode,
108                                    "predicate_test": predicateTest }, [])
109    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
110    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
111    exec_output += PredOpExecute.subst(msrCpsrImmIop)
112
113    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
114    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
115                                  { "code": msrSpsrImmCode,
116                                    "predicate_test": predicateTest }, [])
117    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
118    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
119    exec_output += PredOpExecute.subst(msrSpsrImmIop)
120}};
121