misc.isa revision 12646:3fa08822f79c
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2013,2017-2018 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 svcCode = ''' 43 ThreadContext *tc = xc->tcBase(); 44 45 const auto semihost_imm = Thumb? 0xAB : 0x123456; 46 47 if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { 48 R0 = ArmSystem::callSemihosting32(tc, R0, R1); 49 } else { 50 fault = std::make_shared<SupervisorCall>(machInst, imm); 51 } 52 ''' 53 54 svcIop = InstObjParams("svc", "Svc", "ImmOp", 55 { "code": svcCode, 56 "predicate_test": predicateTest, 57 "thumb_semihost": '0xAB', 58 "arm_semihost": '0x123456' }, 59 ["IsSyscall", "IsNonSpeculative", 60 "IsSerializeAfter"]) 61 header_output = ImmOpDeclare.subst(svcIop) 62 decoder_output = SemihostConstructor.subst(svcIop) 63 exec_output = PredOpExecute.subst(svcIop) 64 65 hltCode = ''' 66 ThreadContext *tc = xc->tcBase(); 67 68 const auto semihost_imm = Thumb? 0x3C : 0xF000; 69 70 if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { 71 R0 = ArmSystem::callSemihosting32(tc, R0, R1); 72 } else { 73 // HLT instructions aren't implemented, so treat them as undefined 74 // instructions. 75 fault = std::make_shared<UndefinedInstruction>( 76 machInst, false, mnemonic); 77 } 78 ''' 79 80 hltIop = InstObjParams("hlt", "Hlt", "ImmOp", 81 { "code": hltCode, 82 "predicate_test": predicateTest, 83 "thumb_semihost": '0x3C', 84 "arm_semihost": '0xF000' }, 85 ["IsNonSpeculative"]) 86 header_output += ImmOpDeclare.subst(hltIop) 87 decoder_output += SemihostConstructor.subst(hltIop) 88 exec_output += PredOpExecute.subst(hltIop) 89 90 smcCode = ''' 91 HCR hcr = Hcr; 92 CPSR cpsr = Cpsr; 93 SCR scr = Scr; 94 95 if ((cpsr.mode != MODE_USER) && FullSystem) { 96 if (ArmSystem::haveVirtualization(xc->tcBase()) && 97 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) { 98 fault = std::make_shared<HypervisorTrap>(machInst, 0, 99 EC_SMC_TO_HYP); 100 } else { 101 if (scr.scd) { 102 fault = disabledFault(); 103 } else { 104 fault = std::make_shared<SecureMonitorCall>(machInst); 105 } 106 } 107 } else { 108 fault = disabledFault(); 109 } 110 ''' 111 112 smcIop = InstObjParams("smc", "Smc", "PredOp", 113 { "code": smcCode, 114 "predicate_test": predicateTest }, 115 ["IsNonSpeculative", "IsSerializeAfter"]) 116 header_output += BasicDeclare.subst(smcIop) 117 decoder_output += BasicConstructor.subst(smcIop) 118 exec_output += PredOpExecute.subst(smcIop) 119 120 hvcCode = ''' 121 CPSR cpsr = Cpsr; 122 SCR scr = Scr; 123 124 // Filter out the various cases where this instruction isn't defined 125 if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) || 126 (cpsr.mode == MODE_USER) || 127 (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { 128 fault = disabledFault(); 129 } else { 130 fault = std::make_shared<HypervisorCall>(machInst, imm); 131 } 132 ''' 133 134 hvcIop = InstObjParams("hvc", "Hvc", "ImmOp", 135 { "code": hvcCode, 136 "predicate_test": predicateTest }, 137 ["IsNonSpeculative", "IsSerializeAfter"]) 138 header_output += ImmOpDeclare.subst(hvcIop) 139 decoder_output += ImmOpConstructor.subst(hvcIop) 140 exec_output += PredOpExecute.subst(hvcIop) 141 142 eretCode = ''' 143 SCTLR sctlr = Sctlr; 144 CPSR old_cpsr = Cpsr; 145 old_cpsr.nz = CondCodesNZ; 146 old_cpsr.c = CondCodesC; 147 old_cpsr.v = CondCodesV; 148 old_cpsr.ge = CondCodesGE; 149 150 CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, 151 true, sctlr.nmfi, xc->tcBase()); 152 Cpsr = ~CondCodesMask & new_cpsr; 153 CondCodesNZ = new_cpsr.nz; 154 CondCodesC = new_cpsr.c; 155 CondCodesV = new_cpsr.v; 156 CondCodesGE = new_cpsr.ge; 157 158 NextThumb = (new_cpsr).t; 159 NextJazelle = (new_cpsr).j; 160 NextItState = (((new_cpsr).it2 << 2) & 0xFC) 161 | ((new_cpsr).it1 & 0x3); 162 163 NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR; 164 ''' 165 166 eretIop = InstObjParams("eret", "Eret", "PredOp", 167 { "code": eretCode, 168 "predicate_test": predicateTest }, 169 ["IsNonSpeculative", "IsSerializeAfter", 170 "IsSquashAfter"]) 171 header_output += BasicDeclare.subst(eretIop) 172 decoder_output += BasicConstructor.subst(eretIop) 173 exec_output += PredOpExecute.subst(eretIop) 174 175 crcCode = ''' 176 constexpr uint8_t size_bytes = %(sz)d; 177 constexpr uint32_t poly = %(polynom)s; 178 179 uint32_t data = htole(Op2); 180 auto data_buffer = reinterpret_cast<uint8_t*>(&data); 181 182 Dest = crc32<poly>( 183 data_buffer, /* Message Register */ 184 Op1, /* Initial Value of the CRC */ 185 size_bytes /* Size of the original Message */ 186 ); 187 ''' 188 189 def crc32Emit(mnem, implCode, castagnoli, size): 190 global header_output, decoder_output, exec_output 191 192 if castagnoli: 193 # crc32c instructions 194 poly = "0x1EDC6F41" 195 else: 196 # crc32 instructions 197 poly = "0x04C11DB7" 198 199 data = {'sz' : size, 'polynom': poly} 200 201 instCode = implCode % data 202 203 crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp", 204 { "code": instCode, 205 "predicate_test": predicateTest }, []) 206 header_output += RegRegRegOpDeclare.subst(crcIop) 207 decoder_output += RegRegRegOpConstructor.subst(crcIop) 208 exec_output += PredOpExecute.subst(crcIop) 209 210 crc32Emit("crc32b", crcCode, False, 1); 211 crc32Emit("crc32h", crcCode, False, 2); 212 crc32Emit("crc32w", crcCode, False, 4); 213 crc32Emit("crc32cb", crcCode, True, 1); 214 crc32Emit("crc32ch", crcCode, True, 2); 215 crc32Emit("crc32cw", crcCode, True, 4); 216 217}}; 218 219let {{ 220 221 header_output = decoder_output = exec_output = "" 222 223 mrsCpsrCode = ''' 224 CPSR cpsr = Cpsr; 225 cpsr.nz = CondCodesNZ; 226 cpsr.c = CondCodesC; 227 cpsr.v = CondCodesV; 228 cpsr.ge = CondCodesGE; 229 Dest = cpsr & 0xF8FF03DF 230 ''' 231 232 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 233 { "code": mrsCpsrCode, 234 "predicate_test": condPredicateTest }, 235 ["IsSerializeBefore"]) 236 header_output += MrsDeclare.subst(mrsCpsrIop) 237 decoder_output += MrsConstructor.subst(mrsCpsrIop) 238 exec_output += PredOpExecute.subst(mrsCpsrIop) 239 240 mrsSpsrCode = "Dest = Spsr" 241 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 242 { "code": mrsSpsrCode, 243 "predicate_test": predicateTest }, 244 ["IsSerializeBefore"]) 245 header_output += MrsDeclare.subst(mrsSpsrIop) 246 decoder_output += MrsConstructor.subst(mrsSpsrIop) 247 exec_output += PredOpExecute.subst(mrsSpsrIop) 248 249 mrsBankedRegCode = ''' 250 bool isIntReg; 251 int regIdx; 252 253 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 254 if (isIntReg) { 255 Dest = DecodedBankedIntReg; 256 } else { 257 Dest = xc->readMiscReg(regIdx); 258 } 259 } else { 260 return std::make_shared<UndefinedInstruction>(machInst, false, 261 mnemonic); 262 } 263 ''' 264 mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp", 265 { "code": mrsBankedRegCode, 266 "predicate_test": predicateTest }, 267 ["IsSerializeBefore"]) 268 header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop) 269 decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop) 270 exec_output += PredOpExecute.subst(mrsBankedRegIop) 271 272 msrBankedRegCode = ''' 273 bool isIntReg; 274 int regIdx; 275 276 if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 277 if (isIntReg) { 278 // This is a bit nasty, you would have thought that 279 // DecodedBankedIntReg wouldn't be written to unless the 280 // conditions on the IF statements above are met, however if 281 // you look at the generated C code you'll find that they are. 282 // However this is safe as DecodedBankedIntReg (which is used 283 // in operands.isa to get the index of DecodedBankedIntReg) 284 // will return INTREG_DUMMY if its not a valid integer 285 // register, so redirecting the write to somewhere we don't 286 // care about. 287 DecodedBankedIntReg = Op1; 288 } else { 289 xc->setMiscReg(regIdx, Op1); 290 } 291 } else { 292 return std::make_shared<UndefinedInstruction>(machInst, false, 293 mnemonic); 294 } 295 ''' 296 msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", 297 { "code": msrBankedRegCode, 298 "predicate_test": predicateTest }, 299 ["IsSerializeAfter", "IsNonSpeculative"]) 300 header_output += MsrBankedRegDeclare.subst(msrBankedRegIop) 301 decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop) 302 exec_output += PredOpExecute.subst(msrBankedRegIop) 303 304 msrCpsrRegCode = ''' 305 SCTLR sctlr = Sctlr; 306 CPSR old_cpsr = Cpsr; 307 old_cpsr.nz = CondCodesNZ; 308 old_cpsr.c = CondCodesC; 309 old_cpsr.v = CondCodesV; 310 old_cpsr.ge = CondCodesGE; 311 312 CPSR new_cpsr = 313 cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false, 314 sctlr.nmfi, xc->tcBase()); 315 Cpsr = ~CondCodesMask & new_cpsr; 316 CondCodesNZ = new_cpsr.nz; 317 CondCodesC = new_cpsr.c; 318 CondCodesV = new_cpsr.v; 319 CondCodesGE = new_cpsr.ge; 320 ''' 321 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 322 { "code": msrCpsrRegCode, 323 "predicate_test": condPredicateTest }, 324 ["IsSerializeAfter","IsNonSpeculative"]) 325 header_output += MsrRegDeclare.subst(msrCpsrRegIop) 326 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 327 exec_output += PredOpExecute.subst(msrCpsrRegIop) 328 329 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 330 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 331 { "code": msrSpsrRegCode, 332 "predicate_test": predicateTest }, 333 ["IsSerializeAfter","IsNonSpeculative"]) 334 header_output += MsrRegDeclare.subst(msrSpsrRegIop) 335 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 336 exec_output += PredOpExecute.subst(msrSpsrRegIop) 337 338 msrCpsrImmCode = ''' 339 SCTLR sctlr = Sctlr; 340 CPSR old_cpsr = Cpsr; 341 old_cpsr.nz = CondCodesNZ; 342 old_cpsr.c = CondCodesC; 343 old_cpsr.v = CondCodesV; 344 old_cpsr.ge = CondCodesGE; 345 CPSR new_cpsr = 346 cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false, 347 sctlr.nmfi, xc->tcBase()); 348 Cpsr = ~CondCodesMask & new_cpsr; 349 CondCodesNZ = new_cpsr.nz; 350 CondCodesC = new_cpsr.c; 351 CondCodesV = new_cpsr.v; 352 CondCodesGE = new_cpsr.ge; 353 ''' 354 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 355 { "code": msrCpsrImmCode, 356 "predicate_test": condPredicateTest }, 357 ["IsSerializeAfter","IsNonSpeculative"]) 358 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 359 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 360 exec_output += PredOpExecute.subst(msrCpsrImmIop) 361 362 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 363 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 364 { "code": msrSpsrImmCode, 365 "predicate_test": predicateTest }, 366 ["IsSerializeAfter","IsNonSpeculative"]) 367 header_output += MsrImmDeclare.subst(msrSpsrImmIop) 368 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 369 exec_output += PredOpExecute.subst(msrSpsrImmIop) 370 371 revCode = ''' 372 uint32_t val = Op1; 373 Dest = swap_byte(val); 374 ''' 375 revIop = InstObjParams("rev", "Rev", "RegRegOp", 376 { "code": revCode, 377 "predicate_test": predicateTest }, []) 378 header_output += RegRegOpDeclare.subst(revIop) 379 decoder_output += RegRegOpConstructor.subst(revIop) 380 exec_output += PredOpExecute.subst(revIop) 381 382 rev16Code = ''' 383 uint32_t val = Op1; 384 Dest = (bits(val, 15, 8) << 0) | 385 (bits(val, 7, 0) << 8) | 386 (bits(val, 31, 24) << 16) | 387 (bits(val, 23, 16) << 24); 388 ''' 389 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 390 { "code": rev16Code, 391 "predicate_test": predicateTest }, []) 392 header_output += RegRegOpDeclare.subst(rev16Iop) 393 decoder_output += RegRegOpConstructor.subst(rev16Iop) 394 exec_output += PredOpExecute.subst(rev16Iop) 395 396 revshCode = ''' 397 uint16_t val = Op1; 398 Dest = sext<16>(swap_byte(val)); 399 ''' 400 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 401 { "code": revshCode, 402 "predicate_test": predicateTest }, []) 403 header_output += RegRegOpDeclare.subst(revshIop) 404 decoder_output += RegRegOpConstructor.subst(revshIop) 405 exec_output += PredOpExecute.subst(revshIop) 406 407 rbitCode = ''' 408 Dest = reverseBits(Op1); 409 ''' 410 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 411 { "code": rbitCode, 412 "predicate_test": predicateTest }, []) 413 header_output += RegRegOpDeclare.subst(rbitIop) 414 decoder_output += RegRegOpConstructor.subst(rbitIop) 415 exec_output += PredOpExecute.subst(rbitIop) 416 417 clzCode = ''' 418 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 419 ''' 420 clzIop = InstObjParams("clz", "Clz", "RegRegOp", 421 { "code": clzCode, 422 "predicate_test": predicateTest }, []) 423 header_output += RegRegOpDeclare.subst(clzIop) 424 decoder_output += RegRegOpConstructor.subst(clzIop) 425 exec_output += PredOpExecute.subst(clzIop) 426 427 ssatCode = ''' 428 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 429 int32_t res; 430 if (satInt(res, operand, imm)) 431 CpsrQ = 1 << 27; 432 Dest = res; 433 ''' 434 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 435 { "code": ssatCode, 436 "predicate_test": pickPredicate(ssatCode) }, []) 437 header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 438 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 439 exec_output += PredOpExecute.subst(ssatIop) 440 441 usatCode = ''' 442 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 443 int32_t res; 444 if (uSatInt(res, operand, imm)) 445 CpsrQ = 1 << 27; 446 Dest = res; 447 ''' 448 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 449 { "code": usatCode, 450 "predicate_test": pickPredicate(usatCode) }, []) 451 header_output += RegImmRegShiftOpDeclare.subst(usatIop) 452 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 453 exec_output += PredOpExecute.subst(usatIop) 454 455 ssat16Code = ''' 456 int32_t res; 457 uint32_t resTemp = 0; 458 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 459 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 460 if (satInt(res, argLow, imm)) 461 CpsrQ = 1 << 27; 462 replaceBits(resTemp, 15, 0, res); 463 if (satInt(res, argHigh, imm)) 464 CpsrQ = 1 << 27; 465 replaceBits(resTemp, 31, 16, res); 466 Dest = resTemp; 467 ''' 468 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 469 { "code": ssat16Code, 470 "predicate_test": pickPredicate(ssat16Code) }, []) 471 header_output += RegImmRegOpDeclare.subst(ssat16Iop) 472 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 473 exec_output += PredOpExecute.subst(ssat16Iop) 474 475 usat16Code = ''' 476 int32_t res; 477 uint32_t resTemp = 0; 478 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 479 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 480 if (uSatInt(res, argLow, imm)) 481 CpsrQ = 1 << 27; 482 replaceBits(resTemp, 15, 0, res); 483 if (uSatInt(res, argHigh, imm)) 484 CpsrQ = 1 << 27; 485 replaceBits(resTemp, 31, 16, res); 486 Dest = resTemp; 487 ''' 488 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 489 { "code": usat16Code, 490 "predicate_test": pickPredicate(usat16Code) }, []) 491 header_output += RegImmRegOpDeclare.subst(usat16Iop) 492 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 493 exec_output += PredOpExecute.subst(usat16Iop) 494 495 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 496 { "code": 497 "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", 498 "predicate_test": predicateTest }, []) 499 header_output += RegImmRegOpDeclare.subst(sxtbIop) 500 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 501 exec_output += PredOpExecute.subst(sxtbIop) 502 503 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 504 { "code": 505 ''' 506 Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + 507 Op1; 508 ''', 509 "predicate_test": predicateTest }, []) 510 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 511 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 512 exec_output += PredOpExecute.subst(sxtabIop) 513 514 sxtb16Code = ''' 515 uint32_t resTemp = 0; 516 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 517 replaceBits(resTemp, 31, 16, 518 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 519 Dest = resTemp; 520 ''' 521 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 522 { "code": sxtb16Code, 523 "predicate_test": predicateTest }, []) 524 header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 525 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 526 exec_output += PredOpExecute.subst(sxtb16Iop) 527 528 sxtab16Code = ''' 529 uint32_t resTemp = 0; 530 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 531 bits(Op1, 15, 0)); 532 replaceBits(resTemp, 31, 16, 533 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 534 bits(Op1, 31, 16)); 535 Dest = resTemp; 536 ''' 537 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 538 { "code": sxtab16Code, 539 "predicate_test": predicateTest }, []) 540 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 541 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 542 exec_output += PredOpExecute.subst(sxtab16Iop) 543 544 sxthCode = ''' 545 uint64_t rotated = (uint32_t)Op1; 546 rotated = (rotated | (rotated << 32)) >> imm; 547 Dest = sext<16>((uint16_t)rotated); 548 ''' 549 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 550 { "code": sxthCode, 551 "predicate_test": predicateTest }, []) 552 header_output += RegImmRegOpDeclare.subst(sxthIop) 553 decoder_output += RegImmRegOpConstructor.subst(sxthIop) 554 exec_output += PredOpExecute.subst(sxthIop) 555 556 sxtahCode = ''' 557 uint64_t rotated = (uint32_t)Op2; 558 rotated = (rotated | (rotated << 32)) >> imm; 559 Dest = sext<16>((uint16_t)rotated) + Op1; 560 ''' 561 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 562 { "code": sxtahCode, 563 "predicate_test": predicateTest }, []) 564 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 565 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 566 exec_output += PredOpExecute.subst(sxtahIop) 567 568 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 569 { "code": "Dest = (uint8_t)(Op1_ud >> imm);", 570 "predicate_test": predicateTest }, []) 571 header_output += RegImmRegOpDeclare.subst(uxtbIop) 572 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 573 exec_output += PredOpExecute.subst(uxtbIop) 574 575 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 576 { "code": 577 "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", 578 "predicate_test": predicateTest }, []) 579 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 580 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 581 exec_output += PredOpExecute.subst(uxtabIop) 582 583 uxtb16Code = ''' 584 uint32_t resTemp = 0; 585 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 586 replaceBits(resTemp, 31, 16, 587 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 588 Dest = resTemp; 589 ''' 590 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 591 { "code": uxtb16Code, 592 "predicate_test": predicateTest }, []) 593 header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 594 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 595 exec_output += PredOpExecute.subst(uxtb16Iop) 596 597 uxtab16Code = ''' 598 uint32_t resTemp = 0; 599 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 600 bits(Op1, 15, 0)); 601 replaceBits(resTemp, 31, 16, 602 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 603 bits(Op1, 31, 16)); 604 Dest = resTemp; 605 ''' 606 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 607 { "code": uxtab16Code, 608 "predicate_test": predicateTest }, []) 609 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 610 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 611 exec_output += PredOpExecute.subst(uxtab16Iop) 612 613 uxthCode = ''' 614 uint64_t rotated = (uint32_t)Op1; 615 rotated = (rotated | (rotated << 32)) >> imm; 616 Dest = (uint16_t)rotated; 617 ''' 618 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 619 { "code": uxthCode, 620 "predicate_test": predicateTest }, []) 621 header_output += RegImmRegOpDeclare.subst(uxthIop) 622 decoder_output += RegImmRegOpConstructor.subst(uxthIop) 623 exec_output += PredOpExecute.subst(uxthIop) 624 625 uxtahCode = ''' 626 uint64_t rotated = (uint32_t)Op2; 627 rotated = (rotated | (rotated << 32)) >> imm; 628 Dest = (uint16_t)rotated + Op1; 629 ''' 630 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 631 { "code": uxtahCode, 632 "predicate_test": predicateTest }, []) 633 header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 634 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 635 exec_output += PredOpExecute.subst(uxtahIop) 636 637 selCode = ''' 638 uint32_t resTemp = 0; 639 for (unsigned i = 0; i < 4; i++) { 640 int low = i * 8; 641 int high = low + 7; 642 replaceBits(resTemp, high, low, 643 bits(CondCodesGE, i) ? 644 bits(Op1, high, low) : bits(Op2, high, low)); 645 } 646 Dest = resTemp; 647 ''' 648 selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 649 { "code": selCode, 650 "predicate_test": predicateTest }, []) 651 header_output += RegRegRegOpDeclare.subst(selIop) 652 decoder_output += RegRegRegOpConstructor.subst(selIop) 653 exec_output += PredOpExecute.subst(selIop) 654 655 usad8Code = ''' 656 uint32_t resTemp = 0; 657 for (unsigned i = 0; i < 4; i++) { 658 int low = i * 8; 659 int high = low + 7; 660 int32_t diff = bits(Op1, high, low) - 661 bits(Op2, high, low); 662 resTemp += ((diff < 0) ? -diff : diff); 663 } 664 Dest = resTemp; 665 ''' 666 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 667 { "code": usad8Code, 668 "predicate_test": predicateTest }, []) 669 header_output += RegRegRegOpDeclare.subst(usad8Iop) 670 decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 671 exec_output += PredOpExecute.subst(usad8Iop) 672 673 usada8Code = ''' 674 uint32_t resTemp = 0; 675 for (unsigned i = 0; i < 4; i++) { 676 int low = i * 8; 677 int high = low + 7; 678 int32_t diff = bits(Op1, high, low) - 679 bits(Op2, high, low); 680 resTemp += ((diff < 0) ? -diff : diff); 681 } 682 Dest = Op3 + resTemp; 683 ''' 684 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 685 { "code": usada8Code, 686 "predicate_test": predicateTest }, []) 687 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 688 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 689 exec_output += PredOpExecute.subst(usada8Iop) 690 691 bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n' 692 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 693 header_output += BasicDeclare.subst(bkptIop) 694 decoder_output += BasicConstructor.subst(bkptIop) 695 exec_output += BasicExecute.subst(bkptIop) 696 697 nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop']) 698 header_output += BasicDeclare.subst(nopIop) 699 decoder_output += BasicConstructor64.subst(nopIop) 700 exec_output += BasicExecute.subst(nopIop) 701 702 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 703 { "code" : "", "predicate_test" : predicateTest }) 704 header_output += BasicDeclare.subst(yieldIop) 705 decoder_output += BasicConstructor.subst(yieldIop) 706 exec_output += PredOpExecute.subst(yieldIop) 707 708 wfeCode = ''' 709 CPSR cpsr = Cpsr; 710 SCR scr = Scr64; 711 712 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending, 713 ThreadContext *tc = xc->tcBase(); 714 if (SevMailbox == 1) { 715 SevMailbox = 0; 716 PseudoInst::quiesceSkip(tc); 717 } else if (tc->getCpuPtr()->getInterruptController( 718 tc->threadId())->checkInterrupts(tc)) { 719 PseudoInst::quiesceSkip(tc); 720 } else { 721 fault = trapWFx(tc, cpsr, scr, true); 722 if (fault == NoFault) { 723 PseudoInst::quiesce(tc); 724 } else { 725 PseudoInst::quiesceSkip(tc); 726 } 727 } 728 ''' 729 wfePredFixUpCode = ''' 730 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps 731 // and SEV interrupts 732 SevMailbox = 1; 733 ''' 734 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 735 { "code" : wfeCode, 736 "pred_fixup" : wfePredFixUpCode, 737 "predicate_test" : predicateTest }, 738 ["IsNonSpeculative", "IsQuiesce", 739 "IsSerializeAfter", "IsUnverifiable"]) 740 header_output += BasicDeclare.subst(wfeIop) 741 decoder_output += BasicConstructor.subst(wfeIop) 742 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) 743 744 wfiCode = ''' 745 HCR hcr = Hcr; 746 CPSR cpsr = Cpsr; 747 SCR scr = Scr64; 748 749 // WFI doesn't sleep if interrupts are pending (masked or not) 750 ThreadContext *tc = xc->tcBase(); 751 if (tc->getCpuPtr()->getInterruptController( 752 tc->threadId())->checkWfiWake(hcr, cpsr, scr)) { 753 PseudoInst::quiesceSkip(tc); 754 } else { 755 fault = trapWFx(tc, cpsr, scr, false); 756 if (fault == NoFault) { 757 PseudoInst::quiesce(tc); 758 } else { 759 PseudoInst::quiesceSkip(tc); 760 } 761 } 762 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 763 ''' 764 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 765 { "code" : wfiCode, "predicate_test" : predicateTest }, 766 ["IsNonSpeculative", "IsQuiesce", 767 "IsSerializeAfter", "IsUnverifiable"]) 768 header_output += BasicDeclare.subst(wfiIop) 769 decoder_output += BasicConstructor.subst(wfiIop) 770 exec_output += QuiescePredOpExecute.subst(wfiIop) 771 772 sevCode = ''' 773 SevMailbox = 1; 774 System *sys = xc->tcBase()->getSystemPtr(); 775 for (int x = 0; x < sys->numContexts(); x++) { 776 ThreadContext *oc = sys->getThreadContext(x); 777 if (oc == xc->tcBase()) 778 continue; 779 // Wake CPU with interrupt if they were sleeping 780 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 781 // Post Interrupt and wake cpu if needed 782 oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0); 783 } 784 } 785 ''' 786 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 787 { "code" : sevCode, "predicate_test" : predicateTest }, 788 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 789 header_output += BasicDeclare.subst(sevIop) 790 decoder_output += BasicConstructor.subst(sevIop) 791 exec_output += PredOpExecute.subst(sevIop) 792 793 sevlCode = ''' 794 SevMailbox = 1; 795 ''' 796 sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \ 797 { "code" : sevlCode, "predicate_test" : predicateTest }, 798 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 799 header_output += BasicDeclare.subst(sevlIop) 800 decoder_output += BasicConstructor.subst(sevlIop) 801 exec_output += BasicExecute.subst(sevlIop) 802 803 itIop = InstObjParams("it", "ItInst", "PredOp", \ 804 { "code" : ";", 805 "predicate_test" : predicateTest }, []) 806 header_output += BasicDeclare.subst(itIop) 807 decoder_output += BasicConstructor.subst(itIop) 808 exec_output += PredOpExecute.subst(itIop) 809 unknownCode = ''' 810 return std::make_shared<UndefinedInstruction>(machInst, true); 811 ''' 812 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 813 { "code": unknownCode, 814 "predicate_test": predicateTest }) 815 header_output += BasicDeclare.subst(unknownIop) 816 decoder_output += BasicConstructor.subst(unknownIop) 817 exec_output += PredOpExecute.subst(unknownIop) 818 819 ubfxCode = ''' 820 Dest = bits(Op1, imm2, imm1); 821 ''' 822 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 823 { "code": ubfxCode, 824 "predicate_test": predicateTest }, []) 825 header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 826 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 827 exec_output += PredOpExecute.subst(ubfxIop) 828 829 sbfxCode = ''' 830 int32_t resTemp = bits(Op1, imm2, imm1); 831 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 832 ''' 833 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 834 { "code": sbfxCode, 835 "predicate_test": predicateTest }, []) 836 header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 837 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 838 exec_output += PredOpExecute.subst(sbfxIop) 839 840 bfcCode = ''' 841 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 842 ''' 843 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 844 { "code": bfcCode, 845 "predicate_test": predicateTest }, []) 846 header_output += RegRegImmImmOpDeclare.subst(bfcIop) 847 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 848 exec_output += PredOpExecute.subst(bfcIop) 849 850 bfiCode = ''' 851 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 852 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 853 ''' 854 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 855 { "code": bfiCode, 856 "predicate_test": predicateTest }, []) 857 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 858 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 859 exec_output += PredOpExecute.subst(bfiIop) 860 861 mrc14code = ''' 862 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 863 RegId(MiscRegClass, op1)).index(); 864 bool can_read, undefined; 865 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 866 if (!can_read || undefined) { 867 return std::make_shared<UndefinedInstruction>(machInst, false, 868 mnemonic); 869 } 870 if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr, 871 Hstr, Hcptr, imm)) { 872 return std::make_shared<HypervisorTrap>(machInst, imm, 873 EC_TRAPPED_CP14_MCR_MRC); 874 } 875 Dest = MiscOp1; 876 ''' 877 878 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp", 879 { "code": mrc14code, 880 "predicate_test": predicateTest }, []) 881 header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop) 882 decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop) 883 exec_output += PredOpExecute.subst(mrc14Iop) 884 885 886 mcr14code = ''' 887 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 888 RegId(MiscRegClass, dest)).index(); 889 bool can_write, undefined; 890 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 891 if (undefined || !can_write) { 892 return std::make_shared<UndefinedInstruction>(machInst, false, 893 mnemonic); 894 } 895 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, 896 Hstr, Hcptr, imm)) { 897 return std::make_shared<HypervisorTrap>(machInst, imm, 898 EC_TRAPPED_CP14_MCR_MRC); 899 } 900 MiscDest = Op1; 901 ''' 902 mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp", 903 { "code": mcr14code, 904 "predicate_test": predicateTest }, 905 ["IsSerializeAfter","IsNonSpeculative"]) 906 header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop) 907 decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop) 908 exec_output += PredOpExecute.subst(mcr14Iop) 909 910 mrc15code = ''' 911 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); 912 MiscRegIndex miscReg = (MiscRegIndex) 913 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 914 preFlatOp1)).index(); 915 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 916 Hcptr, imm); 917 bool can_read, undefined; 918 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 919 // if we're in non secure PL1 mode then we can trap regargless of whether 920 // the register is accessable, in other modes we trap if only if the register 921 // IS accessable. 922 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 923 !inSecureState(Scr, Cpsr)))) { 924 return std::make_shared<UndefinedInstruction>(machInst, false, 925 mnemonic); 926 } 927 if (hypTrap) { 928 return std::make_shared<HypervisorTrap>(machInst, imm, 929 EC_TRAPPED_CP15_MCR_MRC); 930 } 931 Dest = MiscNsBankedOp1; 932 ''' 933 934 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", 935 { "code": mrc15code, 936 "predicate_test": predicateTest }, []) 937 header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop) 938 decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop) 939 exec_output += PredOpExecute.subst(mrc15Iop) 940 941 942 mcr15code = ''' 943 int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 944 MiscRegIndex miscReg = (MiscRegIndex) 945 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 946 preFlatDest)).index(); 947 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 948 Hcptr, imm); 949 bool can_write, undefined; 950 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 951 952 // if we're in non secure PL1 mode then we can trap regargless of whether 953 // the register is accessable, in other modes we trap if only if the register 954 // IS accessable. 955 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 956 !inSecureState(Scr, Cpsr)))) { 957 return std::make_shared<UndefinedInstruction>(machInst, false, 958 mnemonic); 959 } 960 if (hypTrap) { 961 return std::make_shared<HypervisorTrap>(machInst, imm, 962 EC_TRAPPED_CP15_MCR_MRC); 963 } 964 MiscNsBankedDest = Op1; 965 ''' 966 mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", 967 { "code": mcr15code, 968 "predicate_test": predicateTest }, 969 ["IsSerializeAfter","IsNonSpeculative"]) 970 header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop) 971 decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop) 972 exec_output += PredOpExecute.subst(mcr15Iop) 973 974 975 mrrc15code = ''' 976 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); 977 MiscRegIndex miscReg = (MiscRegIndex) 978 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 979 preFlatOp1)).index(); 980 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 981 bool can_read, undefined; 982 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 983 // if we're in non secure PL1 mode then we can trap regargless of whether 984 // the register is accessable, in other modes we trap if only if the register 985 // IS accessable. 986 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 987 !inSecureState(Scr, Cpsr)))) { 988 return std::make_shared<UndefinedInstruction>(machInst, false, 989 mnemonic); 990 } 991 if (hypTrap) { 992 return std::make_shared<HypervisorTrap>(machInst, imm, 993 EC_TRAPPED_CP15_MCRR_MRRC); 994 } 995 Dest = bits(MiscNsBankedOp164, 63, 32); 996 Dest2 = bits(MiscNsBankedOp164, 31, 0); 997 ''' 998 mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp", 999 { "code": mrrc15code, 1000 "predicate_test": predicateTest }, []) 1001 header_output += MrrcOpDeclare.subst(mrrc15Iop) 1002 decoder_output += MrrcOpConstructor.subst(mrrc15Iop) 1003 exec_output += PredOpExecute.subst(mrrc15Iop) 1004 1005 1006 mcrr15code = ''' 1007 int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 1008 MiscRegIndex miscReg = (MiscRegIndex) 1009 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 1010 preFlatDest)).index(); 1011 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 1012 bool can_write, undefined; 1013 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 1014 1015 // if we're in non secure PL1 mode then we can trap regargless of whether 1016 // the register is accessable, in other modes we trap if only if the register 1017 // IS accessable. 1018 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 1019 !inSecureState(Scr, Cpsr)))) { 1020 return std::make_shared<UndefinedInstruction>(machInst, false, 1021 mnemonic); 1022 } 1023 if (hypTrap) { 1024 return std::make_shared<HypervisorTrap>(machInst, imm, 1025 EC_TRAPPED_CP15_MCRR_MRRC); 1026 } 1027 MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2; 1028 ''' 1029 mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp", 1030 { "code": mcrr15code, 1031 "predicate_test": predicateTest }, []) 1032 header_output += McrrOpDeclare.subst(mcrr15Iop) 1033 decoder_output += McrrOpConstructor.subst(mcrr15Iop) 1034 exec_output += PredOpExecute.subst(mcrr15Iop) 1035 1036 1037 enterxCode = ''' 1038 NextThumb = true; 1039 NextJazelle = true; 1040 ''' 1041 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 1042 { "code": enterxCode, 1043 "predicate_test": predicateTest }, []) 1044 header_output += BasicDeclare.subst(enterxIop) 1045 decoder_output += BasicConstructor.subst(enterxIop) 1046 exec_output += PredOpExecute.subst(enterxIop) 1047 1048 leavexCode = ''' 1049 NextThumb = true; 1050 NextJazelle = false; 1051 ''' 1052 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 1053 { "code": leavexCode, 1054 "predicate_test": predicateTest }, []) 1055 header_output += BasicDeclare.subst(leavexIop) 1056 decoder_output += BasicConstructor.subst(leavexIop) 1057 exec_output += PredOpExecute.subst(leavexIop) 1058 1059 setendCode = ''' 1060 CPSR cpsr = Cpsr; 1061 cpsr.e = imm; 1062 Cpsr = cpsr; 1063 fault = checkSETENDEnabled(xc->tcBase(), cpsr); 1064 ''' 1065 setendIop = InstObjParams("setend", "Setend", "ImmOp", 1066 { "code": setendCode, 1067 "predicate_test": predicateTest }, 1068 ["IsSerializeAfter","IsNonSpeculative"]) 1069 header_output += ImmOpDeclare.subst(setendIop) 1070 decoder_output += ImmOpConstructor.subst(setendIop) 1071 exec_output += PredOpExecute.subst(setendIop) 1072 1073 clrexCode = ''' 1074 LLSCLock = 0; 1075 ''' 1076 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 1077 { "code": clrexCode, 1078 "predicate_test": predicateTest },[]) 1079 header_output += BasicDeclare.subst(clrexIop) 1080 decoder_output += BasicConstructor.subst(clrexIop) 1081 exec_output += PredOpExecute.subst(clrexIop) 1082 1083 McrDcCheckCode = ''' 1084 int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 1085 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 1086 RegId(MiscRegClass, preFlatDest)).index(); 1087 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 1088 Hcptr, imm); 1089 bool can_write, undefined; 1090 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 1091 1092 // if we're in non secure PL1 mode then we can trap regardless 1093 // of whether the register is accessible, in other modes we 1094 // trap if only if the register IS accessible. 1095 if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) & 1096 !inSecureState(Scr, Cpsr)))) { 1097 return std::make_shared<UndefinedInstruction>(machInst, false, 1098 mnemonic); 1099 } 1100 if (hypTrap) { 1101 return std::make_shared<HypervisorTrap>(machInst, imm, 1102 EC_TRAPPED_CP15_MCR_MRC); 1103 } 1104 ''' 1105 1106 McrDcimvacCode = ''' 1107 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1108 Request::INVALIDATE | 1109 Request::DST_POC); 1110 EA = Op1; 1111 ''' 1112 McrDcimvacIop = InstObjParams("mcr", "McrDcimvac", 1113 "MiscRegRegImmOp", 1114 {"memacc_code": McrDcCheckCode, 1115 "postacc_code": "", 1116 "ea_code": McrDcimvacCode, 1117 "predicate_test": predicateTest}, 1118 ['IsMemRef', 'IsStore']) 1119 header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop) 1120 decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop) 1121 exec_output += Mcr15Execute.subst(McrDcimvacIop) + \ 1122 Mcr15InitiateAcc.subst(McrDcimvacIop) + \ 1123 Mcr15CompleteAcc.subst(McrDcimvacIop) 1124 1125 McrDccmvacCode = ''' 1126 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1127 Request::CLEAN | 1128 Request::DST_POC); 1129 EA = Op1; 1130 ''' 1131 McrDccmvacIop = InstObjParams("mcr", "McrDccmvac", 1132 "MiscRegRegImmOp", 1133 {"memacc_code": McrDcCheckCode, 1134 "postacc_code": "", 1135 "ea_code": McrDccmvacCode, 1136 "predicate_test": predicateTest}, 1137 ['IsMemRef', 'IsStore']) 1138 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop) 1139 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop) 1140 exec_output += Mcr15Execute.subst(McrDccmvacIop) + \ 1141 Mcr15InitiateAcc.subst(McrDccmvacIop) + \ 1142 Mcr15CompleteAcc.subst(McrDccmvacIop) 1143 1144 McrDccmvauCode = ''' 1145 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1146 Request::CLEAN | 1147 Request::DST_POU); 1148 EA = Op1; 1149 ''' 1150 McrDccmvauIop = InstObjParams("mcr", "McrDccmvau", 1151 "MiscRegRegImmOp", 1152 {"memacc_code": McrDcCheckCode, 1153 "postacc_code": "", 1154 "ea_code": McrDccmvauCode, 1155 "predicate_test": predicateTest}, 1156 ['IsMemRef', 'IsStore']) 1157 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop) 1158 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop) 1159 exec_output += Mcr15Execute.subst(McrDccmvauIop) + \ 1160 Mcr15InitiateAcc.subst(McrDccmvauIop) + \ 1161 Mcr15CompleteAcc.subst(McrDccmvauIop) 1162 1163 McrDccimvacCode = ''' 1164 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1165 Request::CLEAN | 1166 Request::INVALIDATE | 1167 Request::DST_POC); 1168 EA = Op1; 1169 ''' 1170 McrDccimvacIop = InstObjParams("mcr", "McrDccimvac", 1171 "MiscRegRegImmOp", 1172 {"memacc_code": McrDcCheckCode, 1173 "postacc_code": "", 1174 "ea_code": McrDccimvacCode, 1175 "predicate_test": predicateTest}, 1176 ['IsMemRef', 'IsStore']) 1177 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop) 1178 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop) 1179 exec_output += Mcr15Execute.subst(McrDccimvacIop) + \ 1180 Mcr15InitiateAcc.subst(McrDccimvacIop) + \ 1181 Mcr15CompleteAcc.subst(McrDccimvacIop) 1182 1183 isbCode = ''' 1184 // If the barrier is due to a CP15 access check for hyp traps 1185 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr, 1186 Hdcr, Hstr, Hcptr, imm)) { 1187 return std::make_shared<HypervisorTrap>(machInst, imm, 1188 EC_TRAPPED_CP15_MCR_MRC); 1189 } 1190 ''' 1191 isbIop = InstObjParams("isb", "Isb", "ImmOp", 1192 {"code": isbCode, 1193 "predicate_test": predicateTest}, 1194 ['IsSquashAfter']) 1195 header_output += ImmOpDeclare.subst(isbIop) 1196 decoder_output += ImmOpConstructor.subst(isbIop) 1197 exec_output += PredOpExecute.subst(isbIop) 1198 1199 dsbCode = ''' 1200 // If the barrier is due to a CP15 access check for hyp traps 1201 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr, 1202 Hdcr, Hstr, Hcptr, imm)) { 1203 return std::make_shared<HypervisorTrap>(machInst, imm, 1204 EC_TRAPPED_CP15_MCR_MRC); 1205 } 1206 ''' 1207 dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", 1208 {"code": dsbCode, 1209 "predicate_test": predicateTest}, 1210 ['IsMemBarrier', 'IsSerializeAfter']) 1211 header_output += ImmOpDeclare.subst(dsbIop) 1212 decoder_output += ImmOpConstructor.subst(dsbIop) 1213 exec_output += PredOpExecute.subst(dsbIop) 1214 1215 dmbCode = ''' 1216 // If the barrier is due to a CP15 access check for hyp traps 1217 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr, 1218 Hdcr, Hstr, Hcptr, imm)) { 1219 return std::make_shared<HypervisorTrap>(machInst, imm, 1220 EC_TRAPPED_CP15_MCR_MRC); 1221 } 1222 ''' 1223 dmbIop = InstObjParams("dmb", "Dmb", "ImmOp", 1224 {"code": dmbCode, 1225 "predicate_test": predicateTest}, 1226 ['IsMemBarrier']) 1227 header_output += ImmOpDeclare.subst(dmbIop) 1228 decoder_output += ImmOpConstructor.subst(dmbIop) 1229 exec_output += PredOpExecute.subst(dmbIop) 1230 1231 dbgCode = ''' 1232 ''' 1233 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 1234 {"code": dbgCode, 1235 "predicate_test": predicateTest}) 1236 header_output += BasicDeclare.subst(dbgIop) 1237 decoder_output += BasicConstructor.subst(dbgIop) 1238 exec_output += PredOpExecute.subst(dbgIop) 1239 1240 cpsCode = ''' 1241 uint32_t mode = bits(imm, 4, 0); 1242 uint32_t f = bits(imm, 5); 1243 uint32_t i = bits(imm, 6); 1244 uint32_t a = bits(imm, 7); 1245 bool setMode = bits(imm, 8); 1246 bool enable = bits(imm, 9); 1247 CPSR cpsr = Cpsr; 1248 SCTLR sctlr = Sctlr; 1249 if (cpsr.mode != MODE_USER) { 1250 if (enable) { 1251 if (f) cpsr.f = 0; 1252 if (i) cpsr.i = 0; 1253 if (a) cpsr.a = 0; 1254 } else { 1255 if (f && !sctlr.nmfi) cpsr.f = 1; 1256 if (i) cpsr.i = 1; 1257 if (a) cpsr.a = 1; 1258 } 1259 if (setMode) { 1260 cpsr.mode = mode; 1261 } 1262 } 1263 Cpsr = cpsr; 1264 ''' 1265 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 1266 { "code": cpsCode, 1267 "predicate_test": predicateTest }, 1268 ["IsSerializeAfter","IsNonSpeculative"]) 1269 header_output += ImmOpDeclare.subst(cpsIop) 1270 decoder_output += ImmOpConstructor.subst(cpsIop) 1271 exec_output += PredOpExecute.subst(cpsIop) 1272}}; 1273