misc.isa revision 8302
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 37199Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 437199Sgblack@eecs.umich.edu#if FULL_SYSTEM 447199Sgblack@eecs.umich.edu fault = new SupervisorCall; 457199Sgblack@eecs.umich.edu#else 467199Sgblack@eecs.umich.edu fault = new SupervisorCall(machInst); 477199Sgblack@eecs.umich.edu#endif 487199Sgblack@eecs.umich.edu ''' 497199Sgblack@eecs.umich.edu 507199Sgblack@eecs.umich.edu svcIop = InstObjParams("svc", "Svc", "PredOp", 517199Sgblack@eecs.umich.edu { "code": svcCode, 527199Sgblack@eecs.umich.edu "predicate_test": predicateTest }, ["IsSyscall"]) 537199Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(svcIop) 547199Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(svcIop) 557199Sgblack@eecs.umich.edu exec_output = PredOpExecute.subst(svcIop) 567199Sgblack@eecs.umich.edu 577199Sgblack@eecs.umich.edu}}; 587202Sgblack@eecs.umich.edu 597202Sgblack@eecs.umich.edulet {{ 607202Sgblack@eecs.umich.edu 617202Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 627202Sgblack@eecs.umich.edu 638301SAli.Saidi@ARM.com mrsCpsrCode = ''' 648302SAli.Saidi@ARM.com Dest = (Cpsr | CondCodesF | CondCodesGE) & 0xF8FF03DF 658301SAli.Saidi@ARM.com ''' 668301SAli.Saidi@ARM.com 677202Sgblack@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 687202Sgblack@eecs.umich.edu { "code": mrsCpsrCode, 697599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 707783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 717202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsCpsrIop) 727202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 737202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 747202Sgblack@eecs.umich.edu 757202Sgblack@eecs.umich.edu mrsSpsrCode = "Dest = Spsr" 767202Sgblack@eecs.umich.edu mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 777202Sgblack@eecs.umich.edu { "code": mrsSpsrCode, 787599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 797783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 807202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsSpsrIop) 817202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 827202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsSpsrIop) 837202Sgblack@eecs.umich.edu 847202Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 857400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 867202Sgblack@eecs.umich.edu uint32_t newCpsr = 878302SAli.Saidi@ARM.com cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Op1, 888301SAli.Saidi@ARM.com byteMask, false, sctlr.nmfi); 897202Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 908301SAli.Saidi@ARM.com CondCodesF = CondCodesMaskF & newCpsr; 918301SAli.Saidi@ARM.com CondCodesGE = CondCodesMaskGE & newCpsr; 927202Sgblack@eecs.umich.edu ''' 937202Sgblack@eecs.umich.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 947202Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 957599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 967599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 977202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrCpsrRegIop) 987202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 997202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrRegIop) 1007202Sgblack@eecs.umich.edu 1017202Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 1027202Sgblack@eecs.umich.edu msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 1037202Sgblack@eecs.umich.edu { "code": msrSpsrRegCode, 1047599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1057599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1067202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrSpsrRegIop) 1077202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 1087202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrRegIop) 1097202Sgblack@eecs.umich.edu 1107202Sgblack@eecs.umich.edu msrCpsrImmCode = ''' 1117400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 1127202Sgblack@eecs.umich.edu uint32_t newCpsr = 1138302SAli.Saidi@ARM.com cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm, 1148301SAli.Saidi@ARM.com byteMask, false, sctlr.nmfi); 1157202Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 1168301SAli.Saidi@ARM.com CondCodesF = CondCodesMaskF & newCpsr; 1178301SAli.Saidi@ARM.com CondCodesGE = CondCodesMaskGE & newCpsr; 1187202Sgblack@eecs.umich.edu ''' 1197202Sgblack@eecs.umich.edu msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 1207202Sgblack@eecs.umich.edu { "code": msrCpsrImmCode, 1217599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 1227599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1237202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrCpsrImmIop) 1247202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 1257202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrImmIop) 1267202Sgblack@eecs.umich.edu 1277202Sgblack@eecs.umich.edu msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 1287202Sgblack@eecs.umich.edu msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 1297202Sgblack@eecs.umich.edu { "code": msrSpsrImmCode, 1307599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1317599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1327202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrSpsrImmIop) 1337202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 1347202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrImmIop) 1357209Sgblack@eecs.umich.edu 1367209Sgblack@eecs.umich.edu revCode = ''' 1377209Sgblack@eecs.umich.edu uint32_t val = Op1; 1387209Sgblack@eecs.umich.edu Dest = swap_byte(val); 1397209Sgblack@eecs.umich.edu ''' 1407261Sgblack@eecs.umich.edu revIop = InstObjParams("rev", "Rev", "RegRegOp", 1417209Sgblack@eecs.umich.edu { "code": revCode, 1427209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1437261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revIop) 1447261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revIop) 1457209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revIop) 1467209Sgblack@eecs.umich.edu 1477209Sgblack@eecs.umich.edu rev16Code = ''' 1487209Sgblack@eecs.umich.edu uint32_t val = Op1; 1497209Sgblack@eecs.umich.edu Dest = (bits(val, 15, 8) << 0) | 1507209Sgblack@eecs.umich.edu (bits(val, 7, 0) << 8) | 1517209Sgblack@eecs.umich.edu (bits(val, 31, 24) << 16) | 1527209Sgblack@eecs.umich.edu (bits(val, 23, 16) << 24); 1537209Sgblack@eecs.umich.edu ''' 1547261Sgblack@eecs.umich.edu rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 1557209Sgblack@eecs.umich.edu { "code": rev16Code, 1567209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1577261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rev16Iop) 1587261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rev16Iop) 1597209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rev16Iop) 1607209Sgblack@eecs.umich.edu 1617209Sgblack@eecs.umich.edu revshCode = ''' 1627209Sgblack@eecs.umich.edu uint16_t val = Op1; 1637209Sgblack@eecs.umich.edu Dest = sext<16>(swap_byte(val)); 1647209Sgblack@eecs.umich.edu ''' 1657261Sgblack@eecs.umich.edu revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 1667209Sgblack@eecs.umich.edu { "code": revshCode, 1677209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1687261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revshIop) 1697261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revshIop) 1707209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revshIop) 1717226Sgblack@eecs.umich.edu 1727249Sgblack@eecs.umich.edu rbitCode = ''' 1737249Sgblack@eecs.umich.edu uint8_t *opBytes = (uint8_t *)&Op1; 1747249Sgblack@eecs.umich.edu uint32_t resTemp; 1757249Sgblack@eecs.umich.edu uint8_t *destBytes = (uint8_t *)&resTemp; 1767249Sgblack@eecs.umich.edu // This reverses the bytes and bits of the input, or so says the 1777249Sgblack@eecs.umich.edu // internet. 1787249Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 1797249Sgblack@eecs.umich.edu uint32_t temp = opBytes[i]; 1807249Sgblack@eecs.umich.edu temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 1817249Sgblack@eecs.umich.edu destBytes[3 - i] = (temp * 0x10101) >> 16; 1827249Sgblack@eecs.umich.edu } 1837249Sgblack@eecs.umich.edu Dest = resTemp; 1847249Sgblack@eecs.umich.edu ''' 1857261Sgblack@eecs.umich.edu rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 1867249Sgblack@eecs.umich.edu { "code": rbitCode, 1877249Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1887261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rbitIop) 1897261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rbitIop) 1907249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rbitIop) 1917249Sgblack@eecs.umich.edu 1927251Sgblack@eecs.umich.edu clzCode = ''' 1937251Sgblack@eecs.umich.edu Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 1947251Sgblack@eecs.umich.edu ''' 1957261Sgblack@eecs.umich.edu clzIop = InstObjParams("clz", "Clz", "RegRegOp", 1967251Sgblack@eecs.umich.edu { "code": clzCode, 1977251Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1987261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(clzIop) 1997261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(clzIop) 2007251Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clzIop) 2017251Sgblack@eecs.umich.edu 2027226Sgblack@eecs.umich.edu ssatCode = ''' 2037226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2047226Sgblack@eecs.umich.edu int32_t res; 2057232Sgblack@eecs.umich.edu if (satInt(res, operand, imm)) 2068302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2077226Sgblack@eecs.umich.edu Dest = res; 2087226Sgblack@eecs.umich.edu ''' 2097232Sgblack@eecs.umich.edu ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 2107226Sgblack@eecs.umich.edu { "code": ssatCode, 2117422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2127232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 2137232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 2147226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssatIop) 2157226Sgblack@eecs.umich.edu 2167226Sgblack@eecs.umich.edu usatCode = ''' 2177226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2187226Sgblack@eecs.umich.edu int32_t res; 2197232Sgblack@eecs.umich.edu if (uSatInt(res, operand, imm)) 2208302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2217226Sgblack@eecs.umich.edu Dest = res; 2227226Sgblack@eecs.umich.edu ''' 2237232Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 2247226Sgblack@eecs.umich.edu { "code": usatCode, 2257422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2267232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(usatIop) 2277232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 2287226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usatIop) 2297226Sgblack@eecs.umich.edu 2307226Sgblack@eecs.umich.edu ssat16Code = ''' 2317226Sgblack@eecs.umich.edu int32_t res; 2327226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2337226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2347226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2357232Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 2368302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2377226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2387232Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 2398302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2407226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2417226Sgblack@eecs.umich.edu Dest = resTemp; 2427226Sgblack@eecs.umich.edu ''' 2437232Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 2447226Sgblack@eecs.umich.edu { "code": ssat16Code, 2457422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2467232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(ssat16Iop) 2477232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 2487226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssat16Iop) 2497226Sgblack@eecs.umich.edu 2507226Sgblack@eecs.umich.edu usat16Code = ''' 2517226Sgblack@eecs.umich.edu int32_t res; 2527226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2537226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2547226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2557232Sgblack@eecs.umich.edu if (uSatInt(res, argLow, imm)) 2568302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2577226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2587232Sgblack@eecs.umich.edu if (uSatInt(res, argHigh, imm)) 2598302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2607226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2617226Sgblack@eecs.umich.edu Dest = resTemp; 2627226Sgblack@eecs.umich.edu ''' 2637232Sgblack@eecs.umich.edu usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 2647226Sgblack@eecs.umich.edu { "code": usat16Code, 2657422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2667232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(usat16Iop) 2677232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 2687226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usat16Iop) 2697234Sgblack@eecs.umich.edu 2707234Sgblack@eecs.umich.edu sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 2717234Sgblack@eecs.umich.edu { "code": 2727234Sgblack@eecs.umich.edu "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 2737234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2747234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtbIop) 2757234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 2767234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtbIop) 2777234Sgblack@eecs.umich.edu 2787234Sgblack@eecs.umich.edu sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 2797234Sgblack@eecs.umich.edu { "code": 2807234Sgblack@eecs.umich.edu ''' 2817234Sgblack@eecs.umich.edu Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 2827234Sgblack@eecs.umich.edu Op1; 2837234Sgblack@eecs.umich.edu ''', 2847234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2857234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 2867234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 2877234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtabIop) 2887234Sgblack@eecs.umich.edu 2897234Sgblack@eecs.umich.edu sxtb16Code = ''' 2907234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2917234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 2927234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 2937234Sgblack@eecs.umich.edu sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 2947234Sgblack@eecs.umich.edu Dest = resTemp; 2957234Sgblack@eecs.umich.edu ''' 2967234Sgblack@eecs.umich.edu sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 2977234Sgblack@eecs.umich.edu { "code": sxtb16Code, 2987234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2997234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 3007234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 3017234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtb16Iop) 3027234Sgblack@eecs.umich.edu 3037234Sgblack@eecs.umich.edu sxtab16Code = ''' 3047234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3057234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 3067234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3077234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3087234Sgblack@eecs.umich.edu sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3097234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3107234Sgblack@eecs.umich.edu Dest = resTemp; 3117234Sgblack@eecs.umich.edu ''' 3127234Sgblack@eecs.umich.edu sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 3137234Sgblack@eecs.umich.edu { "code": sxtab16Code, 3147234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3157234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 3167234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 3177234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtab16Iop) 3187234Sgblack@eecs.umich.edu 3197234Sgblack@eecs.umich.edu sxthCode = ''' 3207234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 3217234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3227234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 3237234Sgblack@eecs.umich.edu ''' 3247234Sgblack@eecs.umich.edu sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 3257234Sgblack@eecs.umich.edu { "code": sxthCode, 3267234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3277234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 3287234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 3297234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 3307234Sgblack@eecs.umich.edu 3317234Sgblack@eecs.umich.edu sxtahCode = ''' 3327234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 3337234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3347234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated) + Op1; 3357234Sgblack@eecs.umich.edu ''' 3367234Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 3377234Sgblack@eecs.umich.edu { "code": sxtahCode, 3387234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3397234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 3407234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 3417234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtahIop) 3427234Sgblack@eecs.umich.edu 3437234Sgblack@eecs.umich.edu uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 3447234Sgblack@eecs.umich.edu { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 3457234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3467234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtbIop) 3477234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 3487234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtbIop) 3497234Sgblack@eecs.umich.edu 3507234Sgblack@eecs.umich.edu uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 3517234Sgblack@eecs.umich.edu { "code": 3527234Sgblack@eecs.umich.edu "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 3537234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3547234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 3557234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 3567234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 3577234Sgblack@eecs.umich.edu 3587234Sgblack@eecs.umich.edu uxtb16Code = ''' 3597234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3607234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 3617234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3627234Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 3637234Sgblack@eecs.umich.edu Dest = resTemp; 3647234Sgblack@eecs.umich.edu ''' 3657234Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 3667234Sgblack@eecs.umich.edu { "code": uxtb16Code, 3677234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3687234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 3697234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 3707234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtb16Iop) 3717234Sgblack@eecs.umich.edu 3727234Sgblack@eecs.umich.edu uxtab16Code = ''' 3737234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3747234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 3757234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3767234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3777234Sgblack@eecs.umich.edu (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3787234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3797234Sgblack@eecs.umich.edu Dest = resTemp; 3807234Sgblack@eecs.umich.edu ''' 3817234Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 3827234Sgblack@eecs.umich.edu { "code": uxtab16Code, 3837234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3847234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 3857234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 3867234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 3877234Sgblack@eecs.umich.edu 3887234Sgblack@eecs.umich.edu uxthCode = ''' 3897234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 3907234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3917234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated; 3927234Sgblack@eecs.umich.edu ''' 3937234Sgblack@eecs.umich.edu uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 3947234Sgblack@eecs.umich.edu { "code": uxthCode, 3957234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3967234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxthIop) 3977234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxthIop) 3987234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxthIop) 3997234Sgblack@eecs.umich.edu 4007234Sgblack@eecs.umich.edu uxtahCode = ''' 4017234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 4027234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4037234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 4047234Sgblack@eecs.umich.edu ''' 4057234Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 4067234Sgblack@eecs.umich.edu { "code": uxtahCode, 4077234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4087234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 4097234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 4107234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 4117239Sgblack@eecs.umich.edu 4127239Sgblack@eecs.umich.edu selCode = ''' 4137239Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4147239Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4157239Sgblack@eecs.umich.edu int low = i * 8; 4167239Sgblack@eecs.umich.edu int high = low + 7; 4177239Sgblack@eecs.umich.edu replaceBits(resTemp, high, low, 4188301SAli.Saidi@ARM.com bits(CondCodesGE, 16 + i) ? 4197239Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 4207239Sgblack@eecs.umich.edu } 4217239Sgblack@eecs.umich.edu Dest = resTemp; 4227239Sgblack@eecs.umich.edu ''' 4237239Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 4247239Sgblack@eecs.umich.edu { "code": selCode, 4257422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 4267239Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 4277239Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 4287239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 4297242Sgblack@eecs.umich.edu 4307242Sgblack@eecs.umich.edu usad8Code = ''' 4317242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4327242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4337242Sgblack@eecs.umich.edu int low = i * 8; 4347242Sgblack@eecs.umich.edu int high = low + 7; 4357242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4367242Sgblack@eecs.umich.edu bits(Op2, high, low); 4377242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4387242Sgblack@eecs.umich.edu } 4397242Sgblack@eecs.umich.edu Dest = resTemp; 4407242Sgblack@eecs.umich.edu ''' 4417242Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 4427242Sgblack@eecs.umich.edu { "code": usad8Code, 4437242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4447242Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 4457242Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 4467242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usad8Iop) 4477242Sgblack@eecs.umich.edu 4487242Sgblack@eecs.umich.edu usada8Code = ''' 4497242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4507242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4517242Sgblack@eecs.umich.edu int low = i * 8; 4527242Sgblack@eecs.umich.edu int high = low + 7; 4537242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4547242Sgblack@eecs.umich.edu bits(Op2, high, low); 4557242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4567242Sgblack@eecs.umich.edu } 4577242Sgblack@eecs.umich.edu Dest = Op3 + resTemp; 4587242Sgblack@eecs.umich.edu ''' 4597242Sgblack@eecs.umich.edu usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 4607242Sgblack@eecs.umich.edu { "code": usada8Code, 4617242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4627242Sgblack@eecs.umich.edu header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 4637242Sgblack@eecs.umich.edu decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 4647242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usada8Iop) 4657247Sgblack@eecs.umich.edu 4667797Sgblack@eecs.umich.edu bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 4677848SAli.Saidi@ARM.com bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 4687410Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(bkptIop) 4697410Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(bkptIop) 4707410Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(bkptIop) 4717410Sgblack@eecs.umich.edu 4727408Sgblack@eecs.umich.edu nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 4738065SAli.Saidi@ARM.com { "code" : "", "predicate_test" : predicateTest }, 4748065SAli.Saidi@ARM.com ['IsNop']) 4757247Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(nopIop) 4767247Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(nopIop) 4777408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(nopIop) 4787408Sgblack@eecs.umich.edu 4797418Sgblack@eecs.umich.edu yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 4807418Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 4817418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(yieldIop) 4827418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(yieldIop) 4837418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(yieldIop) 4847418Sgblack@eecs.umich.edu 4857418Sgblack@eecs.umich.edu wfeCode = ''' 4867418Sgblack@eecs.umich.edu#if FULL_SYSTEM 4878285SPrakash.Ramrakhyani@arm.com if (SevMailbox == 1) { 4887418Sgblack@eecs.umich.edu SevMailbox = 0; 4898142SAli.Saidi@ARM.com PseudoInst::quiesceSkip(xc->tcBase()); 4908285SPrakash.Ramrakhyani@arm.com } else { 4917418Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 4928142SAli.Saidi@ARM.com } 4937418Sgblack@eecs.umich.edu#endif 4947418Sgblack@eecs.umich.edu ''' 4957418Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 4967418Sgblack@eecs.umich.edu { "code" : wfeCode, "predicate_test" : predicateTest }, 4977648SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 4987418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 4997418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfeIop) 5008142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(wfeIop) 5017418Sgblack@eecs.umich.edu 5027418Sgblack@eecs.umich.edu wfiCode = ''' 5037418Sgblack@eecs.umich.edu#if FULL_SYSTEM 5048285SPrakash.Ramrakhyani@arm.com // WFI doesn't sleep if interrupts are pending (masked or not) 5058285SPrakash.Ramrakhyani@arm.com if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) { 5068285SPrakash.Ramrakhyani@arm.com PseudoInst::quiesceSkip(xc->tcBase()); 5078285SPrakash.Ramrakhyani@arm.com } else { 5088285SPrakash.Ramrakhyani@arm.com PseudoInst::quiesce(xc->tcBase()); 5098285SPrakash.Ramrakhyani@arm.com } 5107418Sgblack@eecs.umich.edu#endif 5117418Sgblack@eecs.umich.edu ''' 5127418Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 5137418Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 5148142SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 5157418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfiIop) 5167418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfiIop) 5178142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(wfiIop) 5187418Sgblack@eecs.umich.edu 5197418Sgblack@eecs.umich.edu sevCode = ''' 5207418Sgblack@eecs.umich.edu // Need a way for O3 to not scoreboard these accesses as pipe flushes. 5218142SAli.Saidi@ARM.com SevMailbox = 1; 5227418Sgblack@eecs.umich.edu System *sys = xc->tcBase()->getSystemPtr(); 5237418Sgblack@eecs.umich.edu for (int x = 0; x < sys->numContexts(); x++) { 5247418Sgblack@eecs.umich.edu ThreadContext *oc = sys->getThreadContext(x); 5258285SPrakash.Ramrakhyani@arm.com if (oc == xc->tcBase()) 5268285SPrakash.Ramrakhyani@arm.com continue; 5278285SPrakash.Ramrakhyani@arm.com // Only wake if they were sleeping 5288285SPrakash.Ramrakhyani@arm.com if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 5298142SAli.Saidi@ARM.com oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5308285SPrakash.Ramrakhyani@arm.com PseudoInst::wakeCPU(xc->tcBase(), x); 5318142SAli.Saidi@ARM.com } 5327418Sgblack@eecs.umich.edu } 5337418Sgblack@eecs.umich.edu ''' 5347418Sgblack@eecs.umich.edu sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 5357418Sgblack@eecs.umich.edu { "code" : sevCode, "predicate_test" : predicateTest }, 5368142SAli.Saidi@ARM.com ["IsNonSpeculative", "IsSquashAfter"]) 5377418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sevIop) 5387418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sevIop) 5397418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sevIop) 5407418Sgblack@eecs.umich.edu 5417408Sgblack@eecs.umich.edu itIop = InstObjParams("it", "ItInst", "PredOp", \ 5428205SAli.Saidi@ARM.com { "code" : ";", 5437648SAli.Saidi@ARM.com "predicate_test" : predicateTest }, 5447648SAli.Saidi@ARM.com ["IsNonSpeculative", "IsSerializeAfter"]) 5457408Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(itIop) 5467408Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(itIop) 5477408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(itIop) 5487409Sgblack@eecs.umich.edu unknownCode = ''' 5497409Sgblack@eecs.umich.edu#if FULL_SYSTEM 5507409Sgblack@eecs.umich.edu return new UndefinedInstruction; 5517409Sgblack@eecs.umich.edu#else 5527409Sgblack@eecs.umich.edu return new UndefinedInstruction(machInst, true); 5537409Sgblack@eecs.umich.edu#endif 5547409Sgblack@eecs.umich.edu ''' 5557409Sgblack@eecs.umich.edu unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 5567409Sgblack@eecs.umich.edu { "code": unknownCode, 5577409Sgblack@eecs.umich.edu "predicate_test": predicateTest }) 5587409Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(unknownIop) 5597409Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(unknownIop) 5607409Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(unknownIop) 5617254Sgblack@eecs.umich.edu 5627254Sgblack@eecs.umich.edu ubfxCode = ''' 5637254Sgblack@eecs.umich.edu Dest = bits(Op1, imm2, imm1); 5647254Sgblack@eecs.umich.edu ''' 5657254Sgblack@eecs.umich.edu ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 5667254Sgblack@eecs.umich.edu { "code": ubfxCode, 5677254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5687254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 5697254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 5707254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ubfxIop) 5717254Sgblack@eecs.umich.edu 5727254Sgblack@eecs.umich.edu sbfxCode = ''' 5737254Sgblack@eecs.umich.edu int32_t resTemp = bits(Op1, imm2, imm1); 5747254Sgblack@eecs.umich.edu Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 5757254Sgblack@eecs.umich.edu ''' 5767254Sgblack@eecs.umich.edu sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 5777254Sgblack@eecs.umich.edu { "code": sbfxCode, 5787254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5797254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 5807254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 5817254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sbfxIop) 5827257Sgblack@eecs.umich.edu 5837257Sgblack@eecs.umich.edu bfcCode = ''' 5847257Sgblack@eecs.umich.edu Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 5857257Sgblack@eecs.umich.edu ''' 5867257Sgblack@eecs.umich.edu bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 5877257Sgblack@eecs.umich.edu { "code": bfcCode, 5887257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5897257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfcIop) 5907257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 5917257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfcIop) 5927257Sgblack@eecs.umich.edu 5937257Sgblack@eecs.umich.edu bfiCode = ''' 5947257Sgblack@eecs.umich.edu uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 5957257Sgblack@eecs.umich.edu Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 5967257Sgblack@eecs.umich.edu ''' 5977257Sgblack@eecs.umich.edu bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 5987257Sgblack@eecs.umich.edu { "code": bfiCode, 5997257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6007257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfiIop) 6017257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 6027257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfiIop) 6037262Sgblack@eecs.umich.edu 6047347SAli.Saidi@ARM.com mrc15code = ''' 6057347SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 6067347SAli.Saidi@ARM.com if (cpsr.mode == MODE_USER) 6077347SAli.Saidi@ARM.com#if FULL_SYSTEM 6087347SAli.Saidi@ARM.com return new UndefinedInstruction; 6097347SAli.Saidi@ARM.com#else 6107347SAli.Saidi@ARM.com return new UndefinedInstruction(false, mnemonic); 6117347SAli.Saidi@ARM.com#endif 6127347SAli.Saidi@ARM.com Dest = MiscOp1; 6137347SAli.Saidi@ARM.com ''' 6147347SAli.Saidi@ARM.com 6157262Sgblack@eecs.umich.edu mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 6167347SAli.Saidi@ARM.com { "code": mrc15code, 6177262Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6187262Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15Iop) 6197262Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15Iop) 6207262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15Iop) 6217262Sgblack@eecs.umich.edu 6227347SAli.Saidi@ARM.com 6237347SAli.Saidi@ARM.com mcr15code = ''' 6247347SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 6257347SAli.Saidi@ARM.com if (cpsr.mode == MODE_USER) 6267347SAli.Saidi@ARM.com#if FULL_SYSTEM 6277347SAli.Saidi@ARM.com return new UndefinedInstruction; 6287347SAli.Saidi@ARM.com#else 6297347SAli.Saidi@ARM.com return new UndefinedInstruction(false, mnemonic); 6307347SAli.Saidi@ARM.com#endif 6317347SAli.Saidi@ARM.com MiscDest = Op1; 6327347SAli.Saidi@ARM.com ''' 6337262Sgblack@eecs.umich.edu mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 6347347SAli.Saidi@ARM.com { "code": mcr15code, 6357599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 6367599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 6377262Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15Iop) 6387262Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15Iop) 6397262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15Iop) 6407283Sgblack@eecs.umich.edu 6417420Sgblack@eecs.umich.edu mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 6427420Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 6437420Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6447420Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15UserIop) 6457420Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 6467420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15UserIop) 6477420Sgblack@eecs.umich.edu 6487420Sgblack@eecs.umich.edu mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 6497420Sgblack@eecs.umich.edu { "code": "MiscDest = Op1", 6507599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 6517599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 6527420Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15UserIop) 6537420Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 6547420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15UserIop) 6557420Sgblack@eecs.umich.edu 6567283Sgblack@eecs.umich.edu enterxCode = ''' 6577797Sgblack@eecs.umich.edu NextThumb = true; 6587797Sgblack@eecs.umich.edu NextJazelle = true; 6597283Sgblack@eecs.umich.edu ''' 6607283Sgblack@eecs.umich.edu enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 6617283Sgblack@eecs.umich.edu { "code": enterxCode, 6627283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6637283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(enterxIop) 6647283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(enterxIop) 6657283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(enterxIop) 6667283Sgblack@eecs.umich.edu 6677283Sgblack@eecs.umich.edu leavexCode = ''' 6687797Sgblack@eecs.umich.edu NextThumb = true; 6697797Sgblack@eecs.umich.edu NextJazelle = false; 6707283Sgblack@eecs.umich.edu ''' 6717283Sgblack@eecs.umich.edu leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 6727283Sgblack@eecs.umich.edu { "code": leavexCode, 6737283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6747283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(leavexIop) 6757283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(leavexIop) 6767283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(leavexIop) 6777307Sgblack@eecs.umich.edu 6787307Sgblack@eecs.umich.edu setendCode = ''' 6797307Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 6807307Sgblack@eecs.umich.edu cpsr.e = imm; 6817307Sgblack@eecs.umich.edu Cpsr = cpsr; 6827307Sgblack@eecs.umich.edu ''' 6837307Sgblack@eecs.umich.edu setendIop = InstObjParams("setend", "Setend", "ImmOp", 6847307Sgblack@eecs.umich.edu { "code": setendCode, 6857648SAli.Saidi@ARM.com "predicate_test": predicateTest }, 6867648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 6877307Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(setendIop) 6887307Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(setendIop) 6897307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(setendIop) 6907315Sgblack@eecs.umich.edu 6917603SGene.Wu@arm.com clrexCode = ''' 6928209SAli.Saidi@ARM.com LLSCLock = 0; 6937603SGene.Wu@arm.com ''' 6947603SGene.Wu@arm.com clrexIop = InstObjParams("clrex", "Clrex","PredOp", 6957603SGene.Wu@arm.com { "code": clrexCode, 6967603SGene.Wu@arm.com "predicate_test": predicateTest },[]) 6978209SAli.Saidi@ARM.com header_output += BasicDeclare.subst(clrexIop) 6987603SGene.Wu@arm.com decoder_output += BasicConstructor.subst(clrexIop) 6997603SGene.Wu@arm.com exec_output += PredOpExecute.subst(clrexIop) 7007603SGene.Wu@arm.com 7017605SGene.Wu@arm.com isbCode = ''' 7028068SAli.Saidi@ARM.com fault = new FlushPipe; 7037605SGene.Wu@arm.com ''' 7047605SGene.Wu@arm.com isbIop = InstObjParams("isb", "Isb", "PredOp", 7057605SGene.Wu@arm.com {"code": isbCode, 7068068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 7078068SAli.Saidi@ARM.com ['IsSerializeAfter']) 7087605SGene.Wu@arm.com header_output += BasicDeclare.subst(isbIop) 7097605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(isbIop) 7107605SGene.Wu@arm.com exec_output += PredOpExecute.subst(isbIop) 7117605SGene.Wu@arm.com 7127605SGene.Wu@arm.com dsbCode = ''' 7138068SAli.Saidi@ARM.com fault = new FlushPipe; 7147605SGene.Wu@arm.com ''' 7157605SGene.Wu@arm.com dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 7167605SGene.Wu@arm.com {"code": dsbCode, 7178068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 7188068SAli.Saidi@ARM.com ['IsMemBarrier', 'IsSerializeAfter']) 7197605SGene.Wu@arm.com header_output += BasicDeclare.subst(dsbIop) 7207605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dsbIop) 7217605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dsbIop) 7227605SGene.Wu@arm.com 7237605SGene.Wu@arm.com dmbCode = ''' 7247605SGene.Wu@arm.com ''' 7257605SGene.Wu@arm.com dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 7267605SGene.Wu@arm.com {"code": dmbCode, 7278068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 7288068SAli.Saidi@ARM.com ['IsMemBarrier']) 7297605SGene.Wu@arm.com header_output += BasicDeclare.subst(dmbIop) 7307605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dmbIop) 7317605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dmbIop) 7327605SGene.Wu@arm.com 7337613SGene.Wu@arm.com dbgCode = ''' 7347613SGene.Wu@arm.com ''' 7357613SGene.Wu@arm.com dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 7367613SGene.Wu@arm.com {"code": dbgCode, 7377613SGene.Wu@arm.com "predicate_test": predicateTest}) 7387613SGene.Wu@arm.com header_output += BasicDeclare.subst(dbgIop) 7397613SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dbgIop) 7407613SGene.Wu@arm.com exec_output += PredOpExecute.subst(dbgIop) 7417613SGene.Wu@arm.com 7427315Sgblack@eecs.umich.edu cpsCode = ''' 7437315Sgblack@eecs.umich.edu uint32_t mode = bits(imm, 4, 0); 7447315Sgblack@eecs.umich.edu uint32_t f = bits(imm, 5); 7457315Sgblack@eecs.umich.edu uint32_t i = bits(imm, 6); 7467315Sgblack@eecs.umich.edu uint32_t a = bits(imm, 7); 7477315Sgblack@eecs.umich.edu bool setMode = bits(imm, 8); 7487315Sgblack@eecs.umich.edu bool enable = bits(imm, 9); 7497315Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 7507400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 7517315Sgblack@eecs.umich.edu if (cpsr.mode != MODE_USER) { 7527315Sgblack@eecs.umich.edu if (enable) { 7537315Sgblack@eecs.umich.edu if (f) cpsr.f = 0; 7547315Sgblack@eecs.umich.edu if (i) cpsr.i = 0; 7557315Sgblack@eecs.umich.edu if (a) cpsr.a = 0; 7567315Sgblack@eecs.umich.edu } else { 7577400SAli.Saidi@ARM.com if (f && !sctlr.nmfi) cpsr.f = 1; 7587315Sgblack@eecs.umich.edu if (i) cpsr.i = 1; 7597315Sgblack@eecs.umich.edu if (a) cpsr.a = 1; 7607315Sgblack@eecs.umich.edu } 7617315Sgblack@eecs.umich.edu if (setMode) { 7627315Sgblack@eecs.umich.edu cpsr.mode = mode; 7637315Sgblack@eecs.umich.edu } 7647315Sgblack@eecs.umich.edu } 7657315Sgblack@eecs.umich.edu Cpsr = cpsr; 7667315Sgblack@eecs.umich.edu ''' 7677315Sgblack@eecs.umich.edu cpsIop = InstObjParams("cps", "Cps", "ImmOp", 7687315Sgblack@eecs.umich.edu { "code": cpsCode, 7697599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 7707599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 7717315Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(cpsIop) 7727315Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(cpsIop) 7737315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(cpsIop) 7747202Sgblack@eecs.umich.edu}}; 775