misc.isa revision 8285
17584SN/A// -*- mode:c++ -*- 28869SAli.Saidi@ARM.com 37584SN/A// Copyright (c) 2010 ARM Limited 47584SN/A// All rights reserved 57584SN/A// 67584SN/A// The license below extends only to copyright in the software and shall 77584SN/A// not be construed as granting a license to any other intellectual 87584SN/A// property including but not limited to intellectual property relating 97584SN/A// to a hardware implementation of the functionality of the software 107584SN/A// licensed hereunder. You may use the software subject to the license 117584SN/A// terms below provided that you ensure that this notice is replicated 127584SN/A// unmodified and in its entirety in all distributions of the software, 137584SN/A// modified or unmodified, in source code or in binary form. 147584SN/A// 157584SN/A// Redistribution and use in source and binary forms, with or without 167584SN/A// modification, are permitted provided that the following conditions are 177584SN/A// met: redistributions of source code must retain the above copyright 187584SN/A// notice, this list of conditions and the following disclaimer; 197584SN/A// redistributions in binary form must reproduce the above copyright 207584SN/A// notice, this list of conditions and the following disclaimer in the 217584SN/A// documentation and/or other materials provided with the distribution; 227584SN/A// neither the name of the copyright holders nor the names of its 237584SN/A// contributors may be used to endorse or promote products derived from 247584SN/A// this software without specific prior written permission. 257584SN/A// 267584SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277584SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287584SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297584SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307584SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317584SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327584SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337584SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347584SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357584SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367584SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377584SN/A// 387584SN/A// Authors: Gabe Black 397584SN/A 407584SN/Alet {{ 418869SAli.Saidi@ARM.com 427584SN/A svcCode = ''' 438245SN/A#if FULL_SYSTEM 448245SN/A fault = new SupervisorCall; 458869SAli.Saidi@ARM.com#else 468869SAli.Saidi@ARM.com fault = new SupervisorCall(machInst); 477584SN/A#endif 487584SN/A ''' 497584SN/A 508869SAli.Saidi@ARM.com svcIop = InstObjParams("svc", "Svc", "PredOp", 519808Sstever@gmail.com { "code": svcCode, 529808Sstever@gmail.com "predicate_test": predicateTest }, ["IsSyscall"]) 539808Sstever@gmail.com header_output = BasicDeclare.subst(svcIop) 547584SN/A decoder_output = BasicConstructor.subst(svcIop) 557584SN/A exec_output = PredOpExecute.subst(svcIop) 567584SN/A 577584SN/A}}; 587584SN/A 598869SAli.Saidi@ARM.comlet {{ 607584SN/A 617584SN/A header_output = decoder_output = exec_output = "" 627584SN/A 637584SN/A mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF" 648869SAli.Saidi@ARM.com mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 657584SN/A { "code": mrsCpsrCode, 668869SAli.Saidi@ARM.com "predicate_test": condPredicateTest }, 678869SAli.Saidi@ARM.com ["IsSerializeBefore"]) 688869SAli.Saidi@ARM.com header_output += MrsDeclare.subst(mrsCpsrIop) 698869SAli.Saidi@ARM.com decoder_output += MrsConstructor.subst(mrsCpsrIop) 708869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(mrsCpsrIop) 718869SAli.Saidi@ARM.com 728869SAli.Saidi@ARM.com mrsSpsrCode = "Dest = Spsr" 738869SAli.Saidi@ARM.com mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 748869SAli.Saidi@ARM.com { "code": mrsSpsrCode, 758869SAli.Saidi@ARM.com "predicate_test": predicateTest }, 768869SAli.Saidi@ARM.com ["IsSerializeBefore"]) 778869SAli.Saidi@ARM.com header_output += MrsDeclare.subst(mrsSpsrIop) 788869SAli.Saidi@ARM.com decoder_output += MrsConstructor.subst(mrsSpsrIop) 798869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(mrsSpsrIop) 808869SAli.Saidi@ARM.com 818869SAli.Saidi@ARM.com msrCpsrRegCode = ''' 828869SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 838869SAli.Saidi@ARM.com uint32_t newCpsr = 848869SAli.Saidi@ARM.com cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); 858869SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & newCpsr; 868869SAli.Saidi@ARM.com CondCodes = CondCodesMask & newCpsr; 878869SAli.Saidi@ARM.com ''' 888869SAli.Saidi@ARM.com msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 898869SAli.Saidi@ARM.com { "code": msrCpsrRegCode, 908869SAli.Saidi@ARM.com "predicate_test": condPredicateTest }, 919806Sstever@gmail.com ["IsSerializeAfter","IsNonSpeculative"]) 928869SAli.Saidi@ARM.com header_output += MsrRegDeclare.subst(msrCpsrRegIop) 938869SAli.Saidi@ARM.com decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 948869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(msrCpsrRegIop) 958869SAli.Saidi@ARM.com 968869SAli.Saidi@ARM.com msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 978869SAli.Saidi@ARM.com msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 988869SAli.Saidi@ARM.com { "code": msrSpsrRegCode, 998869SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1008869SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 1018869SAli.Saidi@ARM.com header_output += MsrRegDeclare.subst(msrSpsrRegIop) 1028869SAli.Saidi@ARM.com decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 1038869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(msrSpsrRegIop) 1048869SAli.Saidi@ARM.com 1058869SAli.Saidi@ARM.com msrCpsrImmCode = ''' 1068869SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 1078869SAli.Saidi@ARM.com uint32_t newCpsr = 1088869SAli.Saidi@ARM.com cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); 1098869SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & newCpsr; 1108869SAli.Saidi@ARM.com CondCodes = CondCodesMask & newCpsr; 1118869SAli.Saidi@ARM.com ''' 1128869SAli.Saidi@ARM.com msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 1138869SAli.Saidi@ARM.com { "code": msrCpsrImmCode, 1148869SAli.Saidi@ARM.com "predicate_test": condPredicateTest }, 1158869SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 1167584SN/A header_output += MsrImmDeclare.subst(msrCpsrImmIop) 1177584SN/A decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 1187584SN/A exec_output += PredOpExecute.subst(msrCpsrImmIop) 1197584SN/A 1207584SN/A msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 1218869SAli.Saidi@ARM.com msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 1227584SN/A { "code": msrSpsrImmCode, 1237584SN/A "predicate_test": predicateTest }, 1247584SN/A ["IsSerializeAfter","IsNonSpeculative"]) 1257584SN/A header_output += MsrImmDeclare.subst(msrSpsrImmIop) 1268869SAli.Saidi@ARM.com decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 1277584SN/A exec_output += PredOpExecute.subst(msrSpsrImmIop) 1288869SAli.Saidi@ARM.com 1298869SAli.Saidi@ARM.com revCode = ''' 1308869SAli.Saidi@ARM.com uint32_t val = Op1; 1318869SAli.Saidi@ARM.com Dest = swap_byte(val); 1328869SAli.Saidi@ARM.com ''' 1338869SAli.Saidi@ARM.com revIop = InstObjParams("rev", "Rev", "RegRegOp", 1348869SAli.Saidi@ARM.com { "code": revCode, 1358869SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 1368869SAli.Saidi@ARM.com header_output += RegRegOpDeclare.subst(revIop) 1378869SAli.Saidi@ARM.com decoder_output += RegRegOpConstructor.subst(revIop) 1388869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(revIop) 1398869SAli.Saidi@ARM.com 1408869SAli.Saidi@ARM.com rev16Code = ''' 1418869SAli.Saidi@ARM.com uint32_t val = Op1; 1428869SAli.Saidi@ARM.com Dest = (bits(val, 15, 8) << 0) | 1438869SAli.Saidi@ARM.com (bits(val, 7, 0) << 8) | 1448869SAli.Saidi@ARM.com (bits(val, 31, 24) << 16) | 1458869SAli.Saidi@ARM.com (bits(val, 23, 16) << 24); 1468869SAli.Saidi@ARM.com ''' 1478869SAli.Saidi@ARM.com rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 1488869SAli.Saidi@ARM.com { "code": rev16Code, 1498869SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 1508869SAli.Saidi@ARM.com header_output += RegRegOpDeclare.subst(rev16Iop) 1518869SAli.Saidi@ARM.com decoder_output += RegRegOpConstructor.subst(rev16Iop) 1528869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(rev16Iop) 1539806Sstever@gmail.com 1548869SAli.Saidi@ARM.com revshCode = ''' 1558869SAli.Saidi@ARM.com uint16_t val = Op1; 1568869SAli.Saidi@ARM.com Dest = sext<16>(swap_byte(val)); 1578869SAli.Saidi@ARM.com ''' 1588869SAli.Saidi@ARM.com revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 1597584SN/A { "code": revshCode, 1607584SN/A "predicate_test": predicateTest }, []) 1617584SN/A header_output += RegRegOpDeclare.subst(revshIop) 1627584SN/A decoder_output += RegRegOpConstructor.subst(revshIop) 1637584SN/A exec_output += PredOpExecute.subst(revshIop) 1648869SAli.Saidi@ARM.com 1657584SN/A rbitCode = ''' 1668869SAli.Saidi@ARM.com uint8_t *opBytes = (uint8_t *)&Op1; 1678869SAli.Saidi@ARM.com uint32_t resTemp; 1688869SAli.Saidi@ARM.com uint8_t *destBytes = (uint8_t *)&resTemp; 1698869SAli.Saidi@ARM.com // This reverses the bytes and bits of the input, or so says the 1708869SAli.Saidi@ARM.com // internet. 1718869SAli.Saidi@ARM.com for (int i = 0; i < 4; i++) { 1728869SAli.Saidi@ARM.com uint32_t temp = opBytes[i]; 1738869SAli.Saidi@ARM.com temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 1748869SAli.Saidi@ARM.com destBytes[3 - i] = (temp * 0x10101) >> 16; 1758869SAli.Saidi@ARM.com } 1768869SAli.Saidi@ARM.com Dest = resTemp; 1778869SAli.Saidi@ARM.com ''' 1788869SAli.Saidi@ARM.com rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 1798869SAli.Saidi@ARM.com { "code": rbitCode, 1808869SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 1818869SAli.Saidi@ARM.com header_output += RegRegOpDeclare.subst(rbitIop) 1828869SAli.Saidi@ARM.com decoder_output += RegRegOpConstructor.subst(rbitIop) 1838869SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(rbitIop) 1848869SAli.Saidi@ARM.com 1858869SAli.Saidi@ARM.com clzCode = ''' 1868869SAli.Saidi@ARM.com Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 1878869SAli.Saidi@ARM.com ''' 1888993SAli.Saidi@ARM.com clzIop = InstObjParams("clz", "Clz", "RegRegOp", 1898869SAli.Saidi@ARM.com { "code": clzCode, 1908869SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 1917584SN/A header_output += RegRegOpDeclare.subst(clzIop) 1927584SN/A decoder_output += RegRegOpConstructor.subst(clzIop) 1937584SN/A exec_output += PredOpExecute.subst(clzIop) 1947584SN/A 19510905Sandreas.sandberg@arm.com ssatCode = ''' 1967584SN/A int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 1978869SAli.Saidi@ARM.com int32_t res; 1988869SAli.Saidi@ARM.com if (satInt(res, operand, imm)) 1998869SAli.Saidi@ARM.com CondCodes = CondCodes | (1 << 27); 2008869SAli.Saidi@ARM.com else 2018869SAli.Saidi@ARM.com CondCodes = CondCodes; 2028869SAli.Saidi@ARM.com Dest = res; 2038869SAli.Saidi@ARM.com ''' 2048869SAli.Saidi@ARM.com ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 2057584SN/A { "code": ssatCode, 2068869SAli.Saidi@ARM.com "predicate_test": condPredicateTest }, []) 2077733SN/A header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 2087733SN/A decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 2097733SN/A exec_output += PredOpExecute.subst(ssatIop) 2107733SN/A 2118869SAli.Saidi@ARM.com usatCode = ''' 2127733SN/A int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2137733SN/A int32_t res; 2147733SN/A if (uSatInt(res, operand, imm)) 2157733SN/A CondCodes = CondCodes | (1 << 27); 2167733SN/A else 21710905Sandreas.sandberg@arm.com CondCodes = CondCodes; 2187733SN/A Dest = res; 2198869SAli.Saidi@ARM.com ''' 2207733SN/A usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 2218869SAli.Saidi@ARM.com { "code": usatCode, 2228869SAli.Saidi@ARM.com "predicate_test": condPredicateTest }, []) 2238869SAli.Saidi@ARM.com header_output += RegImmRegShiftOpDeclare.subst(usatIop) 2248869SAli.Saidi@ARM.com decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 2257733SN/A exec_output += PredOpExecute.subst(usatIop) 2268869SAli.Saidi@ARM.com 2277733SN/A ssat16Code = ''' 2287733SN/A int32_t res; 2297733SN/A uint32_t resTemp = 0; 2307733SN/A CondCodes = CondCodes; 2317733SN/A int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2327733SN/A int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2337733SN/A if (satInt(res, argLow, imm)) 2347733SN/A CondCodes = CondCodes | (1 << 27); 2358869SAli.Saidi@ARM.com replaceBits(resTemp, 15, 0, res); 2367733SN/A if (satInt(res, argHigh, imm)) 2377733SN/A CondCodes = CondCodes | (1 << 27); 2387733SN/A replaceBits(resTemp, 31, 16, res); 2397733SN/A Dest = resTemp; 2407584SN/A ''' 2418869SAli.Saidi@ARM.com ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 2428869SAli.Saidi@ARM.com { "code": ssat16Code, 2437584SN/A "predicate_test": condPredicateTest }, []) 2448869SAli.Saidi@ARM.com header_output += RegImmRegOpDeclare.subst(ssat16Iop) 2457584SN/A decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 246 exec_output += PredOpExecute.subst(ssat16Iop) 247 248 usat16Code = ''' 249 int32_t res; 250 uint32_t resTemp = 0; 251 CondCodes = CondCodes; 252 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 253 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 254 if (uSatInt(res, argLow, imm)) 255 CondCodes = CondCodes | (1 << 27); 256 replaceBits(resTemp, 15, 0, res); 257 if (uSatInt(res, argHigh, imm)) 258 CondCodes = CondCodes | (1 << 27); 259 replaceBits(resTemp, 31, 16, res); 260 Dest = resTemp; 261 ''' 262 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 263 { "code": usat16Code, 264 "predicate_test": condPredicateTest }, []) 265 header_output += RegImmRegOpDeclare.subst(usat16Iop) 266 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 267 exec_output += PredOpExecute.subst(usat16Iop) 268 269 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 270 { "code": 271 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 272 "predicate_test": predicateTest }, []) 273 header_output += RegImmRegOpDeclare.subst(sxtbIop) 274 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 275 exec_output += PredOpExecute.subst(sxtbIop) 276 277 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 278 { "code": 279 ''' 280 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 281 Op1; 282 ''', 283 "predicate_test": predicateTest }, []) 284 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 285 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 286 exec_output += PredOpExecute.subst(sxtabIop) 287 288 sxtb16Code = ''' 289 uint32_t resTemp = 0; 290 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 291 replaceBits(resTemp, 31, 16, 292 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 293 Dest = resTemp; 294 ''' 295 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 296 { "code": sxtb16Code, 297 "predicate_test": predicateTest }, []) 298 header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 299 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 300 exec_output += PredOpExecute.subst(sxtb16Iop) 301 302 sxtab16Code = ''' 303 uint32_t resTemp = 0; 304 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 305 bits(Op1, 15, 0)); 306 replaceBits(resTemp, 31, 16, 307 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 308 bits(Op1, 31, 16)); 309 Dest = resTemp; 310 ''' 311 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 312 { "code": sxtab16Code, 313 "predicate_test": predicateTest }, []) 314 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 315 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 316 exec_output += PredOpExecute.subst(sxtab16Iop) 317 318 sxthCode = ''' 319 uint64_t rotated = (uint32_t)Op1; 320 rotated = (rotated | (rotated << 32)) >> imm; 321 Dest = sext<16>((uint16_t)rotated); 322 ''' 323 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 324 { "code": sxthCode, 325 "predicate_test": predicateTest }, []) 326 header_output += RegImmRegOpDeclare.subst(sxthIop) 327 decoder_output += RegImmRegOpConstructor.subst(sxthIop) 328 exec_output += PredOpExecute.subst(sxthIop) 329 330 sxtahCode = ''' 331 uint64_t rotated = (uint32_t)Op2; 332 rotated = (rotated | (rotated << 32)) >> imm; 333 Dest = sext<16>((uint16_t)rotated) + Op1; 334 ''' 335 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 336 { "code": sxtahCode, 337 "predicate_test": predicateTest }, []) 338 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 339 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 340 exec_output += PredOpExecute.subst(sxtahIop) 341 342 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 343 { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 344 "predicate_test": predicateTest }, []) 345 header_output += RegImmRegOpDeclare.subst(uxtbIop) 346 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 347 exec_output += PredOpExecute.subst(uxtbIop) 348 349 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 350 { "code": 351 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 352 "predicate_test": predicateTest }, []) 353 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 354 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 355 exec_output += PredOpExecute.subst(uxtabIop) 356 357 uxtb16Code = ''' 358 uint32_t resTemp = 0; 359 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 360 replaceBits(resTemp, 31, 16, 361 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 362 Dest = resTemp; 363 ''' 364 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 365 { "code": uxtb16Code, 366 "predicate_test": predicateTest }, []) 367 header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 368 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 369 exec_output += PredOpExecute.subst(uxtb16Iop) 370 371 uxtab16Code = ''' 372 uint32_t resTemp = 0; 373 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 374 bits(Op1, 15, 0)); 375 replaceBits(resTemp, 31, 16, 376 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 377 bits(Op1, 31, 16)); 378 Dest = resTemp; 379 ''' 380 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 381 { "code": uxtab16Code, 382 "predicate_test": predicateTest }, []) 383 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 384 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 385 exec_output += PredOpExecute.subst(uxtab16Iop) 386 387 uxthCode = ''' 388 uint64_t rotated = (uint32_t)Op1; 389 rotated = (rotated | (rotated << 32)) >> imm; 390 Dest = (uint16_t)rotated; 391 ''' 392 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 393 { "code": uxthCode, 394 "predicate_test": predicateTest }, []) 395 header_output += RegImmRegOpDeclare.subst(uxthIop) 396 decoder_output += RegImmRegOpConstructor.subst(uxthIop) 397 exec_output += PredOpExecute.subst(uxthIop) 398 399 uxtahCode = ''' 400 uint64_t rotated = (uint32_t)Op2; 401 rotated = (rotated | (rotated << 32)) >> imm; 402 Dest = (uint16_t)rotated + Op1; 403 ''' 404 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 405 { "code": uxtahCode, 406 "predicate_test": predicateTest }, []) 407 header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 408 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 409 exec_output += PredOpExecute.subst(uxtahIop) 410 411 selCode = ''' 412 uint32_t resTemp = 0; 413 for (unsigned i = 0; i < 4; i++) { 414 int low = i * 8; 415 int high = low + 7; 416 replaceBits(resTemp, high, low, 417 bits(CondCodes, 16 + i) ? 418 bits(Op1, high, low) : bits(Op2, high, low)); 419 } 420 Dest = resTemp; 421 ''' 422 selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 423 { "code": selCode, 424 "predicate_test": condPredicateTest }, []) 425 header_output += RegRegRegOpDeclare.subst(selIop) 426 decoder_output += RegRegRegOpConstructor.subst(selIop) 427 exec_output += PredOpExecute.subst(selIop) 428 429 usad8Code = ''' 430 uint32_t resTemp = 0; 431 for (unsigned i = 0; i < 4; i++) { 432 int low = i * 8; 433 int high = low + 7; 434 int32_t diff = bits(Op1, high, low) - 435 bits(Op2, high, low); 436 resTemp += ((diff < 0) ? -diff : diff); 437 } 438 Dest = resTemp; 439 ''' 440 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 441 { "code": usad8Code, 442 "predicate_test": predicateTest }, []) 443 header_output += RegRegRegOpDeclare.subst(usad8Iop) 444 decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 445 exec_output += PredOpExecute.subst(usad8Iop) 446 447 usada8Code = ''' 448 uint32_t resTemp = 0; 449 for (unsigned i = 0; i < 4; i++) { 450 int low = i * 8; 451 int high = low + 7; 452 int32_t diff = bits(Op1, high, low) - 453 bits(Op2, high, low); 454 resTemp += ((diff < 0) ? -diff : diff); 455 } 456 Dest = Op3 + resTemp; 457 ''' 458 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 459 { "code": usada8Code, 460 "predicate_test": predicateTest }, []) 461 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 462 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 463 exec_output += PredOpExecute.subst(usada8Iop) 464 465 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 466 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 467 header_output += BasicDeclare.subst(bkptIop) 468 decoder_output += BasicConstructor.subst(bkptIop) 469 exec_output += BasicExecute.subst(bkptIop) 470 471 nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 472 { "code" : "", "predicate_test" : predicateTest }, 473 ['IsNop']) 474 header_output += BasicDeclare.subst(nopIop) 475 decoder_output += BasicConstructor.subst(nopIop) 476 exec_output += PredOpExecute.subst(nopIop) 477 478 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 479 { "code" : "", "predicate_test" : predicateTest }) 480 header_output += BasicDeclare.subst(yieldIop) 481 decoder_output += BasicConstructor.subst(yieldIop) 482 exec_output += PredOpExecute.subst(yieldIop) 483 484 wfeCode = ''' 485#if FULL_SYSTEM 486 if (SevMailbox == 1) { 487 SevMailbox = 0; 488 PseudoInst::quiesceSkip(xc->tcBase()); 489 } else { 490 PseudoInst::quiesce(xc->tcBase()); 491 } 492#endif 493 ''' 494 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 495 { "code" : wfeCode, "predicate_test" : predicateTest }, 496 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 497 header_output += BasicDeclare.subst(wfeIop) 498 decoder_output += BasicConstructor.subst(wfeIop) 499 exec_output += QuiescePredOpExecute.subst(wfeIop) 500 501 wfiCode = ''' 502#if FULL_SYSTEM 503 // WFI doesn't sleep if interrupts are pending (masked or not) 504 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) { 505 PseudoInst::quiesceSkip(xc->tcBase()); 506 } else { 507 PseudoInst::quiesce(xc->tcBase()); 508 } 509#endif 510 ''' 511 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 512 { "code" : wfiCode, "predicate_test" : predicateTest }, 513 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 514 header_output += BasicDeclare.subst(wfiIop) 515 decoder_output += BasicConstructor.subst(wfiIop) 516 exec_output += QuiescePredOpExecute.subst(wfiIop) 517 518 sevCode = ''' 519 // Need a way for O3 to not scoreboard these accesses as pipe flushes. 520 SevMailbox = 1; 521 System *sys = xc->tcBase()->getSystemPtr(); 522 for (int x = 0; x < sys->numContexts(); x++) { 523 ThreadContext *oc = sys->getThreadContext(x); 524 if (oc == xc->tcBase()) 525 continue; 526 // Only wake if they were sleeping 527 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 528 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 529 PseudoInst::wakeCPU(xc->tcBase(), x); 530 } 531 } 532 ''' 533 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 534 { "code" : sevCode, "predicate_test" : predicateTest }, 535 ["IsNonSpeculative", "IsSquashAfter"]) 536 header_output += BasicDeclare.subst(sevIop) 537 decoder_output += BasicConstructor.subst(sevIop) 538 exec_output += PredOpExecute.subst(sevIop) 539 540 itIop = InstObjParams("it", "ItInst", "PredOp", \ 541 { "code" : ";", 542 "predicate_test" : predicateTest }, 543 ["IsNonSpeculative", "IsSerializeAfter"]) 544 header_output += BasicDeclare.subst(itIop) 545 decoder_output += BasicConstructor.subst(itIop) 546 exec_output += PredOpExecute.subst(itIop) 547 unknownCode = ''' 548#if FULL_SYSTEM 549 return new UndefinedInstruction; 550#else 551 return new UndefinedInstruction(machInst, true); 552#endif 553 ''' 554 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 555 { "code": unknownCode, 556 "predicate_test": predicateTest }) 557 header_output += BasicDeclare.subst(unknownIop) 558 decoder_output += BasicConstructor.subst(unknownIop) 559 exec_output += PredOpExecute.subst(unknownIop) 560 561 ubfxCode = ''' 562 Dest = bits(Op1, imm2, imm1); 563 ''' 564 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 565 { "code": ubfxCode, 566 "predicate_test": predicateTest }, []) 567 header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 568 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 569 exec_output += PredOpExecute.subst(ubfxIop) 570 571 sbfxCode = ''' 572 int32_t resTemp = bits(Op1, imm2, imm1); 573 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 574 ''' 575 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 576 { "code": sbfxCode, 577 "predicate_test": predicateTest }, []) 578 header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 579 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 580 exec_output += PredOpExecute.subst(sbfxIop) 581 582 bfcCode = ''' 583 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 584 ''' 585 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 586 { "code": bfcCode, 587 "predicate_test": predicateTest }, []) 588 header_output += RegRegImmImmOpDeclare.subst(bfcIop) 589 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 590 exec_output += PredOpExecute.subst(bfcIop) 591 592 bfiCode = ''' 593 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 594 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 595 ''' 596 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 597 { "code": bfiCode, 598 "predicate_test": predicateTest }, []) 599 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 600 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 601 exec_output += PredOpExecute.subst(bfiIop) 602 603 mrc15code = ''' 604 CPSR cpsr = Cpsr; 605 if (cpsr.mode == MODE_USER) 606#if FULL_SYSTEM 607 return new UndefinedInstruction; 608#else 609 return new UndefinedInstruction(false, mnemonic); 610#endif 611 Dest = MiscOp1; 612 ''' 613 614 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 615 { "code": mrc15code, 616 "predicate_test": predicateTest }, []) 617 header_output += RegRegOpDeclare.subst(mrc15Iop) 618 decoder_output += RegRegOpConstructor.subst(mrc15Iop) 619 exec_output += PredOpExecute.subst(mrc15Iop) 620 621 622 mcr15code = ''' 623 CPSR cpsr = Cpsr; 624 if (cpsr.mode == MODE_USER) 625#if FULL_SYSTEM 626 return new UndefinedInstruction; 627#else 628 return new UndefinedInstruction(false, mnemonic); 629#endif 630 MiscDest = Op1; 631 ''' 632 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 633 { "code": mcr15code, 634 "predicate_test": predicateTest }, 635 ["IsSerializeAfter","IsNonSpeculative"]) 636 header_output += RegRegOpDeclare.subst(mcr15Iop) 637 decoder_output += RegRegOpConstructor.subst(mcr15Iop) 638 exec_output += PredOpExecute.subst(mcr15Iop) 639 640 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 641 { "code": "Dest = MiscOp1;", 642 "predicate_test": predicateTest }, []) 643 header_output += RegRegOpDeclare.subst(mrc15UserIop) 644 decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 645 exec_output += PredOpExecute.subst(mrc15UserIop) 646 647 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 648 { "code": "MiscDest = Op1", 649 "predicate_test": predicateTest }, 650 ["IsSerializeAfter","IsNonSpeculative"]) 651 header_output += RegRegOpDeclare.subst(mcr15UserIop) 652 decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 653 exec_output += PredOpExecute.subst(mcr15UserIop) 654 655 enterxCode = ''' 656 NextThumb = true; 657 NextJazelle = true; 658 ''' 659 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 660 { "code": enterxCode, 661 "predicate_test": predicateTest }, []) 662 header_output += BasicDeclare.subst(enterxIop) 663 decoder_output += BasicConstructor.subst(enterxIop) 664 exec_output += PredOpExecute.subst(enterxIop) 665 666 leavexCode = ''' 667 NextThumb = true; 668 NextJazelle = false; 669 ''' 670 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 671 { "code": leavexCode, 672 "predicate_test": predicateTest }, []) 673 header_output += BasicDeclare.subst(leavexIop) 674 decoder_output += BasicConstructor.subst(leavexIop) 675 exec_output += PredOpExecute.subst(leavexIop) 676 677 setendCode = ''' 678 CPSR cpsr = Cpsr; 679 cpsr.e = imm; 680 Cpsr = cpsr; 681 ''' 682 setendIop = InstObjParams("setend", "Setend", "ImmOp", 683 { "code": setendCode, 684 "predicate_test": predicateTest }, 685 ["IsSerializeAfter","IsNonSpeculative"]) 686 header_output += ImmOpDeclare.subst(setendIop) 687 decoder_output += ImmOpConstructor.subst(setendIop) 688 exec_output += PredOpExecute.subst(setendIop) 689 690 clrexCode = ''' 691 LLSCLock = 0; 692 ''' 693 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 694 { "code": clrexCode, 695 "predicate_test": predicateTest },[]) 696 header_output += BasicDeclare.subst(clrexIop) 697 decoder_output += BasicConstructor.subst(clrexIop) 698 exec_output += PredOpExecute.subst(clrexIop) 699 700 isbCode = ''' 701 fault = new FlushPipe; 702 ''' 703 isbIop = InstObjParams("isb", "Isb", "PredOp", 704 {"code": isbCode, 705 "predicate_test": predicateTest}, 706 ['IsSerializeAfter']) 707 header_output += BasicDeclare.subst(isbIop) 708 decoder_output += BasicConstructor.subst(isbIop) 709 exec_output += PredOpExecute.subst(isbIop) 710 711 dsbCode = ''' 712 fault = new FlushPipe; 713 ''' 714 dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 715 {"code": dsbCode, 716 "predicate_test": predicateTest}, 717 ['IsMemBarrier', 'IsSerializeAfter']) 718 header_output += BasicDeclare.subst(dsbIop) 719 decoder_output += BasicConstructor.subst(dsbIop) 720 exec_output += PredOpExecute.subst(dsbIop) 721 722 dmbCode = ''' 723 ''' 724 dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 725 {"code": dmbCode, 726 "predicate_test": predicateTest}, 727 ['IsMemBarrier']) 728 header_output += BasicDeclare.subst(dmbIop) 729 decoder_output += BasicConstructor.subst(dmbIop) 730 exec_output += PredOpExecute.subst(dmbIop) 731 732 dbgCode = ''' 733 ''' 734 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 735 {"code": dbgCode, 736 "predicate_test": predicateTest}) 737 header_output += BasicDeclare.subst(dbgIop) 738 decoder_output += BasicConstructor.subst(dbgIop) 739 exec_output += PredOpExecute.subst(dbgIop) 740 741 cpsCode = ''' 742 uint32_t mode = bits(imm, 4, 0); 743 uint32_t f = bits(imm, 5); 744 uint32_t i = bits(imm, 6); 745 uint32_t a = bits(imm, 7); 746 bool setMode = bits(imm, 8); 747 bool enable = bits(imm, 9); 748 CPSR cpsr = Cpsr; 749 SCTLR sctlr = Sctlr; 750 if (cpsr.mode != MODE_USER) { 751 if (enable) { 752 if (f) cpsr.f = 0; 753 if (i) cpsr.i = 0; 754 if (a) cpsr.a = 0; 755 } else { 756 if (f && !sctlr.nmfi) cpsr.f = 1; 757 if (i) cpsr.i = 1; 758 if (a) cpsr.a = 1; 759 } 760 if (setMode) { 761 cpsr.mode = mode; 762 } 763 } 764 Cpsr = cpsr; 765 ''' 766 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 767 { "code": cpsCode, 768 "predicate_test": predicateTest }, 769 ["IsSerializeAfter","IsNonSpeculative"]) 770 header_output += ImmOpDeclare.subst(cpsIop) 771 decoder_output += ImmOpConstructor.subst(cpsIop) 772 exec_output += PredOpExecute.subst(cpsIop) 773}}; 774