misc.isa revision 8209
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 312504Snikos.nikoleris@arm.com// Copyright (c) 2010 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 4312541Sgiacomo.travaglini@arm.com#if FULL_SYSTEM 4412541Sgiacomo.travaglini@arm.com fault = new SupervisorCall; 4512541Sgiacomo.travaglini@arm.com#else 4612541Sgiacomo.travaglini@arm.com fault = new SupervisorCall(machInst); 4712541Sgiacomo.travaglini@arm.com#endif 4812541Sgiacomo.travaglini@arm.com ''' 4912541Sgiacomo.travaglini@arm.com 5012541Sgiacomo.travaglini@arm.com svcIop = InstObjParams("svc", "Svc", "PredOp", 5112541Sgiacomo.travaglini@arm.com { "code": svcCode, 5210037SARM gem5 Developers "predicate_test": predicateTest }, ["IsSyscall"]) 5310037SARM gem5 Developers header_output = BasicDeclare.subst(svcIop) 5410037SARM gem5 Developers decoder_output = BasicConstructor.subst(svcIop) 5510037SARM gem5 Developers exec_output = PredOpExecute.subst(svcIop) 5612541Sgiacomo.travaglini@arm.com 5712541Sgiacomo.travaglini@arm.com}}; 5812541Sgiacomo.travaglini@arm.com 5912541Sgiacomo.travaglini@arm.comlet {{ 6012541Sgiacomo.travaglini@arm.com 6110037SARM gem5 Developers header_output = decoder_output = exec_output = "" 6212541Sgiacomo.travaglini@arm.com 6310037SARM gem5 Developers mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF" 6410037SARM gem5 Developers mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 6512542Sgiacomo.travaglini@arm.com { "code": mrsCpsrCode, 6612542Sgiacomo.travaglini@arm.com "predicate_test": condPredicateTest }, 6712542Sgiacomo.travaglini@arm.com ["IsSerializeBefore"]) 6812542Sgiacomo.travaglini@arm.com header_output += MrsDeclare.subst(mrsCpsrIop) 6912542Sgiacomo.travaglini@arm.com decoder_output += MrsConstructor.subst(mrsCpsrIop) 7012542Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(mrsCpsrIop) 7112542Sgiacomo.travaglini@arm.com 7212542Sgiacomo.travaglini@arm.com mrsSpsrCode = "Dest = Spsr" 7312542Sgiacomo.travaglini@arm.com mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 7412542Sgiacomo.travaglini@arm.com { "code": mrsSpsrCode, 7512542Sgiacomo.travaglini@arm.com "predicate_test": predicateTest }, 7612542Sgiacomo.travaglini@arm.com ["IsSerializeBefore"]) 7712542Sgiacomo.travaglini@arm.com header_output += MrsDeclare.subst(mrsSpsrIop) 7812542Sgiacomo.travaglini@arm.com decoder_output += MrsConstructor.subst(mrsSpsrIop) 7912542Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(mrsSpsrIop) 8012542Sgiacomo.travaglini@arm.com 8112542Sgiacomo.travaglini@arm.com msrCpsrRegCode = ''' 8212542Sgiacomo.travaglini@arm.com SCTLR sctlr = Sctlr; 8312542Sgiacomo.travaglini@arm.com uint32_t newCpsr = 8412542Sgiacomo.travaglini@arm.com cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); 8512542Sgiacomo.travaglini@arm.com Cpsr = ~CondCodesMask & newCpsr; 8612542Sgiacomo.travaglini@arm.com CondCodes = CondCodesMask & newCpsr; 8712542Sgiacomo.travaglini@arm.com ''' 8812542Sgiacomo.travaglini@arm.com msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 8912542Sgiacomo.travaglini@arm.com { "code": msrCpsrRegCode, 9010037SARM gem5 Developers "predicate_test": condPredicateTest }, 9110037SARM gem5 Developers ["IsSerializeAfter","IsNonSpeculative"]) 9210037SARM gem5 Developers header_output += MsrRegDeclare.subst(msrCpsrRegIop) 9310037SARM gem5 Developers decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 9410037SARM gem5 Developers exec_output += PredOpExecute.subst(msrCpsrRegIop) 9510037SARM gem5 Developers 9610037SARM gem5 Developers msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 9710037SARM gem5 Developers msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 9810474Sandreas.hansson@arm.com { "code": msrSpsrRegCode, 9910474Sandreas.hansson@arm.com "predicate_test": predicateTest }, 10010037SARM gem5 Developers ["IsSerializeAfter","IsNonSpeculative"]) 10110037SARM gem5 Developers header_output += MsrRegDeclare.subst(msrSpsrRegIop) 10210037SARM gem5 Developers decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 10310037SARM gem5 Developers exec_output += PredOpExecute.subst(msrSpsrRegIop) 10410474Sandreas.hansson@arm.com 10510037SARM gem5 Developers msrCpsrImmCode = ''' 10610037SARM gem5 Developers SCTLR sctlr = Sctlr; 1078782Sgblack@eecs.umich.edu uint32_t newCpsr = 10810037SARM gem5 Developers cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); 1098782Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 1107199Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 1117199Sgblack@eecs.umich.edu ''' 11210037SARM gem5 Developers msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 11310037SARM gem5 Developers { "code": msrCpsrImmCode, 1148628SAli.Saidi@ARM.com "predicate_test": condPredicateTest }, 11510037SARM gem5 Developers ["IsSerializeAfter","IsNonSpeculative"]) 11610037SARM gem5 Developers header_output += MsrImmDeclare.subst(msrCpsrImmIop) 11710037SARM gem5 Developers decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 11810037SARM gem5 Developers exec_output += PredOpExecute.subst(msrCpsrImmIop) 11910037SARM gem5 Developers 12010037SARM gem5 Developers msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 12110037SARM gem5 Developers msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 12210037SARM gem5 Developers { "code": msrSpsrImmCode, 12310037SARM gem5 Developers "predicate_test": predicateTest }, 12410037SARM gem5 Developers ["IsSerializeAfter","IsNonSpeculative"]) 12510037SARM gem5 Developers header_output += MsrImmDeclare.subst(msrSpsrImmIop) 12610037SARM gem5 Developers decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 12710037SARM gem5 Developers exec_output += PredOpExecute.subst(msrSpsrImmIop) 12810037SARM gem5 Developers 12910037SARM gem5 Developers revCode = ''' 13010474Sandreas.hansson@arm.com uint32_t val = Op1; 13110037SARM gem5 Developers Dest = swap_byte(val); 13210037SARM gem5 Developers ''' 13310037SARM gem5 Developers revIop = InstObjParams("rev", "Rev", "RegRegOp", 13410037SARM gem5 Developers { "code": revCode, 13510037SARM gem5 Developers "predicate_test": predicateTest }, []) 13610037SARM gem5 Developers header_output += RegRegOpDeclare.subst(revIop) 13710037SARM gem5 Developers decoder_output += RegRegOpConstructor.subst(revIop) 13810037SARM gem5 Developers exec_output += PredOpExecute.subst(revIop) 13910037SARM gem5 Developers 14010037SARM gem5 Developers rev16Code = ''' 14110037SARM gem5 Developers uint32_t val = Op1; 14210037SARM gem5 Developers Dest = (bits(val, 15, 8) << 0) | 14310037SARM gem5 Developers (bits(val, 7, 0) << 8) | 14410037SARM gem5 Developers (bits(val, 31, 24) << 16) | 14510037SARM gem5 Developers (bits(val, 23, 16) << 24); 14610037SARM gem5 Developers ''' 14710037SARM gem5 Developers rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 14810037SARM gem5 Developers { "code": rev16Code, 14910037SARM gem5 Developers "predicate_test": predicateTest }, []) 15010037SARM gem5 Developers header_output += RegRegOpDeclare.subst(rev16Iop) 15110037SARM gem5 Developers decoder_output += RegRegOpConstructor.subst(rev16Iop) 15210037SARM gem5 Developers exec_output += PredOpExecute.subst(rev16Iop) 15310037SARM gem5 Developers 15410037SARM gem5 Developers revshCode = ''' 15510037SARM gem5 Developers uint16_t val = Op1; 15610037SARM gem5 Developers Dest = sext<16>(swap_byte(val)); 15710037SARM gem5 Developers ''' 15810037SARM gem5 Developers revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 15910037SARM gem5 Developers { "code": revshCode, 16010037SARM gem5 Developers "predicate_test": predicateTest }, []) 16110037SARM gem5 Developers header_output += RegRegOpDeclare.subst(revshIop) 16210037SARM gem5 Developers decoder_output += RegRegOpConstructor.subst(revshIop) 16310037SARM gem5 Developers exec_output += PredOpExecute.subst(revshIop) 16410037SARM gem5 Developers 16510037SARM gem5 Developers rbitCode = ''' 16610037SARM gem5 Developers uint8_t *opBytes = (uint8_t *)&Op1; 16710037SARM gem5 Developers uint32_t resTemp; 16810037SARM gem5 Developers uint8_t *destBytes = (uint8_t *)&resTemp; 16911355Smitch.hayenga@arm.com // This reverses the bytes and bits of the input, or so says the 17011355Smitch.hayenga@arm.com // internet. 17110037SARM gem5 Developers for (int i = 0; i < 4; i++) { 17210037SARM gem5 Developers uint32_t temp = opBytes[i]; 17310037SARM gem5 Developers temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 17410037SARM gem5 Developers destBytes[3 - i] = (temp * 0x10101) >> 16; 17512258Sgiacomo.travaglini@arm.com } 17612258Sgiacomo.travaglini@arm.com Dest = resTemp; 17712258Sgiacomo.travaglini@arm.com ''' 17810037SARM gem5 Developers rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 17912258Sgiacomo.travaglini@arm.com { "code": rbitCode, 18012258Sgiacomo.travaglini@arm.com "predicate_test": predicateTest }, []) 18112258Sgiacomo.travaglini@arm.com header_output += RegRegOpDeclare.subst(rbitIop) 18212258Sgiacomo.travaglini@arm.com decoder_output += RegRegOpConstructor.subst(rbitIop) 18312258Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(rbitIop) 18412258Sgiacomo.travaglini@arm.com 18512258Sgiacomo.travaglini@arm.com clzCode = ''' 18612258Sgiacomo.travaglini@arm.com Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 18712258Sgiacomo.travaglini@arm.com ''' 18812258Sgiacomo.travaglini@arm.com clzIop = InstObjParams("clz", "Clz", "RegRegOp", 18912258Sgiacomo.travaglini@arm.com { "code": clzCode, 19012258Sgiacomo.travaglini@arm.com "predicate_test": predicateTest }, []) 19112258Sgiacomo.travaglini@arm.com header_output += RegRegOpDeclare.subst(clzIop) 19212258Sgiacomo.travaglini@arm.com decoder_output += RegRegOpConstructor.subst(clzIop) 19312258Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(clzIop) 19412258Sgiacomo.travaglini@arm.com 19512258Sgiacomo.travaglini@arm.com ssatCode = ''' 19612258Sgiacomo.travaglini@arm.com int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 19712258Sgiacomo.travaglini@arm.com int32_t res; 19812258Sgiacomo.travaglini@arm.com if (satInt(res, operand, imm)) 19912258Sgiacomo.travaglini@arm.com CondCodes = CondCodes | (1 << 27); 20012258Sgiacomo.travaglini@arm.com else 20112258Sgiacomo.travaglini@arm.com CondCodes = CondCodes; 20212258Sgiacomo.travaglini@arm.com Dest = res; 20312258Sgiacomo.travaglini@arm.com ''' 20412258Sgiacomo.travaglini@arm.com ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 20512258Sgiacomo.travaglini@arm.com { "code": ssatCode, 20612258Sgiacomo.travaglini@arm.com "predicate_test": condPredicateTest }, []) 20712258Sgiacomo.travaglini@arm.com header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 20812258Sgiacomo.travaglini@arm.com decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 20912258Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(ssatIop) 21012258Sgiacomo.travaglini@arm.com 21112258Sgiacomo.travaglini@arm.com usatCode = ''' 21212258Sgiacomo.travaglini@arm.com int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 21312258Sgiacomo.travaglini@arm.com int32_t res; 21412258Sgiacomo.travaglini@arm.com if (uSatInt(res, operand, imm)) 21512258Sgiacomo.travaglini@arm.com CondCodes = CondCodes | (1 << 27); 2167199Sgblack@eecs.umich.edu else 2177199Sgblack@eecs.umich.edu CondCodes = CondCodes; 2187202Sgblack@eecs.umich.edu Dest = res; 2197202Sgblack@eecs.umich.edu ''' 2207202Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 2217202Sgblack@eecs.umich.edu { "code": usatCode, 2227202Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2238301SAli.Saidi@ARM.com header_output += RegImmRegShiftOpDeclare.subst(usatIop) 2248303SAli.Saidi@ARM.com decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 2258303SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(usatIop) 2268303SAli.Saidi@ARM.com 2278303SAli.Saidi@ARM.com ssat16Code = ''' 2288303SAli.Saidi@ARM.com int32_t res; 2298303SAli.Saidi@ARM.com uint32_t resTemp = 0; 2308301SAli.Saidi@ARM.com CondCodes = CondCodes; 2318301SAli.Saidi@ARM.com int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2327202Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2337202Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 2347599Sminkyu.jeong@arm.com CondCodes = CondCodes | (1 << 27); 2357783SGiacomo.Gabrielli@arm.com replaceBits(resTemp, 15, 0, res); 2367202Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 2377202Sgblack@eecs.umich.edu CondCodes = CondCodes | (1 << 27); 2387202Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2397202Sgblack@eecs.umich.edu Dest = resTemp; 2407202Sgblack@eecs.umich.edu ''' 2417202Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 2427202Sgblack@eecs.umich.edu { "code": ssat16Code, 2437599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, []) 2447783SGiacomo.Gabrielli@arm.com header_output += RegImmRegOpDeclare.subst(ssat16Iop) 2457202Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 2467202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssat16Iop) 2477202Sgblack@eecs.umich.edu 2487202Sgblack@eecs.umich.edu usat16Code = ''' 24910037SARM gem5 Developers int32_t res; 25010037SARM gem5 Developers uint32_t resTemp = 0; 25110037SARM gem5 Developers CondCodes = CondCodes; 25210037SARM gem5 Developers int32_t argLow = sext<16>(bits(Op1, 15, 0)); 25310037SARM gem5 Developers int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 25410037SARM gem5 Developers if (uSatInt(res, argLow, imm)) 25510037SARM gem5 Developers CondCodes = CondCodes | (1 << 27); 25610037SARM gem5 Developers replaceBits(resTemp, 15, 0, res); 25710037SARM gem5 Developers if (uSatInt(res, argHigh, imm)) 25810037SARM gem5 Developers CondCodes = CondCodes | (1 << 27); 25910037SARM gem5 Developers replaceBits(resTemp, 31, 16, res); 26010474Sandreas.hansson@arm.com Dest = resTemp; 26110474Sandreas.hansson@arm.com ''' 26210037SARM gem5 Developers usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 26310037SARM gem5 Developers { "code": usat16Code, 26410037SARM gem5 Developers "predicate_test": condPredicateTest }, []) 26510037SARM gem5 Developers header_output += RegImmRegOpDeclare.subst(usat16Iop) 26610037SARM gem5 Developers decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 26710037SARM gem5 Developers exec_output += PredOpExecute.subst(usat16Iop) 26810037SARM gem5 Developers 26910037SARM gem5 Developers sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 27010037SARM gem5 Developers { "code": 27110037SARM gem5 Developers "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 27210037SARM gem5 Developers "predicate_test": predicateTest }, []) 27310037SARM gem5 Developers header_output += RegImmRegOpDeclare.subst(sxtbIop) 27410037SARM gem5 Developers decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 27510037SARM gem5 Developers exec_output += PredOpExecute.subst(sxtbIop) 27610037SARM gem5 Developers 27710037SARM gem5 Developers sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 27810037SARM gem5 Developers { "code": 27910037SARM gem5 Developers ''' 28010037SARM gem5 Developers Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 28110037SARM gem5 Developers Op1; 28210037SARM gem5 Developers ''', 28310037SARM gem5 Developers "predicate_test": predicateTest }, []) 28410037SARM gem5 Developers header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 28510037SARM gem5 Developers decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 28610037SARM gem5 Developers exec_output += PredOpExecute.subst(sxtabIop) 28710037SARM gem5 Developers 28810037SARM gem5 Developers sxtb16Code = ''' 28910037SARM gem5 Developers uint32_t resTemp = 0; 29010037SARM gem5 Developers replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 29110037SARM gem5 Developers replaceBits(resTemp, 31, 16, 29210474Sandreas.hansson@arm.com sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 29310474Sandreas.hansson@arm.com Dest = resTemp; 29410037SARM gem5 Developers ''' 29510037SARM gem5 Developers sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 29610037SARM gem5 Developers { "code": sxtb16Code, 29710037SARM gem5 Developers "predicate_test": predicateTest }, []) 29810037SARM gem5 Developers header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 29910501Sakash.bagdia@ARM.com decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 30010037SARM gem5 Developers exec_output += PredOpExecute.subst(sxtb16Iop) 30110037SARM gem5 Developers 30210037SARM gem5 Developers sxtab16Code = ''' 30310037SARM gem5 Developers uint32_t resTemp = 0; 3047202Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 3057400SAli.Saidi@ARM.com bits(Op1, 15, 0)); 3068303SAli.Saidi@ARM.com replaceBits(resTemp, 31, 16, 3078303SAli.Saidi@ARM.com sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3088303SAli.Saidi@ARM.com bits(Op1, 31, 16)); 3098303SAli.Saidi@ARM.com Dest = resTemp; 3108303SAli.Saidi@ARM.com ''' 3118303SAli.Saidi@ARM.com sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 3128303SAli.Saidi@ARM.com { "code": sxtab16Code, 31310037SARM gem5 Developers "predicate_test": predicateTest }, []) 31410037SARM gem5 Developers header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 3158303SAli.Saidi@ARM.com decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 3168303SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(sxtab16Iop) 3178303SAli.Saidi@ARM.com 3188303SAli.Saidi@ARM.com sxthCode = ''' 3198303SAli.Saidi@ARM.com uint64_t rotated = (uint32_t)Op1; 3207202Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3217202Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 3227202Sgblack@eecs.umich.edu ''' 3237599Sminkyu.jeong@arm.com sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 3247599Sminkyu.jeong@arm.com { "code": sxthCode, 3257202Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3267202Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 3277202Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 3287202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 3297202Sgblack@eecs.umich.edu 3307202Sgblack@eecs.umich.edu sxtahCode = ''' 3317202Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 3327599Sminkyu.jeong@arm.com rotated = (rotated | (rotated << 32)) >> imm; 3337599Sminkyu.jeong@arm.com Dest = sext<16>((uint16_t)rotated) + Op1; 3347202Sgblack@eecs.umich.edu ''' 3357202Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 3367202Sgblack@eecs.umich.edu { "code": sxtahCode, 3377202Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3387202Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 3397400SAli.Saidi@ARM.com decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 3408303SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(sxtahIop) 3418303SAli.Saidi@ARM.com 3428303SAli.Saidi@ARM.com uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 3438303SAli.Saidi@ARM.com { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 3448303SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 3458303SAli.Saidi@ARM.com header_output += RegImmRegOpDeclare.subst(uxtbIop) 34610037SARM gem5 Developers decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 34710037SARM gem5 Developers exec_output += PredOpExecute.subst(uxtbIop) 3488303SAli.Saidi@ARM.com 3498303SAli.Saidi@ARM.com uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 3508303SAli.Saidi@ARM.com { "code": 3518303SAli.Saidi@ARM.com "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 3528303SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 3537202Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 3547202Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 3557202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 3567599Sminkyu.jeong@arm.com 3577599Sminkyu.jeong@arm.com uxtb16Code = ''' 3587202Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3597202Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 3607202Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3617202Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 3627202Sgblack@eecs.umich.edu Dest = resTemp; 3637202Sgblack@eecs.umich.edu ''' 3647202Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 3657599Sminkyu.jeong@arm.com { "code": uxtb16Code, 3667599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, []) 3677202Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 3687202Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 3697202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtb16Iop) 3707209Sgblack@eecs.umich.edu 3717209Sgblack@eecs.umich.edu uxtab16Code = ''' 3727209Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3737209Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 3747209Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3757261Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3767209Sgblack@eecs.umich.edu (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3777209Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3787261Sgblack@eecs.umich.edu Dest = resTemp; 3797261Sgblack@eecs.umich.edu ''' 3807209Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 3817209Sgblack@eecs.umich.edu { "code": uxtab16Code, 3827209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3837209Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 3847209Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 3857209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 3867209Sgblack@eecs.umich.edu 3877209Sgblack@eecs.umich.edu uxthCode = ''' 3887209Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 3897261Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3907209Sgblack@eecs.umich.edu Dest = (uint16_t)rotated; 3917209Sgblack@eecs.umich.edu ''' 3927261Sgblack@eecs.umich.edu uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 3937261Sgblack@eecs.umich.edu { "code": uxthCode, 3947209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3957209Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxthIop) 3967209Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxthIop) 3977209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxthIop) 3987209Sgblack@eecs.umich.edu 3997209Sgblack@eecs.umich.edu uxtahCode = ''' 4007261Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 4017209Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4027209Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 4037261Sgblack@eecs.umich.edu ''' 4047261Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 4057209Sgblack@eecs.umich.edu { "code": uxtahCode, 4067226Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4077249Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 40812227Sgiacomo.travaglini@arm.com decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 4097249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 4107261Sgblack@eecs.umich.edu 4117249Sgblack@eecs.umich.edu selCode = ''' 4127249Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4137261Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4147261Sgblack@eecs.umich.edu int low = i * 8; 4157249Sgblack@eecs.umich.edu int high = low + 7; 4167249Sgblack@eecs.umich.edu replaceBits(resTemp, high, low, 4177251Sgblack@eecs.umich.edu bits(CondCodes, 16 + i) ? 4187251Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 4197251Sgblack@eecs.umich.edu } 4207261Sgblack@eecs.umich.edu Dest = resTemp; 4217251Sgblack@eecs.umich.edu ''' 4227251Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 4237261Sgblack@eecs.umich.edu { "code": selCode, 4247261Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 4257251Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 4267251Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 4277226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 4287226Sgblack@eecs.umich.edu 4297226Sgblack@eecs.umich.edu usad8Code = ''' 4307232Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4318302SAli.Saidi@ARM.com for (unsigned i = 0; i < 4; i++) { 4327226Sgblack@eecs.umich.edu int low = i * 8; 4337226Sgblack@eecs.umich.edu int high = low + 7; 4347232Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4357226Sgblack@eecs.umich.edu bits(Op2, high, low); 4368304SAli.Saidi@ARM.com resTemp += ((diff < 0) ? -diff : diff); 4377232Sgblack@eecs.umich.edu } 4387232Sgblack@eecs.umich.edu Dest = resTemp; 4397226Sgblack@eecs.umich.edu ''' 4407226Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 4417226Sgblack@eecs.umich.edu { "code": usad8Code, 4427226Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4437226Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 4447232Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 4458302SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(usad8Iop) 4467226Sgblack@eecs.umich.edu 4477226Sgblack@eecs.umich.edu usada8Code = ''' 4487232Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4497226Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4508304SAli.Saidi@ARM.com int low = i * 8; 4517232Sgblack@eecs.umich.edu int high = low + 7; 4527232Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4537226Sgblack@eecs.umich.edu bits(Op2, high, low); 4547226Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4557226Sgblack@eecs.umich.edu } 4567226Sgblack@eecs.umich.edu Dest = Op3 + resTemp; 4577226Sgblack@eecs.umich.edu ''' 4587226Sgblack@eecs.umich.edu usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 4597226Sgblack@eecs.umich.edu { "code": usada8Code, 4607232Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4618302SAli.Saidi@ARM.com header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 4627226Sgblack@eecs.umich.edu decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 4637232Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usada8Iop) 4648302SAli.Saidi@ARM.com 4657226Sgblack@eecs.umich.edu bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 4667226Sgblack@eecs.umich.edu bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 4677226Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(bkptIop) 4687232Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(bkptIop) 4697226Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(bkptIop) 4708304SAli.Saidi@ARM.com 4717232Sgblack@eecs.umich.edu nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 4727232Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }, 4737226Sgblack@eecs.umich.edu ['IsNop']) 4747226Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(nopIop) 4757226Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(nopIop) 4767226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(nopIop) 4777226Sgblack@eecs.umich.edu 4787226Sgblack@eecs.umich.edu yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 4797226Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 4807232Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(yieldIop) 4818302SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(yieldIop) 4827226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(yieldIop) 4837232Sgblack@eecs.umich.edu 4848302SAli.Saidi@ARM.com wfeCode = ''' 4857226Sgblack@eecs.umich.edu#if FULL_SYSTEM 4867226Sgblack@eecs.umich.edu if (SevMailbox) { 4877226Sgblack@eecs.umich.edu SevMailbox = 0; 4887232Sgblack@eecs.umich.edu PseudoInst::quiesceSkip(xc->tcBase()); 4897226Sgblack@eecs.umich.edu } 4908304SAli.Saidi@ARM.com else { 4917232Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 4927232Sgblack@eecs.umich.edu } 4937226Sgblack@eecs.umich.edu#endif 4947234Sgblack@eecs.umich.edu ''' 4957234Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 4967234Sgblack@eecs.umich.edu { "code" : wfeCode, "predicate_test" : predicateTest }, 4978588Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 4987234Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 4997234Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfeIop) 5007234Sgblack@eecs.umich.edu exec_output += QuiescePredOpExecute.subst(wfeIop) 5017234Sgblack@eecs.umich.edu 5027234Sgblack@eecs.umich.edu wfiCode = ''' 5037234Sgblack@eecs.umich.edu#if FULL_SYSTEM 5047234Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 5057234Sgblack@eecs.umich.edu#endif 5068588Sgblack@eecs.umich.edu ''' 5077234Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 5087234Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 5097234Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 5107234Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfiIop) 5117234Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfiIop) 5127234Sgblack@eecs.umich.edu exec_output += QuiescePredOpExecute.subst(wfiIop) 5137234Sgblack@eecs.umich.edu 5147234Sgblack@eecs.umich.edu sevCode = ''' 5157234Sgblack@eecs.umich.edu // Need a way for O3 to not scoreboard these accesses as pipe flushes. 5167234Sgblack@eecs.umich.edu SevMailbox = 1; 5177234Sgblack@eecs.umich.edu System *sys = xc->tcBase()->getSystemPtr(); 5187234Sgblack@eecs.umich.edu for (int x = 0; x < sys->numContexts(); x++) { 5197234Sgblack@eecs.umich.edu ThreadContext *oc = sys->getThreadContext(x); 5207234Sgblack@eecs.umich.edu if (oc != xc->tcBase()) { 5217234Sgblack@eecs.umich.edu oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5227234Sgblack@eecs.umich.edu } 5237234Sgblack@eecs.umich.edu } 5247234Sgblack@eecs.umich.edu ''' 5257234Sgblack@eecs.umich.edu sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 5267234Sgblack@eecs.umich.edu { "code" : sevCode, "predicate_test" : predicateTest }, 5277234Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsSquashAfter"]) 5287234Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sevIop) 5297234Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sevIop) 5307234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sevIop) 5317234Sgblack@eecs.umich.edu 5327234Sgblack@eecs.umich.edu itIop = InstObjParams("it", "ItInst", "PredOp", \ 5337234Sgblack@eecs.umich.edu { "code" : ";", 5347234Sgblack@eecs.umich.edu "predicate_test" : predicateTest }, 5357234Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsSerializeAfter"]) 5367234Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(itIop) 5377234Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(itIop) 5387234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(itIop) 5397234Sgblack@eecs.umich.edu unknownCode = ''' 5407234Sgblack@eecs.umich.edu#if FULL_SYSTEM 5417234Sgblack@eecs.umich.edu return new UndefinedInstruction; 5427234Sgblack@eecs.umich.edu#else 5437234Sgblack@eecs.umich.edu return new UndefinedInstruction(machInst, true); 5447234Sgblack@eecs.umich.edu#endif 5457234Sgblack@eecs.umich.edu ''' 5467234Sgblack@eecs.umich.edu unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 5477234Sgblack@eecs.umich.edu { "code": unknownCode, 5487234Sgblack@eecs.umich.edu "predicate_test": predicateTest }) 5497234Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(unknownIop) 5507234Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(unknownIop) 5517234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(unknownIop) 5527234Sgblack@eecs.umich.edu 5537234Sgblack@eecs.umich.edu ubfxCode = ''' 5547234Sgblack@eecs.umich.edu Dest = bits(Op1, imm2, imm1); 5557234Sgblack@eecs.umich.edu ''' 5567234Sgblack@eecs.umich.edu ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 5577234Sgblack@eecs.umich.edu { "code": ubfxCode, 5587234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5597234Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 5607234Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 5617234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ubfxIop) 5627234Sgblack@eecs.umich.edu 5637234Sgblack@eecs.umich.edu sbfxCode = ''' 5647234Sgblack@eecs.umich.edu int32_t resTemp = bits(Op1, imm2, imm1); 5657234Sgblack@eecs.umich.edu Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 5667234Sgblack@eecs.umich.edu ''' 5677234Sgblack@eecs.umich.edu sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 5687234Sgblack@eecs.umich.edu { "code": sbfxCode, 5698588Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5707234Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 5717234Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 5727234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sbfxIop) 5737234Sgblack@eecs.umich.edu 5747234Sgblack@eecs.umich.edu bfcCode = ''' 5757234Sgblack@eecs.umich.edu Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 5767234Sgblack@eecs.umich.edu ''' 5778588Sgblack@eecs.umich.edu bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 5787234Sgblack@eecs.umich.edu { "code": bfcCode, 5797234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5807234Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfcIop) 5817234Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 5827234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfcIop) 5837234Sgblack@eecs.umich.edu 5847234Sgblack@eecs.umich.edu bfiCode = ''' 5857234Sgblack@eecs.umich.edu uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 5867234Sgblack@eecs.umich.edu Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 5877234Sgblack@eecs.umich.edu ''' 5887234Sgblack@eecs.umich.edu bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 5897234Sgblack@eecs.umich.edu { "code": bfiCode, 5907234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5917234Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfiIop) 5927234Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 5937234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfiIop) 5947234Sgblack@eecs.umich.edu 5957234Sgblack@eecs.umich.edu mrc15code = ''' 5967234Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 5977234Sgblack@eecs.umich.edu if (cpsr.mode == MODE_USER) 5987234Sgblack@eecs.umich.edu#if FULL_SYSTEM 5997234Sgblack@eecs.umich.edu return new UndefinedInstruction; 6007234Sgblack@eecs.umich.edu#else 6017234Sgblack@eecs.umich.edu return new UndefinedInstruction(false, mnemonic); 6027234Sgblack@eecs.umich.edu#endif 6037234Sgblack@eecs.umich.edu Dest = MiscOp1; 6047234Sgblack@eecs.umich.edu ''' 6057234Sgblack@eecs.umich.edu 6067234Sgblack@eecs.umich.edu mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 6077234Sgblack@eecs.umich.edu { "code": mrc15code, 6087234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6097234Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15Iop) 6107234Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15Iop) 6117234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15Iop) 6127234Sgblack@eecs.umich.edu 6137234Sgblack@eecs.umich.edu 6147234Sgblack@eecs.umich.edu mcr15code = ''' 6157234Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 6167234Sgblack@eecs.umich.edu if (cpsr.mode == MODE_USER) 6177234Sgblack@eecs.umich.edu#if FULL_SYSTEM 6187234Sgblack@eecs.umich.edu return new UndefinedInstruction; 6197234Sgblack@eecs.umich.edu#else 6207234Sgblack@eecs.umich.edu return new UndefinedInstruction(false, mnemonic); 6217234Sgblack@eecs.umich.edu#endif 6227234Sgblack@eecs.umich.edu MiscDest = Op1; 6237234Sgblack@eecs.umich.edu ''' 6247234Sgblack@eecs.umich.edu mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 6257234Sgblack@eecs.umich.edu { "code": mcr15code, 6267234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 6277234Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 6287234Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15Iop) 6297234Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15Iop) 6307234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15Iop) 6317234Sgblack@eecs.umich.edu 6327234Sgblack@eecs.umich.edu mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 6337234Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 6347234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6357234Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15UserIop) 6367239Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 6377239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15UserIop) 6387239Sgblack@eecs.umich.edu 6397239Sgblack@eecs.umich.edu mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 6407239Sgblack@eecs.umich.edu { "code": "MiscDest = Op1", 6417239Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 6427239Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 6438303SAli.Saidi@ARM.com header_output += RegRegOpDeclare.subst(mcr15UserIop) 6447239Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 6457239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15UserIop) 6467239Sgblack@eecs.umich.edu 6477239Sgblack@eecs.umich.edu enterxCode = ''' 6487239Sgblack@eecs.umich.edu NextThumb = true; 6497239Sgblack@eecs.umich.edu NextJazelle = true; 6508303SAli.Saidi@ARM.com ''' 6517239Sgblack@eecs.umich.edu enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 6527239Sgblack@eecs.umich.edu { "code": enterxCode, 6537239Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6547242Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(enterxIop) 6557242Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(enterxIop) 6567242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(enterxIop) 6577242Sgblack@eecs.umich.edu 6587242Sgblack@eecs.umich.edu leavexCode = ''' 6597242Sgblack@eecs.umich.edu NextThumb = true; 6607242Sgblack@eecs.umich.edu NextJazelle = false; 6617242Sgblack@eecs.umich.edu ''' 6627242Sgblack@eecs.umich.edu leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 6637242Sgblack@eecs.umich.edu { "code": leavexCode, 6647242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6657242Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(leavexIop) 6667242Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(leavexIop) 6677242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(leavexIop) 6687242Sgblack@eecs.umich.edu 6697242Sgblack@eecs.umich.edu setendCode = ''' 6707242Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 6717242Sgblack@eecs.umich.edu cpsr.e = imm; 6727242Sgblack@eecs.umich.edu Cpsr = cpsr; 6737242Sgblack@eecs.umich.edu ''' 6747242Sgblack@eecs.umich.edu setendIop = InstObjParams("setend", "Setend", "ImmOp", 6757242Sgblack@eecs.umich.edu { "code": setendCode, 6767242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 6777242Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 6787242Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(setendIop) 6797242Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(setendIop) 6807242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(setendIop) 6817242Sgblack@eecs.umich.edu 6827242Sgblack@eecs.umich.edu clrexCode = ''' 6837242Sgblack@eecs.umich.edu LLSCLock = 0; 6847242Sgblack@eecs.umich.edu ''' 6857242Sgblack@eecs.umich.edu clrexIop = InstObjParams("clrex", "Clrex","PredOp", 6867242Sgblack@eecs.umich.edu { "code": clrexCode, 6877242Sgblack@eecs.umich.edu "predicate_test": predicateTest },[]) 6887242Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(clrexIop) 6897242Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(clrexIop) 6907247Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clrexIop) 69110474Sandreas.hansson@arm.com 6927848SAli.Saidi@ARM.com isbCode = ''' 6937410Sgblack@eecs.umich.edu fault = new FlushPipe; 6947410Sgblack@eecs.umich.edu ''' 6957410Sgblack@eecs.umich.edu isbIop = InstObjParams("isb", "Isb", "PredOp", 6967410Sgblack@eecs.umich.edu {"code": isbCode, 69710037SARM gem5 Developers "predicate_test": predicateTest}, 6987247Sgblack@eecs.umich.edu ['IsSerializeAfter']) 69910037SARM gem5 Developers header_output += BasicDeclare.subst(isbIop) 70010037SARM gem5 Developers decoder_output += BasicConstructor.subst(isbIop) 7017408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(isbIop) 7027418Sgblack@eecs.umich.edu 7037418Sgblack@eecs.umich.edu dsbCode = ''' 7047418Sgblack@eecs.umich.edu fault = new FlushPipe; 7057418Sgblack@eecs.umich.edu ''' 7067418Sgblack@eecs.umich.edu dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 7077418Sgblack@eecs.umich.edu {"code": dsbCode, 7087418Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 70910037SARM gem5 Developers ['IsMemBarrier', 'IsSerializeAfter']) 71010037SARM gem5 Developers header_output += BasicDeclare.subst(dsbIop) 71110037SARM gem5 Developers decoder_output += BasicConstructor.subst(dsbIop) 71210037SARM gem5 Developers exec_output += PredOpExecute.subst(dsbIop) 71310037SARM gem5 Developers 7148285SPrakash.Ramrakhyani@arm.com dmbCode = ''' 7157418Sgblack@eecs.umich.edu ''' 71610037SARM gem5 Developers dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 71711150Smitch.hayenga@arm.com {"code": dmbCode, 71811150Smitch.hayenga@arm.com "predicate_test": predicateTest}, 71910037SARM gem5 Developers ['IsMemBarrier']) 7208285SPrakash.Ramrakhyani@arm.com header_output += BasicDeclare.subst(dmbIop) 72112403Sgiacomo.travaglini@arm.com decoder_output += BasicConstructor.subst(dmbIop) 72212403Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(dmbIop) 72312403Sgiacomo.travaglini@arm.com 72412403Sgiacomo.travaglini@arm.com dbgCode = ''' 72512403Sgiacomo.travaglini@arm.com ''' 72612403Sgiacomo.travaglini@arm.com dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 7278142SAli.Saidi@ARM.com {"code": dbgCode, 7287418Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 7298518Sgeoffrey.blake@arm.com header_output += BasicDeclare.subst(dbgIop) 7308518Sgeoffrey.blake@arm.com decoder_output += BasicConstructor.subst(dbgIop) 7318518Sgeoffrey.blake@arm.com exec_output += PredOpExecute.subst(dbgIop) 7328518Sgeoffrey.blake@arm.com 7338518Sgeoffrey.blake@arm.com cpsCode = ''' 7347418Sgblack@eecs.umich.edu uint32_t mode = bits(imm, 4, 0); 7358518Sgeoffrey.blake@arm.com uint32_t f = bits(imm, 5); 7368518Sgeoffrey.blake@arm.com uint32_t i = bits(imm, 6); 7378518Sgeoffrey.blake@arm.com uint32_t a = bits(imm, 7); 7388733Sgeoffrey.blake@arm.com bool setMode = bits(imm, 8); 7398733Sgeoffrey.blake@arm.com bool enable = bits(imm, 9); 7407418Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 7417418Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 7428518Sgeoffrey.blake@arm.com if (cpsr.mode != MODE_USER) { 7437418Sgblack@eecs.umich.edu if (enable) { 7447418Sgblack@eecs.umich.edu if (f) cpsr.f = 0; 74510037SARM gem5 Developers if (i) cpsr.i = 0; 74610037SARM gem5 Developers if (a) cpsr.a = 0; 74710037SARM gem5 Developers } else { 74810037SARM gem5 Developers if (f && !sctlr.nmfi) cpsr.f = 1; 7498285SPrakash.Ramrakhyani@arm.com if (i) cpsr.i = 1; 75010037SARM gem5 Developers if (a) cpsr.a = 1; 75111150Smitch.hayenga@arm.com } 75211150Smitch.hayenga@arm.com if (setMode) { 75310037SARM gem5 Developers cpsr.mode = mode; 7548285SPrakash.Ramrakhyani@arm.com } 75512403Sgiacomo.travaglini@arm.com } 75612403Sgiacomo.travaglini@arm.com Cpsr = cpsr; 75712403Sgiacomo.travaglini@arm.com ''' 75812403Sgiacomo.travaglini@arm.com cpsIop = InstObjParams("cps", "Cps", "ImmOp", 75912403Sgiacomo.travaglini@arm.com { "code": cpsCode, 76012403Sgiacomo.travaglini@arm.com "predicate_test": predicateTest }, 7618285SPrakash.Ramrakhyani@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 76211150Smitch.hayenga@arm.com header_output += ImmOpDeclare.subst(cpsIop) 7637418Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(cpsIop) 7647418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(cpsIop) 7657418Sgblack@eecs.umich.edu}}; 7668733Sgeoffrey.blake@arm.com