misc.isa revision 7848
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 37199Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 437199Sgblack@eecs.umich.edu#if FULL_SYSTEM 447199Sgblack@eecs.umich.edu fault = new SupervisorCall; 457199Sgblack@eecs.umich.edu#else 467199Sgblack@eecs.umich.edu fault = new SupervisorCall(machInst); 477199Sgblack@eecs.umich.edu#endif 487199Sgblack@eecs.umich.edu ''' 497199Sgblack@eecs.umich.edu 507199Sgblack@eecs.umich.edu svcIop = InstObjParams("svc", "Svc", "PredOp", 517199Sgblack@eecs.umich.edu { "code": svcCode, 527199Sgblack@eecs.umich.edu "predicate_test": predicateTest }, ["IsSyscall"]) 537199Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(svcIop) 547199Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(svcIop) 557199Sgblack@eecs.umich.edu exec_output = PredOpExecute.subst(svcIop) 567199Sgblack@eecs.umich.edu 577199Sgblack@eecs.umich.edu}}; 587202Sgblack@eecs.umich.edu 597202Sgblack@eecs.umich.edulet {{ 607202Sgblack@eecs.umich.edu 617202Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 627202Sgblack@eecs.umich.edu 637202Sgblack@eecs.umich.edu mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF" 647202Sgblack@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 657202Sgblack@eecs.umich.edu { "code": mrsCpsrCode, 667599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 677783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 687202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsCpsrIop) 697202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 707202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 717202Sgblack@eecs.umich.edu 727202Sgblack@eecs.umich.edu mrsSpsrCode = "Dest = Spsr" 737202Sgblack@eecs.umich.edu mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 747202Sgblack@eecs.umich.edu { "code": mrsSpsrCode, 757599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 767783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 777202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsSpsrIop) 787202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 797202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsSpsrIop) 807202Sgblack@eecs.umich.edu 817202Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 827400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 837202Sgblack@eecs.umich.edu uint32_t newCpsr = 847400SAli.Saidi@ARM.com cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); 857202Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 867797Sgblack@eecs.umich.edu NextThumb = ((CPSR)newCpsr).t; 877797Sgblack@eecs.umich.edu NextJazelle = ((CPSR)newCpsr).j; 887202Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 897202Sgblack@eecs.umich.edu ''' 907202Sgblack@eecs.umich.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 917202Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 927599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 937599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 947202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrCpsrRegIop) 957202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 967202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrRegIop) 977202Sgblack@eecs.umich.edu 987202Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 997202Sgblack@eecs.umich.edu msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 1007202Sgblack@eecs.umich.edu { "code": msrSpsrRegCode, 1017599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1027599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1037202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrSpsrRegIop) 1047202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 1057202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrRegIop) 1067202Sgblack@eecs.umich.edu 1077202Sgblack@eecs.umich.edu msrCpsrImmCode = ''' 1087400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 1097202Sgblack@eecs.umich.edu uint32_t newCpsr = 1107400SAli.Saidi@ARM.com cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); 1117202Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 1127797Sgblack@eecs.umich.edu NextThumb = ((CPSR)newCpsr).t; 1137797Sgblack@eecs.umich.edu NextJazelle = ((CPSR)newCpsr).j; 1147202Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 1157202Sgblack@eecs.umich.edu ''' 1167202Sgblack@eecs.umich.edu msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 1177202Sgblack@eecs.umich.edu { "code": msrCpsrImmCode, 1187599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 1197599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1207202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrCpsrImmIop) 1217202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 1227202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrImmIop) 1237202Sgblack@eecs.umich.edu 1247202Sgblack@eecs.umich.edu msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 1257202Sgblack@eecs.umich.edu msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 1267202Sgblack@eecs.umich.edu { "code": msrSpsrImmCode, 1277599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1287599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1297202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrSpsrImmIop) 1307202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 1317202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrImmIop) 1327209Sgblack@eecs.umich.edu 1337209Sgblack@eecs.umich.edu revCode = ''' 1347209Sgblack@eecs.umich.edu uint32_t val = Op1; 1357209Sgblack@eecs.umich.edu Dest = swap_byte(val); 1367209Sgblack@eecs.umich.edu ''' 1377261Sgblack@eecs.umich.edu revIop = InstObjParams("rev", "Rev", "RegRegOp", 1387209Sgblack@eecs.umich.edu { "code": revCode, 1397209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1407261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revIop) 1417261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revIop) 1427209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revIop) 1437209Sgblack@eecs.umich.edu 1447209Sgblack@eecs.umich.edu rev16Code = ''' 1457209Sgblack@eecs.umich.edu uint32_t val = Op1; 1467209Sgblack@eecs.umich.edu Dest = (bits(val, 15, 8) << 0) | 1477209Sgblack@eecs.umich.edu (bits(val, 7, 0) << 8) | 1487209Sgblack@eecs.umich.edu (bits(val, 31, 24) << 16) | 1497209Sgblack@eecs.umich.edu (bits(val, 23, 16) << 24); 1507209Sgblack@eecs.umich.edu ''' 1517261Sgblack@eecs.umich.edu rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 1527209Sgblack@eecs.umich.edu { "code": rev16Code, 1537209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1547261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rev16Iop) 1557261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rev16Iop) 1567209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rev16Iop) 1577209Sgblack@eecs.umich.edu 1587209Sgblack@eecs.umich.edu revshCode = ''' 1597209Sgblack@eecs.umich.edu uint16_t val = Op1; 1607209Sgblack@eecs.umich.edu Dest = sext<16>(swap_byte(val)); 1617209Sgblack@eecs.umich.edu ''' 1627261Sgblack@eecs.umich.edu revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 1637209Sgblack@eecs.umich.edu { "code": revshCode, 1647209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1657261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revshIop) 1667261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revshIop) 1677209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revshIop) 1687226Sgblack@eecs.umich.edu 1697249Sgblack@eecs.umich.edu rbitCode = ''' 1707249Sgblack@eecs.umich.edu uint8_t *opBytes = (uint8_t *)&Op1; 1717249Sgblack@eecs.umich.edu uint32_t resTemp; 1727249Sgblack@eecs.umich.edu uint8_t *destBytes = (uint8_t *)&resTemp; 1737249Sgblack@eecs.umich.edu // This reverses the bytes and bits of the input, or so says the 1747249Sgblack@eecs.umich.edu // internet. 1757249Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 1767249Sgblack@eecs.umich.edu uint32_t temp = opBytes[i]; 1777249Sgblack@eecs.umich.edu temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 1787249Sgblack@eecs.umich.edu destBytes[3 - i] = (temp * 0x10101) >> 16; 1797249Sgblack@eecs.umich.edu } 1807249Sgblack@eecs.umich.edu Dest = resTemp; 1817249Sgblack@eecs.umich.edu ''' 1827261Sgblack@eecs.umich.edu rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 1837249Sgblack@eecs.umich.edu { "code": rbitCode, 1847249Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1857261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rbitIop) 1867261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rbitIop) 1877249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rbitIop) 1887249Sgblack@eecs.umich.edu 1897251Sgblack@eecs.umich.edu clzCode = ''' 1907251Sgblack@eecs.umich.edu Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 1917251Sgblack@eecs.umich.edu ''' 1927261Sgblack@eecs.umich.edu clzIop = InstObjParams("clz", "Clz", "RegRegOp", 1937251Sgblack@eecs.umich.edu { "code": clzCode, 1947251Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1957261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(clzIop) 1967261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(clzIop) 1977251Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clzIop) 1987251Sgblack@eecs.umich.edu 1997226Sgblack@eecs.umich.edu ssatCode = ''' 2007226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2017226Sgblack@eecs.umich.edu int32_t res; 2027232Sgblack@eecs.umich.edu if (satInt(res, operand, imm)) 2037226Sgblack@eecs.umich.edu CondCodes = CondCodes | (1 << 27); 2047226Sgblack@eecs.umich.edu else 2057226Sgblack@eecs.umich.edu CondCodes = CondCodes; 2067226Sgblack@eecs.umich.edu Dest = res; 2077226Sgblack@eecs.umich.edu ''' 2087232Sgblack@eecs.umich.edu ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 2097226Sgblack@eecs.umich.edu { "code": ssatCode, 2107422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2117232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 2127232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 2137226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssatIop) 2147226Sgblack@eecs.umich.edu 2157226Sgblack@eecs.umich.edu usatCode = ''' 2167226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2177226Sgblack@eecs.umich.edu int32_t res; 2187232Sgblack@eecs.umich.edu if (uSatInt(res, operand, imm)) 2197226Sgblack@eecs.umich.edu CondCodes = CondCodes | (1 << 27); 2207226Sgblack@eecs.umich.edu else 2217226Sgblack@eecs.umich.edu CondCodes = CondCodes; 2227226Sgblack@eecs.umich.edu Dest = res; 2237226Sgblack@eecs.umich.edu ''' 2247232Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 2257226Sgblack@eecs.umich.edu { "code": usatCode, 2267422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2277232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(usatIop) 2287232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 2297226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usatIop) 2307226Sgblack@eecs.umich.edu 2317226Sgblack@eecs.umich.edu ssat16Code = ''' 2327226Sgblack@eecs.umich.edu int32_t res; 2337226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2347226Sgblack@eecs.umich.edu CondCodes = CondCodes; 2357226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2367226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2377232Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 2387226Sgblack@eecs.umich.edu CondCodes = CondCodes | (1 << 27); 2397226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2407232Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 2417226Sgblack@eecs.umich.edu CondCodes = CondCodes | (1 << 27); 2427226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2437226Sgblack@eecs.umich.edu Dest = resTemp; 2447226Sgblack@eecs.umich.edu ''' 2457232Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 2467226Sgblack@eecs.umich.edu { "code": ssat16Code, 2477422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2487232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(ssat16Iop) 2497232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 2507226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssat16Iop) 2517226Sgblack@eecs.umich.edu 2527226Sgblack@eecs.umich.edu usat16Code = ''' 2537226Sgblack@eecs.umich.edu int32_t res; 2547226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2557226Sgblack@eecs.umich.edu CondCodes = CondCodes; 2567226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2577226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2587232Sgblack@eecs.umich.edu if (uSatInt(res, argLow, imm)) 2597226Sgblack@eecs.umich.edu CondCodes = CondCodes | (1 << 27); 2607226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2617232Sgblack@eecs.umich.edu if (uSatInt(res, argHigh, imm)) 2627226Sgblack@eecs.umich.edu CondCodes = CondCodes | (1 << 27); 2637226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2647226Sgblack@eecs.umich.edu Dest = resTemp; 2657226Sgblack@eecs.umich.edu ''' 2667232Sgblack@eecs.umich.edu usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 2677226Sgblack@eecs.umich.edu { "code": usat16Code, 2687422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 2697232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(usat16Iop) 2707232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 2717226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usat16Iop) 2727234Sgblack@eecs.umich.edu 2737234Sgblack@eecs.umich.edu sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 2747234Sgblack@eecs.umich.edu { "code": 2757234Sgblack@eecs.umich.edu "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 2767234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2777234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtbIop) 2787234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 2797234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtbIop) 2807234Sgblack@eecs.umich.edu 2817234Sgblack@eecs.umich.edu sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 2827234Sgblack@eecs.umich.edu { "code": 2837234Sgblack@eecs.umich.edu ''' 2847234Sgblack@eecs.umich.edu Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 2857234Sgblack@eecs.umich.edu Op1; 2867234Sgblack@eecs.umich.edu ''', 2877234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2887234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 2897234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 2907234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtabIop) 2917234Sgblack@eecs.umich.edu 2927234Sgblack@eecs.umich.edu sxtb16Code = ''' 2937234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2947234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 2957234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 2967234Sgblack@eecs.umich.edu sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 2977234Sgblack@eecs.umich.edu Dest = resTemp; 2987234Sgblack@eecs.umich.edu ''' 2997234Sgblack@eecs.umich.edu sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 3007234Sgblack@eecs.umich.edu { "code": sxtb16Code, 3017234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3027234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 3037234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 3047234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtb16Iop) 3057234Sgblack@eecs.umich.edu 3067234Sgblack@eecs.umich.edu sxtab16Code = ''' 3077234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3087234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 3097234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3107234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3117234Sgblack@eecs.umich.edu sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3127234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3137234Sgblack@eecs.umich.edu Dest = resTemp; 3147234Sgblack@eecs.umich.edu ''' 3157234Sgblack@eecs.umich.edu sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 3167234Sgblack@eecs.umich.edu { "code": sxtab16Code, 3177234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3187234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 3197234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 3207234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtab16Iop) 3217234Sgblack@eecs.umich.edu 3227234Sgblack@eecs.umich.edu sxthCode = ''' 3237234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 3247234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3257234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 3267234Sgblack@eecs.umich.edu ''' 3277234Sgblack@eecs.umich.edu sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 3287234Sgblack@eecs.umich.edu { "code": sxthCode, 3297234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3307234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 3317234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 3327234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 3337234Sgblack@eecs.umich.edu 3347234Sgblack@eecs.umich.edu sxtahCode = ''' 3357234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 3367234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3377234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated) + Op1; 3387234Sgblack@eecs.umich.edu ''' 3397234Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 3407234Sgblack@eecs.umich.edu { "code": sxtahCode, 3417234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3427234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 3437234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 3447234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtahIop) 3457234Sgblack@eecs.umich.edu 3467234Sgblack@eecs.umich.edu uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 3477234Sgblack@eecs.umich.edu { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 3487234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3497234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtbIop) 3507234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 3517234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtbIop) 3527234Sgblack@eecs.umich.edu 3537234Sgblack@eecs.umich.edu uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 3547234Sgblack@eecs.umich.edu { "code": 3557234Sgblack@eecs.umich.edu "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 3567234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3577234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 3587234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 3597234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 3607234Sgblack@eecs.umich.edu 3617234Sgblack@eecs.umich.edu uxtb16Code = ''' 3627234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3637234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 3647234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3657234Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 3667234Sgblack@eecs.umich.edu Dest = resTemp; 3677234Sgblack@eecs.umich.edu ''' 3687234Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 3697234Sgblack@eecs.umich.edu { "code": uxtb16Code, 3707234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3717234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 3727234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 3737234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtb16Iop) 3747234Sgblack@eecs.umich.edu 3757234Sgblack@eecs.umich.edu uxtab16Code = ''' 3767234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3777234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 3787234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3797234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3807234Sgblack@eecs.umich.edu (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3817234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3827234Sgblack@eecs.umich.edu Dest = resTemp; 3837234Sgblack@eecs.umich.edu ''' 3847234Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 3857234Sgblack@eecs.umich.edu { "code": uxtab16Code, 3867234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3877234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 3887234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 3897234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 3907234Sgblack@eecs.umich.edu 3917234Sgblack@eecs.umich.edu uxthCode = ''' 3927234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 3937234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3947234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated; 3957234Sgblack@eecs.umich.edu ''' 3967234Sgblack@eecs.umich.edu uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 3977234Sgblack@eecs.umich.edu { "code": uxthCode, 3987234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3997234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxthIop) 4007234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxthIop) 4017234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxthIop) 4027234Sgblack@eecs.umich.edu 4037234Sgblack@eecs.umich.edu uxtahCode = ''' 4047234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 4057234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4067234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 4077234Sgblack@eecs.umich.edu ''' 4087234Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 4097234Sgblack@eecs.umich.edu { "code": uxtahCode, 4107234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4117234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 4127234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 4137234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 4147239Sgblack@eecs.umich.edu 4157239Sgblack@eecs.umich.edu selCode = ''' 4167239Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4177239Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4187239Sgblack@eecs.umich.edu int low = i * 8; 4197239Sgblack@eecs.umich.edu int high = low + 7; 4207239Sgblack@eecs.umich.edu replaceBits(resTemp, high, low, 4217239Sgblack@eecs.umich.edu bits(CondCodes, 16 + i) ? 4227239Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 4237239Sgblack@eecs.umich.edu } 4247239Sgblack@eecs.umich.edu Dest = resTemp; 4257239Sgblack@eecs.umich.edu ''' 4267239Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 4277239Sgblack@eecs.umich.edu { "code": selCode, 4287422Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, []) 4297239Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 4307239Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 4317239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 4327242Sgblack@eecs.umich.edu 4337242Sgblack@eecs.umich.edu usad8Code = ''' 4347242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4357242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4367242Sgblack@eecs.umich.edu int low = i * 8; 4377242Sgblack@eecs.umich.edu int high = low + 7; 4387242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4397242Sgblack@eecs.umich.edu bits(Op2, high, low); 4407242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4417242Sgblack@eecs.umich.edu } 4427242Sgblack@eecs.umich.edu Dest = resTemp; 4437242Sgblack@eecs.umich.edu ''' 4447242Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 4457242Sgblack@eecs.umich.edu { "code": usad8Code, 4467242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4477242Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 4487242Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 4497242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usad8Iop) 4507242Sgblack@eecs.umich.edu 4517242Sgblack@eecs.umich.edu usada8Code = ''' 4527242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4537242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4547242Sgblack@eecs.umich.edu int low = i * 8; 4557242Sgblack@eecs.umich.edu int high = low + 7; 4567242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4577242Sgblack@eecs.umich.edu bits(Op2, high, low); 4587242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4597242Sgblack@eecs.umich.edu } 4607242Sgblack@eecs.umich.edu Dest = Op3 + resTemp; 4617242Sgblack@eecs.umich.edu ''' 4627242Sgblack@eecs.umich.edu usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 4637242Sgblack@eecs.umich.edu { "code": usada8Code, 4647242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4657242Sgblack@eecs.umich.edu header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 4667242Sgblack@eecs.umich.edu decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 4677242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usada8Iop) 4687247Sgblack@eecs.umich.edu 4697797Sgblack@eecs.umich.edu bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 4707848SAli.Saidi@ARM.com bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 4717410Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(bkptIop) 4727410Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(bkptIop) 4737410Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(bkptIop) 4747410Sgblack@eecs.umich.edu 4757408Sgblack@eecs.umich.edu nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 4767408Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 4777247Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(nopIop) 4787247Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(nopIop) 4797408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(nopIop) 4807408Sgblack@eecs.umich.edu 4817418Sgblack@eecs.umich.edu yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 4827418Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 4837418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(yieldIop) 4847418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(yieldIop) 4857418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(yieldIop) 4867418Sgblack@eecs.umich.edu 4877418Sgblack@eecs.umich.edu wfeCode = ''' 4887418Sgblack@eecs.umich.edu#if FULL_SYSTEM 4897418Sgblack@eecs.umich.edu if (SevMailbox) 4907418Sgblack@eecs.umich.edu SevMailbox = 0; 4917418Sgblack@eecs.umich.edu else 4927418Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 4937418Sgblack@eecs.umich.edu#endif 4947418Sgblack@eecs.umich.edu ''' 4957418Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 4967418Sgblack@eecs.umich.edu { "code" : wfeCode, "predicate_test" : predicateTest }, 4977648SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 4987418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 4997418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfeIop) 5007418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(wfeIop) 5017418Sgblack@eecs.umich.edu 5027418Sgblack@eecs.umich.edu wfiCode = ''' 5037418Sgblack@eecs.umich.edu#if FULL_SYSTEM 5047418Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 5057418Sgblack@eecs.umich.edu#endif 5067418Sgblack@eecs.umich.edu ''' 5077418Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 5087418Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 5097418Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsQuiesce"]) 5107418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfiIop) 5117418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfiIop) 5127418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(wfiIop) 5137418Sgblack@eecs.umich.edu 5147418Sgblack@eecs.umich.edu sevCode = ''' 5157418Sgblack@eecs.umich.edu // Need a way for O3 to not scoreboard these accesses as pipe flushes. 5167418Sgblack@eecs.umich.edu System *sys = xc->tcBase()->getSystemPtr(); 5177418Sgblack@eecs.umich.edu for (int x = 0; x < sys->numContexts(); x++) { 5187418Sgblack@eecs.umich.edu ThreadContext *oc = sys->getThreadContext(x); 5197418Sgblack@eecs.umich.edu oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5207418Sgblack@eecs.umich.edu } 5217418Sgblack@eecs.umich.edu ''' 5227418Sgblack@eecs.umich.edu sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 5237418Sgblack@eecs.umich.edu { "code" : sevCode, "predicate_test" : predicateTest }, 5247648SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 5257418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sevIop) 5267418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sevIop) 5277418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sevIop) 5287418Sgblack@eecs.umich.edu 5297408Sgblack@eecs.umich.edu itIop = InstObjParams("it", "ItInst", "PredOp", \ 5307408Sgblack@eecs.umich.edu { "code" : "Itstate = machInst.newItstate;", 5317648SAli.Saidi@ARM.com "predicate_test" : predicateTest }, 5327648SAli.Saidi@ARM.com ["IsNonSpeculative", "IsSerializeAfter"]) 5337408Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(itIop) 5347408Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(itIop) 5357408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(itIop) 5367409Sgblack@eecs.umich.edu unknownCode = ''' 5377409Sgblack@eecs.umich.edu#if FULL_SYSTEM 5387409Sgblack@eecs.umich.edu return new UndefinedInstruction; 5397409Sgblack@eecs.umich.edu#else 5407409Sgblack@eecs.umich.edu return new UndefinedInstruction(machInst, true); 5417409Sgblack@eecs.umich.edu#endif 5427409Sgblack@eecs.umich.edu ''' 5437409Sgblack@eecs.umich.edu unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 5447409Sgblack@eecs.umich.edu { "code": unknownCode, 5457409Sgblack@eecs.umich.edu "predicate_test": predicateTest }) 5467409Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(unknownIop) 5477409Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(unknownIop) 5487409Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(unknownIop) 5497254Sgblack@eecs.umich.edu 5507254Sgblack@eecs.umich.edu ubfxCode = ''' 5517254Sgblack@eecs.umich.edu Dest = bits(Op1, imm2, imm1); 5527254Sgblack@eecs.umich.edu ''' 5537254Sgblack@eecs.umich.edu ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 5547254Sgblack@eecs.umich.edu { "code": ubfxCode, 5557254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5567254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 5577254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 5587254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ubfxIop) 5597254Sgblack@eecs.umich.edu 5607254Sgblack@eecs.umich.edu sbfxCode = ''' 5617254Sgblack@eecs.umich.edu int32_t resTemp = bits(Op1, imm2, imm1); 5627254Sgblack@eecs.umich.edu Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 5637254Sgblack@eecs.umich.edu ''' 5647254Sgblack@eecs.umich.edu sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 5657254Sgblack@eecs.umich.edu { "code": sbfxCode, 5667254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5677254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 5687254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 5697254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sbfxIop) 5707257Sgblack@eecs.umich.edu 5717257Sgblack@eecs.umich.edu bfcCode = ''' 5727257Sgblack@eecs.umich.edu Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 5737257Sgblack@eecs.umich.edu ''' 5747257Sgblack@eecs.umich.edu bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 5757257Sgblack@eecs.umich.edu { "code": bfcCode, 5767257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5777257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfcIop) 5787257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 5797257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfcIop) 5807257Sgblack@eecs.umich.edu 5817257Sgblack@eecs.umich.edu bfiCode = ''' 5827257Sgblack@eecs.umich.edu uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 5837257Sgblack@eecs.umich.edu Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 5847257Sgblack@eecs.umich.edu ''' 5857257Sgblack@eecs.umich.edu bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 5867257Sgblack@eecs.umich.edu { "code": bfiCode, 5877257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5887257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfiIop) 5897257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 5907257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfiIop) 5917262Sgblack@eecs.umich.edu 5927347SAli.Saidi@ARM.com mrc15code = ''' 5937347SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 5947347SAli.Saidi@ARM.com if (cpsr.mode == MODE_USER) 5957347SAli.Saidi@ARM.com#if FULL_SYSTEM 5967347SAli.Saidi@ARM.com return new UndefinedInstruction; 5977347SAli.Saidi@ARM.com#else 5987347SAli.Saidi@ARM.com return new UndefinedInstruction(false, mnemonic); 5997347SAli.Saidi@ARM.com#endif 6007347SAli.Saidi@ARM.com Dest = MiscOp1; 6017347SAli.Saidi@ARM.com ''' 6027347SAli.Saidi@ARM.com 6037262Sgblack@eecs.umich.edu mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 6047347SAli.Saidi@ARM.com { "code": mrc15code, 6057262Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6067262Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15Iop) 6077262Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15Iop) 6087262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15Iop) 6097262Sgblack@eecs.umich.edu 6107347SAli.Saidi@ARM.com 6117347SAli.Saidi@ARM.com mcr15code = ''' 6127347SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 6137347SAli.Saidi@ARM.com if (cpsr.mode == MODE_USER) 6147347SAli.Saidi@ARM.com#if FULL_SYSTEM 6157347SAli.Saidi@ARM.com return new UndefinedInstruction; 6167347SAli.Saidi@ARM.com#else 6177347SAli.Saidi@ARM.com return new UndefinedInstruction(false, mnemonic); 6187347SAli.Saidi@ARM.com#endif 6197347SAli.Saidi@ARM.com MiscDest = Op1; 6207347SAli.Saidi@ARM.com ''' 6217262Sgblack@eecs.umich.edu mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 6227347SAli.Saidi@ARM.com { "code": mcr15code, 6237599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 6247599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 6257262Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15Iop) 6267262Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15Iop) 6277262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15Iop) 6287283Sgblack@eecs.umich.edu 6297420Sgblack@eecs.umich.edu mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 6307420Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 6317420Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6327420Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15UserIop) 6337420Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 6347420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15UserIop) 6357420Sgblack@eecs.umich.edu 6367420Sgblack@eecs.umich.edu mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 6377420Sgblack@eecs.umich.edu { "code": "MiscDest = Op1", 6387599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 6397599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 6407420Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15UserIop) 6417420Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 6427420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15UserIop) 6437420Sgblack@eecs.umich.edu 6447283Sgblack@eecs.umich.edu enterxCode = ''' 6457797Sgblack@eecs.umich.edu NextThumb = true; 6467797Sgblack@eecs.umich.edu NextJazelle = true; 6477283Sgblack@eecs.umich.edu ''' 6487283Sgblack@eecs.umich.edu enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 6497283Sgblack@eecs.umich.edu { "code": enterxCode, 6507283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6517283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(enterxIop) 6527283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(enterxIop) 6537283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(enterxIop) 6547283Sgblack@eecs.umich.edu 6557283Sgblack@eecs.umich.edu leavexCode = ''' 6567797Sgblack@eecs.umich.edu NextThumb = true; 6577797Sgblack@eecs.umich.edu NextJazelle = false; 6587283Sgblack@eecs.umich.edu ''' 6597283Sgblack@eecs.umich.edu leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 6607283Sgblack@eecs.umich.edu { "code": leavexCode, 6617283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6627283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(leavexIop) 6637283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(leavexIop) 6647283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(leavexIop) 6657307Sgblack@eecs.umich.edu 6667307Sgblack@eecs.umich.edu setendCode = ''' 6677307Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 6687307Sgblack@eecs.umich.edu cpsr.e = imm; 6697307Sgblack@eecs.umich.edu Cpsr = cpsr; 6707307Sgblack@eecs.umich.edu ''' 6717307Sgblack@eecs.umich.edu setendIop = InstObjParams("setend", "Setend", "ImmOp", 6727307Sgblack@eecs.umich.edu { "code": setendCode, 6737648SAli.Saidi@ARM.com "predicate_test": predicateTest }, 6747648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 6757307Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(setendIop) 6767307Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(setendIop) 6777307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(setendIop) 6787315Sgblack@eecs.umich.edu 6797603SGene.Wu@arm.com clrexCode = ''' 6807705Sgblack@eecs.umich.edu unsigned memAccessFlags = Request::CLEAR_LL | 6817705Sgblack@eecs.umich.edu ArmISA::TLB::AlignWord | Request::LLSC; 6827603SGene.Wu@arm.com fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); 6837603SGene.Wu@arm.com ''' 6847603SGene.Wu@arm.com clrexIop = InstObjParams("clrex", "Clrex","PredOp", 6857603SGene.Wu@arm.com { "code": clrexCode, 6867603SGene.Wu@arm.com "predicate_test": predicateTest },[]) 6877609SGene.Wu@arm.com header_output += ClrexDeclare.subst(clrexIop) 6887603SGene.Wu@arm.com decoder_output += BasicConstructor.subst(clrexIop) 6897603SGene.Wu@arm.com exec_output += PredOpExecute.subst(clrexIop) 6907609SGene.Wu@arm.com exec_output += ClrexInitiateAcc.subst(clrexIop) 6917609SGene.Wu@arm.com exec_output += ClrexCompleteAcc.subst(clrexIop) 6927603SGene.Wu@arm.com 6937605SGene.Wu@arm.com isbCode = ''' 6947605SGene.Wu@arm.com ''' 6957605SGene.Wu@arm.com isbIop = InstObjParams("isb", "Isb", "PredOp", 6967605SGene.Wu@arm.com {"code": isbCode, 6977605SGene.Wu@arm.com "predicate_test": predicateTest}, ['IsSerializing']) 6987605SGene.Wu@arm.com header_output += BasicDeclare.subst(isbIop) 6997605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(isbIop) 7007605SGene.Wu@arm.com exec_output += PredOpExecute.subst(isbIop) 7017605SGene.Wu@arm.com 7027605SGene.Wu@arm.com dsbCode = ''' 7037605SGene.Wu@arm.com ''' 7047605SGene.Wu@arm.com dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 7057605SGene.Wu@arm.com {"code": dsbCode, 7067605SGene.Wu@arm.com "predicate_test": predicateTest},['IsMemBarrier']) 7077605SGene.Wu@arm.com header_output += BasicDeclare.subst(dsbIop) 7087605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dsbIop) 7097605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dsbIop) 7107605SGene.Wu@arm.com 7117605SGene.Wu@arm.com dmbCode = ''' 7127605SGene.Wu@arm.com ''' 7137605SGene.Wu@arm.com dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 7147605SGene.Wu@arm.com {"code": dmbCode, 7157605SGene.Wu@arm.com "predicate_test": predicateTest},['IsMemBarrier']) 7167605SGene.Wu@arm.com header_output += BasicDeclare.subst(dmbIop) 7177605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dmbIop) 7187605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dmbIop) 7197605SGene.Wu@arm.com 7207613SGene.Wu@arm.com dbgCode = ''' 7217613SGene.Wu@arm.com ''' 7227613SGene.Wu@arm.com dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 7237613SGene.Wu@arm.com {"code": dbgCode, 7247613SGene.Wu@arm.com "predicate_test": predicateTest}) 7257613SGene.Wu@arm.com header_output += BasicDeclare.subst(dbgIop) 7267613SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dbgIop) 7277613SGene.Wu@arm.com exec_output += PredOpExecute.subst(dbgIop) 7287613SGene.Wu@arm.com 7297315Sgblack@eecs.umich.edu cpsCode = ''' 7307315Sgblack@eecs.umich.edu uint32_t mode = bits(imm, 4, 0); 7317315Sgblack@eecs.umich.edu uint32_t f = bits(imm, 5); 7327315Sgblack@eecs.umich.edu uint32_t i = bits(imm, 6); 7337315Sgblack@eecs.umich.edu uint32_t a = bits(imm, 7); 7347315Sgblack@eecs.umich.edu bool setMode = bits(imm, 8); 7357315Sgblack@eecs.umich.edu bool enable = bits(imm, 9); 7367315Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 7377400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 7387315Sgblack@eecs.umich.edu if (cpsr.mode != MODE_USER) { 7397315Sgblack@eecs.umich.edu if (enable) { 7407315Sgblack@eecs.umich.edu if (f) cpsr.f = 0; 7417315Sgblack@eecs.umich.edu if (i) cpsr.i = 0; 7427315Sgblack@eecs.umich.edu if (a) cpsr.a = 0; 7437315Sgblack@eecs.umich.edu } else { 7447400SAli.Saidi@ARM.com if (f && !sctlr.nmfi) cpsr.f = 1; 7457315Sgblack@eecs.umich.edu if (i) cpsr.i = 1; 7467315Sgblack@eecs.umich.edu if (a) cpsr.a = 1; 7477315Sgblack@eecs.umich.edu } 7487315Sgblack@eecs.umich.edu if (setMode) { 7497315Sgblack@eecs.umich.edu cpsr.mode = mode; 7507315Sgblack@eecs.umich.edu } 7517315Sgblack@eecs.umich.edu } 7527315Sgblack@eecs.umich.edu Cpsr = cpsr; 7537315Sgblack@eecs.umich.edu ''' 7547315Sgblack@eecs.umich.edu cpsIop = InstObjParams("cps", "Cps", "ImmOp", 7557315Sgblack@eecs.umich.edu { "code": cpsCode, 7567599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 7577599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 7587315Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(cpsIop) 7597315Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(cpsIop) 7607315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(cpsIop) 7617202Sgblack@eecs.umich.edu}}; 762