misc.isa revision 13999
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 312504Snikos.nikoleris@arm.com// Copyright (c) 2010-2013,2017-2018 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 4312541Sgiacomo.travaglini@arm.com ThreadContext *tc = xc->tcBase(); 4412541Sgiacomo.travaglini@arm.com 4512541Sgiacomo.travaglini@arm.com const auto semihost_imm = Thumb? 0xAB : 0x123456; 4612541Sgiacomo.travaglini@arm.com 4712541Sgiacomo.travaglini@arm.com if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { 4812541Sgiacomo.travaglini@arm.com R0 = ArmSystem::callSemihosting32(tc, R0, R1); 4912541Sgiacomo.travaglini@arm.com } else { 5012541Sgiacomo.travaglini@arm.com fault = std::make_shared<SupervisorCall>(machInst, imm); 5112541Sgiacomo.travaglini@arm.com } 5210037SARM gem5 Developers ''' 5310037SARM gem5 Developers 5410037SARM gem5 Developers svcIop = InstObjParams("svc", "Svc", "ImmOp", 5510037SARM gem5 Developers { "code": svcCode, 5612541Sgiacomo.travaglini@arm.com "predicate_test": predicateTest, 5712541Sgiacomo.travaglini@arm.com "thumb_semihost": '0xAB', 5812541Sgiacomo.travaglini@arm.com "arm_semihost": '0x123456' }, 5912541Sgiacomo.travaglini@arm.com ["IsSyscall", "IsNonSpeculative", 6012541Sgiacomo.travaglini@arm.com "IsSerializeAfter"]) 6110037SARM gem5 Developers header_output = ImmOpDeclare.subst(svcIop) 6212541Sgiacomo.travaglini@arm.com decoder_output = SemihostConstructor.subst(svcIop) 6310037SARM gem5 Developers exec_output = PredOpExecute.subst(svcIop) 6410037SARM gem5 Developers 6512542Sgiacomo.travaglini@arm.com hltCode = ''' 6612542Sgiacomo.travaglini@arm.com ThreadContext *tc = xc->tcBase(); 6712542Sgiacomo.travaglini@arm.com 6812542Sgiacomo.travaglini@arm.com const auto semihost_imm = Thumb? 0x3C : 0xF000; 6912542Sgiacomo.travaglini@arm.com 7012542Sgiacomo.travaglini@arm.com if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { 7112542Sgiacomo.travaglini@arm.com R0 = ArmSystem::callSemihosting32(tc, R0, R1); 7212542Sgiacomo.travaglini@arm.com } else { 7312542Sgiacomo.travaglini@arm.com // HLT instructions aren't implemented, so treat them as undefined 7412542Sgiacomo.travaglini@arm.com // instructions. 7512542Sgiacomo.travaglini@arm.com fault = std::make_shared<UndefinedInstruction>( 7612542Sgiacomo.travaglini@arm.com machInst, false, mnemonic); 7712542Sgiacomo.travaglini@arm.com } 7812542Sgiacomo.travaglini@arm.com ''' 7912542Sgiacomo.travaglini@arm.com 8012542Sgiacomo.travaglini@arm.com hltIop = InstObjParams("hlt", "Hlt", "ImmOp", 8112542Sgiacomo.travaglini@arm.com { "code": hltCode, 8212542Sgiacomo.travaglini@arm.com "predicate_test": predicateTest, 8312542Sgiacomo.travaglini@arm.com "thumb_semihost": '0x3C', 8412542Sgiacomo.travaglini@arm.com "arm_semihost": '0xF000' }, 8512542Sgiacomo.travaglini@arm.com ["IsNonSpeculative"]) 8612542Sgiacomo.travaglini@arm.com header_output += ImmOpDeclare.subst(hltIop) 8712542Sgiacomo.travaglini@arm.com decoder_output += SemihostConstructor.subst(hltIop) 8812542Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(hltIop) 8912542Sgiacomo.travaglini@arm.com 9010037SARM gem5 Developers smcCode = ''' 9110037SARM gem5 Developers HCR hcr = Hcr; 9210037SARM gem5 Developers CPSR cpsr = Cpsr; 9310037SARM gem5 Developers SCR scr = Scr; 9410037SARM gem5 Developers 9510037SARM gem5 Developers if ((cpsr.mode != MODE_USER) && FullSystem) { 9610037SARM gem5 Developers if (ArmSystem::haveVirtualization(xc->tcBase()) && 9710037SARM gem5 Developers !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) { 9810474Sandreas.hansson@arm.com fault = std::make_shared<HypervisorTrap>(machInst, 0, 9910474Sandreas.hansson@arm.com EC_SMC_TO_HYP); 10010037SARM gem5 Developers } else { 10110037SARM gem5 Developers if (scr.scd) { 10210037SARM gem5 Developers fault = disabledFault(); 10310037SARM gem5 Developers } else { 10410474Sandreas.hansson@arm.com fault = std::make_shared<SecureMonitorCall>(machInst); 10510037SARM gem5 Developers } 10610037SARM gem5 Developers } 1078782Sgblack@eecs.umich.edu } else { 10810037SARM gem5 Developers fault = disabledFault(); 1098782Sgblack@eecs.umich.edu } 1107199Sgblack@eecs.umich.edu ''' 1117199Sgblack@eecs.umich.edu 11210037SARM gem5 Developers smcIop = InstObjParams("smc", "Smc", "PredOp", 11310037SARM gem5 Developers { "code": smcCode, 1148628SAli.Saidi@ARM.com "predicate_test": predicateTest }, 11510037SARM gem5 Developers ["IsNonSpeculative", "IsSerializeAfter"]) 11610037SARM gem5 Developers header_output += BasicDeclare.subst(smcIop) 11710037SARM gem5 Developers decoder_output += BasicConstructor.subst(smcIop) 11810037SARM gem5 Developers exec_output += PredOpExecute.subst(smcIop) 11910037SARM gem5 Developers 12010037SARM gem5 Developers hvcCode = ''' 12110037SARM gem5 Developers CPSR cpsr = Cpsr; 12210037SARM gem5 Developers SCR scr = Scr; 12310037SARM gem5 Developers 12410037SARM gem5 Developers // Filter out the various cases where this instruction isn't defined 12510037SARM gem5 Developers if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) || 12610037SARM gem5 Developers (cpsr.mode == MODE_USER) || 12710037SARM gem5 Developers (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { 12810037SARM gem5 Developers fault = disabledFault(); 12910037SARM gem5 Developers } else { 13010474Sandreas.hansson@arm.com fault = std::make_shared<HypervisorCall>(machInst, imm); 13110037SARM gem5 Developers } 13210037SARM gem5 Developers ''' 13310037SARM gem5 Developers 13410037SARM gem5 Developers hvcIop = InstObjParams("hvc", "Hvc", "ImmOp", 13510037SARM gem5 Developers { "code": hvcCode, 13610037SARM gem5 Developers "predicate_test": predicateTest }, 13710037SARM gem5 Developers ["IsNonSpeculative", "IsSerializeAfter"]) 13810037SARM gem5 Developers header_output += ImmOpDeclare.subst(hvcIop) 13910037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(hvcIop) 14010037SARM gem5 Developers exec_output += PredOpExecute.subst(hvcIop) 14110037SARM gem5 Developers 14210037SARM gem5 Developers eretCode = ''' 14310037SARM gem5 Developers SCTLR sctlr = Sctlr; 14410037SARM gem5 Developers CPSR old_cpsr = Cpsr; 14510037SARM gem5 Developers old_cpsr.nz = CondCodesNZ; 14610037SARM gem5 Developers old_cpsr.c = CondCodesC; 14710037SARM gem5 Developers old_cpsr.v = CondCodesV; 14810037SARM gem5 Developers old_cpsr.ge = CondCodesGE; 14910037SARM gem5 Developers 15010037SARM gem5 Developers CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, 15110037SARM gem5 Developers true, sctlr.nmfi, xc->tcBase()); 15210037SARM gem5 Developers Cpsr = ~CondCodesMask & new_cpsr; 15310037SARM gem5 Developers CondCodesNZ = new_cpsr.nz; 15410037SARM gem5 Developers CondCodesC = new_cpsr.c; 15510037SARM gem5 Developers CondCodesV = new_cpsr.v; 15610037SARM gem5 Developers CondCodesGE = new_cpsr.ge; 15710037SARM gem5 Developers 15810037SARM gem5 Developers NextThumb = (new_cpsr).t; 15910037SARM gem5 Developers NextJazelle = (new_cpsr).j; 16010037SARM gem5 Developers NextItState = (((new_cpsr).it2 << 2) & 0xFC) 16110037SARM gem5 Developers | ((new_cpsr).it1 & 0x3); 16210037SARM gem5 Developers 16310037SARM gem5 Developers NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR; 16410037SARM gem5 Developers ''' 16510037SARM gem5 Developers 16610037SARM gem5 Developers eretIop = InstObjParams("eret", "Eret", "PredOp", 16710037SARM gem5 Developers { "code": eretCode, 16810037SARM gem5 Developers "predicate_test": predicateTest }, 16911355Smitch.hayenga@arm.com ["IsNonSpeculative", "IsSerializeAfter", 17011355Smitch.hayenga@arm.com "IsSquashAfter"]) 17110037SARM gem5 Developers header_output += BasicDeclare.subst(eretIop) 17210037SARM gem5 Developers decoder_output += BasicConstructor.subst(eretIop) 17310037SARM gem5 Developers exec_output += PredOpExecute.subst(eretIop) 17410037SARM gem5 Developers 17512258Sgiacomo.travaglini@arm.com crcCode = ''' 17612258Sgiacomo.travaglini@arm.com constexpr uint8_t size_bytes = %(sz)d; 17712258Sgiacomo.travaglini@arm.com constexpr uint32_t poly = %(polynom)s; 17810037SARM gem5 Developers 17912258Sgiacomo.travaglini@arm.com uint32_t data = htole(Op2); 18012258Sgiacomo.travaglini@arm.com auto data_buffer = reinterpret_cast<uint8_t*>(&data); 18112258Sgiacomo.travaglini@arm.com 18212258Sgiacomo.travaglini@arm.com Dest = crc32<poly>( 18312258Sgiacomo.travaglini@arm.com data_buffer, /* Message Register */ 18412258Sgiacomo.travaglini@arm.com Op1, /* Initial Value of the CRC */ 18512258Sgiacomo.travaglini@arm.com size_bytes /* Size of the original Message */ 18612258Sgiacomo.travaglini@arm.com ); 18712258Sgiacomo.travaglini@arm.com ''' 18812258Sgiacomo.travaglini@arm.com 18912258Sgiacomo.travaglini@arm.com def crc32Emit(mnem, implCode, castagnoli, size): 19012258Sgiacomo.travaglini@arm.com global header_output, decoder_output, exec_output 19112258Sgiacomo.travaglini@arm.com 19212258Sgiacomo.travaglini@arm.com if castagnoli: 19312258Sgiacomo.travaglini@arm.com # crc32c instructions 19412258Sgiacomo.travaglini@arm.com poly = "0x1EDC6F41" 19512258Sgiacomo.travaglini@arm.com else: 19612258Sgiacomo.travaglini@arm.com # crc32 instructions 19712258Sgiacomo.travaglini@arm.com poly = "0x04C11DB7" 19812258Sgiacomo.travaglini@arm.com 19912258Sgiacomo.travaglini@arm.com data = {'sz' : size, 'polynom': poly} 20012258Sgiacomo.travaglini@arm.com 20112258Sgiacomo.travaglini@arm.com instCode = implCode % data 20212258Sgiacomo.travaglini@arm.com 20312258Sgiacomo.travaglini@arm.com crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp", 20412258Sgiacomo.travaglini@arm.com { "code": instCode, 20512258Sgiacomo.travaglini@arm.com "predicate_test": predicateTest }, []) 20612258Sgiacomo.travaglini@arm.com header_output += RegRegRegOpDeclare.subst(crcIop) 20712258Sgiacomo.travaglini@arm.com decoder_output += RegRegRegOpConstructor.subst(crcIop) 20812258Sgiacomo.travaglini@arm.com exec_output += PredOpExecute.subst(crcIop) 20912258Sgiacomo.travaglini@arm.com 21012258Sgiacomo.travaglini@arm.com crc32Emit("crc32b", crcCode, False, 1); 21112258Sgiacomo.travaglini@arm.com crc32Emit("crc32h", crcCode, False, 2); 21212258Sgiacomo.travaglini@arm.com crc32Emit("crc32w", crcCode, False, 4); 21312258Sgiacomo.travaglini@arm.com crc32Emit("crc32cb", crcCode, True, 1); 21412258Sgiacomo.travaglini@arm.com crc32Emit("crc32ch", crcCode, True, 2); 21512258Sgiacomo.travaglini@arm.com crc32Emit("crc32cw", crcCode, True, 4); 2167199Sgblack@eecs.umich.edu 2177199Sgblack@eecs.umich.edu}}; 2187202Sgblack@eecs.umich.edu 2197202Sgblack@eecs.umich.edulet {{ 2207202Sgblack@eecs.umich.edu 2217202Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 2227202Sgblack@eecs.umich.edu 2238301SAli.Saidi@ARM.com mrsCpsrCode = ''' 2248303SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 2258303SAli.Saidi@ARM.com cpsr.nz = CondCodesNZ; 2268303SAli.Saidi@ARM.com cpsr.c = CondCodesC; 2278303SAli.Saidi@ARM.com cpsr.v = CondCodesV; 2288303SAli.Saidi@ARM.com cpsr.ge = CondCodesGE; 22912762Sgiacomo.travaglini@arm.com Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask); 2308301SAli.Saidi@ARM.com ''' 2318301SAli.Saidi@ARM.com 2327202Sgblack@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 2337202Sgblack@eecs.umich.edu { "code": mrsCpsrCode, 2347599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 2357783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2367202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsCpsrIop) 2377202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 2387202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 2397202Sgblack@eecs.umich.edu 2407202Sgblack@eecs.umich.edu mrsSpsrCode = "Dest = Spsr" 2417202Sgblack@eecs.umich.edu mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 2427202Sgblack@eecs.umich.edu { "code": mrsSpsrCode, 2437599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 2447783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2457202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsSpsrIop) 2467202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 2477202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsSpsrIop) 2487202Sgblack@eecs.umich.edu 24910037SARM gem5 Developers mrsBankedRegCode = ''' 25010037SARM gem5 Developers bool isIntReg; 25110037SARM gem5 Developers int regIdx; 25210037SARM gem5 Developers 25310037SARM gem5 Developers if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 25410037SARM gem5 Developers if (isIntReg) { 25510037SARM gem5 Developers Dest = DecodedBankedIntReg; 25610037SARM gem5 Developers } else { 25710037SARM gem5 Developers Dest = xc->readMiscReg(regIdx); 25810037SARM gem5 Developers } 25910037SARM gem5 Developers } else { 26010474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 26110474Sandreas.hansson@arm.com mnemonic); 26210037SARM gem5 Developers } 26310037SARM gem5 Developers ''' 26410037SARM gem5 Developers mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp", 26510037SARM gem5 Developers { "code": mrsBankedRegCode, 26610037SARM gem5 Developers "predicate_test": predicateTest }, 26710037SARM gem5 Developers ["IsSerializeBefore"]) 26810037SARM gem5 Developers header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop) 26910037SARM gem5 Developers decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop) 27010037SARM gem5 Developers exec_output += PredOpExecute.subst(mrsBankedRegIop) 27110037SARM gem5 Developers 27210037SARM gem5 Developers msrBankedRegCode = ''' 27310037SARM gem5 Developers bool isIntReg; 27410037SARM gem5 Developers int regIdx; 27510037SARM gem5 Developers 27610037SARM gem5 Developers if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 27710037SARM gem5 Developers if (isIntReg) { 27810037SARM gem5 Developers // This is a bit nasty, you would have thought that 27910037SARM gem5 Developers // DecodedBankedIntReg wouldn't be written to unless the 28010037SARM gem5 Developers // conditions on the IF statements above are met, however if 28110037SARM gem5 Developers // you look at the generated C code you'll find that they are. 28210037SARM gem5 Developers // However this is safe as DecodedBankedIntReg (which is used 28310037SARM gem5 Developers // in operands.isa to get the index of DecodedBankedIntReg) 28410037SARM gem5 Developers // will return INTREG_DUMMY if its not a valid integer 28510037SARM gem5 Developers // register, so redirecting the write to somewhere we don't 28610037SARM gem5 Developers // care about. 28710037SARM gem5 Developers DecodedBankedIntReg = Op1; 28810037SARM gem5 Developers } else { 28910037SARM gem5 Developers xc->setMiscReg(regIdx, Op1); 29010037SARM gem5 Developers } 29110037SARM gem5 Developers } else { 29210474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 29310474Sandreas.hansson@arm.com mnemonic); 29410037SARM gem5 Developers } 29510037SARM gem5 Developers ''' 29610037SARM gem5 Developers msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", 29710037SARM gem5 Developers { "code": msrBankedRegCode, 29810037SARM gem5 Developers "predicate_test": predicateTest }, 29910501Sakash.bagdia@ARM.com ["IsSerializeAfter", "IsNonSpeculative"]) 30010037SARM gem5 Developers header_output += MsrBankedRegDeclare.subst(msrBankedRegIop) 30110037SARM gem5 Developers decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop) 30210037SARM gem5 Developers exec_output += PredOpExecute.subst(msrBankedRegIop) 30310037SARM gem5 Developers 3047202Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 3057400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 3068303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 3078303SAli.Saidi@ARM.com old_cpsr.nz = CondCodesNZ; 3088303SAli.Saidi@ARM.com old_cpsr.c = CondCodesC; 3098303SAli.Saidi@ARM.com old_cpsr.v = CondCodesV; 3108303SAli.Saidi@ARM.com old_cpsr.ge = CondCodesGE; 3118303SAli.Saidi@ARM.com 3128303SAli.Saidi@ARM.com CPSR new_cpsr = 31310037SARM gem5 Developers cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false, 31410037SARM gem5 Developers sctlr.nmfi, xc->tcBase()); 3158303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 3168303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 3178303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 3188303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 3198303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 3207202Sgblack@eecs.umich.edu ''' 3217202Sgblack@eecs.umich.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 3227202Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 3237599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 3247599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 3257202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrCpsrRegIop) 3267202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 3277202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrRegIop) 3287202Sgblack@eecs.umich.edu 3297202Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 3307202Sgblack@eecs.umich.edu msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 3317202Sgblack@eecs.umich.edu { "code": msrSpsrRegCode, 3327599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 3337599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 3347202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrSpsrRegIop) 3357202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 3367202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrRegIop) 3377202Sgblack@eecs.umich.edu 3387202Sgblack@eecs.umich.edu msrCpsrImmCode = ''' 3397400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 3408303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 3418303SAli.Saidi@ARM.com old_cpsr.nz = CondCodesNZ; 3428303SAli.Saidi@ARM.com old_cpsr.c = CondCodesC; 3438303SAli.Saidi@ARM.com old_cpsr.v = CondCodesV; 3448303SAli.Saidi@ARM.com old_cpsr.ge = CondCodesGE; 3458303SAli.Saidi@ARM.com CPSR new_cpsr = 34610037SARM gem5 Developers cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false, 34710037SARM gem5 Developers sctlr.nmfi, xc->tcBase()); 3488303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 3498303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 3508303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 3518303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 3528303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 3537202Sgblack@eecs.umich.edu ''' 3547202Sgblack@eecs.umich.edu msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 3557202Sgblack@eecs.umich.edu { "code": msrCpsrImmCode, 3567599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 3577599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 3587202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrCpsrImmIop) 3597202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 3607202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrImmIop) 3617202Sgblack@eecs.umich.edu 3627202Sgblack@eecs.umich.edu msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 3637202Sgblack@eecs.umich.edu msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 3647202Sgblack@eecs.umich.edu { "code": msrSpsrImmCode, 3657599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 3667599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 3677202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrSpsrImmIop) 3687202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 3697202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrImmIop) 3707209Sgblack@eecs.umich.edu 3717209Sgblack@eecs.umich.edu revCode = ''' 3727209Sgblack@eecs.umich.edu uint32_t val = Op1; 3737209Sgblack@eecs.umich.edu Dest = swap_byte(val); 3747209Sgblack@eecs.umich.edu ''' 3757261Sgblack@eecs.umich.edu revIop = InstObjParams("rev", "Rev", "RegRegOp", 3767209Sgblack@eecs.umich.edu { "code": revCode, 3777209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3787261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revIop) 3797261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revIop) 3807209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revIop) 3817209Sgblack@eecs.umich.edu 3827209Sgblack@eecs.umich.edu rev16Code = ''' 3837209Sgblack@eecs.umich.edu uint32_t val = Op1; 3847209Sgblack@eecs.umich.edu Dest = (bits(val, 15, 8) << 0) | 3857209Sgblack@eecs.umich.edu (bits(val, 7, 0) << 8) | 3867209Sgblack@eecs.umich.edu (bits(val, 31, 24) << 16) | 3877209Sgblack@eecs.umich.edu (bits(val, 23, 16) << 24); 3887209Sgblack@eecs.umich.edu ''' 3897261Sgblack@eecs.umich.edu rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 3907209Sgblack@eecs.umich.edu { "code": rev16Code, 3917209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3927261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rev16Iop) 3937261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rev16Iop) 3947209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rev16Iop) 3957209Sgblack@eecs.umich.edu 3967209Sgblack@eecs.umich.edu revshCode = ''' 3977209Sgblack@eecs.umich.edu uint16_t val = Op1; 3987209Sgblack@eecs.umich.edu Dest = sext<16>(swap_byte(val)); 3997209Sgblack@eecs.umich.edu ''' 4007261Sgblack@eecs.umich.edu revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 4017209Sgblack@eecs.umich.edu { "code": revshCode, 4027209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4037261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revshIop) 4047261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revshIop) 4057209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revshIop) 4067226Sgblack@eecs.umich.edu 4077249Sgblack@eecs.umich.edu rbitCode = ''' 40812227Sgiacomo.travaglini@arm.com Dest = reverseBits(Op1); 4097249Sgblack@eecs.umich.edu ''' 4107261Sgblack@eecs.umich.edu rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 4117249Sgblack@eecs.umich.edu { "code": rbitCode, 4127249Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4137261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rbitIop) 4147261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rbitIop) 4157249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rbitIop) 4167249Sgblack@eecs.umich.edu 4177251Sgblack@eecs.umich.edu clzCode = ''' 4187251Sgblack@eecs.umich.edu Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 4197251Sgblack@eecs.umich.edu ''' 4207261Sgblack@eecs.umich.edu clzIop = InstObjParams("clz", "Clz", "RegRegOp", 4217251Sgblack@eecs.umich.edu { "code": clzCode, 4227251Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4237261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(clzIop) 4247261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(clzIop) 4257251Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clzIop) 4267251Sgblack@eecs.umich.edu 4277226Sgblack@eecs.umich.edu ssatCode = ''' 4287226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 4297226Sgblack@eecs.umich.edu int32_t res; 4307232Sgblack@eecs.umich.edu if (satInt(res, operand, imm)) 4318302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4327226Sgblack@eecs.umich.edu Dest = res; 4337226Sgblack@eecs.umich.edu ''' 4347232Sgblack@eecs.umich.edu ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 4357226Sgblack@eecs.umich.edu { "code": ssatCode, 4368304SAli.Saidi@ARM.com "predicate_test": pickPredicate(ssatCode) }, []) 4377232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 4387232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 4397226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssatIop) 4407226Sgblack@eecs.umich.edu 4417226Sgblack@eecs.umich.edu usatCode = ''' 4427226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 4437226Sgblack@eecs.umich.edu int32_t res; 4447232Sgblack@eecs.umich.edu if (uSatInt(res, operand, imm)) 4458302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4467226Sgblack@eecs.umich.edu Dest = res; 4477226Sgblack@eecs.umich.edu ''' 4487232Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 4497226Sgblack@eecs.umich.edu { "code": usatCode, 4508304SAli.Saidi@ARM.com "predicate_test": pickPredicate(usatCode) }, []) 4517232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(usatIop) 4527232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 4537226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usatIop) 4547226Sgblack@eecs.umich.edu 4557226Sgblack@eecs.umich.edu ssat16Code = ''' 4567226Sgblack@eecs.umich.edu int32_t res; 4577226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4587226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 4597226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 4607232Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 4618302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4627226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 4637232Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 4648302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4657226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 4667226Sgblack@eecs.umich.edu Dest = resTemp; 4677226Sgblack@eecs.umich.edu ''' 4687232Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 4697226Sgblack@eecs.umich.edu { "code": ssat16Code, 4708304SAli.Saidi@ARM.com "predicate_test": pickPredicate(ssat16Code) }, []) 4717232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(ssat16Iop) 4727232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 4737226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssat16Iop) 4747226Sgblack@eecs.umich.edu 4757226Sgblack@eecs.umich.edu usat16Code = ''' 4767226Sgblack@eecs.umich.edu int32_t res; 4777226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4787226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 4797226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 4807232Sgblack@eecs.umich.edu if (uSatInt(res, argLow, imm)) 4818302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4827226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 4837232Sgblack@eecs.umich.edu if (uSatInt(res, argHigh, imm)) 4848302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4857226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 4867226Sgblack@eecs.umich.edu Dest = resTemp; 4877226Sgblack@eecs.umich.edu ''' 4887232Sgblack@eecs.umich.edu usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 4897226Sgblack@eecs.umich.edu { "code": usat16Code, 4908304SAli.Saidi@ARM.com "predicate_test": pickPredicate(usat16Code) }, []) 4917232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(usat16Iop) 4927232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 4937226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usat16Iop) 4947234Sgblack@eecs.umich.edu 4957234Sgblack@eecs.umich.edu sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 4967234Sgblack@eecs.umich.edu { "code": 4978588Sgblack@eecs.umich.edu "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", 4987234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4997234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtbIop) 5007234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 5017234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtbIop) 5027234Sgblack@eecs.umich.edu 5037234Sgblack@eecs.umich.edu sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 5047234Sgblack@eecs.umich.edu { "code": 5057234Sgblack@eecs.umich.edu ''' 5068588Sgblack@eecs.umich.edu Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + 5077234Sgblack@eecs.umich.edu Op1; 5087234Sgblack@eecs.umich.edu ''', 5097234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5107234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 5117234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 5127234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtabIop) 5137234Sgblack@eecs.umich.edu 5147234Sgblack@eecs.umich.edu sxtb16Code = ''' 5157234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5167234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 5177234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5187234Sgblack@eecs.umich.edu sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 5197234Sgblack@eecs.umich.edu Dest = resTemp; 5207234Sgblack@eecs.umich.edu ''' 5217234Sgblack@eecs.umich.edu sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 5227234Sgblack@eecs.umich.edu { "code": sxtb16Code, 5237234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5247234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 5257234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 5267234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtb16Iop) 5277234Sgblack@eecs.umich.edu 5287234Sgblack@eecs.umich.edu sxtab16Code = ''' 5297234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5307234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 5317234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 5327234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5337234Sgblack@eecs.umich.edu sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 5347234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 5357234Sgblack@eecs.umich.edu Dest = resTemp; 5367234Sgblack@eecs.umich.edu ''' 5377234Sgblack@eecs.umich.edu sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 5387234Sgblack@eecs.umich.edu { "code": sxtab16Code, 5397234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5407234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 5417234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 5427234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtab16Iop) 5437234Sgblack@eecs.umich.edu 5447234Sgblack@eecs.umich.edu sxthCode = ''' 5457234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 5467234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 5477234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 5487234Sgblack@eecs.umich.edu ''' 5497234Sgblack@eecs.umich.edu sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 5507234Sgblack@eecs.umich.edu { "code": sxthCode, 5517234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5527234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 5537234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 5547234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 5557234Sgblack@eecs.umich.edu 5567234Sgblack@eecs.umich.edu sxtahCode = ''' 5577234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 5587234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 5597234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated) + Op1; 5607234Sgblack@eecs.umich.edu ''' 5617234Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 5627234Sgblack@eecs.umich.edu { "code": sxtahCode, 5637234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5647234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 5657234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 5667234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtahIop) 5677234Sgblack@eecs.umich.edu 5687234Sgblack@eecs.umich.edu uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 5698588Sgblack@eecs.umich.edu { "code": "Dest = (uint8_t)(Op1_ud >> imm);", 5707234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5717234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtbIop) 5727234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 5737234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtbIop) 5747234Sgblack@eecs.umich.edu 5757234Sgblack@eecs.umich.edu uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 5767234Sgblack@eecs.umich.edu { "code": 5778588Sgblack@eecs.umich.edu "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", 5787234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5797234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 5807234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 5817234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 5827234Sgblack@eecs.umich.edu 5837234Sgblack@eecs.umich.edu uxtb16Code = ''' 5847234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5857234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 5867234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5877234Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 5887234Sgblack@eecs.umich.edu Dest = resTemp; 5897234Sgblack@eecs.umich.edu ''' 5907234Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 5917234Sgblack@eecs.umich.edu { "code": uxtb16Code, 5927234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5937234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 5947234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 5957234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtb16Iop) 5967234Sgblack@eecs.umich.edu 5977234Sgblack@eecs.umich.edu uxtab16Code = ''' 5987234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5997234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 6007234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 6017234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 6027234Sgblack@eecs.umich.edu (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 6037234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 6047234Sgblack@eecs.umich.edu Dest = resTemp; 6057234Sgblack@eecs.umich.edu ''' 6067234Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 6077234Sgblack@eecs.umich.edu { "code": uxtab16Code, 6087234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6097234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 6107234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 6117234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 6127234Sgblack@eecs.umich.edu 6137234Sgblack@eecs.umich.edu uxthCode = ''' 6147234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 6157234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 6167234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated; 6177234Sgblack@eecs.umich.edu ''' 6187234Sgblack@eecs.umich.edu uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 6197234Sgblack@eecs.umich.edu { "code": uxthCode, 6207234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6217234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxthIop) 6227234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxthIop) 6237234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxthIop) 6247234Sgblack@eecs.umich.edu 6257234Sgblack@eecs.umich.edu uxtahCode = ''' 6267234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 6277234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 6287234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 6297234Sgblack@eecs.umich.edu ''' 6307234Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 6317234Sgblack@eecs.umich.edu { "code": uxtahCode, 6327234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6337234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 6347234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 6357234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 6367239Sgblack@eecs.umich.edu 6377239Sgblack@eecs.umich.edu selCode = ''' 6387239Sgblack@eecs.umich.edu uint32_t resTemp = 0; 6397239Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 6407239Sgblack@eecs.umich.edu int low = i * 8; 6417239Sgblack@eecs.umich.edu int high = low + 7; 6427239Sgblack@eecs.umich.edu replaceBits(resTemp, high, low, 6438303SAli.Saidi@ARM.com bits(CondCodesGE, i) ? 6447239Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 6457239Sgblack@eecs.umich.edu } 6467239Sgblack@eecs.umich.edu Dest = resTemp; 6477239Sgblack@eecs.umich.edu ''' 6487239Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 6497239Sgblack@eecs.umich.edu { "code": selCode, 6508303SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 6517239Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 6527239Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 6537239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 6547242Sgblack@eecs.umich.edu 6557242Sgblack@eecs.umich.edu usad8Code = ''' 6567242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 6577242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 6587242Sgblack@eecs.umich.edu int low = i * 8; 6597242Sgblack@eecs.umich.edu int high = low + 7; 6607242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 6617242Sgblack@eecs.umich.edu bits(Op2, high, low); 6627242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 6637242Sgblack@eecs.umich.edu } 6647242Sgblack@eecs.umich.edu Dest = resTemp; 6657242Sgblack@eecs.umich.edu ''' 6667242Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 6677242Sgblack@eecs.umich.edu { "code": usad8Code, 6687242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6697242Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 6707242Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 6717242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usad8Iop) 6727242Sgblack@eecs.umich.edu 6737242Sgblack@eecs.umich.edu usada8Code = ''' 6747242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 6757242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 6767242Sgblack@eecs.umich.edu int low = i * 8; 6777242Sgblack@eecs.umich.edu int high = low + 7; 6787242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 6797242Sgblack@eecs.umich.edu bits(Op2, high, low); 6807242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 6817242Sgblack@eecs.umich.edu } 6827242Sgblack@eecs.umich.edu Dest = Op3 + resTemp; 6837242Sgblack@eecs.umich.edu ''' 6847242Sgblack@eecs.umich.edu usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 6857242Sgblack@eecs.umich.edu { "code": usada8Code, 6867242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6877242Sgblack@eecs.umich.edu header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 6887242Sgblack@eecs.umich.edu decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 6897242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usada8Iop) 6907247Sgblack@eecs.umich.edu 69112789Sgiacomo.travaglini@arm.com bkptCode = ''' 69212789Sgiacomo.travaglini@arm.com uint16_t imm16; 69312789Sgiacomo.travaglini@arm.com if (!machInst.thumb) 69412789Sgiacomo.travaglini@arm.com imm16 = ((bits(machInst, 19, 8) << 4) | bits(machInst, 3, 0)); 69512789Sgiacomo.travaglini@arm.com else 69612789Sgiacomo.travaglini@arm.com imm16 = bits(machInst, 7, 0); 69712789Sgiacomo.travaglini@arm.com 69812789Sgiacomo.travaglini@arm.com return softwareBreakpoint32(xc, imm16); 69912789Sgiacomo.travaglini@arm.com ''' 7007848SAli.Saidi@ARM.com bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 7017410Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(bkptIop) 7027410Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(bkptIop) 7037410Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(bkptIop) 7047410Sgblack@eecs.umich.edu 70510037SARM gem5 Developers nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop']) 7067247Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(nopIop) 70710037SARM gem5 Developers decoder_output += BasicConstructor64.subst(nopIop) 70810037SARM gem5 Developers exec_output += BasicExecute.subst(nopIop) 7097408Sgblack@eecs.umich.edu 7107418Sgblack@eecs.umich.edu yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 7117418Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 7127418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(yieldIop) 7137418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(yieldIop) 7147418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(yieldIop) 7157418Sgblack@eecs.umich.edu 7167418Sgblack@eecs.umich.edu wfeCode = ''' 71710037SARM gem5 Developers CPSR cpsr = Cpsr; 71810037SARM gem5 Developers SCR scr = Scr64; 71910037SARM gem5 Developers 72010037SARM gem5 Developers // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending, 72110037SARM gem5 Developers ThreadContext *tc = xc->tcBase(); 7228285SPrakash.Ramrakhyani@arm.com if (SevMailbox == 1) { 7237418Sgblack@eecs.umich.edu SevMailbox = 0; 72410037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 72511150Smitch.hayenga@arm.com } else if (tc->getCpuPtr()->getInterruptController( 72611150Smitch.hayenga@arm.com tc->threadId())->checkInterrupts(tc)) { 72710037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 7288285SPrakash.Ramrakhyani@arm.com } else { 72912403Sgiacomo.travaglini@arm.com fault = trapWFx(tc, cpsr, scr, true); 73012403Sgiacomo.travaglini@arm.com if (fault == NoFault) { 73112403Sgiacomo.travaglini@arm.com PseudoInst::quiesce(tc); 73212403Sgiacomo.travaglini@arm.com } else { 73312403Sgiacomo.travaglini@arm.com PseudoInst::quiesceSkip(tc); 73412403Sgiacomo.travaglini@arm.com } 7358142SAli.Saidi@ARM.com } 7367418Sgblack@eecs.umich.edu ''' 7378518Sgeoffrey.blake@arm.com wfePredFixUpCode = ''' 7388518Sgeoffrey.blake@arm.com // WFE is predicated false, reset SevMailbox to reduce spurious sleeps 7398518Sgeoffrey.blake@arm.com // and SEV interrupts 7408518Sgeoffrey.blake@arm.com SevMailbox = 1; 7418518Sgeoffrey.blake@arm.com ''' 7427418Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 7438518Sgeoffrey.blake@arm.com { "code" : wfeCode, 7448518Sgeoffrey.blake@arm.com "pred_fixup" : wfePredFixUpCode, 7458518Sgeoffrey.blake@arm.com "predicate_test" : predicateTest }, 7468733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsQuiesce", 7478733Sgeoffrey.blake@arm.com "IsSerializeAfter", "IsUnverifiable"]) 7487418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 7497418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfeIop) 7508518Sgeoffrey.blake@arm.com exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) 7517418Sgblack@eecs.umich.edu 7527418Sgblack@eecs.umich.edu wfiCode = ''' 75310037SARM gem5 Developers HCR hcr = Hcr; 75410037SARM gem5 Developers CPSR cpsr = Cpsr; 75510037SARM gem5 Developers SCR scr = Scr64; 75610037SARM gem5 Developers 7578285SPrakash.Ramrakhyani@arm.com // WFI doesn't sleep if interrupts are pending (masked or not) 75810037SARM gem5 Developers ThreadContext *tc = xc->tcBase(); 75911150Smitch.hayenga@arm.com if (tc->getCpuPtr()->getInterruptController( 76011150Smitch.hayenga@arm.com tc->threadId())->checkWfiWake(hcr, cpsr, scr)) { 76110037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 7628285SPrakash.Ramrakhyani@arm.com } else { 76312403Sgiacomo.travaglini@arm.com fault = trapWFx(tc, cpsr, scr, false); 76412403Sgiacomo.travaglini@arm.com if (fault == NoFault) { 76512403Sgiacomo.travaglini@arm.com PseudoInst::quiesce(tc); 76612403Sgiacomo.travaglini@arm.com } else { 76712403Sgiacomo.travaglini@arm.com PseudoInst::quiesceSkip(tc); 76812403Sgiacomo.travaglini@arm.com } 7698285SPrakash.Ramrakhyani@arm.com } 77011150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 7717418Sgblack@eecs.umich.edu ''' 7727418Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 7737418Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 7748733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsQuiesce", 7758733Sgeoffrey.blake@arm.com "IsSerializeAfter", "IsUnverifiable"]) 7767418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfiIop) 7777418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfiIop) 7788142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(wfiIop) 7797418Sgblack@eecs.umich.edu 7807418Sgblack@eecs.umich.edu sevCode = ''' 7818142SAli.Saidi@ARM.com SevMailbox = 1; 7827418Sgblack@eecs.umich.edu System *sys = xc->tcBase()->getSystemPtr(); 7837418Sgblack@eecs.umich.edu for (int x = 0; x < sys->numContexts(); x++) { 7847418Sgblack@eecs.umich.edu ThreadContext *oc = sys->getThreadContext(x); 7858285SPrakash.Ramrakhyani@arm.com if (oc == xc->tcBase()) 7868285SPrakash.Ramrakhyani@arm.com continue; 7878518Sgeoffrey.blake@arm.com // Wake CPU with interrupt if they were sleeping 7888285SPrakash.Ramrakhyani@arm.com if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 7898518Sgeoffrey.blake@arm.com // Post Interrupt and wake cpu if needed 79011150Smitch.hayenga@arm.com oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0); 7918142SAli.Saidi@ARM.com } 7927418Sgblack@eecs.umich.edu } 7937418Sgblack@eecs.umich.edu ''' 7947418Sgblack@eecs.umich.edu sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 7957418Sgblack@eecs.umich.edu { "code" : sevCode, "predicate_test" : predicateTest }, 7968733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 7977418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sevIop) 7987418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sevIop) 7997418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sevIop) 8007418Sgblack@eecs.umich.edu 80110037SARM gem5 Developers sevlCode = ''' 80210037SARM gem5 Developers SevMailbox = 1; 80310037SARM gem5 Developers ''' 80410037SARM gem5 Developers sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \ 80510037SARM gem5 Developers { "code" : sevlCode, "predicate_test" : predicateTest }, 80610037SARM gem5 Developers ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 80710037SARM gem5 Developers header_output += BasicDeclare.subst(sevlIop) 80810037SARM gem5 Developers decoder_output += BasicConstructor.subst(sevlIop) 80910037SARM gem5 Developers exec_output += BasicExecute.subst(sevlIop) 81010037SARM gem5 Developers 8117408Sgblack@eecs.umich.edu itIop = InstObjParams("it", "ItInst", "PredOp", \ 8128205SAli.Saidi@ARM.com { "code" : ";", 8138908Sgeoffrey.blake@arm.com "predicate_test" : predicateTest }, []) 8147408Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(itIop) 8157408Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(itIop) 8167408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(itIop) 8177409Sgblack@eecs.umich.edu unknownCode = ''' 81810474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, true); 8197409Sgblack@eecs.umich.edu ''' 8207409Sgblack@eecs.umich.edu unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 8217409Sgblack@eecs.umich.edu { "code": unknownCode, 8227409Sgblack@eecs.umich.edu "predicate_test": predicateTest }) 8237409Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(unknownIop) 8247409Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(unknownIop) 8257409Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(unknownIop) 8267254Sgblack@eecs.umich.edu 8277254Sgblack@eecs.umich.edu ubfxCode = ''' 8287254Sgblack@eecs.umich.edu Dest = bits(Op1, imm2, imm1); 8297254Sgblack@eecs.umich.edu ''' 8307254Sgblack@eecs.umich.edu ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 8317254Sgblack@eecs.umich.edu { "code": ubfxCode, 8327254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8337254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 8347254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 8357254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ubfxIop) 8367254Sgblack@eecs.umich.edu 8377254Sgblack@eecs.umich.edu sbfxCode = ''' 8387254Sgblack@eecs.umich.edu int32_t resTemp = bits(Op1, imm2, imm1); 8397254Sgblack@eecs.umich.edu Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 8407254Sgblack@eecs.umich.edu ''' 8417254Sgblack@eecs.umich.edu sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 8427254Sgblack@eecs.umich.edu { "code": sbfxCode, 8437254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8447254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 8457254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 8467254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sbfxIop) 8477257Sgblack@eecs.umich.edu 8487257Sgblack@eecs.umich.edu bfcCode = ''' 8497257Sgblack@eecs.umich.edu Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 8507257Sgblack@eecs.umich.edu ''' 8517257Sgblack@eecs.umich.edu bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 8527257Sgblack@eecs.umich.edu { "code": bfcCode, 8537257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8547257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfcIop) 8557257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 8567257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfcIop) 8577257Sgblack@eecs.umich.edu 8587257Sgblack@eecs.umich.edu bfiCode = ''' 8597257Sgblack@eecs.umich.edu uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 8607257Sgblack@eecs.umich.edu Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 8617257Sgblack@eecs.umich.edu ''' 8627257Sgblack@eecs.umich.edu bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 8637257Sgblack@eecs.umich.edu { "code": bfiCode, 8647257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8657257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfiIop) 8667257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 8677257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfiIop) 8687262Sgblack@eecs.umich.edu 8698868SMatt.Horsnell@arm.com mrc14code = ''' 87012106SRekai.GonzalezAlberquilla@arm.com MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 87112106SRekai.GonzalezAlberquilla@arm.com RegId(MiscRegClass, op1)).index(); 87211939Snikos.nikoleris@arm.com bool can_read, undefined; 87311939Snikos.nikoleris@arm.com std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 87411939Snikos.nikoleris@arm.com if (!can_read || undefined) { 87510474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 87610474Sandreas.hansson@arm.com mnemonic); 87710037SARM gem5 Developers } 87812560Ssiddhesh.poyarekar@gmail.com if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr, 87910037SARM gem5 Developers Hstr, Hcptr, imm)) { 88010474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 88110474Sandreas.hansson@arm.com EC_TRAPPED_CP14_MCR_MRC); 8828868SMatt.Horsnell@arm.com } 8838868SMatt.Horsnell@arm.com Dest = MiscOp1; 8848868SMatt.Horsnell@arm.com ''' 8858868SMatt.Horsnell@arm.com 88612646Sgiacomo.travaglini@arm.com mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp", 8878868SMatt.Horsnell@arm.com { "code": mrc14code, 8888868SMatt.Horsnell@arm.com "predicate_test": predicateTest }, []) 88912646Sgiacomo.travaglini@arm.com header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop) 89012646Sgiacomo.travaglini@arm.com decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop) 8918868SMatt.Horsnell@arm.com exec_output += PredOpExecute.subst(mrc14Iop) 8928868SMatt.Horsnell@arm.com 8938868SMatt.Horsnell@arm.com 8948868SMatt.Horsnell@arm.com mcr14code = ''' 89512106SRekai.GonzalezAlberquilla@arm.com MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 89612106SRekai.GonzalezAlberquilla@arm.com RegId(MiscRegClass, dest)).index(); 89711939Snikos.nikoleris@arm.com bool can_write, undefined; 89811939Snikos.nikoleris@arm.com std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 89911939Snikos.nikoleris@arm.com if (undefined || !can_write) { 90010474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 90110474Sandreas.hansson@arm.com mnemonic); 90210037SARM gem5 Developers } 90310037SARM gem5 Developers if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, 90410037SARM gem5 Developers Hstr, Hcptr, imm)) { 90510474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 90610474Sandreas.hansson@arm.com EC_TRAPPED_CP14_MCR_MRC); 9078868SMatt.Horsnell@arm.com } 9088868SMatt.Horsnell@arm.com MiscDest = Op1; 9098868SMatt.Horsnell@arm.com ''' 91012646Sgiacomo.travaglini@arm.com mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp", 9118868SMatt.Horsnell@arm.com { "code": mcr14code, 9128868SMatt.Horsnell@arm.com "predicate_test": predicateTest }, 9138868SMatt.Horsnell@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 91412646Sgiacomo.travaglini@arm.com header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop) 91512646Sgiacomo.travaglini@arm.com decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop) 9168868SMatt.Horsnell@arm.com exec_output += PredOpExecute.subst(mcr14Iop) 9178868SMatt.Horsnell@arm.com 91810037SARM gem5 Developers mrc15code = ''' 91912499Sgiacomo.travaglini@arm.com int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); 92010037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 92112106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 92212106SRekai.GonzalezAlberquilla@arm.com preFlatOp1)).index(); 92313999Sgiacomo.travaglini@arm.com 92413999Sgiacomo.travaglini@arm.com bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm); 92513999Sgiacomo.travaglini@arm.com 92611939Snikos.nikoleris@arm.com bool can_read, undefined; 92711939Snikos.nikoleris@arm.com std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 92810037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 92910037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 93010037SARM gem5 Developers // IS accessable. 93111939Snikos.nikoleris@arm.com if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 93211939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 93310474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 93410474Sandreas.hansson@arm.com mnemonic); 9358782Sgblack@eecs.umich.edu } 93610037SARM gem5 Developers if (hypTrap) { 93710474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 93810474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCR_MRC); 93910037SARM gem5 Developers } 94010037SARM gem5 Developers Dest = MiscNsBankedOp1; 9417347SAli.Saidi@ARM.com ''' 9427347SAli.Saidi@ARM.com 94310418Sandreas.hansson@arm.com mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", 9447347SAli.Saidi@ARM.com { "code": mrc15code, 9457262Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 94610418Sandreas.hansson@arm.com header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop) 94710418Sandreas.hansson@arm.com decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop) 9487262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15Iop) 9497262Sgblack@eecs.umich.edu 9507347SAli.Saidi@ARM.com 9517347SAli.Saidi@ARM.com mcr15code = ''' 95212499Sgiacomo.travaglini@arm.com int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 95310037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 95412106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 95512106SRekai.GonzalezAlberquilla@arm.com preFlatDest)).index(); 95613999Sgiacomo.travaglini@arm.com 95713999Sgiacomo.travaglini@arm.com bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm); 95813999Sgiacomo.travaglini@arm.com 95911939Snikos.nikoleris@arm.com bool can_write, undefined; 96011939Snikos.nikoleris@arm.com std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 96110037SARM gem5 Developers 96210037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 96310037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 96410037SARM gem5 Developers // IS accessable. 96511939Snikos.nikoleris@arm.com if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 96611939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 96710474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 96810474Sandreas.hansson@arm.com mnemonic); 9698782Sgblack@eecs.umich.edu } 97010037SARM gem5 Developers if (hypTrap) { 97110474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 97210474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCR_MRC); 97310037SARM gem5 Developers } 97410037SARM gem5 Developers MiscNsBankedDest = Op1; 9757347SAli.Saidi@ARM.com ''' 97610418Sandreas.hansson@arm.com mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", 9777347SAli.Saidi@ARM.com { "code": mcr15code, 9787599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 9797599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 98010418Sandreas.hansson@arm.com header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop) 98110418Sandreas.hansson@arm.com decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop) 9827262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15Iop) 9837283Sgblack@eecs.umich.edu 9847420Sgblack@eecs.umich.edu 98510037SARM gem5 Developers mrrc15code = ''' 98612499Sgiacomo.travaglini@arm.com int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); 98710037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 98812106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 98912106SRekai.GonzalezAlberquilla@arm.com preFlatOp1)).index(); 99010037SARM gem5 Developers bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 99111939Snikos.nikoleris@arm.com bool can_read, undefined; 99211939Snikos.nikoleris@arm.com std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 99310037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 99410037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 99510037SARM gem5 Developers // IS accessable. 99611939Snikos.nikoleris@arm.com if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 99711939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 99810474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 99910474Sandreas.hansson@arm.com mnemonic); 100010037SARM gem5 Developers } 100110037SARM gem5 Developers if (hypTrap) { 100210474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 100310474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCRR_MRRC); 100410037SARM gem5 Developers } 100510037SARM gem5 Developers Dest = bits(MiscNsBankedOp164, 63, 32); 100610037SARM gem5 Developers Dest2 = bits(MiscNsBankedOp164, 31, 0); 100710037SARM gem5 Developers ''' 100810037SARM gem5 Developers mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp", 100910037SARM gem5 Developers { "code": mrrc15code, 101010037SARM gem5 Developers "predicate_test": predicateTest }, []) 101110037SARM gem5 Developers header_output += MrrcOpDeclare.subst(mrrc15Iop) 101210037SARM gem5 Developers decoder_output += MrrcOpConstructor.subst(mrrc15Iop) 101310037SARM gem5 Developers exec_output += PredOpExecute.subst(mrrc15Iop) 101410037SARM gem5 Developers 101510037SARM gem5 Developers 101610037SARM gem5 Developers mcrr15code = ''' 101712499Sgiacomo.travaglini@arm.com int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 101810037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 101912106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 102012106SRekai.GonzalezAlberquilla@arm.com preFlatDest)).index(); 102110037SARM gem5 Developers bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 102211939Snikos.nikoleris@arm.com bool can_write, undefined; 102311939Snikos.nikoleris@arm.com std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 102410037SARM gem5 Developers 102510037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 102610037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 102710037SARM gem5 Developers // IS accessable. 102811939Snikos.nikoleris@arm.com if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 102911939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 103010474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 103110474Sandreas.hansson@arm.com mnemonic); 103210037SARM gem5 Developers } 103310037SARM gem5 Developers if (hypTrap) { 103410474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 103510474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCRR_MRRC); 103610037SARM gem5 Developers } 103710037SARM gem5 Developers MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2; 103810037SARM gem5 Developers ''' 103910037SARM gem5 Developers mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp", 104010037SARM gem5 Developers { "code": mcrr15code, 104110037SARM gem5 Developers "predicate_test": predicateTest }, []) 104210037SARM gem5 Developers header_output += McrrOpDeclare.subst(mcrr15Iop) 104310037SARM gem5 Developers decoder_output += McrrOpConstructor.subst(mcrr15Iop) 104410037SARM gem5 Developers exec_output += PredOpExecute.subst(mcrr15Iop) 104510037SARM gem5 Developers 10467420Sgblack@eecs.umich.edu 10477283Sgblack@eecs.umich.edu enterxCode = ''' 10487797Sgblack@eecs.umich.edu NextThumb = true; 10497797Sgblack@eecs.umich.edu NextJazelle = true; 10507283Sgblack@eecs.umich.edu ''' 10517283Sgblack@eecs.umich.edu enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 10527283Sgblack@eecs.umich.edu { "code": enterxCode, 10537283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10547283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(enterxIop) 10557283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(enterxIop) 10567283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(enterxIop) 10577283Sgblack@eecs.umich.edu 10587283Sgblack@eecs.umich.edu leavexCode = ''' 10597797Sgblack@eecs.umich.edu NextThumb = true; 10607797Sgblack@eecs.umich.edu NextJazelle = false; 10617283Sgblack@eecs.umich.edu ''' 10627283Sgblack@eecs.umich.edu leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 10637283Sgblack@eecs.umich.edu { "code": leavexCode, 10647283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10657283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(leavexIop) 10667283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(leavexIop) 10677283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(leavexIop) 10687307Sgblack@eecs.umich.edu 10697307Sgblack@eecs.umich.edu setendCode = ''' 10707307Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 10717307Sgblack@eecs.umich.edu cpsr.e = imm; 10727307Sgblack@eecs.umich.edu Cpsr = cpsr; 107312498Sgiacomo.travaglini@arm.com fault = checkSETENDEnabled(xc->tcBase(), cpsr); 10747307Sgblack@eecs.umich.edu ''' 10757307Sgblack@eecs.umich.edu setendIop = InstObjParams("setend", "Setend", "ImmOp", 10767307Sgblack@eecs.umich.edu { "code": setendCode, 10777648SAli.Saidi@ARM.com "predicate_test": predicateTest }, 10787648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 10797307Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(setendIop) 10807307Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(setendIop) 10817307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(setendIop) 10827315Sgblack@eecs.umich.edu 10837603SGene.Wu@arm.com clrexCode = ''' 10848209SAli.Saidi@ARM.com LLSCLock = 0; 10857603SGene.Wu@arm.com ''' 10867603SGene.Wu@arm.com clrexIop = InstObjParams("clrex", "Clrex","PredOp", 10877603SGene.Wu@arm.com { "code": clrexCode, 10887603SGene.Wu@arm.com "predicate_test": predicateTest },[]) 10898209SAli.Saidi@ARM.com header_output += BasicDeclare.subst(clrexIop) 10907603SGene.Wu@arm.com decoder_output += BasicConstructor.subst(clrexIop) 10917603SGene.Wu@arm.com exec_output += PredOpExecute.subst(clrexIop) 10927603SGene.Wu@arm.com 109312358Snikos.nikoleris@arm.com McrDcCheckCode = ''' 109412499Sgiacomo.travaglini@arm.com int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 109512358Snikos.nikoleris@arm.com MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 109612358Snikos.nikoleris@arm.com RegId(MiscRegClass, preFlatDest)).index(); 109713999Sgiacomo.travaglini@arm.com 109813999Sgiacomo.travaglini@arm.com bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm); 109913999Sgiacomo.travaglini@arm.com 110012358Snikos.nikoleris@arm.com bool can_write, undefined; 110112358Snikos.nikoleris@arm.com std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 110212358Snikos.nikoleris@arm.com 110312358Snikos.nikoleris@arm.com // if we're in non secure PL1 mode then we can trap regardless 110412358Snikos.nikoleris@arm.com // of whether the register is accessible, in other modes we 110512358Snikos.nikoleris@arm.com // trap if only if the register IS accessible. 110612358Snikos.nikoleris@arm.com if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) & 110712358Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 110812358Snikos.nikoleris@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 110912358Snikos.nikoleris@arm.com mnemonic); 111012358Snikos.nikoleris@arm.com } 111112358Snikos.nikoleris@arm.com if (hypTrap) { 111212358Snikos.nikoleris@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 111312358Snikos.nikoleris@arm.com EC_TRAPPED_CP15_MCR_MRC); 111412358Snikos.nikoleris@arm.com } 111512358Snikos.nikoleris@arm.com ''' 111612358Snikos.nikoleris@arm.com 111712358Snikos.nikoleris@arm.com McrDcimvacCode = ''' 111812358Snikos.nikoleris@arm.com const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 111912358Snikos.nikoleris@arm.com Request::INVALIDATE | 112012358Snikos.nikoleris@arm.com Request::DST_POC); 112112358Snikos.nikoleris@arm.com EA = Op1; 112212358Snikos.nikoleris@arm.com ''' 112312504Snikos.nikoleris@arm.com McrDcimvacIop = InstObjParams("mcr", "McrDcimvac", 112412504Snikos.nikoleris@arm.com "MiscRegRegImmOp", 112512358Snikos.nikoleris@arm.com {"memacc_code": McrDcCheckCode, 112612358Snikos.nikoleris@arm.com "postacc_code": "", 112712358Snikos.nikoleris@arm.com "ea_code": McrDcimvacCode, 112812358Snikos.nikoleris@arm.com "predicate_test": predicateTest}, 112912358Snikos.nikoleris@arm.com ['IsMemRef', 'IsStore']) 113012358Snikos.nikoleris@arm.com header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop) 113112358Snikos.nikoleris@arm.com decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop) 113212358Snikos.nikoleris@arm.com exec_output += Mcr15Execute.subst(McrDcimvacIop) + \ 113312358Snikos.nikoleris@arm.com Mcr15InitiateAcc.subst(McrDcimvacIop) + \ 113412358Snikos.nikoleris@arm.com Mcr15CompleteAcc.subst(McrDcimvacIop) 113512358Snikos.nikoleris@arm.com 113612358Snikos.nikoleris@arm.com McrDccmvacCode = ''' 113712358Snikos.nikoleris@arm.com const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 113812358Snikos.nikoleris@arm.com Request::CLEAN | 113912358Snikos.nikoleris@arm.com Request::DST_POC); 114012358Snikos.nikoleris@arm.com EA = Op1; 114112358Snikos.nikoleris@arm.com ''' 114212504Snikos.nikoleris@arm.com McrDccmvacIop = InstObjParams("mcr", "McrDccmvac", 114312504Snikos.nikoleris@arm.com "MiscRegRegImmOp", 114412358Snikos.nikoleris@arm.com {"memacc_code": McrDcCheckCode, 114512358Snikos.nikoleris@arm.com "postacc_code": "", 114612358Snikos.nikoleris@arm.com "ea_code": McrDccmvacCode, 114712358Snikos.nikoleris@arm.com "predicate_test": predicateTest}, 114812358Snikos.nikoleris@arm.com ['IsMemRef', 'IsStore']) 114912358Snikos.nikoleris@arm.com header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop) 115012358Snikos.nikoleris@arm.com decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop) 115112358Snikos.nikoleris@arm.com exec_output += Mcr15Execute.subst(McrDccmvacIop) + \ 115212358Snikos.nikoleris@arm.com Mcr15InitiateAcc.subst(McrDccmvacIop) + \ 115312358Snikos.nikoleris@arm.com Mcr15CompleteAcc.subst(McrDccmvacIop) 115412358Snikos.nikoleris@arm.com 115512358Snikos.nikoleris@arm.com McrDccmvauCode = ''' 115612358Snikos.nikoleris@arm.com const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 115712358Snikos.nikoleris@arm.com Request::CLEAN | 115812358Snikos.nikoleris@arm.com Request::DST_POU); 115912358Snikos.nikoleris@arm.com EA = Op1; 116012358Snikos.nikoleris@arm.com ''' 116112504Snikos.nikoleris@arm.com McrDccmvauIop = InstObjParams("mcr", "McrDccmvau", 116212504Snikos.nikoleris@arm.com "MiscRegRegImmOp", 116312358Snikos.nikoleris@arm.com {"memacc_code": McrDcCheckCode, 116412358Snikos.nikoleris@arm.com "postacc_code": "", 116512358Snikos.nikoleris@arm.com "ea_code": McrDccmvauCode, 116612358Snikos.nikoleris@arm.com "predicate_test": predicateTest}, 116712358Snikos.nikoleris@arm.com ['IsMemRef', 'IsStore']) 116812358Snikos.nikoleris@arm.com header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop) 116912358Snikos.nikoleris@arm.com decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop) 117012358Snikos.nikoleris@arm.com exec_output += Mcr15Execute.subst(McrDccmvauIop) + \ 117112358Snikos.nikoleris@arm.com Mcr15InitiateAcc.subst(McrDccmvauIop) + \ 117212358Snikos.nikoleris@arm.com Mcr15CompleteAcc.subst(McrDccmvauIop) 117312358Snikos.nikoleris@arm.com 117412358Snikos.nikoleris@arm.com McrDccimvacCode = ''' 117512358Snikos.nikoleris@arm.com const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 117612358Snikos.nikoleris@arm.com Request::CLEAN | 117712358Snikos.nikoleris@arm.com Request::INVALIDATE | 117812358Snikos.nikoleris@arm.com Request::DST_POC); 117912358Snikos.nikoleris@arm.com EA = Op1; 118012358Snikos.nikoleris@arm.com ''' 118112504Snikos.nikoleris@arm.com McrDccimvacIop = InstObjParams("mcr", "McrDccimvac", 118212504Snikos.nikoleris@arm.com "MiscRegRegImmOp", 118312358Snikos.nikoleris@arm.com {"memacc_code": McrDcCheckCode, 118412358Snikos.nikoleris@arm.com "postacc_code": "", 118512358Snikos.nikoleris@arm.com "ea_code": McrDccimvacCode, 118612358Snikos.nikoleris@arm.com "predicate_test": predicateTest}, 118712358Snikos.nikoleris@arm.com ['IsMemRef', 'IsStore']) 118812358Snikos.nikoleris@arm.com header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop) 118912358Snikos.nikoleris@arm.com decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop) 119012358Snikos.nikoleris@arm.com exec_output += Mcr15Execute.subst(McrDccimvacIop) + \ 119112358Snikos.nikoleris@arm.com Mcr15InitiateAcc.subst(McrDccimvacIop) + \ 119212358Snikos.nikoleris@arm.com Mcr15CompleteAcc.subst(McrDccimvacIop) 119312358Snikos.nikoleris@arm.com 11947605SGene.Wu@arm.com isbCode = ''' 119510037SARM gem5 Developers // If the barrier is due to a CP15 access check for hyp traps 119613999Sgiacomo.travaglini@arm.com if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, 119713999Sgiacomo.travaglini@arm.com xc->tcBase(), imm)) { 119810474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 119910037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC); 120010037SARM gem5 Developers } 12017605SGene.Wu@arm.com ''' 120210037SARM gem5 Developers isbIop = InstObjParams("isb", "Isb", "ImmOp", 12037605SGene.Wu@arm.com {"code": isbCode, 12048068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 120512488Sgiacomo.travaglini@arm.com ['IsSquashAfter']) 120610037SARM gem5 Developers header_output += ImmOpDeclare.subst(isbIop) 120710037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(isbIop) 12087605SGene.Wu@arm.com exec_output += PredOpExecute.subst(isbIop) 12097605SGene.Wu@arm.com 12107605SGene.Wu@arm.com dsbCode = ''' 121110037SARM gem5 Developers // If the barrier is due to a CP15 access check for hyp traps 121213999Sgiacomo.travaglini@arm.com if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, 121313999Sgiacomo.travaglini@arm.com xc->tcBase(), imm)) { 121410474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 121510037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC); 121610037SARM gem5 Developers } 12177605SGene.Wu@arm.com ''' 121810037SARM gem5 Developers dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", 12197605SGene.Wu@arm.com {"code": dsbCode, 12208068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 122112261Sgiacomo.travaglini@arm.com ['IsMemBarrier', 'IsSerializeAfter']) 122210037SARM gem5 Developers header_output += ImmOpDeclare.subst(dsbIop) 122310037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(dsbIop) 12247605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dsbIop) 12257605SGene.Wu@arm.com 12267605SGene.Wu@arm.com dmbCode = ''' 122710037SARM gem5 Developers // If the barrier is due to a CP15 access check for hyp traps 122813999Sgiacomo.travaglini@arm.com if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, 122913999Sgiacomo.travaglini@arm.com xc->tcBase(), imm)) { 123010474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 123110037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC); 123210037SARM gem5 Developers } 12337605SGene.Wu@arm.com ''' 123410037SARM gem5 Developers dmbIop = InstObjParams("dmb", "Dmb", "ImmOp", 12357605SGene.Wu@arm.com {"code": dmbCode, 12368068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 12378068SAli.Saidi@ARM.com ['IsMemBarrier']) 123810037SARM gem5 Developers header_output += ImmOpDeclare.subst(dmbIop) 123910037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(dmbIop) 12407605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dmbIop) 12417605SGene.Wu@arm.com 12427613SGene.Wu@arm.com dbgCode = ''' 12437613SGene.Wu@arm.com ''' 12447613SGene.Wu@arm.com dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 12457613SGene.Wu@arm.com {"code": dbgCode, 12467613SGene.Wu@arm.com "predicate_test": predicateTest}) 12477613SGene.Wu@arm.com header_output += BasicDeclare.subst(dbgIop) 12487613SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dbgIop) 12497613SGene.Wu@arm.com exec_output += PredOpExecute.subst(dbgIop) 12507613SGene.Wu@arm.com 12517315Sgblack@eecs.umich.edu cpsCode = ''' 12527315Sgblack@eecs.umich.edu uint32_t mode = bits(imm, 4, 0); 12537315Sgblack@eecs.umich.edu uint32_t f = bits(imm, 5); 12547315Sgblack@eecs.umich.edu uint32_t i = bits(imm, 6); 12557315Sgblack@eecs.umich.edu uint32_t a = bits(imm, 7); 12567315Sgblack@eecs.umich.edu bool setMode = bits(imm, 8); 12577315Sgblack@eecs.umich.edu bool enable = bits(imm, 9); 12587315Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 12597400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 12607315Sgblack@eecs.umich.edu if (cpsr.mode != MODE_USER) { 12617315Sgblack@eecs.umich.edu if (enable) { 12627315Sgblack@eecs.umich.edu if (f) cpsr.f = 0; 12637315Sgblack@eecs.umich.edu if (i) cpsr.i = 0; 12647315Sgblack@eecs.umich.edu if (a) cpsr.a = 0; 12657315Sgblack@eecs.umich.edu } else { 12667400SAli.Saidi@ARM.com if (f && !sctlr.nmfi) cpsr.f = 1; 12677315Sgblack@eecs.umich.edu if (i) cpsr.i = 1; 12687315Sgblack@eecs.umich.edu if (a) cpsr.a = 1; 12697315Sgblack@eecs.umich.edu } 12707315Sgblack@eecs.umich.edu if (setMode) { 12717315Sgblack@eecs.umich.edu cpsr.mode = mode; 12727315Sgblack@eecs.umich.edu } 12737315Sgblack@eecs.umich.edu } 12747315Sgblack@eecs.umich.edu Cpsr = cpsr; 12757315Sgblack@eecs.umich.edu ''' 12767315Sgblack@eecs.umich.edu cpsIop = InstObjParams("cps", "Cps", "ImmOp", 12777315Sgblack@eecs.umich.edu { "code": cpsCode, 12787599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 12797599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 12807315Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(cpsIop) 12817315Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(cpsIop) 12827315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(cpsIop) 12837202Sgblack@eecs.umich.edu}}; 1284