misc.isa revision 12646
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 37199Sgblack@eecs.umich.edu// Copyright (c) 2010-2013,2017-2018 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 437199Sgblack@eecs.umich.edu ThreadContext *tc = xc->tcBase(); 447199Sgblack@eecs.umich.edu 457199Sgblack@eecs.umich.edu const auto semihost_imm = Thumb? 0xAB : 0x123456; 467199Sgblack@eecs.umich.edu 477199Sgblack@eecs.umich.edu if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { 487199Sgblack@eecs.umich.edu R0 = ArmSystem::callSemihosting32(tc, R0, R1); 497199Sgblack@eecs.umich.edu } else { 507199Sgblack@eecs.umich.edu fault = std::make_shared<SupervisorCall>(machInst, imm); 517199Sgblack@eecs.umich.edu } 527199Sgblack@eecs.umich.edu ''' 537199Sgblack@eecs.umich.edu 547199Sgblack@eecs.umich.edu svcIop = InstObjParams("svc", "Svc", "ImmOp", 557199Sgblack@eecs.umich.edu { "code": svcCode, 567199Sgblack@eecs.umich.edu "predicate_test": predicateTest, 577199Sgblack@eecs.umich.edu "thumb_semihost": '0xAB', 587202Sgblack@eecs.umich.edu "arm_semihost": '0x123456' }, 597202Sgblack@eecs.umich.edu ["IsSyscall", "IsNonSpeculative", 607202Sgblack@eecs.umich.edu "IsSerializeAfter"]) 617202Sgblack@eecs.umich.edu header_output = ImmOpDeclare.subst(svcIop) 627202Sgblack@eecs.umich.edu decoder_output = SemihostConstructor.subst(svcIop) 637202Sgblack@eecs.umich.edu exec_output = PredOpExecute.subst(svcIop) 647202Sgblack@eecs.umich.edu 657202Sgblack@eecs.umich.edu hltCode = ''' 667599Sminkyu.jeong@arm.com ThreadContext *tc = xc->tcBase(); 677783SGiacomo.Gabrielli@arm.com 687202Sgblack@eecs.umich.edu const auto semihost_imm = Thumb? 0x3C : 0xF000; 697202Sgblack@eecs.umich.edu 707202Sgblack@eecs.umich.edu if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { 717202Sgblack@eecs.umich.edu R0 = ArmSystem::callSemihosting32(tc, R0, R1); 727202Sgblack@eecs.umich.edu } else { 737202Sgblack@eecs.umich.edu // HLT instructions aren't implemented, so treat them as undefined 747202Sgblack@eecs.umich.edu // instructions. 757599Sminkyu.jeong@arm.com fault = std::make_shared<UndefinedInstruction>( 767783SGiacomo.Gabrielli@arm.com machInst, false, mnemonic); 777202Sgblack@eecs.umich.edu } 787202Sgblack@eecs.umich.edu ''' 797202Sgblack@eecs.umich.edu 807202Sgblack@eecs.umich.edu hltIop = InstObjParams("hlt", "Hlt", "ImmOp", 817202Sgblack@eecs.umich.edu { "code": hltCode, 827400SAli.Saidi@ARM.com "predicate_test": predicateTest, 837202Sgblack@eecs.umich.edu "thumb_semihost": '0x3C', 847400SAli.Saidi@ARM.com "arm_semihost": '0xF000' }, 857202Sgblack@eecs.umich.edu ["IsNonSpeculative"]) 867202Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(hltIop) 877202Sgblack@eecs.umich.edu decoder_output += SemihostConstructor.subst(hltIop) 887202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(hltIop) 897202Sgblack@eecs.umich.edu 907599Sminkyu.jeong@arm.com smcCode = ''' 917599Sminkyu.jeong@arm.com HCR hcr = Hcr; 927202Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 937202Sgblack@eecs.umich.edu SCR scr = Scr; 947202Sgblack@eecs.umich.edu 957202Sgblack@eecs.umich.edu if ((cpsr.mode != MODE_USER) && FullSystem) { 967202Sgblack@eecs.umich.edu if (ArmSystem::haveVirtualization(xc->tcBase()) && 977202Sgblack@eecs.umich.edu !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) { 987202Sgblack@eecs.umich.edu fault = std::make_shared<HypervisorTrap>(machInst, 0, 997599Sminkyu.jeong@arm.com EC_SMC_TO_HYP); 1007599Sminkyu.jeong@arm.com } else { 1017202Sgblack@eecs.umich.edu if (scr.scd) { 1027202Sgblack@eecs.umich.edu fault = disabledFault(); 1037202Sgblack@eecs.umich.edu } else { 1047202Sgblack@eecs.umich.edu fault = std::make_shared<SecureMonitorCall>(machInst); 1057202Sgblack@eecs.umich.edu } 1067400SAli.Saidi@ARM.com } 1077202Sgblack@eecs.umich.edu } else { 1087400SAli.Saidi@ARM.com fault = disabledFault(); 1097202Sgblack@eecs.umich.edu } 1107202Sgblack@eecs.umich.edu ''' 1117202Sgblack@eecs.umich.edu 1127202Sgblack@eecs.umich.edu smcIop = InstObjParams("smc", "Smc", "PredOp", 1137202Sgblack@eecs.umich.edu { "code": smcCode, 1147599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1157599Sminkyu.jeong@arm.com ["IsNonSpeculative", "IsSerializeAfter"]) 1167202Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(smcIop) 1177202Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(smcIop) 1187202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(smcIop) 1197202Sgblack@eecs.umich.edu 1207202Sgblack@eecs.umich.edu hvcCode = ''' 1217202Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 1227202Sgblack@eecs.umich.edu SCR scr = Scr; 1237599Sminkyu.jeong@arm.com 1247599Sminkyu.jeong@arm.com // Filter out the various cases where this instruction isn't defined 1257202Sgblack@eecs.umich.edu if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) || 1267202Sgblack@eecs.umich.edu (cpsr.mode == MODE_USER) || 1277202Sgblack@eecs.umich.edu (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { 1287209Sgblack@eecs.umich.edu fault = disabledFault(); 1297209Sgblack@eecs.umich.edu } else { 1307209Sgblack@eecs.umich.edu fault = std::make_shared<HypervisorCall>(machInst, imm); 1317209Sgblack@eecs.umich.edu } 1327209Sgblack@eecs.umich.edu ''' 1337261Sgblack@eecs.umich.edu 1347209Sgblack@eecs.umich.edu hvcIop = InstObjParams("hvc", "Hvc", "ImmOp", 1357209Sgblack@eecs.umich.edu { "code": hvcCode, 1367261Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 1377261Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsSerializeAfter"]) 1387209Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(hvcIop) 1397209Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(hvcIop) 1407209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(hvcIop) 1417209Sgblack@eecs.umich.edu 1427209Sgblack@eecs.umich.edu eretCode = ''' 1437209Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 1447209Sgblack@eecs.umich.edu CPSR old_cpsr = Cpsr; 1457209Sgblack@eecs.umich.edu old_cpsr.nz = CondCodesNZ; 1467209Sgblack@eecs.umich.edu old_cpsr.c = CondCodesC; 1477261Sgblack@eecs.umich.edu old_cpsr.v = CondCodesV; 1487209Sgblack@eecs.umich.edu old_cpsr.ge = CondCodesGE; 1497209Sgblack@eecs.umich.edu 1507261Sgblack@eecs.umich.edu CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, 1517261Sgblack@eecs.umich.edu true, sctlr.nmfi, xc->tcBase()); 1527209Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & new_cpsr; 1537209Sgblack@eecs.umich.edu CondCodesNZ = new_cpsr.nz; 1547209Sgblack@eecs.umich.edu CondCodesC = new_cpsr.c; 1557209Sgblack@eecs.umich.edu CondCodesV = new_cpsr.v; 1567209Sgblack@eecs.umich.edu CondCodesGE = new_cpsr.ge; 1577209Sgblack@eecs.umich.edu 1587261Sgblack@eecs.umich.edu NextThumb = (new_cpsr).t; 1597209Sgblack@eecs.umich.edu NextJazelle = (new_cpsr).j; 1607209Sgblack@eecs.umich.edu NextItState = (((new_cpsr).it2 << 2) & 0xFC) 1617261Sgblack@eecs.umich.edu | ((new_cpsr).it1 & 0x3); 1627261Sgblack@eecs.umich.edu 1637209Sgblack@eecs.umich.edu NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR; 1647226Sgblack@eecs.umich.edu ''' 1657249Sgblack@eecs.umich.edu 1667249Sgblack@eecs.umich.edu eretIop = InstObjParams("eret", "Eret", "PredOp", 1677249Sgblack@eecs.umich.edu { "code": eretCode, 1687249Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 1697249Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsSerializeAfter", 1707249Sgblack@eecs.umich.edu "IsSquashAfter"]) 1717249Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(eretIop) 1727249Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(eretIop) 1737249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(eretIop) 1747249Sgblack@eecs.umich.edu 1757249Sgblack@eecs.umich.edu crcCode = ''' 1767249Sgblack@eecs.umich.edu constexpr uint8_t size_bytes = %(sz)d; 1777249Sgblack@eecs.umich.edu constexpr uint32_t poly = %(polynom)s; 1787261Sgblack@eecs.umich.edu 1797249Sgblack@eecs.umich.edu uint32_t data = htole(Op2); 1807249Sgblack@eecs.umich.edu auto data_buffer = reinterpret_cast<uint8_t*>(&data); 1817261Sgblack@eecs.umich.edu 1827261Sgblack@eecs.umich.edu Dest = crc32<poly>( 1837249Sgblack@eecs.umich.edu data_buffer, /* Message Register */ 1847249Sgblack@eecs.umich.edu Op1, /* Initial Value of the CRC */ 1857251Sgblack@eecs.umich.edu size_bytes /* Size of the original Message */ 1867251Sgblack@eecs.umich.edu ); 1877251Sgblack@eecs.umich.edu ''' 1887261Sgblack@eecs.umich.edu 1897251Sgblack@eecs.umich.edu def crc32Emit(mnem, implCode, castagnoli, size): 1907251Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1917261Sgblack@eecs.umich.edu 1927261Sgblack@eecs.umich.edu if castagnoli: 1937251Sgblack@eecs.umich.edu # crc32c instructions 1947251Sgblack@eecs.umich.edu poly = "0x1EDC6F41" 1957226Sgblack@eecs.umich.edu else: 1967226Sgblack@eecs.umich.edu # crc32 instructions 1977226Sgblack@eecs.umich.edu poly = "0x04C11DB7" 1987232Sgblack@eecs.umich.edu 1997226Sgblack@eecs.umich.edu data = {'sz' : size, 'polynom': poly} 2007226Sgblack@eecs.umich.edu 2017226Sgblack@eecs.umich.edu instCode = implCode % data 2027226Sgblack@eecs.umich.edu 2037226Sgblack@eecs.umich.edu crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp", 2047232Sgblack@eecs.umich.edu { "code": instCode, 2057226Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2067422Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(crcIop) 2077232Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(crcIop) 2087232Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(crcIop) 2097226Sgblack@eecs.umich.edu 2107226Sgblack@eecs.umich.edu crc32Emit("crc32b", crcCode, False, 1); 2117226Sgblack@eecs.umich.edu crc32Emit("crc32h", crcCode, False, 2); 2127226Sgblack@eecs.umich.edu crc32Emit("crc32w", crcCode, False, 4); 2137226Sgblack@eecs.umich.edu crc32Emit("crc32cb", crcCode, True, 1); 2147232Sgblack@eecs.umich.edu crc32Emit("crc32ch", crcCode, True, 2); 2157226Sgblack@eecs.umich.edu crc32Emit("crc32cw", crcCode, True, 4); 2167226Sgblack@eecs.umich.edu 2177226Sgblack@eecs.umich.edu}}; 2187226Sgblack@eecs.umich.edu 2197226Sgblack@eecs.umich.edulet {{ 2207232Sgblack@eecs.umich.edu 2217226Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 2227422Sgblack@eecs.umich.edu 2237232Sgblack@eecs.umich.edu mrsCpsrCode = ''' 2247232Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 2257226Sgblack@eecs.umich.edu cpsr.nz = CondCodesNZ; 2267226Sgblack@eecs.umich.edu cpsr.c = CondCodesC; 2277226Sgblack@eecs.umich.edu cpsr.v = CondCodesV; 2287226Sgblack@eecs.umich.edu cpsr.ge = CondCodesGE; 2297226Sgblack@eecs.umich.edu Dest = cpsr & 0xF8FF03DF 2307226Sgblack@eecs.umich.edu ''' 2317226Sgblack@eecs.umich.edu 2327226Sgblack@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 2337232Sgblack@eecs.umich.edu { "code": mrsCpsrCode, 2347226Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, 2357226Sgblack@eecs.umich.edu ["IsSerializeBefore"]) 2367232Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsCpsrIop) 2377226Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 2387226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 2397226Sgblack@eecs.umich.edu 2407226Sgblack@eecs.umich.edu mrsSpsrCode = "Dest = Spsr" 2417232Sgblack@eecs.umich.edu mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 2427226Sgblack@eecs.umich.edu { "code": mrsSpsrCode, 2437422Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 2447232Sgblack@eecs.umich.edu ["IsSerializeBefore"]) 2457232Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsSpsrIop) 2467226Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 2477226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsSpsrIop) 2487226Sgblack@eecs.umich.edu 2497226Sgblack@eecs.umich.edu mrsBankedRegCode = ''' 2507226Sgblack@eecs.umich.edu bool isIntReg; 2517226Sgblack@eecs.umich.edu int regIdx; 2527226Sgblack@eecs.umich.edu 2537226Sgblack@eecs.umich.edu if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 2547232Sgblack@eecs.umich.edu if (isIntReg) { 2557226Sgblack@eecs.umich.edu Dest = DecodedBankedIntReg; 2567226Sgblack@eecs.umich.edu } else { 2577232Sgblack@eecs.umich.edu Dest = xc->readMiscReg(regIdx); 2587226Sgblack@eecs.umich.edu } 2597226Sgblack@eecs.umich.edu } else { 2607226Sgblack@eecs.umich.edu return std::make_shared<UndefinedInstruction>(machInst, false, 2617226Sgblack@eecs.umich.edu mnemonic); 2627232Sgblack@eecs.umich.edu } 2637226Sgblack@eecs.umich.edu ''' 2647422Sgblack@eecs.umich.edu mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp", 2657232Sgblack@eecs.umich.edu { "code": mrsBankedRegCode, 2667232Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 2677226Sgblack@eecs.umich.edu ["IsSerializeBefore"]) 2687234Sgblack@eecs.umich.edu header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop) 2697234Sgblack@eecs.umich.edu decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop) 2707234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsBankedRegIop) 2717234Sgblack@eecs.umich.edu 2727234Sgblack@eecs.umich.edu msrBankedRegCode = ''' 2737234Sgblack@eecs.umich.edu bool isIntReg; 2747234Sgblack@eecs.umich.edu int regIdx; 2757234Sgblack@eecs.umich.edu 2767234Sgblack@eecs.umich.edu if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 2777234Sgblack@eecs.umich.edu if (isIntReg) { 2787234Sgblack@eecs.umich.edu // This is a bit nasty, you would have thought that 2797234Sgblack@eecs.umich.edu // DecodedBankedIntReg wouldn't be written to unless the 2807234Sgblack@eecs.umich.edu // conditions on the IF statements above are met, however if 2817234Sgblack@eecs.umich.edu // you look at the generated C code you'll find that they are. 2827234Sgblack@eecs.umich.edu // However this is safe as DecodedBankedIntReg (which is used 2837234Sgblack@eecs.umich.edu // in operands.isa to get the index of DecodedBankedIntReg) 2847234Sgblack@eecs.umich.edu // will return INTREG_DUMMY if its not a valid integer 2857234Sgblack@eecs.umich.edu // register, so redirecting the write to somewhere we don't 2867234Sgblack@eecs.umich.edu // care about. 2877234Sgblack@eecs.umich.edu DecodedBankedIntReg = Op1; 2887234Sgblack@eecs.umich.edu } else { 2897234Sgblack@eecs.umich.edu xc->setMiscReg(regIdx, Op1); 2907234Sgblack@eecs.umich.edu } 2917234Sgblack@eecs.umich.edu } else { 2927234Sgblack@eecs.umich.edu return std::make_shared<UndefinedInstruction>(machInst, false, 2937234Sgblack@eecs.umich.edu mnemonic); 2947234Sgblack@eecs.umich.edu } 2957234Sgblack@eecs.umich.edu ''' 2967234Sgblack@eecs.umich.edu msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", 2977234Sgblack@eecs.umich.edu { "code": msrBankedRegCode, 2987234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 2997234Sgblack@eecs.umich.edu ["IsSerializeAfter", "IsNonSpeculative"]) 3007234Sgblack@eecs.umich.edu header_output += MsrBankedRegDeclare.subst(msrBankedRegIop) 3017234Sgblack@eecs.umich.edu decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop) 3027234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrBankedRegIop) 3037234Sgblack@eecs.umich.edu 3047234Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 3057234Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 3067234Sgblack@eecs.umich.edu CPSR old_cpsr = Cpsr; 3077234Sgblack@eecs.umich.edu old_cpsr.nz = CondCodesNZ; 3087234Sgblack@eecs.umich.edu old_cpsr.c = CondCodesC; 3097234Sgblack@eecs.umich.edu old_cpsr.v = CondCodesV; 3107234Sgblack@eecs.umich.edu old_cpsr.ge = CondCodesGE; 3117234Sgblack@eecs.umich.edu 3127234Sgblack@eecs.umich.edu CPSR new_cpsr = 3137234Sgblack@eecs.umich.edu cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false, 3147234Sgblack@eecs.umich.edu sctlr.nmfi, xc->tcBase()); 3157234Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & new_cpsr; 3167234Sgblack@eecs.umich.edu CondCodesNZ = new_cpsr.nz; 3177234Sgblack@eecs.umich.edu CondCodesC = new_cpsr.c; 3187234Sgblack@eecs.umich.edu CondCodesV = new_cpsr.v; 3197234Sgblack@eecs.umich.edu CondCodesGE = new_cpsr.ge; 3207234Sgblack@eecs.umich.edu ''' 3217234Sgblack@eecs.umich.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 3227234Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 3237234Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, 3247234Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 3257234Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrCpsrRegIop) 3267234Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 3277234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrRegIop) 3287234Sgblack@eecs.umich.edu 3297234Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 3307234Sgblack@eecs.umich.edu msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 3317234Sgblack@eecs.umich.edu { "code": msrSpsrRegCode, 3327234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 3337234Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 3347234Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrSpsrRegIop) 3357234Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 3367234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrRegIop) 3377234Sgblack@eecs.umich.edu 3387234Sgblack@eecs.umich.edu msrCpsrImmCode = ''' 3397234Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 3407234Sgblack@eecs.umich.edu CPSR old_cpsr = Cpsr; 3417234Sgblack@eecs.umich.edu old_cpsr.nz = CondCodesNZ; 3427234Sgblack@eecs.umich.edu old_cpsr.c = CondCodesC; 3437234Sgblack@eecs.umich.edu old_cpsr.v = CondCodesV; 3447234Sgblack@eecs.umich.edu old_cpsr.ge = CondCodesGE; 3457234Sgblack@eecs.umich.edu CPSR new_cpsr = 3467234Sgblack@eecs.umich.edu cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false, 3477234Sgblack@eecs.umich.edu sctlr.nmfi, xc->tcBase()); 3487234Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & new_cpsr; 3497234Sgblack@eecs.umich.edu CondCodesNZ = new_cpsr.nz; 3507234Sgblack@eecs.umich.edu CondCodesC = new_cpsr.c; 3517234Sgblack@eecs.umich.edu CondCodesV = new_cpsr.v; 3527234Sgblack@eecs.umich.edu CondCodesGE = new_cpsr.ge; 3537234Sgblack@eecs.umich.edu ''' 3547234Sgblack@eecs.umich.edu msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 3557234Sgblack@eecs.umich.edu { "code": msrCpsrImmCode, 3567234Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, 3577234Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 3587234Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrCpsrImmIop) 3597234Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 3607234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrImmIop) 3617234Sgblack@eecs.umich.edu 3627234Sgblack@eecs.umich.edu msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 3637234Sgblack@eecs.umich.edu msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 3647234Sgblack@eecs.umich.edu { "code": msrSpsrImmCode, 3657234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 3667234Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 3677234Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrSpsrImmIop) 3687234Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 3697234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrImmIop) 3707234Sgblack@eecs.umich.edu 3717234Sgblack@eecs.umich.edu revCode = ''' 3727234Sgblack@eecs.umich.edu uint32_t val = Op1; 3737234Sgblack@eecs.umich.edu Dest = swap_byte(val); 3747234Sgblack@eecs.umich.edu ''' 3757234Sgblack@eecs.umich.edu revIop = InstObjParams("rev", "Rev", "RegRegOp", 3767234Sgblack@eecs.umich.edu { "code": revCode, 3777234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3787234Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revIop) 3797234Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revIop) 3807234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revIop) 3817234Sgblack@eecs.umich.edu 3827234Sgblack@eecs.umich.edu rev16Code = ''' 3837234Sgblack@eecs.umich.edu uint32_t val = Op1; 3847234Sgblack@eecs.umich.edu Dest = (bits(val, 15, 8) << 0) | 3857234Sgblack@eecs.umich.edu (bits(val, 7, 0) << 8) | 3867234Sgblack@eecs.umich.edu (bits(val, 31, 24) << 16) | 3877234Sgblack@eecs.umich.edu (bits(val, 23, 16) << 24); 3887234Sgblack@eecs.umich.edu ''' 3897234Sgblack@eecs.umich.edu rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 3907234Sgblack@eecs.umich.edu { "code": rev16Code, 3917234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3927234Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rev16Iop) 3937234Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rev16Iop) 3947234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rev16Iop) 3957234Sgblack@eecs.umich.edu 3967234Sgblack@eecs.umich.edu revshCode = ''' 3977234Sgblack@eecs.umich.edu uint16_t val = Op1; 3987234Sgblack@eecs.umich.edu Dest = sext<16>(swap_byte(val)); 3997234Sgblack@eecs.umich.edu ''' 4007234Sgblack@eecs.umich.edu revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 4017234Sgblack@eecs.umich.edu { "code": revshCode, 4027234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4037234Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revshIop) 4047234Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revshIop) 4057234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revshIop) 4067234Sgblack@eecs.umich.edu 4077234Sgblack@eecs.umich.edu rbitCode = ''' 4087234Sgblack@eecs.umich.edu Dest = reverseBits(Op1); 4097234Sgblack@eecs.umich.edu ''' 4107239Sgblack@eecs.umich.edu rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 4117239Sgblack@eecs.umich.edu { "code": rbitCode, 4127239Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4137239Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rbitIop) 4147239Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rbitIop) 4157239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rbitIop) 4167239Sgblack@eecs.umich.edu 4177239Sgblack@eecs.umich.edu clzCode = ''' 4187239Sgblack@eecs.umich.edu Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 4197239Sgblack@eecs.umich.edu ''' 4207239Sgblack@eecs.umich.edu clzIop = InstObjParams("clz", "Clz", "RegRegOp", 4217239Sgblack@eecs.umich.edu { "code": clzCode, 4227239Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4237239Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(clzIop) 4247422Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(clzIop) 4257239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clzIop) 4267239Sgblack@eecs.umich.edu 4277239Sgblack@eecs.umich.edu ssatCode = ''' 4287242Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 4297242Sgblack@eecs.umich.edu int32_t res; 4307242Sgblack@eecs.umich.edu if (satInt(res, operand, imm)) 4317242Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 4327242Sgblack@eecs.umich.edu Dest = res; 4337242Sgblack@eecs.umich.edu ''' 4347242Sgblack@eecs.umich.edu ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 4357242Sgblack@eecs.umich.edu { "code": ssatCode, 4367242Sgblack@eecs.umich.edu "predicate_test": pickPredicate(ssatCode) }, []) 4377242Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 4387242Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 4397242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssatIop) 4407242Sgblack@eecs.umich.edu 4417242Sgblack@eecs.umich.edu usatCode = ''' 4427242Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 4437242Sgblack@eecs.umich.edu int32_t res; 4447242Sgblack@eecs.umich.edu if (uSatInt(res, operand, imm)) 4457242Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 4467242Sgblack@eecs.umich.edu Dest = res; 4477242Sgblack@eecs.umich.edu ''' 4487242Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 4497242Sgblack@eecs.umich.edu { "code": usatCode, 4507242Sgblack@eecs.umich.edu "predicate_test": pickPredicate(usatCode) }, []) 4517242Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(usatIop) 4527242Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 4537242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usatIop) 4547242Sgblack@eecs.umich.edu 4557242Sgblack@eecs.umich.edu ssat16Code = ''' 4567242Sgblack@eecs.umich.edu int32_t res; 4577242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4587242Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 4597242Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 4607242Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 4617242Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 4627242Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 4637242Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 4647247Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 4657797Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 4667848SAli.Saidi@ARM.com Dest = resTemp; 4677410Sgblack@eecs.umich.edu ''' 4687410Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 4697410Sgblack@eecs.umich.edu { "code": ssat16Code, 4707410Sgblack@eecs.umich.edu "predicate_test": pickPredicate(ssat16Code) }, []) 4717408Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(ssat16Iop) 4728065SAli.Saidi@ARM.com decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 4738065SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(ssat16Iop) 4747247Sgblack@eecs.umich.edu 4757247Sgblack@eecs.umich.edu usat16Code = ''' 4767408Sgblack@eecs.umich.edu int32_t res; 4777408Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4787418Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 4797418Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 4807418Sgblack@eecs.umich.edu if (uSatInt(res, argLow, imm)) 4817418Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 4827418Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 4837418Sgblack@eecs.umich.edu if (uSatInt(res, argHigh, imm)) 4847418Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 4857418Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 4868142SAli.Saidi@ARM.com Dest = resTemp; 4877418Sgblack@eecs.umich.edu ''' 4888142SAli.Saidi@ARM.com usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 4898142SAli.Saidi@ARM.com { "code": usat16Code, 4908142SAli.Saidi@ARM.com "predicate_test": pickPredicate(usat16Code) }, []) 4917418Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(usat16Iop) 4928142SAli.Saidi@ARM.com decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 4937418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usat16Iop) 4947418Sgblack@eecs.umich.edu 4957418Sgblack@eecs.umich.edu sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 4967418Sgblack@eecs.umich.edu { "code": 4977648SAli.Saidi@ARM.com "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", 4987418Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4997418Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtbIop) 5008142SAli.Saidi@ARM.com decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 5017418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtbIop) 5027418Sgblack@eecs.umich.edu 5037418Sgblack@eecs.umich.edu sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 5047418Sgblack@eecs.umich.edu { "code": 5057418Sgblack@eecs.umich.edu ''' 5067418Sgblack@eecs.umich.edu Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + 5077418Sgblack@eecs.umich.edu Op1; 5087418Sgblack@eecs.umich.edu ''', 5098142SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 5107418Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 5117418Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 5128142SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(sxtabIop) 5137418Sgblack@eecs.umich.edu 5147418Sgblack@eecs.umich.edu sxtb16Code = ''' 5157418Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5168142SAli.Saidi@ARM.com replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 5177418Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5187418Sgblack@eecs.umich.edu sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 5197418Sgblack@eecs.umich.edu Dest = resTemp; 5208142SAli.Saidi@ARM.com ''' 5218142SAli.Saidi@ARM.com sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 5228142SAli.Saidi@ARM.com { "code": sxtb16Code, 5237418Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5247418Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 5257418Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 5267418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtb16Iop) 5278142SAli.Saidi@ARM.com 5287418Sgblack@eecs.umich.edu sxtab16Code = ''' 5297418Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5307418Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 5317418Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 5327408Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5338205SAli.Saidi@ARM.com sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 5347648SAli.Saidi@ARM.com bits(Op1, 31, 16)); 5357648SAli.Saidi@ARM.com Dest = resTemp; 5367408Sgblack@eecs.umich.edu ''' 5377408Sgblack@eecs.umich.edu sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 5387408Sgblack@eecs.umich.edu { "code": sxtab16Code, 5397409Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5407409Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 5417409Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 5427409Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtab16Iop) 5437409Sgblack@eecs.umich.edu 5447409Sgblack@eecs.umich.edu sxthCode = ''' 5457409Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 5467409Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 5477409Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 5487409Sgblack@eecs.umich.edu ''' 5497409Sgblack@eecs.umich.edu sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 5507409Sgblack@eecs.umich.edu { "code": sxthCode, 5517409Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5527254Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 5537254Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 5547254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 5557254Sgblack@eecs.umich.edu 5567254Sgblack@eecs.umich.edu sxtahCode = ''' 5577254Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 5587254Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 5597254Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated) + Op1; 5607254Sgblack@eecs.umich.edu ''' 5617254Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 5627254Sgblack@eecs.umich.edu { "code": sxtahCode, 5637254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5647254Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 5657254Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 5667254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtahIop) 5677254Sgblack@eecs.umich.edu 5687254Sgblack@eecs.umich.edu uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 5697254Sgblack@eecs.umich.edu { "code": "Dest = (uint8_t)(Op1_ud >> imm);", 5707254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5717254Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtbIop) 5727254Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 5737257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtbIop) 5747257Sgblack@eecs.umich.edu 5757257Sgblack@eecs.umich.edu uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 5767257Sgblack@eecs.umich.edu { "code": 5777257Sgblack@eecs.umich.edu "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", 5787257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5797257Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 5807257Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 5817257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 5827257Sgblack@eecs.umich.edu 5837257Sgblack@eecs.umich.edu uxtb16Code = ''' 5847257Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5857257Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 5867257Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5877257Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 5887257Sgblack@eecs.umich.edu Dest = resTemp; 5897257Sgblack@eecs.umich.edu ''' 5907257Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 5917257Sgblack@eecs.umich.edu { "code": uxtb16Code, 5927257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5937257Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 5947262Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 5957347SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(uxtb16Iop) 5967347SAli.Saidi@ARM.com 5977347SAli.Saidi@ARM.com uxtab16Code = ''' 5987347SAli.Saidi@ARM.com uint32_t resTemp = 0; 5997347SAli.Saidi@ARM.com replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 6007347SAli.Saidi@ARM.com bits(Op1, 15, 0)); 6017347SAli.Saidi@ARM.com replaceBits(resTemp, 31, 16, 6027347SAli.Saidi@ARM.com (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 6037347SAli.Saidi@ARM.com bits(Op1, 31, 16)); 6047347SAli.Saidi@ARM.com Dest = resTemp; 6057347SAli.Saidi@ARM.com ''' 6067262Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 6077347SAli.Saidi@ARM.com { "code": uxtab16Code, 6087262Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6097262Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 6107262Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 6117262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 6127262Sgblack@eecs.umich.edu 6137347SAli.Saidi@ARM.com uxthCode = ''' 6147347SAli.Saidi@ARM.com uint64_t rotated = (uint32_t)Op1; 6157347SAli.Saidi@ARM.com rotated = (rotated | (rotated << 32)) >> imm; 6167347SAli.Saidi@ARM.com Dest = (uint16_t)rotated; 6177347SAli.Saidi@ARM.com ''' 6187347SAli.Saidi@ARM.com uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 6197347SAli.Saidi@ARM.com { "code": uxthCode, 6207347SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 6217347SAli.Saidi@ARM.com header_output += RegImmRegOpDeclare.subst(uxthIop) 6227347SAli.Saidi@ARM.com decoder_output += RegImmRegOpConstructor.subst(uxthIop) 6237347SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(uxthIop) 6247262Sgblack@eecs.umich.edu 6257347SAli.Saidi@ARM.com uxtahCode = ''' 6267599Sminkyu.jeong@arm.com uint64_t rotated = (uint32_t)Op2; 6277599Sminkyu.jeong@arm.com rotated = (rotated | (rotated << 32)) >> imm; 6287262Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 6297262Sgblack@eecs.umich.edu ''' 6307262Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 6317283Sgblack@eecs.umich.edu { "code": uxtahCode, 6327420Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6337420Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 6347420Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 6357420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 6367420Sgblack@eecs.umich.edu 6377420Sgblack@eecs.umich.edu selCode = ''' 6387420Sgblack@eecs.umich.edu uint32_t resTemp = 0; 6397420Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 6407420Sgblack@eecs.umich.edu int low = i * 8; 6417599Sminkyu.jeong@arm.com int high = low + 7; 6427599Sminkyu.jeong@arm.com replaceBits(resTemp, high, low, 6437420Sgblack@eecs.umich.edu bits(CondCodesGE, i) ? 6447420Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 6457420Sgblack@eecs.umich.edu } 6467420Sgblack@eecs.umich.edu Dest = resTemp; 6477283Sgblack@eecs.umich.edu ''' 6487797Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 6497797Sgblack@eecs.umich.edu { "code": selCode, 6507283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6517283Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 6527283Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 6537283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 6547283Sgblack@eecs.umich.edu 6557283Sgblack@eecs.umich.edu usad8Code = ''' 6567283Sgblack@eecs.umich.edu uint32_t resTemp = 0; 6577283Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 6587283Sgblack@eecs.umich.edu int low = i * 8; 6597797Sgblack@eecs.umich.edu int high = low + 7; 6607797Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 6617283Sgblack@eecs.umich.edu bits(Op2, high, low); 6627283Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 6637283Sgblack@eecs.umich.edu } 6647283Sgblack@eecs.umich.edu Dest = resTemp; 6657283Sgblack@eecs.umich.edu ''' 6667283Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 6677283Sgblack@eecs.umich.edu { "code": usad8Code, 6687307Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6697307Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 6707307Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 6717307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usad8Iop) 6727307Sgblack@eecs.umich.edu 6737307Sgblack@eecs.umich.edu usada8Code = ''' 6747307Sgblack@eecs.umich.edu uint32_t resTemp = 0; 6757307Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 6767648SAli.Saidi@ARM.com int low = i * 8; 6777648SAli.Saidi@ARM.com int high = low + 7; 6787307Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 6797307Sgblack@eecs.umich.edu bits(Op2, high, low); 6807307Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 6817315Sgblack@eecs.umich.edu } 6827603SGene.Wu@arm.com Dest = Op3 + resTemp; 6838209SAli.Saidi@ARM.com ''' 6847603SGene.Wu@arm.com usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 6857603SGene.Wu@arm.com { "code": usada8Code, 6867603SGene.Wu@arm.com "predicate_test": predicateTest }, []) 6877603SGene.Wu@arm.com header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 6888209SAli.Saidi@ARM.com decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 6897603SGene.Wu@arm.com exec_output += PredOpExecute.subst(usada8Iop) 6907603SGene.Wu@arm.com 6917603SGene.Wu@arm.com bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n' 6927605SGene.Wu@arm.com bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 6938068SAli.Saidi@ARM.com header_output += BasicDeclare.subst(bkptIop) 6947605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(bkptIop) 6957605SGene.Wu@arm.com exec_output += BasicExecute.subst(bkptIop) 6967605SGene.Wu@arm.com 6978068SAli.Saidi@ARM.com nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop']) 6988068SAli.Saidi@ARM.com header_output += BasicDeclare.subst(nopIop) 6997605SGene.Wu@arm.com decoder_output += BasicConstructor64.subst(nopIop) 7007605SGene.Wu@arm.com exec_output += BasicExecute.subst(nopIop) 7017605SGene.Wu@arm.com 7027605SGene.Wu@arm.com yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 7037605SGene.Wu@arm.com { "code" : "", "predicate_test" : predicateTest }) 7048068SAli.Saidi@ARM.com header_output += BasicDeclare.subst(yieldIop) 7057605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(yieldIop) 7067605SGene.Wu@arm.com exec_output += PredOpExecute.subst(yieldIop) 7077605SGene.Wu@arm.com 7088068SAli.Saidi@ARM.com wfeCode = ''' 7098068SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 7107605SGene.Wu@arm.com SCR scr = Scr64; 7117605SGene.Wu@arm.com 7127605SGene.Wu@arm.com // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending, 7137605SGene.Wu@arm.com ThreadContext *tc = xc->tcBase(); 7147605SGene.Wu@arm.com if (SevMailbox == 1) { 7157605SGene.Wu@arm.com SevMailbox = 0; 7167605SGene.Wu@arm.com PseudoInst::quiesceSkip(tc); 7177605SGene.Wu@arm.com } else if (tc->getCpuPtr()->getInterruptController( 7188068SAli.Saidi@ARM.com tc->threadId())->checkInterrupts(tc)) { 7198068SAli.Saidi@ARM.com PseudoInst::quiesceSkip(tc); 7207605SGene.Wu@arm.com } else { 7217605SGene.Wu@arm.com fault = trapWFx(tc, cpsr, scr, true); 7227605SGene.Wu@arm.com if (fault == NoFault) { 7237605SGene.Wu@arm.com PseudoInst::quiesce(tc); 7247613SGene.Wu@arm.com } else { 7257613SGene.Wu@arm.com PseudoInst::quiesceSkip(tc); 7267613SGene.Wu@arm.com } 7277613SGene.Wu@arm.com } 7287613SGene.Wu@arm.com ''' 7297613SGene.Wu@arm.com wfePredFixUpCode = ''' 7307613SGene.Wu@arm.com // WFE is predicated false, reset SevMailbox to reduce spurious sleeps 7317613SGene.Wu@arm.com // and SEV interrupts 7327613SGene.Wu@arm.com SevMailbox = 1; 7337315Sgblack@eecs.umich.edu ''' 7347315Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 7357315Sgblack@eecs.umich.edu { "code" : wfeCode, 7367315Sgblack@eecs.umich.edu "pred_fixup" : wfePredFixUpCode, 7377315Sgblack@eecs.umich.edu "predicate_test" : predicateTest }, 7387315Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsQuiesce", 7397315Sgblack@eecs.umich.edu "IsSerializeAfter", "IsUnverifiable"]) 7407315Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 7417400SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(wfeIop) 7427315Sgblack@eecs.umich.edu exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) 7437315Sgblack@eecs.umich.edu 7447315Sgblack@eecs.umich.edu wfiCode = ''' 7457315Sgblack@eecs.umich.edu HCR hcr = Hcr; 7467315Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 7477315Sgblack@eecs.umich.edu SCR scr = Scr64; 7487400SAli.Saidi@ARM.com 7497315Sgblack@eecs.umich.edu // WFI doesn't sleep if interrupts are pending (masked or not) 7507315Sgblack@eecs.umich.edu ThreadContext *tc = xc->tcBase(); 7517315Sgblack@eecs.umich.edu if (tc->getCpuPtr()->getInterruptController( 7527315Sgblack@eecs.umich.edu tc->threadId())->checkWfiWake(hcr, cpsr, scr)) { 7537315Sgblack@eecs.umich.edu PseudoInst::quiesceSkip(tc); 7547315Sgblack@eecs.umich.edu } else { 7557315Sgblack@eecs.umich.edu fault = trapWFx(tc, cpsr, scr, false); 7567315Sgblack@eecs.umich.edu if (fault == NoFault) { 7577315Sgblack@eecs.umich.edu PseudoInst::quiesce(tc); 7587315Sgblack@eecs.umich.edu } else { 7597315Sgblack@eecs.umich.edu PseudoInst::quiesceSkip(tc); 7607599Sminkyu.jeong@arm.com } 7617599Sminkyu.jeong@arm.com } 7627315Sgblack@eecs.umich.edu tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 7637315Sgblack@eecs.umich.edu ''' 7647315Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 7657202Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 766 ["IsNonSpeculative", "IsQuiesce", 767 "IsSerializeAfter", "IsUnverifiable"]) 768 header_output += BasicDeclare.subst(wfiIop) 769 decoder_output += BasicConstructor.subst(wfiIop) 770 exec_output += QuiescePredOpExecute.subst(wfiIop) 771 772 sevCode = ''' 773 SevMailbox = 1; 774 System *sys = xc->tcBase()->getSystemPtr(); 775 for (int x = 0; x < sys->numContexts(); x++) { 776 ThreadContext *oc = sys->getThreadContext(x); 777 if (oc == xc->tcBase()) 778 continue; 779 // Wake CPU with interrupt if they were sleeping 780 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 781 // Post Interrupt and wake cpu if needed 782 oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0); 783 } 784 } 785 ''' 786 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 787 { "code" : sevCode, "predicate_test" : predicateTest }, 788 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 789 header_output += BasicDeclare.subst(sevIop) 790 decoder_output += BasicConstructor.subst(sevIop) 791 exec_output += PredOpExecute.subst(sevIop) 792 793 sevlCode = ''' 794 SevMailbox = 1; 795 ''' 796 sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \ 797 { "code" : sevlCode, "predicate_test" : predicateTest }, 798 ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 799 header_output += BasicDeclare.subst(sevlIop) 800 decoder_output += BasicConstructor.subst(sevlIop) 801 exec_output += BasicExecute.subst(sevlIop) 802 803 itIop = InstObjParams("it", "ItInst", "PredOp", \ 804 { "code" : ";", 805 "predicate_test" : predicateTest }, []) 806 header_output += BasicDeclare.subst(itIop) 807 decoder_output += BasicConstructor.subst(itIop) 808 exec_output += PredOpExecute.subst(itIop) 809 unknownCode = ''' 810 return std::make_shared<UndefinedInstruction>(machInst, true); 811 ''' 812 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 813 { "code": unknownCode, 814 "predicate_test": predicateTest }) 815 header_output += BasicDeclare.subst(unknownIop) 816 decoder_output += BasicConstructor.subst(unknownIop) 817 exec_output += PredOpExecute.subst(unknownIop) 818 819 ubfxCode = ''' 820 Dest = bits(Op1, imm2, imm1); 821 ''' 822 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 823 { "code": ubfxCode, 824 "predicate_test": predicateTest }, []) 825 header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 826 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 827 exec_output += PredOpExecute.subst(ubfxIop) 828 829 sbfxCode = ''' 830 int32_t resTemp = bits(Op1, imm2, imm1); 831 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 832 ''' 833 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 834 { "code": sbfxCode, 835 "predicate_test": predicateTest }, []) 836 header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 837 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 838 exec_output += PredOpExecute.subst(sbfxIop) 839 840 bfcCode = ''' 841 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 842 ''' 843 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 844 { "code": bfcCode, 845 "predicate_test": predicateTest }, []) 846 header_output += RegRegImmImmOpDeclare.subst(bfcIop) 847 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 848 exec_output += PredOpExecute.subst(bfcIop) 849 850 bfiCode = ''' 851 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 852 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 853 ''' 854 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 855 { "code": bfiCode, 856 "predicate_test": predicateTest }, []) 857 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 858 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 859 exec_output += PredOpExecute.subst(bfiIop) 860 861 mrc14code = ''' 862 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 863 RegId(MiscRegClass, op1)).index(); 864 bool can_read, undefined; 865 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 866 if (!can_read || undefined) { 867 return std::make_shared<UndefinedInstruction>(machInst, false, 868 mnemonic); 869 } 870 if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr, 871 Hstr, Hcptr, imm)) { 872 return std::make_shared<HypervisorTrap>(machInst, imm, 873 EC_TRAPPED_CP14_MCR_MRC); 874 } 875 Dest = MiscOp1; 876 ''' 877 878 mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp", 879 { "code": mrc14code, 880 "predicate_test": predicateTest }, []) 881 header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop) 882 decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop) 883 exec_output += PredOpExecute.subst(mrc14Iop) 884 885 886 mcr14code = ''' 887 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 888 RegId(MiscRegClass, dest)).index(); 889 bool can_write, undefined; 890 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 891 if (undefined || !can_write) { 892 return std::make_shared<UndefinedInstruction>(machInst, false, 893 mnemonic); 894 } 895 if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, 896 Hstr, Hcptr, imm)) { 897 return std::make_shared<HypervisorTrap>(machInst, imm, 898 EC_TRAPPED_CP14_MCR_MRC); 899 } 900 MiscDest = Op1; 901 ''' 902 mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp", 903 { "code": mcr14code, 904 "predicate_test": predicateTest }, 905 ["IsSerializeAfter","IsNonSpeculative"]) 906 header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop) 907 decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop) 908 exec_output += PredOpExecute.subst(mcr14Iop) 909 910 mrc15code = ''' 911 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); 912 MiscRegIndex miscReg = (MiscRegIndex) 913 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 914 preFlatOp1)).index(); 915 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 916 Hcptr, imm); 917 bool can_read, undefined; 918 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 919 // if we're in non secure PL1 mode then we can trap regargless of whether 920 // the register is accessable, in other modes we trap if only if the register 921 // IS accessable. 922 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 923 !inSecureState(Scr, Cpsr)))) { 924 return std::make_shared<UndefinedInstruction>(machInst, false, 925 mnemonic); 926 } 927 if (hypTrap) { 928 return std::make_shared<HypervisorTrap>(machInst, imm, 929 EC_TRAPPED_CP15_MCR_MRC); 930 } 931 Dest = MiscNsBankedOp1; 932 ''' 933 934 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", 935 { "code": mrc15code, 936 "predicate_test": predicateTest }, []) 937 header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop) 938 decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop) 939 exec_output += PredOpExecute.subst(mrc15Iop) 940 941 942 mcr15code = ''' 943 int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 944 MiscRegIndex miscReg = (MiscRegIndex) 945 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 946 preFlatDest)).index(); 947 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 948 Hcptr, imm); 949 bool can_write, undefined; 950 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 951 952 // if we're in non secure PL1 mode then we can trap regargless of whether 953 // the register is accessable, in other modes we trap if only if the register 954 // IS accessable. 955 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 956 !inSecureState(Scr, Cpsr)))) { 957 return std::make_shared<UndefinedInstruction>(machInst, false, 958 mnemonic); 959 } 960 if (hypTrap) { 961 return std::make_shared<HypervisorTrap>(machInst, imm, 962 EC_TRAPPED_CP15_MCR_MRC); 963 } 964 MiscNsBankedDest = Op1; 965 ''' 966 mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", 967 { "code": mcr15code, 968 "predicate_test": predicateTest }, 969 ["IsSerializeAfter","IsNonSpeculative"]) 970 header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop) 971 decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop) 972 exec_output += PredOpExecute.subst(mcr15Iop) 973 974 975 mrrc15code = ''' 976 int preFlatOp1 = snsBankedIndex(op1, xc->tcBase()); 977 MiscRegIndex miscReg = (MiscRegIndex) 978 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 979 preFlatOp1)).index(); 980 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 981 bool can_read, undefined; 982 std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 983 // if we're in non secure PL1 mode then we can trap regargless of whether 984 // the register is accessable, in other modes we trap if only if the register 985 // IS accessable. 986 if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 987 !inSecureState(Scr, Cpsr)))) { 988 return std::make_shared<UndefinedInstruction>(machInst, false, 989 mnemonic); 990 } 991 if (hypTrap) { 992 return std::make_shared<HypervisorTrap>(machInst, imm, 993 EC_TRAPPED_CP15_MCRR_MRRC); 994 } 995 Dest = bits(MiscNsBankedOp164, 63, 32); 996 Dest2 = bits(MiscNsBankedOp164, 31, 0); 997 ''' 998 mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp", 999 { "code": mrrc15code, 1000 "predicate_test": predicateTest }, []) 1001 header_output += MrrcOpDeclare.subst(mrrc15Iop) 1002 decoder_output += MrrcOpConstructor.subst(mrrc15Iop) 1003 exec_output += PredOpExecute.subst(mrrc15Iop) 1004 1005 1006 mcrr15code = ''' 1007 int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 1008 MiscRegIndex miscReg = (MiscRegIndex) 1009 xc->tcBase()->flattenRegId(RegId(MiscRegClass, 1010 preFlatDest)).index(); 1011 bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 1012 bool can_write, undefined; 1013 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 1014 1015 // if we're in non secure PL1 mode then we can trap regargless of whether 1016 // the register is accessable, in other modes we trap if only if the register 1017 // IS accessable. 1018 if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 1019 !inSecureState(Scr, Cpsr)))) { 1020 return std::make_shared<UndefinedInstruction>(machInst, false, 1021 mnemonic); 1022 } 1023 if (hypTrap) { 1024 return std::make_shared<HypervisorTrap>(machInst, imm, 1025 EC_TRAPPED_CP15_MCRR_MRRC); 1026 } 1027 MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2; 1028 ''' 1029 mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp", 1030 { "code": mcrr15code, 1031 "predicate_test": predicateTest }, []) 1032 header_output += McrrOpDeclare.subst(mcrr15Iop) 1033 decoder_output += McrrOpConstructor.subst(mcrr15Iop) 1034 exec_output += PredOpExecute.subst(mcrr15Iop) 1035 1036 1037 enterxCode = ''' 1038 NextThumb = true; 1039 NextJazelle = true; 1040 ''' 1041 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 1042 { "code": enterxCode, 1043 "predicate_test": predicateTest }, []) 1044 header_output += BasicDeclare.subst(enterxIop) 1045 decoder_output += BasicConstructor.subst(enterxIop) 1046 exec_output += PredOpExecute.subst(enterxIop) 1047 1048 leavexCode = ''' 1049 NextThumb = true; 1050 NextJazelle = false; 1051 ''' 1052 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 1053 { "code": leavexCode, 1054 "predicate_test": predicateTest }, []) 1055 header_output += BasicDeclare.subst(leavexIop) 1056 decoder_output += BasicConstructor.subst(leavexIop) 1057 exec_output += PredOpExecute.subst(leavexIop) 1058 1059 setendCode = ''' 1060 CPSR cpsr = Cpsr; 1061 cpsr.e = imm; 1062 Cpsr = cpsr; 1063 fault = checkSETENDEnabled(xc->tcBase(), cpsr); 1064 ''' 1065 setendIop = InstObjParams("setend", "Setend", "ImmOp", 1066 { "code": setendCode, 1067 "predicate_test": predicateTest }, 1068 ["IsSerializeAfter","IsNonSpeculative"]) 1069 header_output += ImmOpDeclare.subst(setendIop) 1070 decoder_output += ImmOpConstructor.subst(setendIop) 1071 exec_output += PredOpExecute.subst(setendIop) 1072 1073 clrexCode = ''' 1074 LLSCLock = 0; 1075 ''' 1076 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 1077 { "code": clrexCode, 1078 "predicate_test": predicateTest },[]) 1079 header_output += BasicDeclare.subst(clrexIop) 1080 decoder_output += BasicConstructor.subst(clrexIop) 1081 exec_output += PredOpExecute.subst(clrexIop) 1082 1083 McrDcCheckCode = ''' 1084 int preFlatDest = snsBankedIndex(dest, xc->tcBase()); 1085 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 1086 RegId(MiscRegClass, preFlatDest)).index(); 1087 bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 1088 Hcptr, imm); 1089 bool can_write, undefined; 1090 std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 1091 1092 // if we're in non secure PL1 mode then we can trap regardless 1093 // of whether the register is accessible, in other modes we 1094 // trap if only if the register IS accessible. 1095 if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) & 1096 !inSecureState(Scr, Cpsr)))) { 1097 return std::make_shared<UndefinedInstruction>(machInst, false, 1098 mnemonic); 1099 } 1100 if (hypTrap) { 1101 return std::make_shared<HypervisorTrap>(machInst, imm, 1102 EC_TRAPPED_CP15_MCR_MRC); 1103 } 1104 ''' 1105 1106 McrDcimvacCode = ''' 1107 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1108 Request::INVALIDATE | 1109 Request::DST_POC); 1110 EA = Op1; 1111 ''' 1112 McrDcimvacIop = InstObjParams("mcr", "McrDcimvac", 1113 "MiscRegRegImmOp", 1114 {"memacc_code": McrDcCheckCode, 1115 "postacc_code": "", 1116 "ea_code": McrDcimvacCode, 1117 "predicate_test": predicateTest}, 1118 ['IsMemRef', 'IsStore']) 1119 header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop) 1120 decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop) 1121 exec_output += Mcr15Execute.subst(McrDcimvacIop) + \ 1122 Mcr15InitiateAcc.subst(McrDcimvacIop) + \ 1123 Mcr15CompleteAcc.subst(McrDcimvacIop) 1124 1125 McrDccmvacCode = ''' 1126 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1127 Request::CLEAN | 1128 Request::DST_POC); 1129 EA = Op1; 1130 ''' 1131 McrDccmvacIop = InstObjParams("mcr", "McrDccmvac", 1132 "MiscRegRegImmOp", 1133 {"memacc_code": McrDcCheckCode, 1134 "postacc_code": "", 1135 "ea_code": McrDccmvacCode, 1136 "predicate_test": predicateTest}, 1137 ['IsMemRef', 'IsStore']) 1138 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop) 1139 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop) 1140 exec_output += Mcr15Execute.subst(McrDccmvacIop) + \ 1141 Mcr15InitiateAcc.subst(McrDccmvacIop) + \ 1142 Mcr15CompleteAcc.subst(McrDccmvacIop) 1143 1144 McrDccmvauCode = ''' 1145 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1146 Request::CLEAN | 1147 Request::DST_POU); 1148 EA = Op1; 1149 ''' 1150 McrDccmvauIop = InstObjParams("mcr", "McrDccmvau", 1151 "MiscRegRegImmOp", 1152 {"memacc_code": McrDcCheckCode, 1153 "postacc_code": "", 1154 "ea_code": McrDccmvauCode, 1155 "predicate_test": predicateTest}, 1156 ['IsMemRef', 'IsStore']) 1157 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop) 1158 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop) 1159 exec_output += Mcr15Execute.subst(McrDccmvauIop) + \ 1160 Mcr15InitiateAcc.subst(McrDccmvauIop) + \ 1161 Mcr15CompleteAcc.subst(McrDccmvauIop) 1162 1163 McrDccimvacCode = ''' 1164 const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne | 1165 Request::CLEAN | 1166 Request::INVALIDATE | 1167 Request::DST_POC); 1168 EA = Op1; 1169 ''' 1170 McrDccimvacIop = InstObjParams("mcr", "McrDccimvac", 1171 "MiscRegRegImmOp", 1172 {"memacc_code": McrDcCheckCode, 1173 "postacc_code": "", 1174 "ea_code": McrDccimvacCode, 1175 "predicate_test": predicateTest}, 1176 ['IsMemRef', 'IsStore']) 1177 header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop) 1178 decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop) 1179 exec_output += Mcr15Execute.subst(McrDccimvacIop) + \ 1180 Mcr15InitiateAcc.subst(McrDccimvacIop) + \ 1181 Mcr15CompleteAcc.subst(McrDccimvacIop) 1182 1183 isbCode = ''' 1184 // If the barrier is due to a CP15 access check for hyp traps 1185 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr, 1186 Hdcr, Hstr, Hcptr, imm)) { 1187 return std::make_shared<HypervisorTrap>(machInst, imm, 1188 EC_TRAPPED_CP15_MCR_MRC); 1189 } 1190 ''' 1191 isbIop = InstObjParams("isb", "Isb", "ImmOp", 1192 {"code": isbCode, 1193 "predicate_test": predicateTest}, 1194 ['IsSquashAfter']) 1195 header_output += ImmOpDeclare.subst(isbIop) 1196 decoder_output += ImmOpConstructor.subst(isbIop) 1197 exec_output += PredOpExecute.subst(isbIop) 1198 1199 dsbCode = ''' 1200 // If the barrier is due to a CP15 access check for hyp traps 1201 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr, 1202 Hdcr, Hstr, Hcptr, imm)) { 1203 return std::make_shared<HypervisorTrap>(machInst, imm, 1204 EC_TRAPPED_CP15_MCR_MRC); 1205 } 1206 ''' 1207 dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", 1208 {"code": dsbCode, 1209 "predicate_test": predicateTest}, 1210 ['IsMemBarrier', 'IsSerializeAfter']) 1211 header_output += ImmOpDeclare.subst(dsbIop) 1212 decoder_output += ImmOpConstructor.subst(dsbIop) 1213 exec_output += PredOpExecute.subst(dsbIop) 1214 1215 dmbCode = ''' 1216 // If the barrier is due to a CP15 access check for hyp traps 1217 if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr, 1218 Hdcr, Hstr, Hcptr, imm)) { 1219 return std::make_shared<HypervisorTrap>(machInst, imm, 1220 EC_TRAPPED_CP15_MCR_MRC); 1221 } 1222 ''' 1223 dmbIop = InstObjParams("dmb", "Dmb", "ImmOp", 1224 {"code": dmbCode, 1225 "predicate_test": predicateTest}, 1226 ['IsMemBarrier']) 1227 header_output += ImmOpDeclare.subst(dmbIop) 1228 decoder_output += ImmOpConstructor.subst(dmbIop) 1229 exec_output += PredOpExecute.subst(dmbIop) 1230 1231 dbgCode = ''' 1232 ''' 1233 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 1234 {"code": dbgCode, 1235 "predicate_test": predicateTest}) 1236 header_output += BasicDeclare.subst(dbgIop) 1237 decoder_output += BasicConstructor.subst(dbgIop) 1238 exec_output += PredOpExecute.subst(dbgIop) 1239 1240 cpsCode = ''' 1241 uint32_t mode = bits(imm, 4, 0); 1242 uint32_t f = bits(imm, 5); 1243 uint32_t i = bits(imm, 6); 1244 uint32_t a = bits(imm, 7); 1245 bool setMode = bits(imm, 8); 1246 bool enable = bits(imm, 9); 1247 CPSR cpsr = Cpsr; 1248 SCTLR sctlr = Sctlr; 1249 if (cpsr.mode != MODE_USER) { 1250 if (enable) { 1251 if (f) cpsr.f = 0; 1252 if (i) cpsr.i = 0; 1253 if (a) cpsr.a = 0; 1254 } else { 1255 if (f && !sctlr.nmfi) cpsr.f = 1; 1256 if (i) cpsr.i = 1; 1257 if (a) cpsr.a = 1; 1258 } 1259 if (setMode) { 1260 cpsr.mode = mode; 1261 } 1262 } 1263 Cpsr = cpsr; 1264 ''' 1265 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 1266 { "code": cpsCode, 1267 "predicate_test": predicateTest }, 1268 ["IsSerializeAfter","IsNonSpeculative"]) 1269 header_output += ImmOpDeclare.subst(cpsIop) 1270 decoder_output += ImmOpConstructor.subst(cpsIop) 1271 exec_output += PredOpExecute.subst(cpsIop) 1272}}; 1273