misc.isa revision 12542
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*-
27199Sgblack@eecs.umich.edu
312504Snikos.nikoleris@arm.com// Copyright (c) 2010-2013,2017-2018 ARM Limited
47199Sgblack@eecs.umich.edu// All rights reserved
57199Sgblack@eecs.umich.edu//
67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107199Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147199Sgblack@eecs.umich.edu//
157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
247199Sgblack@eecs.umich.edu// this software without specific prior written permission.
257199Sgblack@eecs.umich.edu//
267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
377199Sgblack@eecs.umich.edu//
387199Sgblack@eecs.umich.edu// Authors: Gabe Black
397199Sgblack@eecs.umich.edu
407199Sgblack@eecs.umich.edulet {{
417199Sgblack@eecs.umich.edu
427199Sgblack@eecs.umich.edu    svcCode = '''
4312541Sgiacomo.travaglini@arm.com    ThreadContext *tc = xc->tcBase();
4412541Sgiacomo.travaglini@arm.com
4512541Sgiacomo.travaglini@arm.com    const auto semihost_imm = Thumb? 0xAB : 0x123456;
4612541Sgiacomo.travaglini@arm.com
4712541Sgiacomo.travaglini@arm.com    if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
4812541Sgiacomo.travaglini@arm.com        R0 = ArmSystem::callSemihosting32(tc, R0, R1);
4912541Sgiacomo.travaglini@arm.com    } else {
5012541Sgiacomo.travaglini@arm.com        fault = std::make_shared<SupervisorCall>(machInst, imm);
5112541Sgiacomo.travaglini@arm.com    }
5210037SARM gem5 Developers    '''
5310037SARM gem5 Developers
5410037SARM gem5 Developers    svcIop = InstObjParams("svc", "Svc", "ImmOp",
5510037SARM gem5 Developers                           { "code": svcCode,
5612541Sgiacomo.travaglini@arm.com                             "predicate_test": predicateTest,
5712541Sgiacomo.travaglini@arm.com                             "thumb_semihost": '0xAB',
5812541Sgiacomo.travaglini@arm.com                             "arm_semihost": '0x123456' },
5912541Sgiacomo.travaglini@arm.com                           ["IsSyscall", "IsNonSpeculative",
6012541Sgiacomo.travaglini@arm.com                            "IsSerializeAfter"])
6110037SARM gem5 Developers    header_output = ImmOpDeclare.subst(svcIop)
6212541Sgiacomo.travaglini@arm.com    decoder_output = SemihostConstructor.subst(svcIop)
6310037SARM gem5 Developers    exec_output = PredOpExecute.subst(svcIop)
6410037SARM gem5 Developers
6512542Sgiacomo.travaglini@arm.com    hltCode = '''
6612542Sgiacomo.travaglini@arm.com    ThreadContext *tc = xc->tcBase();
6712542Sgiacomo.travaglini@arm.com
6812542Sgiacomo.travaglini@arm.com    const auto semihost_imm = Thumb? 0x3C : 0xF000;
6912542Sgiacomo.travaglini@arm.com
7012542Sgiacomo.travaglini@arm.com    if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
7112542Sgiacomo.travaglini@arm.com        R0 = ArmSystem::callSemihosting32(tc, R0, R1);
7212542Sgiacomo.travaglini@arm.com    } else {
7312542Sgiacomo.travaglini@arm.com        // HLT instructions aren't implemented, so treat them as undefined
7412542Sgiacomo.travaglini@arm.com        // instructions.
7512542Sgiacomo.travaglini@arm.com        fault = std::make_shared<UndefinedInstruction>(
7612542Sgiacomo.travaglini@arm.com            machInst, false, mnemonic);
7712542Sgiacomo.travaglini@arm.com    }
7812542Sgiacomo.travaglini@arm.com    '''
7912542Sgiacomo.travaglini@arm.com
8012542Sgiacomo.travaglini@arm.com    hltIop = InstObjParams("hlt", "Hlt", "ImmOp",
8112542Sgiacomo.travaglini@arm.com                           { "code": hltCode,
8212542Sgiacomo.travaglini@arm.com                             "predicate_test": predicateTest,
8312542Sgiacomo.travaglini@arm.com                             "thumb_semihost": '0x3C',
8412542Sgiacomo.travaglini@arm.com                             "arm_semihost": '0xF000' },
8512542Sgiacomo.travaglini@arm.com                           ["IsNonSpeculative"])
8612542Sgiacomo.travaglini@arm.com    header_output += ImmOpDeclare.subst(hltIop)
8712542Sgiacomo.travaglini@arm.com    decoder_output += SemihostConstructor.subst(hltIop)
8812542Sgiacomo.travaglini@arm.com    exec_output += PredOpExecute.subst(hltIop)
8912542Sgiacomo.travaglini@arm.com
9010037SARM gem5 Developers    smcCode = '''
9110037SARM gem5 Developers    HCR  hcr  = Hcr;
9210037SARM gem5 Developers    CPSR cpsr = Cpsr;
9310037SARM gem5 Developers    SCR  scr  = Scr;
9410037SARM gem5 Developers
9510037SARM gem5 Developers    if ((cpsr.mode != MODE_USER) && FullSystem) {
9610037SARM gem5 Developers        if (ArmSystem::haveVirtualization(xc->tcBase()) &&
9710037SARM gem5 Developers            !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
9810474Sandreas.hansson@arm.com            fault = std::make_shared<HypervisorTrap>(machInst, 0,
9910474Sandreas.hansson@arm.com                                                     EC_SMC_TO_HYP);
10010037SARM gem5 Developers        } else {
10110037SARM gem5 Developers            if (scr.scd) {
10210037SARM gem5 Developers                fault = disabledFault();
10310037SARM gem5 Developers            } else {
10410474Sandreas.hansson@arm.com                fault = std::make_shared<SecureMonitorCall>(machInst);
10510037SARM gem5 Developers            }
10610037SARM gem5 Developers        }
1078782Sgblack@eecs.umich.edu    } else {
10810037SARM gem5 Developers        fault = disabledFault();
1098782Sgblack@eecs.umich.edu    }
1107199Sgblack@eecs.umich.edu    '''
1117199Sgblack@eecs.umich.edu
11210037SARM gem5 Developers    smcIop = InstObjParams("smc", "Smc", "PredOp",
11310037SARM gem5 Developers                           { "code": smcCode,
1148628SAli.Saidi@ARM.com                             "predicate_test": predicateTest },
11510037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
11610037SARM gem5 Developers    header_output += BasicDeclare.subst(smcIop)
11710037SARM gem5 Developers    decoder_output += BasicConstructor.subst(smcIop)
11810037SARM gem5 Developers    exec_output += PredOpExecute.subst(smcIop)
11910037SARM gem5 Developers
12010037SARM gem5 Developers    hvcCode = '''
12110037SARM gem5 Developers    CPSR cpsr = Cpsr;
12210037SARM gem5 Developers    SCR  scr  = Scr;
12310037SARM gem5 Developers
12410037SARM gem5 Developers    // Filter out the various cases where this instruction isn't defined
12510037SARM gem5 Developers    if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
12610037SARM gem5 Developers        (cpsr.mode == MODE_USER) ||
12710037SARM gem5 Developers        (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
12810037SARM gem5 Developers        fault = disabledFault();
12910037SARM gem5 Developers    } else {
13010474Sandreas.hansson@arm.com        fault = std::make_shared<HypervisorCall>(machInst, imm);
13110037SARM gem5 Developers    }
13210037SARM gem5 Developers    '''
13310037SARM gem5 Developers
13410037SARM gem5 Developers    hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
13510037SARM gem5 Developers                           { "code": hvcCode,
13610037SARM gem5 Developers                             "predicate_test": predicateTest },
13710037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
13810037SARM gem5 Developers    header_output += ImmOpDeclare.subst(hvcIop)
13910037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(hvcIop)
14010037SARM gem5 Developers    exec_output += PredOpExecute.subst(hvcIop)
14110037SARM gem5 Developers
14210037SARM gem5 Developers    eretCode = '''
14310037SARM gem5 Developers        SCTLR sctlr   = Sctlr;
14410037SARM gem5 Developers        CPSR old_cpsr = Cpsr;
14510037SARM gem5 Developers        old_cpsr.nz   = CondCodesNZ;
14610037SARM gem5 Developers        old_cpsr.c    = CondCodesC;
14710037SARM gem5 Developers        old_cpsr.v    = CondCodesV;
14810037SARM gem5 Developers        old_cpsr.ge   = CondCodesGE;
14910037SARM gem5 Developers
15010037SARM gem5 Developers        CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
15110037SARM gem5 Developers                            true, sctlr.nmfi, xc->tcBase());
15210037SARM gem5 Developers        Cpsr        = ~CondCodesMask & new_cpsr;
15310037SARM gem5 Developers        CondCodesNZ = new_cpsr.nz;
15410037SARM gem5 Developers        CondCodesC  = new_cpsr.c;
15510037SARM gem5 Developers        CondCodesV  = new_cpsr.v;
15610037SARM gem5 Developers        CondCodesGE = new_cpsr.ge;
15710037SARM gem5 Developers
15810037SARM gem5 Developers        NextThumb = (new_cpsr).t;
15910037SARM gem5 Developers                    NextJazelle = (new_cpsr).j;
16010037SARM gem5 Developers                    NextItState = (((new_cpsr).it2 << 2) & 0xFC)
16110037SARM gem5 Developers                        | ((new_cpsr).it1 & 0x3);
16210037SARM gem5 Developers
16310037SARM gem5 Developers        NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
16410037SARM gem5 Developers    '''
16510037SARM gem5 Developers
16610037SARM gem5 Developers    eretIop = InstObjParams("eret", "Eret", "PredOp",
16710037SARM gem5 Developers                           { "code": eretCode,
16810037SARM gem5 Developers                             "predicate_test": predicateTest },
16911355Smitch.hayenga@arm.com                           ["IsNonSpeculative", "IsSerializeAfter",
17011355Smitch.hayenga@arm.com                            "IsSquashAfter"])
17110037SARM gem5 Developers    header_output += BasicDeclare.subst(eretIop)
17210037SARM gem5 Developers    decoder_output += BasicConstructor.subst(eretIop)
17310037SARM gem5 Developers    exec_output += PredOpExecute.subst(eretIop)
17410037SARM gem5 Developers
17512258Sgiacomo.travaglini@arm.com    crcCode = '''
17612258Sgiacomo.travaglini@arm.com    constexpr uint8_t size_bytes = %(sz)d;
17712258Sgiacomo.travaglini@arm.com    constexpr uint32_t poly = %(polynom)s;
17810037SARM gem5 Developers
17912258Sgiacomo.travaglini@arm.com    uint32_t data = htole(Op2);
18012258Sgiacomo.travaglini@arm.com    auto data_buffer = reinterpret_cast<uint8_t*>(&data);
18112258Sgiacomo.travaglini@arm.com
18212258Sgiacomo.travaglini@arm.com    Dest = crc32<poly>(
18312258Sgiacomo.travaglini@arm.com        data_buffer,   /* Message Register */
18412258Sgiacomo.travaglini@arm.com        Op1,           /* Initial Value  of the CRC */
18512258Sgiacomo.travaglini@arm.com        size_bytes     /* Size of the original Message */
18612258Sgiacomo.travaglini@arm.com    );
18712258Sgiacomo.travaglini@arm.com    '''
18812258Sgiacomo.travaglini@arm.com
18912258Sgiacomo.travaglini@arm.com    def crc32Emit(mnem, implCode, castagnoli, size):
19012258Sgiacomo.travaglini@arm.com        global header_output, decoder_output, exec_output
19112258Sgiacomo.travaglini@arm.com
19212258Sgiacomo.travaglini@arm.com        if castagnoli:
19312258Sgiacomo.travaglini@arm.com            # crc32c instructions
19412258Sgiacomo.travaglini@arm.com            poly = "0x1EDC6F41"
19512258Sgiacomo.travaglini@arm.com        else:
19612258Sgiacomo.travaglini@arm.com            # crc32 instructions
19712258Sgiacomo.travaglini@arm.com            poly = "0x04C11DB7"
19812258Sgiacomo.travaglini@arm.com
19912258Sgiacomo.travaglini@arm.com        data = {'sz' : size, 'polynom': poly}
20012258Sgiacomo.travaglini@arm.com
20112258Sgiacomo.travaglini@arm.com        instCode = implCode % data
20212258Sgiacomo.travaglini@arm.com
20312258Sgiacomo.travaglini@arm.com        crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
20412258Sgiacomo.travaglini@arm.com                               { "code": instCode,
20512258Sgiacomo.travaglini@arm.com                                 "predicate_test": predicateTest }, [])
20612258Sgiacomo.travaglini@arm.com        header_output += RegRegRegOpDeclare.subst(crcIop)
20712258Sgiacomo.travaglini@arm.com        decoder_output += RegRegRegOpConstructor.subst(crcIop)
20812258Sgiacomo.travaglini@arm.com        exec_output += PredOpExecute.subst(crcIop)
20912258Sgiacomo.travaglini@arm.com
21012258Sgiacomo.travaglini@arm.com    crc32Emit("crc32b", crcCode, False, 1);
21112258Sgiacomo.travaglini@arm.com    crc32Emit("crc32h", crcCode, False, 2);
21212258Sgiacomo.travaglini@arm.com    crc32Emit("crc32w", crcCode, False, 4);
21312258Sgiacomo.travaglini@arm.com    crc32Emit("crc32cb", crcCode, True, 1);
21412258Sgiacomo.travaglini@arm.com    crc32Emit("crc32ch", crcCode, True, 2);
21512258Sgiacomo.travaglini@arm.com    crc32Emit("crc32cw", crcCode, True, 4);
2167199Sgblack@eecs.umich.edu
2177199Sgblack@eecs.umich.edu}};
2187202Sgblack@eecs.umich.edu
2197202Sgblack@eecs.umich.edulet {{
2207202Sgblack@eecs.umich.edu
2217202Sgblack@eecs.umich.edu    header_output = decoder_output = exec_output = ""
2227202Sgblack@eecs.umich.edu
2238301SAli.Saidi@ARM.com    mrsCpsrCode = '''
2248303SAli.Saidi@ARM.com        CPSR cpsr = Cpsr;
2258303SAli.Saidi@ARM.com        cpsr.nz = CondCodesNZ;
2268303SAli.Saidi@ARM.com        cpsr.c = CondCodesC;
2278303SAli.Saidi@ARM.com        cpsr.v = CondCodesV;
2288303SAli.Saidi@ARM.com        cpsr.ge = CondCodesGE;
2298303SAli.Saidi@ARM.com        Dest = cpsr & 0xF8FF03DF
2308301SAli.Saidi@ARM.com    '''
2318301SAli.Saidi@ARM.com
2327202Sgblack@eecs.umich.edu    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
2337202Sgblack@eecs.umich.edu                               { "code": mrsCpsrCode,
2347599Sminkyu.jeong@arm.com                                 "predicate_test": condPredicateTest },
2357783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
2367202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsCpsrIop)
2377202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsCpsrIop)
2387202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsCpsrIop)
2397202Sgblack@eecs.umich.edu
2407202Sgblack@eecs.umich.edu    mrsSpsrCode = "Dest = Spsr"
2417202Sgblack@eecs.umich.edu    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
2427202Sgblack@eecs.umich.edu                               { "code": mrsSpsrCode,
2437599Sminkyu.jeong@arm.com                                 "predicate_test": predicateTest },
2447783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
2457202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsSpsrIop)
2467202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsSpsrIop)
2477202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsSpsrIop)
2487202Sgblack@eecs.umich.edu
24910037SARM gem5 Developers    mrsBankedRegCode = '''
25010037SARM gem5 Developers        bool isIntReg;
25110037SARM gem5 Developers        int  regIdx;
25210037SARM gem5 Developers
25310037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
25410037SARM gem5 Developers            if (isIntReg) {
25510037SARM gem5 Developers                Dest = DecodedBankedIntReg;
25610037SARM gem5 Developers            } else {
25710037SARM gem5 Developers                Dest = xc->readMiscReg(regIdx);
25810037SARM gem5 Developers            }
25910037SARM gem5 Developers        } else {
26010474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
26110474Sandreas.hansson@arm.com                                                          mnemonic);
26210037SARM gem5 Developers        }
26310037SARM gem5 Developers    '''
26410037SARM gem5 Developers    mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
26510037SARM gem5 Developers                                    { "code": mrsBankedRegCode,
26610037SARM gem5 Developers                                      "predicate_test": predicateTest },
26710037SARM gem5 Developers                                    ["IsSerializeBefore"])
26810037SARM gem5 Developers    header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
26910037SARM gem5 Developers    decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
27010037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrsBankedRegIop)
27110037SARM gem5 Developers
27210037SARM gem5 Developers    msrBankedRegCode = '''
27310037SARM gem5 Developers        bool isIntReg;
27410037SARM gem5 Developers        int  regIdx;
27510037SARM gem5 Developers
27610037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
27710037SARM gem5 Developers            if (isIntReg) {
27810037SARM gem5 Developers                // This is a bit nasty, you would have thought that
27910037SARM gem5 Developers                // DecodedBankedIntReg wouldn't be written to unless the
28010037SARM gem5 Developers                // conditions on the IF statements above are met, however if
28110037SARM gem5 Developers                // you look at the generated C code you'll find that they are.
28210037SARM gem5 Developers                // However this is safe as DecodedBankedIntReg (which is used
28310037SARM gem5 Developers                // in operands.isa to get the index of DecodedBankedIntReg)
28410037SARM gem5 Developers                // will return INTREG_DUMMY if its not a valid integer
28510037SARM gem5 Developers                // register, so redirecting the write to somewhere we don't
28610037SARM gem5 Developers                // care about.
28710037SARM gem5 Developers                DecodedBankedIntReg = Op1;
28810037SARM gem5 Developers            } else {
28910037SARM gem5 Developers                xc->setMiscReg(regIdx, Op1);
29010037SARM gem5 Developers            }
29110037SARM gem5 Developers        } else {
29210474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
29310474Sandreas.hansson@arm.com                                                          mnemonic);
29410037SARM gem5 Developers        }
29510037SARM gem5 Developers    '''
29610037SARM gem5 Developers    msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
29710037SARM gem5 Developers                                    { "code": msrBankedRegCode,
29810037SARM gem5 Developers                                      "predicate_test": predicateTest },
29910501Sakash.bagdia@ARM.com                                    ["IsSerializeAfter", "IsNonSpeculative"])
30010037SARM gem5 Developers    header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
30110037SARM gem5 Developers    decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
30210037SARM gem5 Developers    exec_output += PredOpExecute.subst(msrBankedRegIop)
30310037SARM gem5 Developers
3047202Sgblack@eecs.umich.edu    msrCpsrRegCode = '''
3057400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
3068303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
3078303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
3088303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
3098303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
3108303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
3118303SAli.Saidi@ARM.com
3128303SAli.Saidi@ARM.com        CPSR new_cpsr =
31310037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
31410037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
3158303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
3168303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
3178303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
3188303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
3198303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
3207202Sgblack@eecs.umich.edu    '''
3217202Sgblack@eecs.umich.edu    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
3227202Sgblack@eecs.umich.edu                                  { "code": msrCpsrRegCode,
3237599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
3247599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3257202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
3267202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
3277202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrRegIop)
3287202Sgblack@eecs.umich.edu
3297202Sgblack@eecs.umich.edu    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
3307202Sgblack@eecs.umich.edu    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
3317202Sgblack@eecs.umich.edu                                  { "code": msrSpsrRegCode,
3327599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
3337599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3347202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
3357202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
3367202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrRegIop)
3377202Sgblack@eecs.umich.edu
3387202Sgblack@eecs.umich.edu    msrCpsrImmCode = '''
3397400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
3408303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
3418303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
3428303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
3438303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
3448303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
3458303SAli.Saidi@ARM.com        CPSR new_cpsr =
34610037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
34710037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
3488303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
3498303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
3508303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
3518303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
3528303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
3537202Sgblack@eecs.umich.edu    '''
3547202Sgblack@eecs.umich.edu    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
3557202Sgblack@eecs.umich.edu                                  { "code": msrCpsrImmCode,
3567599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
3577599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3587202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
3597202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
3607202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrImmIop)
3617202Sgblack@eecs.umich.edu
3627202Sgblack@eecs.umich.edu    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
3637202Sgblack@eecs.umich.edu    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
3647202Sgblack@eecs.umich.edu                                  { "code": msrSpsrImmCode,
3657599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
3667599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3677202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
3687202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
3697202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrImmIop)
3707209Sgblack@eecs.umich.edu
3717209Sgblack@eecs.umich.edu    revCode = '''
3727209Sgblack@eecs.umich.edu    uint32_t val = Op1;
3737209Sgblack@eecs.umich.edu    Dest = swap_byte(val);
3747209Sgblack@eecs.umich.edu    '''
3757261Sgblack@eecs.umich.edu    revIop = InstObjParams("rev", "Rev", "RegRegOp",
3767209Sgblack@eecs.umich.edu                           { "code": revCode,
3777209Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
3787261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revIop)
3797261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revIop)
3807209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revIop)
3817209Sgblack@eecs.umich.edu
3827209Sgblack@eecs.umich.edu    rev16Code = '''
3837209Sgblack@eecs.umich.edu    uint32_t val = Op1;
3847209Sgblack@eecs.umich.edu    Dest = (bits(val, 15, 8) << 0) |
3857209Sgblack@eecs.umich.edu           (bits(val, 7, 0) << 8) |
3867209Sgblack@eecs.umich.edu           (bits(val, 31, 24) << 16) |
3877209Sgblack@eecs.umich.edu           (bits(val, 23, 16) << 24);
3887209Sgblack@eecs.umich.edu    '''
3897261Sgblack@eecs.umich.edu    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
3907209Sgblack@eecs.umich.edu                             { "code": rev16Code,
3917209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
3927261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rev16Iop)
3937261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rev16Iop)
3947209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rev16Iop)
3957209Sgblack@eecs.umich.edu
3967209Sgblack@eecs.umich.edu    revshCode = '''
3977209Sgblack@eecs.umich.edu    uint16_t val = Op1;
3987209Sgblack@eecs.umich.edu    Dest = sext<16>(swap_byte(val));
3997209Sgblack@eecs.umich.edu    '''
4007261Sgblack@eecs.umich.edu    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
4017209Sgblack@eecs.umich.edu                             { "code": revshCode,
4027209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
4037261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revshIop)
4047261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revshIop)
4057209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revshIop)
4067226Sgblack@eecs.umich.edu
4077249Sgblack@eecs.umich.edu    rbitCode = '''
40812227Sgiacomo.travaglini@arm.com    Dest = reverseBits(Op1);
4097249Sgblack@eecs.umich.edu    '''
4107261Sgblack@eecs.umich.edu    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
4117249Sgblack@eecs.umich.edu                            { "code": rbitCode,
4127249Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
4137261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rbitIop)
4147261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rbitIop)
4157249Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rbitIop)
4167249Sgblack@eecs.umich.edu
4177251Sgblack@eecs.umich.edu    clzCode = '''
4187251Sgblack@eecs.umich.edu        Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
4197251Sgblack@eecs.umich.edu    '''
4207261Sgblack@eecs.umich.edu    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
4217251Sgblack@eecs.umich.edu                           { "code": clzCode,
4227251Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
4237261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(clzIop)
4247261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(clzIop)
4257251Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(clzIop)
4267251Sgblack@eecs.umich.edu
4277226Sgblack@eecs.umich.edu    ssatCode = '''
4287226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
4297226Sgblack@eecs.umich.edu        int32_t res;
4307232Sgblack@eecs.umich.edu        if (satInt(res, operand, imm))
4318302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4327226Sgblack@eecs.umich.edu        Dest = res;
4337226Sgblack@eecs.umich.edu    '''
4347232Sgblack@eecs.umich.edu    ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
4357226Sgblack@eecs.umich.edu                            { "code": ssatCode,
4368304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(ssatCode) }, [])
4377232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
4387232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
4397226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssatIop)
4407226Sgblack@eecs.umich.edu
4417226Sgblack@eecs.umich.edu    usatCode = '''
4427226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
4437226Sgblack@eecs.umich.edu        int32_t res;
4447232Sgblack@eecs.umich.edu        if (uSatInt(res, operand, imm))
4458302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4467226Sgblack@eecs.umich.edu        Dest = res;
4477226Sgblack@eecs.umich.edu    '''
4487232Sgblack@eecs.umich.edu    usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
4497226Sgblack@eecs.umich.edu                            { "code": usatCode,
4508304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(usatCode) }, [])
4517232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(usatIop)
4527232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
4537226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usatIop)
4547226Sgblack@eecs.umich.edu
4557226Sgblack@eecs.umich.edu    ssat16Code = '''
4567226Sgblack@eecs.umich.edu        int32_t res;
4577226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
4587226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
4597226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
4607232Sgblack@eecs.umich.edu        if (satInt(res, argLow, imm))
4618302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4627226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
4637232Sgblack@eecs.umich.edu        if (satInt(res, argHigh, imm))
4648302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4657226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4667226Sgblack@eecs.umich.edu        Dest = resTemp;
4677226Sgblack@eecs.umich.edu    '''
4687232Sgblack@eecs.umich.edu    ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
4697226Sgblack@eecs.umich.edu                              { "code": ssat16Code,
4708304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(ssat16Code) }, [])
4717232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(ssat16Iop)
4727232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
4737226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssat16Iop)
4747226Sgblack@eecs.umich.edu
4757226Sgblack@eecs.umich.edu    usat16Code = '''
4767226Sgblack@eecs.umich.edu        int32_t res;
4777226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
4787226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
4797226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
4807232Sgblack@eecs.umich.edu        if (uSatInt(res, argLow, imm))
4818302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4827226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
4837232Sgblack@eecs.umich.edu        if (uSatInt(res, argHigh, imm))
4848302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4857226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4867226Sgblack@eecs.umich.edu        Dest = resTemp;
4877226Sgblack@eecs.umich.edu    '''
4887232Sgblack@eecs.umich.edu    usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
4897226Sgblack@eecs.umich.edu                              { "code": usat16Code,
4908304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(usat16Code) }, [])
4917232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(usat16Iop)
4927232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
4937226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usat16Iop)
4947234Sgblack@eecs.umich.edu
4957234Sgblack@eecs.umich.edu    sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
4967234Sgblack@eecs.umich.edu                            { "code":
4978588Sgblack@eecs.umich.edu                              "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
4987234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
4997234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtbIop)
5007234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
5017234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtbIop)
5027234Sgblack@eecs.umich.edu
5037234Sgblack@eecs.umich.edu    sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
5047234Sgblack@eecs.umich.edu                             { "code":
5057234Sgblack@eecs.umich.edu                               '''
5068588Sgblack@eecs.umich.edu                                   Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
5077234Sgblack@eecs.umich.edu                                          Op1;
5087234Sgblack@eecs.umich.edu                               ''',
5097234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5107234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
5117234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
5127234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtabIop)
5137234Sgblack@eecs.umich.edu
5147234Sgblack@eecs.umich.edu    sxtb16Code = '''
5157234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5167234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
5177234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5187234Sgblack@eecs.umich.edu                sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
5197234Sgblack@eecs.umich.edu    Dest = resTemp;
5207234Sgblack@eecs.umich.edu    '''
5217234Sgblack@eecs.umich.edu    sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
5227234Sgblack@eecs.umich.edu                              { "code": sxtb16Code,
5237234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5247234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
5257234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
5267234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtb16Iop)
5277234Sgblack@eecs.umich.edu
5287234Sgblack@eecs.umich.edu    sxtab16Code = '''
5297234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5307234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
5317234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
5327234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5337234Sgblack@eecs.umich.edu                sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
5347234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
5357234Sgblack@eecs.umich.edu    Dest = resTemp;
5367234Sgblack@eecs.umich.edu    '''
5377234Sgblack@eecs.umich.edu    sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
5387234Sgblack@eecs.umich.edu                               { "code": sxtab16Code,
5397234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
5407234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
5417234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
5427234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtab16Iop)
5437234Sgblack@eecs.umich.edu
5447234Sgblack@eecs.umich.edu    sxthCode = '''
5457234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
5467234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5477234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated);
5487234Sgblack@eecs.umich.edu    '''
5497234Sgblack@eecs.umich.edu    sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
5507234Sgblack@eecs.umich.edu                              { "code": sxthCode,
5517234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5527234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxthIop)
5537234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxthIop)
5547234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxthIop)
5557234Sgblack@eecs.umich.edu
5567234Sgblack@eecs.umich.edu    sxtahCode = '''
5577234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
5587234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5597234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated) + Op1;
5607234Sgblack@eecs.umich.edu    '''
5617234Sgblack@eecs.umich.edu    sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
5627234Sgblack@eecs.umich.edu                             { "code": sxtahCode,
5637234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5647234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
5657234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
5667234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtahIop)
5677234Sgblack@eecs.umich.edu
5687234Sgblack@eecs.umich.edu    uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
5698588Sgblack@eecs.umich.edu                            { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
5707234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
5717234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtbIop)
5727234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
5737234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtbIop)
5747234Sgblack@eecs.umich.edu
5757234Sgblack@eecs.umich.edu    uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
5767234Sgblack@eecs.umich.edu                             { "code":
5778588Sgblack@eecs.umich.edu                               "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
5787234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5797234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
5807234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
5817234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtabIop)
5827234Sgblack@eecs.umich.edu
5837234Sgblack@eecs.umich.edu    uxtb16Code = '''
5847234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5857234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
5867234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5877234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
5887234Sgblack@eecs.umich.edu    Dest = resTemp;
5897234Sgblack@eecs.umich.edu    '''
5907234Sgblack@eecs.umich.edu    uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
5917234Sgblack@eecs.umich.edu                              { "code": uxtb16Code,
5927234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5937234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
5947234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
5957234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtb16Iop)
5967234Sgblack@eecs.umich.edu
5977234Sgblack@eecs.umich.edu    uxtab16Code = '''
5987234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5997234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
6007234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
6017234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
6027234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
6037234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
6047234Sgblack@eecs.umich.edu    Dest = resTemp;
6057234Sgblack@eecs.umich.edu    '''
6067234Sgblack@eecs.umich.edu    uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
6077234Sgblack@eecs.umich.edu                               { "code": uxtab16Code,
6087234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
6097234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
6107234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
6117234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtab16Iop)
6127234Sgblack@eecs.umich.edu
6137234Sgblack@eecs.umich.edu    uxthCode = '''
6147234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
6157234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
6167234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated;
6177234Sgblack@eecs.umich.edu    '''
6187234Sgblack@eecs.umich.edu    uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
6197234Sgblack@eecs.umich.edu                              { "code": uxthCode,
6207234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
6217234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxthIop)
6227234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxthIop)
6237234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxthIop)
6247234Sgblack@eecs.umich.edu
6257234Sgblack@eecs.umich.edu    uxtahCode = '''
6267234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
6277234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
6287234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated + Op1;
6297234Sgblack@eecs.umich.edu    '''
6307234Sgblack@eecs.umich.edu    uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
6317234Sgblack@eecs.umich.edu                             { "code": uxtahCode,
6327234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
6337234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
6347234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
6357234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtahIop)
6367239Sgblack@eecs.umich.edu
6377239Sgblack@eecs.umich.edu    selCode = '''
6387239Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6397239Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6407239Sgblack@eecs.umich.edu            int low = i * 8;
6417239Sgblack@eecs.umich.edu            int high = low + 7;
6427239Sgblack@eecs.umich.edu            replaceBits(resTemp, high, low,
6438303SAli.Saidi@ARM.com                        bits(CondCodesGE, i) ?
6447239Sgblack@eecs.umich.edu                            bits(Op1, high, low) : bits(Op2, high, low));
6457239Sgblack@eecs.umich.edu        }
6467239Sgblack@eecs.umich.edu        Dest = resTemp;
6477239Sgblack@eecs.umich.edu    '''
6487239Sgblack@eecs.umich.edu    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
6497239Sgblack@eecs.umich.edu                           { "code": selCode,
6508303SAli.Saidi@ARM.com                             "predicate_test": predicateTest }, [])
6517239Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(selIop)
6527239Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(selIop)
6537239Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(selIop)
6547242Sgblack@eecs.umich.edu
6557242Sgblack@eecs.umich.edu    usad8Code = '''
6567242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6577242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6587242Sgblack@eecs.umich.edu            int low = i * 8;
6597242Sgblack@eecs.umich.edu            int high = low + 7;
6607242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
6617242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
6627242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
6637242Sgblack@eecs.umich.edu        }
6647242Sgblack@eecs.umich.edu        Dest = resTemp;
6657242Sgblack@eecs.umich.edu    '''
6667242Sgblack@eecs.umich.edu    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
6677242Sgblack@eecs.umich.edu                             { "code": usad8Code,
6687242Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
6697242Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(usad8Iop)
6707242Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
6717242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usad8Iop)
6727242Sgblack@eecs.umich.edu
6737242Sgblack@eecs.umich.edu    usada8Code = '''
6747242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6757242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6767242Sgblack@eecs.umich.edu            int low = i * 8;
6777242Sgblack@eecs.umich.edu            int high = low + 7;
6787242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
6797242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
6807242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
6817242Sgblack@eecs.umich.edu        }
6827242Sgblack@eecs.umich.edu        Dest = Op3 + resTemp;
6837242Sgblack@eecs.umich.edu    '''
6847242Sgblack@eecs.umich.edu    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
6857242Sgblack@eecs.umich.edu                              { "code": usada8Code,
6867242Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
6877242Sgblack@eecs.umich.edu    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
6887242Sgblack@eecs.umich.edu    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
6897242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usada8Iop)
6907247Sgblack@eecs.umich.edu
69110474Sandreas.hansson@arm.com    bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n'
6927848SAli.Saidi@ARM.com    bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
6937410Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(bkptIop)
6947410Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(bkptIop)
6957410Sgblack@eecs.umich.edu    exec_output += BasicExecute.subst(bkptIop)
6967410Sgblack@eecs.umich.edu
69710037SARM gem5 Developers    nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
6987247Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(nopIop)
69910037SARM gem5 Developers    decoder_output += BasicConstructor64.subst(nopIop)
70010037SARM gem5 Developers    exec_output += BasicExecute.subst(nopIop)
7017408Sgblack@eecs.umich.edu
7027418Sgblack@eecs.umich.edu    yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
7037418Sgblack@eecs.umich.edu            { "code" : "", "predicate_test" : predicateTest })
7047418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(yieldIop)
7057418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(yieldIop)
7067418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(yieldIop)
7077418Sgblack@eecs.umich.edu
7087418Sgblack@eecs.umich.edu    wfeCode = '''
70910037SARM gem5 Developers    CPSR cpsr = Cpsr;
71010037SARM gem5 Developers    SCR  scr  = Scr64;
71110037SARM gem5 Developers
71210037SARM gem5 Developers    // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
71310037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
7148285SPrakash.Ramrakhyani@arm.com    if (SevMailbox == 1) {
7157418Sgblack@eecs.umich.edu        SevMailbox = 0;
71610037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
71711150Smitch.hayenga@arm.com    } else if (tc->getCpuPtr()->getInterruptController(
71811150Smitch.hayenga@arm.com                tc->threadId())->checkInterrupts(tc)) {
71910037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
7208285SPrakash.Ramrakhyani@arm.com    } else {
72112403Sgiacomo.travaglini@arm.com        fault = trapWFx(tc, cpsr, scr, true);
72212403Sgiacomo.travaglini@arm.com        if (fault == NoFault) {
72312403Sgiacomo.travaglini@arm.com            PseudoInst::quiesce(tc);
72412403Sgiacomo.travaglini@arm.com        } else {
72512403Sgiacomo.travaglini@arm.com            PseudoInst::quiesceSkip(tc);
72612403Sgiacomo.travaglini@arm.com        }
7278142SAli.Saidi@ARM.com    }
7287418Sgblack@eecs.umich.edu    '''
7298518Sgeoffrey.blake@arm.com    wfePredFixUpCode = '''
7308518Sgeoffrey.blake@arm.com    // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
7318518Sgeoffrey.blake@arm.com    // and SEV interrupts
7328518Sgeoffrey.blake@arm.com    SevMailbox = 1;
7338518Sgeoffrey.blake@arm.com    '''
7347418Sgblack@eecs.umich.edu    wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
7358518Sgeoffrey.blake@arm.com            { "code" : wfeCode,
7368518Sgeoffrey.blake@arm.com              "pred_fixup" : wfePredFixUpCode,
7378518Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest },
7388733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
7398733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
7407418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfeIop)
7417418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfeIop)
7428518Sgeoffrey.blake@arm.com    exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
7437418Sgblack@eecs.umich.edu
7447418Sgblack@eecs.umich.edu    wfiCode = '''
74510037SARM gem5 Developers    HCR  hcr  = Hcr;
74610037SARM gem5 Developers    CPSR cpsr = Cpsr;
74710037SARM gem5 Developers    SCR  scr  = Scr64;
74810037SARM gem5 Developers
7498285SPrakash.Ramrakhyani@arm.com    // WFI doesn't sleep if interrupts are pending (masked or not)
75010037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
75111150Smitch.hayenga@arm.com    if (tc->getCpuPtr()->getInterruptController(
75211150Smitch.hayenga@arm.com                tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
75310037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
7548285SPrakash.Ramrakhyani@arm.com    } else {
75512403Sgiacomo.travaglini@arm.com        fault = trapWFx(tc, cpsr, scr, false);
75612403Sgiacomo.travaglini@arm.com        if (fault == NoFault) {
75712403Sgiacomo.travaglini@arm.com            PseudoInst::quiesce(tc);
75812403Sgiacomo.travaglini@arm.com        } else {
75912403Sgiacomo.travaglini@arm.com            PseudoInst::quiesceSkip(tc);
76012403Sgiacomo.travaglini@arm.com        }
7618285SPrakash.Ramrakhyani@arm.com    }
76211150Smitch.hayenga@arm.com    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
7637418Sgblack@eecs.umich.edu    '''
7647418Sgblack@eecs.umich.edu    wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
7657418Sgblack@eecs.umich.edu            { "code" : wfiCode, "predicate_test" : predicateTest },
7668733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
7678733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
7687418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfiIop)
7697418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfiIop)
7708142SAli.Saidi@ARM.com    exec_output += QuiescePredOpExecute.subst(wfiIop)
7717418Sgblack@eecs.umich.edu
7727418Sgblack@eecs.umich.edu    sevCode = '''
7738142SAli.Saidi@ARM.com    SevMailbox = 1;
7747418Sgblack@eecs.umich.edu    System *sys = xc->tcBase()->getSystemPtr();
7757418Sgblack@eecs.umich.edu    for (int x = 0; x < sys->numContexts(); x++) {
7767418Sgblack@eecs.umich.edu        ThreadContext *oc = sys->getThreadContext(x);
7778285SPrakash.Ramrakhyani@arm.com        if (oc == xc->tcBase())
7788285SPrakash.Ramrakhyani@arm.com            continue;
7798518Sgeoffrey.blake@arm.com        // Wake CPU with interrupt if they were sleeping
7808285SPrakash.Ramrakhyani@arm.com        if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
7818518Sgeoffrey.blake@arm.com            // Post Interrupt and wake cpu if needed
78211150Smitch.hayenga@arm.com            oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
7838142SAli.Saidi@ARM.com        }
7847418Sgblack@eecs.umich.edu    }
7857418Sgblack@eecs.umich.edu    '''
7867418Sgblack@eecs.umich.edu    sevIop = InstObjParams("sev", "SevInst", "PredOp", \
7877418Sgblack@eecs.umich.edu            { "code" : sevCode, "predicate_test" : predicateTest },
7888733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
7897418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(sevIop)
7907418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(sevIop)
7917418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sevIop)
7927418Sgblack@eecs.umich.edu
79310037SARM gem5 Developers    sevlCode = '''
79410037SARM gem5 Developers    SevMailbox = 1;
79510037SARM gem5 Developers    '''
79610037SARM gem5 Developers    sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
79710037SARM gem5 Developers            { "code" : sevlCode, "predicate_test" : predicateTest },
79810037SARM gem5 Developers            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
79910037SARM gem5 Developers    header_output += BasicDeclare.subst(sevlIop)
80010037SARM gem5 Developers    decoder_output += BasicConstructor.subst(sevlIop)
80110037SARM gem5 Developers    exec_output += BasicExecute.subst(sevlIop)
80210037SARM gem5 Developers
8037408Sgblack@eecs.umich.edu    itIop = InstObjParams("it", "ItInst", "PredOp", \
8048205SAli.Saidi@ARM.com            { "code" : ";",
8058908Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest }, [])
8067408Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(itIop)
8077408Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(itIop)
8087408Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(itIop)
8097409Sgblack@eecs.umich.edu    unknownCode = '''
81010474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, true);
8117409Sgblack@eecs.umich.edu    '''
8127409Sgblack@eecs.umich.edu    unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
8137409Sgblack@eecs.umich.edu                               { "code": unknownCode,
8147409Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest })
8157409Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(unknownIop)
8167409Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(unknownIop)
8177409Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(unknownIop)
8187254Sgblack@eecs.umich.edu
8197254Sgblack@eecs.umich.edu    ubfxCode = '''
8207254Sgblack@eecs.umich.edu        Dest = bits(Op1, imm2, imm1);
8217254Sgblack@eecs.umich.edu    '''
8227254Sgblack@eecs.umich.edu    ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
8237254Sgblack@eecs.umich.edu                            { "code": ubfxCode,
8247254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
8257254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
8267254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
8277254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ubfxIop)
8287254Sgblack@eecs.umich.edu
8297254Sgblack@eecs.umich.edu    sbfxCode = '''
8307254Sgblack@eecs.umich.edu        int32_t resTemp = bits(Op1, imm2, imm1);
8317254Sgblack@eecs.umich.edu        Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
8327254Sgblack@eecs.umich.edu    '''
8337254Sgblack@eecs.umich.edu    sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
8347254Sgblack@eecs.umich.edu                            { "code": sbfxCode,
8357254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
8367254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
8377254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
8387254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sbfxIop)
8397257Sgblack@eecs.umich.edu
8407257Sgblack@eecs.umich.edu    bfcCode = '''
8417257Sgblack@eecs.umich.edu        Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
8427257Sgblack@eecs.umich.edu    '''
8437257Sgblack@eecs.umich.edu    bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
8447257Sgblack@eecs.umich.edu                           { "code": bfcCode,
8457257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8467257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfcIop)
8477257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
8487257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfcIop)
8497257Sgblack@eecs.umich.edu
8507257Sgblack@eecs.umich.edu    bfiCode = '''
8517257Sgblack@eecs.umich.edu        uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
8527257Sgblack@eecs.umich.edu        Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
8537257Sgblack@eecs.umich.edu    '''
8547257Sgblack@eecs.umich.edu    bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
8557257Sgblack@eecs.umich.edu                           { "code": bfiCode,
8567257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8577257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfiIop)
8587257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
8597257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfiIop)
8607262Sgblack@eecs.umich.edu
8618868SMatt.Horsnell@arm.com    mrc14code = '''
86212106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
86312106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, op1)).index();
86411939Snikos.nikoleris@arm.com    bool can_read, undefined;
86511939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
86611939Snikos.nikoleris@arm.com    if (!can_read || undefined) {
86710474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
86810474Sandreas.hansson@arm.com                                                      mnemonic);
86910037SARM gem5 Developers    }
87010037SARM gem5 Developers    if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
87110037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
87210474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
87310474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8748868SMatt.Horsnell@arm.com    }
8758868SMatt.Horsnell@arm.com    Dest = MiscOp1;
8768868SMatt.Horsnell@arm.com    '''
8778868SMatt.Horsnell@arm.com
87810037SARM gem5 Developers    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
8798868SMatt.Horsnell@arm.com                             { "code": mrc14code,
8808868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest }, [])
88110037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mrc14Iop)
88210037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
8838868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mrc14Iop)
8848868SMatt.Horsnell@arm.com
8858868SMatt.Horsnell@arm.com
8868868SMatt.Horsnell@arm.com    mcr14code = '''
88712106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
88812106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, dest)).index();
88911939Snikos.nikoleris@arm.com    bool can_write, undefined;
89011939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
89111939Snikos.nikoleris@arm.com    if (undefined || !can_write) {
89210474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
89310474Sandreas.hansson@arm.com                                                      mnemonic);
89410037SARM gem5 Developers    }
89510037SARM gem5 Developers    if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
89610037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
89710474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
89810474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8998868SMatt.Horsnell@arm.com    }
9008868SMatt.Horsnell@arm.com    MiscDest = Op1;
9018868SMatt.Horsnell@arm.com    '''
90210037SARM gem5 Developers    mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
9038868SMatt.Horsnell@arm.com                             { "code": mcr14code,
9048868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest },
9058868SMatt.Horsnell@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
90610037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mcr14Iop)
90710037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
9088868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mcr14Iop)
9098868SMatt.Horsnell@arm.com
91010037SARM gem5 Developers    mrc15code = '''
91112499Sgiacomo.travaglini@arm.com    int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
91210037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
91312106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
91412106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
91510037SARM gem5 Developers    bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
91610037SARM gem5 Developers                                     Hcptr, imm);
91711939Snikos.nikoleris@arm.com    bool can_read, undefined;
91811939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
91910037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
92010037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
92110037SARM gem5 Developers    // IS accessable.
92211939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
92311939Snikos.nikoleris@arm.com                                    !inSecureState(Scr, Cpsr)))) {
92410474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
92510474Sandreas.hansson@arm.com                                                      mnemonic);
9268782Sgblack@eecs.umich.edu    }
92710037SARM gem5 Developers    if (hypTrap) {
92810474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
92910474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
93010037SARM gem5 Developers    }
93110037SARM gem5 Developers    Dest = MiscNsBankedOp1;
9327347SAli.Saidi@ARM.com    '''
9337347SAli.Saidi@ARM.com
93410418Sandreas.hansson@arm.com    mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp",
9357347SAli.Saidi@ARM.com                             { "code": mrc15code,
9367262Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
93710418Sandreas.hansson@arm.com    header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
93810418Sandreas.hansson@arm.com    decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
9397262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrc15Iop)
9407262Sgblack@eecs.umich.edu
9417347SAli.Saidi@ARM.com
9427347SAli.Saidi@ARM.com    mcr15code = '''
94312499Sgiacomo.travaglini@arm.com    int preFlatDest = snsBankedIndex(dest, xc->tcBase());
94410037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
94512106SRekai.GonzalezAlberquilla@arm.com                       xc->tcBase()->flattenRegId(RegId(MiscRegClass,
94612106SRekai.GonzalezAlberquilla@arm.com                                                  preFlatDest)).index();
94710037SARM gem5 Developers    bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
94810037SARM gem5 Developers                                      Hcptr, imm);
94911939Snikos.nikoleris@arm.com    bool can_write, undefined;
95011939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
95110037SARM gem5 Developers
95210037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
95310037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
95410037SARM gem5 Developers    // IS accessable.
95511939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
95611939Snikos.nikoleris@arm.com                                      !inSecureState(Scr, Cpsr)))) {
95710474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
95810474Sandreas.hansson@arm.com                                                      mnemonic);
9598782Sgblack@eecs.umich.edu    }
96010037SARM gem5 Developers    if (hypTrap) {
96110474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
96210474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
96310037SARM gem5 Developers    }
96410037SARM gem5 Developers    MiscNsBankedDest = Op1;
9657347SAli.Saidi@ARM.com    '''
96610418Sandreas.hansson@arm.com    mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
9677347SAli.Saidi@ARM.com                             { "code": mcr15code,
9687599Sminkyu.jeong@arm.com                               "predicate_test": predicateTest },
9697599Sminkyu.jeong@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
97010418Sandreas.hansson@arm.com    header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
97110418Sandreas.hansson@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
9727262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mcr15Iop)
9737283Sgblack@eecs.umich.edu
9747420Sgblack@eecs.umich.edu
97510037SARM gem5 Developers    mrrc15code = '''
97612499Sgiacomo.travaglini@arm.com    int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
97710037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
97812106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
97912106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
98010037SARM gem5 Developers    bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
98111939Snikos.nikoleris@arm.com    bool can_read, undefined;
98211939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
98310037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
98410037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
98510037SARM gem5 Developers    // IS accessable.
98611939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
98711939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
98810474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
98910474Sandreas.hansson@arm.com                                                      mnemonic);
99010037SARM gem5 Developers    }
99110037SARM gem5 Developers    if (hypTrap) {
99210474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
99310474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
99410037SARM gem5 Developers    }
99510037SARM gem5 Developers    Dest = bits(MiscNsBankedOp164, 63, 32);
99610037SARM gem5 Developers    Dest2 = bits(MiscNsBankedOp164, 31, 0);
99710037SARM gem5 Developers    '''
99810037SARM gem5 Developers    mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
99910037SARM gem5 Developers                              { "code": mrrc15code,
100010037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
100110037SARM gem5 Developers    header_output += MrrcOpDeclare.subst(mrrc15Iop)
100210037SARM gem5 Developers    decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
100310037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrrc15Iop)
100410037SARM gem5 Developers
100510037SARM gem5 Developers
100610037SARM gem5 Developers    mcrr15code = '''
100712499Sgiacomo.travaglini@arm.com    int preFlatDest = snsBankedIndex(dest, xc->tcBase());
100810037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
100912106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
101012106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatDest)).index();
101110037SARM gem5 Developers    bool hypTrap  = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
101211939Snikos.nikoleris@arm.com    bool can_write, undefined;
101311939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
101410037SARM gem5 Developers
101510037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
101610037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
101710037SARM gem5 Developers    // IS accessable.
101811939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
101911939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
102010474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
102110474Sandreas.hansson@arm.com                                                      mnemonic);
102210037SARM gem5 Developers    }
102310037SARM gem5 Developers    if (hypTrap) {
102410474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
102510474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
102610037SARM gem5 Developers    }
102710037SARM gem5 Developers    MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
102810037SARM gem5 Developers    '''
102910037SARM gem5 Developers    mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
103010037SARM gem5 Developers                              { "code": mcrr15code,
103110037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
103210037SARM gem5 Developers    header_output += McrrOpDeclare.subst(mcrr15Iop)
103310037SARM gem5 Developers    decoder_output += McrrOpConstructor.subst(mcrr15Iop)
103410037SARM gem5 Developers    exec_output += PredOpExecute.subst(mcrr15Iop)
103510037SARM gem5 Developers
10367420Sgblack@eecs.umich.edu
10377283Sgblack@eecs.umich.edu    enterxCode = '''
10387797Sgblack@eecs.umich.edu        NextThumb = true;
10397797Sgblack@eecs.umich.edu        NextJazelle = true;
10407283Sgblack@eecs.umich.edu    '''
10417283Sgblack@eecs.umich.edu    enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
10427283Sgblack@eecs.umich.edu                              { "code": enterxCode,
10437283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
10447283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(enterxIop)
10457283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(enterxIop)
10467283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(enterxIop)
10477283Sgblack@eecs.umich.edu
10487283Sgblack@eecs.umich.edu    leavexCode = '''
10497797Sgblack@eecs.umich.edu        NextThumb = true;
10507797Sgblack@eecs.umich.edu        NextJazelle = false;
10517283Sgblack@eecs.umich.edu    '''
10527283Sgblack@eecs.umich.edu    leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
10537283Sgblack@eecs.umich.edu                              { "code": leavexCode,
10547283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
10557283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(leavexIop)
10567283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(leavexIop)
10577283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(leavexIop)
10587307Sgblack@eecs.umich.edu
10597307Sgblack@eecs.umich.edu    setendCode = '''
10607307Sgblack@eecs.umich.edu        CPSR cpsr = Cpsr;
10617307Sgblack@eecs.umich.edu        cpsr.e = imm;
10627307Sgblack@eecs.umich.edu        Cpsr = cpsr;
106312498Sgiacomo.travaglini@arm.com        fault = checkSETENDEnabled(xc->tcBase(), cpsr);
10647307Sgblack@eecs.umich.edu    '''
10657307Sgblack@eecs.umich.edu    setendIop = InstObjParams("setend", "Setend", "ImmOp",
10667307Sgblack@eecs.umich.edu                              { "code": setendCode,
10677648SAli.Saidi@ARM.com                                "predicate_test": predicateTest },
10687648SAli.Saidi@ARM.com                              ["IsSerializeAfter","IsNonSpeculative"])
10697307Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(setendIop)
10707307Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(setendIop)
10717307Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(setendIop)
10727315Sgblack@eecs.umich.edu
10737603SGene.Wu@arm.com    clrexCode = '''
10748209SAli.Saidi@ARM.com        LLSCLock = 0;
10757603SGene.Wu@arm.com    '''
10767603SGene.Wu@arm.com    clrexIop = InstObjParams("clrex", "Clrex","PredOp",
10777603SGene.Wu@arm.com                             { "code": clrexCode,
10787603SGene.Wu@arm.com                               "predicate_test": predicateTest },[])
10798209SAli.Saidi@ARM.com    header_output += BasicDeclare.subst(clrexIop)
10807603SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(clrexIop)
10817603SGene.Wu@arm.com    exec_output += PredOpExecute.subst(clrexIop)
10827603SGene.Wu@arm.com
108312358Snikos.nikoleris@arm.com    McrDcCheckCode = '''
108412499Sgiacomo.travaglini@arm.com        int preFlatDest = snsBankedIndex(dest, xc->tcBase());
108512358Snikos.nikoleris@arm.com        MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
108612358Snikos.nikoleris@arm.com            RegId(MiscRegClass, preFlatDest)).index();
108712358Snikos.nikoleris@arm.com        bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
108812358Snikos.nikoleris@arm.com                                          Hcptr, imm);
108912358Snikos.nikoleris@arm.com        bool can_write, undefined;
109012358Snikos.nikoleris@arm.com        std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
109112358Snikos.nikoleris@arm.com
109212358Snikos.nikoleris@arm.com        // if we're in non secure PL1 mode then we can trap regardless
109312358Snikos.nikoleris@arm.com        // of whether the register is accessible, in other modes we
109412358Snikos.nikoleris@arm.com        // trap if only if the register IS accessible.
109512358Snikos.nikoleris@arm.com        if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
109612358Snikos.nikoleris@arm.com                                         !inSecureState(Scr, Cpsr)))) {
109712358Snikos.nikoleris@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
109812358Snikos.nikoleris@arm.com                                                          mnemonic);
109912358Snikos.nikoleris@arm.com        }
110012358Snikos.nikoleris@arm.com        if (hypTrap) {
110112358Snikos.nikoleris@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
110212358Snikos.nikoleris@arm.com                                                    EC_TRAPPED_CP15_MCR_MRC);
110312358Snikos.nikoleris@arm.com        }
110412358Snikos.nikoleris@arm.com    '''
110512358Snikos.nikoleris@arm.com
110612358Snikos.nikoleris@arm.com    McrDcimvacCode = '''
110712358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
110812358Snikos.nikoleris@arm.com                                            Request::INVALIDATE |
110912358Snikos.nikoleris@arm.com                                            Request::DST_POC);
111012358Snikos.nikoleris@arm.com        EA = Op1;
111112358Snikos.nikoleris@arm.com    '''
111212504Snikos.nikoleris@arm.com    McrDcimvacIop = InstObjParams("mcr", "McrDcimvac",
111312504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
111412358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
111512358Snikos.nikoleris@arm.com                                   "postacc_code": "",
111612358Snikos.nikoleris@arm.com                                   "ea_code": McrDcimvacCode,
111712358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
111812358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
111912358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop)
112012358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop)
112112358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDcimvacIop) + \
112212358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDcimvacIop) + \
112312358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDcimvacIop)
112412358Snikos.nikoleris@arm.com
112512358Snikos.nikoleris@arm.com    McrDccmvacCode = '''
112612358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
112712358Snikos.nikoleris@arm.com                                            Request::CLEAN |
112812358Snikos.nikoleris@arm.com                                            Request::DST_POC);
112912358Snikos.nikoleris@arm.com        EA = Op1;
113012358Snikos.nikoleris@arm.com    '''
113112504Snikos.nikoleris@arm.com    McrDccmvacIop = InstObjParams("mcr", "McrDccmvac",
113212504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
113312358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
113412358Snikos.nikoleris@arm.com                                   "postacc_code": "",
113512358Snikos.nikoleris@arm.com                                   "ea_code": McrDccmvacCode,
113612358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
113712358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
113812358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop)
113912358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop)
114012358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccmvacIop) + \
114112358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccmvacIop) + \
114212358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccmvacIop)
114312358Snikos.nikoleris@arm.com
114412358Snikos.nikoleris@arm.com    McrDccmvauCode = '''
114512358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
114612358Snikos.nikoleris@arm.com                                            Request::CLEAN |
114712358Snikos.nikoleris@arm.com                                            Request::DST_POU);
114812358Snikos.nikoleris@arm.com        EA = Op1;
114912358Snikos.nikoleris@arm.com    '''
115012504Snikos.nikoleris@arm.com    McrDccmvauIop = InstObjParams("mcr", "McrDccmvau",
115112504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
115212358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
115312358Snikos.nikoleris@arm.com                                   "postacc_code": "",
115412358Snikos.nikoleris@arm.com                                   "ea_code": McrDccmvauCode,
115512358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
115612358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
115712358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop)
115812358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop)
115912358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccmvauIop) + \
116012358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccmvauIop) + \
116112358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccmvauIop)
116212358Snikos.nikoleris@arm.com
116312358Snikos.nikoleris@arm.com    McrDccimvacCode = '''
116412358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
116512358Snikos.nikoleris@arm.com                                            Request::CLEAN |
116612358Snikos.nikoleris@arm.com                                            Request::INVALIDATE |
116712358Snikos.nikoleris@arm.com                                            Request::DST_POC);
116812358Snikos.nikoleris@arm.com        EA = Op1;
116912358Snikos.nikoleris@arm.com    '''
117012504Snikos.nikoleris@arm.com    McrDccimvacIop = InstObjParams("mcr", "McrDccimvac",
117112504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
117212358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
117312358Snikos.nikoleris@arm.com                                   "postacc_code": "",
117412358Snikos.nikoleris@arm.com                                   "ea_code": McrDccimvacCode,
117512358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
117612358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
117712358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
117812358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
117912358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
118012358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccimvacIop) + \
118112358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccimvacIop)
118212358Snikos.nikoleris@arm.com
11837605SGene.Wu@arm.com    isbCode = '''
118410037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
118510037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
118610037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
118710474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
118810037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
118910037SARM gem5 Developers        }
11907605SGene.Wu@arm.com    '''
119110037SARM gem5 Developers    isbIop = InstObjParams("isb", "Isb", "ImmOp",
11927605SGene.Wu@arm.com                             {"code": isbCode,
11938068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
119412488Sgiacomo.travaglini@arm.com                                ['IsSquashAfter'])
119510037SARM gem5 Developers    header_output += ImmOpDeclare.subst(isbIop)
119610037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(isbIop)
11977605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(isbIop)
11987605SGene.Wu@arm.com
11997605SGene.Wu@arm.com    dsbCode = '''
120010037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
120110037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr,
120210037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
120310474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
120410037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
120510037SARM gem5 Developers        }
12067605SGene.Wu@arm.com    '''
120710037SARM gem5 Developers    dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
12087605SGene.Wu@arm.com                             {"code": dsbCode,
12098068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
121012261Sgiacomo.travaglini@arm.com                              ['IsMemBarrier', 'IsSerializeAfter'])
121110037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dsbIop)
121210037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dsbIop)
12137605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dsbIop)
12147605SGene.Wu@arm.com
12157605SGene.Wu@arm.com    dmbCode = '''
121610037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
121710037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr,
121810037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
121910474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
122010037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
122110037SARM gem5 Developers        }
12227605SGene.Wu@arm.com    '''
122310037SARM gem5 Developers    dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
12247605SGene.Wu@arm.com                             {"code": dmbCode,
12258068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
12268068SAli.Saidi@ARM.com                               ['IsMemBarrier'])
122710037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dmbIop)
122810037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dmbIop)
12297605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dmbIop)
12307605SGene.Wu@arm.com
12317613SGene.Wu@arm.com    dbgCode = '''
12327613SGene.Wu@arm.com    '''
12337613SGene.Wu@arm.com    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
12347613SGene.Wu@arm.com                             {"code": dbgCode,
12357613SGene.Wu@arm.com                               "predicate_test": predicateTest})
12367613SGene.Wu@arm.com    header_output += BasicDeclare.subst(dbgIop)
12377613SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(dbgIop)
12387613SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dbgIop)
12397613SGene.Wu@arm.com
12407315Sgblack@eecs.umich.edu    cpsCode = '''
12417315Sgblack@eecs.umich.edu    uint32_t mode = bits(imm, 4, 0);
12427315Sgblack@eecs.umich.edu    uint32_t f = bits(imm, 5);
12437315Sgblack@eecs.umich.edu    uint32_t i = bits(imm, 6);
12447315Sgblack@eecs.umich.edu    uint32_t a = bits(imm, 7);
12457315Sgblack@eecs.umich.edu    bool setMode = bits(imm, 8);
12467315Sgblack@eecs.umich.edu    bool enable = bits(imm, 9);
12477315Sgblack@eecs.umich.edu    CPSR cpsr = Cpsr;
12487400SAli.Saidi@ARM.com    SCTLR sctlr = Sctlr;
12497315Sgblack@eecs.umich.edu    if (cpsr.mode != MODE_USER) {
12507315Sgblack@eecs.umich.edu        if (enable) {
12517315Sgblack@eecs.umich.edu            if (f) cpsr.f = 0;
12527315Sgblack@eecs.umich.edu            if (i) cpsr.i = 0;
12537315Sgblack@eecs.umich.edu            if (a) cpsr.a = 0;
12547315Sgblack@eecs.umich.edu        } else {
12557400SAli.Saidi@ARM.com            if (f && !sctlr.nmfi) cpsr.f = 1;
12567315Sgblack@eecs.umich.edu            if (i) cpsr.i = 1;
12577315Sgblack@eecs.umich.edu            if (a) cpsr.a = 1;
12587315Sgblack@eecs.umich.edu        }
12597315Sgblack@eecs.umich.edu        if (setMode) {
12607315Sgblack@eecs.umich.edu            cpsr.mode = mode;
12617315Sgblack@eecs.umich.edu        }
12627315Sgblack@eecs.umich.edu    }
12637315Sgblack@eecs.umich.edu    Cpsr = cpsr;
12647315Sgblack@eecs.umich.edu    '''
12657315Sgblack@eecs.umich.edu    cpsIop = InstObjParams("cps", "Cps", "ImmOp",
12667315Sgblack@eecs.umich.edu                           { "code": cpsCode,
12677599Sminkyu.jeong@arm.com                             "predicate_test": predicateTest },
12687599Sminkyu.jeong@arm.com                           ["IsSerializeAfter","IsNonSpeculative"])
12697315Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(cpsIop)
12707315Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(cpsIop)
12717315Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(cpsIop)
12727202Sgblack@eecs.umich.edu}};
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