misc.isa revision 12541
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*-
27199Sgblack@eecs.umich.edu
312504Snikos.nikoleris@arm.com// Copyright (c) 2010-2013,2017-2018 ARM Limited
47199Sgblack@eecs.umich.edu// All rights reserved
57199Sgblack@eecs.umich.edu//
67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107199Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147199Sgblack@eecs.umich.edu//
157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
247199Sgblack@eecs.umich.edu// this software without specific prior written permission.
257199Sgblack@eecs.umich.edu//
267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
377199Sgblack@eecs.umich.edu//
387199Sgblack@eecs.umich.edu// Authors: Gabe Black
397199Sgblack@eecs.umich.edu
407199Sgblack@eecs.umich.edulet {{
417199Sgblack@eecs.umich.edu
427199Sgblack@eecs.umich.edu    svcCode = '''
4312541Sgiacomo.travaglini@arm.com    ThreadContext *tc = xc->tcBase();
4412541Sgiacomo.travaglini@arm.com
4512541Sgiacomo.travaglini@arm.com    const auto semihost_imm = Thumb? 0xAB : 0x123456;
4612541Sgiacomo.travaglini@arm.com
4712541Sgiacomo.travaglini@arm.com    if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
4812541Sgiacomo.travaglini@arm.com        R0 = ArmSystem::callSemihosting32(tc, R0, R1);
4912541Sgiacomo.travaglini@arm.com    } else {
5012541Sgiacomo.travaglini@arm.com        fault = std::make_shared<SupervisorCall>(machInst, imm);
5112541Sgiacomo.travaglini@arm.com    }
5210037SARM gem5 Developers    '''
5310037SARM gem5 Developers
5410037SARM gem5 Developers    svcIop = InstObjParams("svc", "Svc", "ImmOp",
5510037SARM gem5 Developers                           { "code": svcCode,
5612541Sgiacomo.travaglini@arm.com                             "predicate_test": predicateTest,
5712541Sgiacomo.travaglini@arm.com                             "thumb_semihost": '0xAB',
5812541Sgiacomo.travaglini@arm.com                             "arm_semihost": '0x123456' },
5912541Sgiacomo.travaglini@arm.com                           ["IsSyscall", "IsNonSpeculative",
6012541Sgiacomo.travaglini@arm.com                            "IsSerializeAfter"])
6110037SARM gem5 Developers    header_output = ImmOpDeclare.subst(svcIop)
6212541Sgiacomo.travaglini@arm.com    decoder_output = SemihostConstructor.subst(svcIop)
6310037SARM gem5 Developers    exec_output = PredOpExecute.subst(svcIop)
6410037SARM gem5 Developers
6510037SARM gem5 Developers    smcCode = '''
6610037SARM gem5 Developers    HCR  hcr  = Hcr;
6710037SARM gem5 Developers    CPSR cpsr = Cpsr;
6810037SARM gem5 Developers    SCR  scr  = Scr;
6910037SARM gem5 Developers
7010037SARM gem5 Developers    if ((cpsr.mode != MODE_USER) && FullSystem) {
7110037SARM gem5 Developers        if (ArmSystem::haveVirtualization(xc->tcBase()) &&
7210037SARM gem5 Developers            !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
7310474Sandreas.hansson@arm.com            fault = std::make_shared<HypervisorTrap>(machInst, 0,
7410474Sandreas.hansson@arm.com                                                     EC_SMC_TO_HYP);
7510037SARM gem5 Developers        } else {
7610037SARM gem5 Developers            if (scr.scd) {
7710037SARM gem5 Developers                fault = disabledFault();
7810037SARM gem5 Developers            } else {
7910474Sandreas.hansson@arm.com                fault = std::make_shared<SecureMonitorCall>(machInst);
8010037SARM gem5 Developers            }
8110037SARM gem5 Developers        }
828782Sgblack@eecs.umich.edu    } else {
8310037SARM gem5 Developers        fault = disabledFault();
848782Sgblack@eecs.umich.edu    }
857199Sgblack@eecs.umich.edu    '''
867199Sgblack@eecs.umich.edu
8710037SARM gem5 Developers    smcIop = InstObjParams("smc", "Smc", "PredOp",
8810037SARM gem5 Developers                           { "code": smcCode,
898628SAli.Saidi@ARM.com                             "predicate_test": predicateTest },
9010037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
9110037SARM gem5 Developers    header_output += BasicDeclare.subst(smcIop)
9210037SARM gem5 Developers    decoder_output += BasicConstructor.subst(smcIop)
9310037SARM gem5 Developers    exec_output += PredOpExecute.subst(smcIop)
9410037SARM gem5 Developers
9510037SARM gem5 Developers    hvcCode = '''
9610037SARM gem5 Developers    CPSR cpsr = Cpsr;
9710037SARM gem5 Developers    SCR  scr  = Scr;
9810037SARM gem5 Developers
9910037SARM gem5 Developers    // Filter out the various cases where this instruction isn't defined
10010037SARM gem5 Developers    if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
10110037SARM gem5 Developers        (cpsr.mode == MODE_USER) ||
10210037SARM gem5 Developers        (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
10310037SARM gem5 Developers        fault = disabledFault();
10410037SARM gem5 Developers    } else {
10510474Sandreas.hansson@arm.com        fault = std::make_shared<HypervisorCall>(machInst, imm);
10610037SARM gem5 Developers    }
10710037SARM gem5 Developers    '''
10810037SARM gem5 Developers
10910037SARM gem5 Developers    hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
11010037SARM gem5 Developers                           { "code": hvcCode,
11110037SARM gem5 Developers                             "predicate_test": predicateTest },
11210037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
11310037SARM gem5 Developers    header_output += ImmOpDeclare.subst(hvcIop)
11410037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(hvcIop)
11510037SARM gem5 Developers    exec_output += PredOpExecute.subst(hvcIop)
11610037SARM gem5 Developers
11710037SARM gem5 Developers    eretCode = '''
11810037SARM gem5 Developers        SCTLR sctlr   = Sctlr;
11910037SARM gem5 Developers        CPSR old_cpsr = Cpsr;
12010037SARM gem5 Developers        old_cpsr.nz   = CondCodesNZ;
12110037SARM gem5 Developers        old_cpsr.c    = CondCodesC;
12210037SARM gem5 Developers        old_cpsr.v    = CondCodesV;
12310037SARM gem5 Developers        old_cpsr.ge   = CondCodesGE;
12410037SARM gem5 Developers
12510037SARM gem5 Developers        CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
12610037SARM gem5 Developers                            true, sctlr.nmfi, xc->tcBase());
12710037SARM gem5 Developers        Cpsr        = ~CondCodesMask & new_cpsr;
12810037SARM gem5 Developers        CondCodesNZ = new_cpsr.nz;
12910037SARM gem5 Developers        CondCodesC  = new_cpsr.c;
13010037SARM gem5 Developers        CondCodesV  = new_cpsr.v;
13110037SARM gem5 Developers        CondCodesGE = new_cpsr.ge;
13210037SARM gem5 Developers
13310037SARM gem5 Developers        NextThumb = (new_cpsr).t;
13410037SARM gem5 Developers                    NextJazelle = (new_cpsr).j;
13510037SARM gem5 Developers                    NextItState = (((new_cpsr).it2 << 2) & 0xFC)
13610037SARM gem5 Developers                        | ((new_cpsr).it1 & 0x3);
13710037SARM gem5 Developers
13810037SARM gem5 Developers        NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
13910037SARM gem5 Developers    '''
14010037SARM gem5 Developers
14110037SARM gem5 Developers    eretIop = InstObjParams("eret", "Eret", "PredOp",
14210037SARM gem5 Developers                           { "code": eretCode,
14310037SARM gem5 Developers                             "predicate_test": predicateTest },
14411355Smitch.hayenga@arm.com                           ["IsNonSpeculative", "IsSerializeAfter",
14511355Smitch.hayenga@arm.com                            "IsSquashAfter"])
14610037SARM gem5 Developers    header_output += BasicDeclare.subst(eretIop)
14710037SARM gem5 Developers    decoder_output += BasicConstructor.subst(eretIop)
14810037SARM gem5 Developers    exec_output += PredOpExecute.subst(eretIop)
14910037SARM gem5 Developers
15012258Sgiacomo.travaglini@arm.com    crcCode = '''
15112258Sgiacomo.travaglini@arm.com    constexpr uint8_t size_bytes = %(sz)d;
15212258Sgiacomo.travaglini@arm.com    constexpr uint32_t poly = %(polynom)s;
15310037SARM gem5 Developers
15412258Sgiacomo.travaglini@arm.com    uint32_t data = htole(Op2);
15512258Sgiacomo.travaglini@arm.com    auto data_buffer = reinterpret_cast<uint8_t*>(&data);
15612258Sgiacomo.travaglini@arm.com
15712258Sgiacomo.travaglini@arm.com    Dest = crc32<poly>(
15812258Sgiacomo.travaglini@arm.com        data_buffer,   /* Message Register */
15912258Sgiacomo.travaglini@arm.com        Op1,           /* Initial Value  of the CRC */
16012258Sgiacomo.travaglini@arm.com        size_bytes     /* Size of the original Message */
16112258Sgiacomo.travaglini@arm.com    );
16212258Sgiacomo.travaglini@arm.com    '''
16312258Sgiacomo.travaglini@arm.com
16412258Sgiacomo.travaglini@arm.com    def crc32Emit(mnem, implCode, castagnoli, size):
16512258Sgiacomo.travaglini@arm.com        global header_output, decoder_output, exec_output
16612258Sgiacomo.travaglini@arm.com
16712258Sgiacomo.travaglini@arm.com        if castagnoli:
16812258Sgiacomo.travaglini@arm.com            # crc32c instructions
16912258Sgiacomo.travaglini@arm.com            poly = "0x1EDC6F41"
17012258Sgiacomo.travaglini@arm.com        else:
17112258Sgiacomo.travaglini@arm.com            # crc32 instructions
17212258Sgiacomo.travaglini@arm.com            poly = "0x04C11DB7"
17312258Sgiacomo.travaglini@arm.com
17412258Sgiacomo.travaglini@arm.com        data = {'sz' : size, 'polynom': poly}
17512258Sgiacomo.travaglini@arm.com
17612258Sgiacomo.travaglini@arm.com        instCode = implCode % data
17712258Sgiacomo.travaglini@arm.com
17812258Sgiacomo.travaglini@arm.com        crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
17912258Sgiacomo.travaglini@arm.com                               { "code": instCode,
18012258Sgiacomo.travaglini@arm.com                                 "predicate_test": predicateTest }, [])
18112258Sgiacomo.travaglini@arm.com        header_output += RegRegRegOpDeclare.subst(crcIop)
18212258Sgiacomo.travaglini@arm.com        decoder_output += RegRegRegOpConstructor.subst(crcIop)
18312258Sgiacomo.travaglini@arm.com        exec_output += PredOpExecute.subst(crcIop)
18412258Sgiacomo.travaglini@arm.com
18512258Sgiacomo.travaglini@arm.com    crc32Emit("crc32b", crcCode, False, 1);
18612258Sgiacomo.travaglini@arm.com    crc32Emit("crc32h", crcCode, False, 2);
18712258Sgiacomo.travaglini@arm.com    crc32Emit("crc32w", crcCode, False, 4);
18812258Sgiacomo.travaglini@arm.com    crc32Emit("crc32cb", crcCode, True, 1);
18912258Sgiacomo.travaglini@arm.com    crc32Emit("crc32ch", crcCode, True, 2);
19012258Sgiacomo.travaglini@arm.com    crc32Emit("crc32cw", crcCode, True, 4);
1917199Sgblack@eecs.umich.edu
1927199Sgblack@eecs.umich.edu}};
1937202Sgblack@eecs.umich.edu
1947202Sgblack@eecs.umich.edulet {{
1957202Sgblack@eecs.umich.edu
1967202Sgblack@eecs.umich.edu    header_output = decoder_output = exec_output = ""
1977202Sgblack@eecs.umich.edu
1988301SAli.Saidi@ARM.com    mrsCpsrCode = '''
1998303SAli.Saidi@ARM.com        CPSR cpsr = Cpsr;
2008303SAli.Saidi@ARM.com        cpsr.nz = CondCodesNZ;
2018303SAli.Saidi@ARM.com        cpsr.c = CondCodesC;
2028303SAli.Saidi@ARM.com        cpsr.v = CondCodesV;
2038303SAli.Saidi@ARM.com        cpsr.ge = CondCodesGE;
2048303SAli.Saidi@ARM.com        Dest = cpsr & 0xF8FF03DF
2058301SAli.Saidi@ARM.com    '''
2068301SAli.Saidi@ARM.com
2077202Sgblack@eecs.umich.edu    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
2087202Sgblack@eecs.umich.edu                               { "code": mrsCpsrCode,
2097599Sminkyu.jeong@arm.com                                 "predicate_test": condPredicateTest },
2107783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
2117202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsCpsrIop)
2127202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsCpsrIop)
2137202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsCpsrIop)
2147202Sgblack@eecs.umich.edu
2157202Sgblack@eecs.umich.edu    mrsSpsrCode = "Dest = Spsr"
2167202Sgblack@eecs.umich.edu    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
2177202Sgblack@eecs.umich.edu                               { "code": mrsSpsrCode,
2187599Sminkyu.jeong@arm.com                                 "predicate_test": predicateTest },
2197783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
2207202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsSpsrIop)
2217202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsSpsrIop)
2227202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsSpsrIop)
2237202Sgblack@eecs.umich.edu
22410037SARM gem5 Developers    mrsBankedRegCode = '''
22510037SARM gem5 Developers        bool isIntReg;
22610037SARM gem5 Developers        int  regIdx;
22710037SARM gem5 Developers
22810037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
22910037SARM gem5 Developers            if (isIntReg) {
23010037SARM gem5 Developers                Dest = DecodedBankedIntReg;
23110037SARM gem5 Developers            } else {
23210037SARM gem5 Developers                Dest = xc->readMiscReg(regIdx);
23310037SARM gem5 Developers            }
23410037SARM gem5 Developers        } else {
23510474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
23610474Sandreas.hansson@arm.com                                                          mnemonic);
23710037SARM gem5 Developers        }
23810037SARM gem5 Developers    '''
23910037SARM gem5 Developers    mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
24010037SARM gem5 Developers                                    { "code": mrsBankedRegCode,
24110037SARM gem5 Developers                                      "predicate_test": predicateTest },
24210037SARM gem5 Developers                                    ["IsSerializeBefore"])
24310037SARM gem5 Developers    header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
24410037SARM gem5 Developers    decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
24510037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrsBankedRegIop)
24610037SARM gem5 Developers
24710037SARM gem5 Developers    msrBankedRegCode = '''
24810037SARM gem5 Developers        bool isIntReg;
24910037SARM gem5 Developers        int  regIdx;
25010037SARM gem5 Developers
25110037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
25210037SARM gem5 Developers            if (isIntReg) {
25310037SARM gem5 Developers                // This is a bit nasty, you would have thought that
25410037SARM gem5 Developers                // DecodedBankedIntReg wouldn't be written to unless the
25510037SARM gem5 Developers                // conditions on the IF statements above are met, however if
25610037SARM gem5 Developers                // you look at the generated C code you'll find that they are.
25710037SARM gem5 Developers                // However this is safe as DecodedBankedIntReg (which is used
25810037SARM gem5 Developers                // in operands.isa to get the index of DecodedBankedIntReg)
25910037SARM gem5 Developers                // will return INTREG_DUMMY if its not a valid integer
26010037SARM gem5 Developers                // register, so redirecting the write to somewhere we don't
26110037SARM gem5 Developers                // care about.
26210037SARM gem5 Developers                DecodedBankedIntReg = Op1;
26310037SARM gem5 Developers            } else {
26410037SARM gem5 Developers                xc->setMiscReg(regIdx, Op1);
26510037SARM gem5 Developers            }
26610037SARM gem5 Developers        } else {
26710474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
26810474Sandreas.hansson@arm.com                                                          mnemonic);
26910037SARM gem5 Developers        }
27010037SARM gem5 Developers    '''
27110037SARM gem5 Developers    msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
27210037SARM gem5 Developers                                    { "code": msrBankedRegCode,
27310037SARM gem5 Developers                                      "predicate_test": predicateTest },
27410501Sakash.bagdia@ARM.com                                    ["IsSerializeAfter", "IsNonSpeculative"])
27510037SARM gem5 Developers    header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
27610037SARM gem5 Developers    decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
27710037SARM gem5 Developers    exec_output += PredOpExecute.subst(msrBankedRegIop)
27810037SARM gem5 Developers
2797202Sgblack@eecs.umich.edu    msrCpsrRegCode = '''
2807400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
2818303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
2828303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
2838303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
2848303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
2858303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
2868303SAli.Saidi@ARM.com
2878303SAli.Saidi@ARM.com        CPSR new_cpsr =
28810037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
28910037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
2908303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
2918303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
2928303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
2938303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
2948303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
2957202Sgblack@eecs.umich.edu    '''
2967202Sgblack@eecs.umich.edu    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
2977202Sgblack@eecs.umich.edu                                  { "code": msrCpsrRegCode,
2987599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
2997599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3007202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
3017202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
3027202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrRegIop)
3037202Sgblack@eecs.umich.edu
3047202Sgblack@eecs.umich.edu    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
3057202Sgblack@eecs.umich.edu    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
3067202Sgblack@eecs.umich.edu                                  { "code": msrSpsrRegCode,
3077599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
3087599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3097202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
3107202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
3117202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrRegIop)
3127202Sgblack@eecs.umich.edu
3137202Sgblack@eecs.umich.edu    msrCpsrImmCode = '''
3147400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
3158303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
3168303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
3178303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
3188303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
3198303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
3208303SAli.Saidi@ARM.com        CPSR new_cpsr =
32110037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
32210037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
3238303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
3248303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
3258303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
3268303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
3278303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
3287202Sgblack@eecs.umich.edu    '''
3297202Sgblack@eecs.umich.edu    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
3307202Sgblack@eecs.umich.edu                                  { "code": msrCpsrImmCode,
3317599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
3327599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3337202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
3347202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
3357202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrImmIop)
3367202Sgblack@eecs.umich.edu
3377202Sgblack@eecs.umich.edu    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
3387202Sgblack@eecs.umich.edu    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
3397202Sgblack@eecs.umich.edu                                  { "code": msrSpsrImmCode,
3407599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
3417599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3427202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
3437202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
3447202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrImmIop)
3457209Sgblack@eecs.umich.edu
3467209Sgblack@eecs.umich.edu    revCode = '''
3477209Sgblack@eecs.umich.edu    uint32_t val = Op1;
3487209Sgblack@eecs.umich.edu    Dest = swap_byte(val);
3497209Sgblack@eecs.umich.edu    '''
3507261Sgblack@eecs.umich.edu    revIop = InstObjParams("rev", "Rev", "RegRegOp",
3517209Sgblack@eecs.umich.edu                           { "code": revCode,
3527209Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
3537261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revIop)
3547261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revIop)
3557209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revIop)
3567209Sgblack@eecs.umich.edu
3577209Sgblack@eecs.umich.edu    rev16Code = '''
3587209Sgblack@eecs.umich.edu    uint32_t val = Op1;
3597209Sgblack@eecs.umich.edu    Dest = (bits(val, 15, 8) << 0) |
3607209Sgblack@eecs.umich.edu           (bits(val, 7, 0) << 8) |
3617209Sgblack@eecs.umich.edu           (bits(val, 31, 24) << 16) |
3627209Sgblack@eecs.umich.edu           (bits(val, 23, 16) << 24);
3637209Sgblack@eecs.umich.edu    '''
3647261Sgblack@eecs.umich.edu    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
3657209Sgblack@eecs.umich.edu                             { "code": rev16Code,
3667209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
3677261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rev16Iop)
3687261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rev16Iop)
3697209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rev16Iop)
3707209Sgblack@eecs.umich.edu
3717209Sgblack@eecs.umich.edu    revshCode = '''
3727209Sgblack@eecs.umich.edu    uint16_t val = Op1;
3737209Sgblack@eecs.umich.edu    Dest = sext<16>(swap_byte(val));
3747209Sgblack@eecs.umich.edu    '''
3757261Sgblack@eecs.umich.edu    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
3767209Sgblack@eecs.umich.edu                             { "code": revshCode,
3777209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
3787261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revshIop)
3797261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revshIop)
3807209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revshIop)
3817226Sgblack@eecs.umich.edu
3827249Sgblack@eecs.umich.edu    rbitCode = '''
38312227Sgiacomo.travaglini@arm.com    Dest = reverseBits(Op1);
3847249Sgblack@eecs.umich.edu    '''
3857261Sgblack@eecs.umich.edu    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
3867249Sgblack@eecs.umich.edu                            { "code": rbitCode,
3877249Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
3887261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rbitIop)
3897261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rbitIop)
3907249Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rbitIop)
3917249Sgblack@eecs.umich.edu
3927251Sgblack@eecs.umich.edu    clzCode = '''
3937251Sgblack@eecs.umich.edu        Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
3947251Sgblack@eecs.umich.edu    '''
3957261Sgblack@eecs.umich.edu    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
3967251Sgblack@eecs.umich.edu                           { "code": clzCode,
3977251Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
3987261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(clzIop)
3997261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(clzIop)
4007251Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(clzIop)
4017251Sgblack@eecs.umich.edu
4027226Sgblack@eecs.umich.edu    ssatCode = '''
4037226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
4047226Sgblack@eecs.umich.edu        int32_t res;
4057232Sgblack@eecs.umich.edu        if (satInt(res, operand, imm))
4068302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4077226Sgblack@eecs.umich.edu        Dest = res;
4087226Sgblack@eecs.umich.edu    '''
4097232Sgblack@eecs.umich.edu    ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
4107226Sgblack@eecs.umich.edu                            { "code": ssatCode,
4118304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(ssatCode) }, [])
4127232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
4137232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
4147226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssatIop)
4157226Sgblack@eecs.umich.edu
4167226Sgblack@eecs.umich.edu    usatCode = '''
4177226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
4187226Sgblack@eecs.umich.edu        int32_t res;
4197232Sgblack@eecs.umich.edu        if (uSatInt(res, operand, imm))
4208302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4217226Sgblack@eecs.umich.edu        Dest = res;
4227226Sgblack@eecs.umich.edu    '''
4237232Sgblack@eecs.umich.edu    usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
4247226Sgblack@eecs.umich.edu                            { "code": usatCode,
4258304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(usatCode) }, [])
4267232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(usatIop)
4277232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
4287226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usatIop)
4297226Sgblack@eecs.umich.edu
4307226Sgblack@eecs.umich.edu    ssat16Code = '''
4317226Sgblack@eecs.umich.edu        int32_t res;
4327226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
4337226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
4347226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
4357232Sgblack@eecs.umich.edu        if (satInt(res, argLow, imm))
4368302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4377226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
4387232Sgblack@eecs.umich.edu        if (satInt(res, argHigh, imm))
4398302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4407226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4417226Sgblack@eecs.umich.edu        Dest = resTemp;
4427226Sgblack@eecs.umich.edu    '''
4437232Sgblack@eecs.umich.edu    ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
4447226Sgblack@eecs.umich.edu                              { "code": ssat16Code,
4458304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(ssat16Code) }, [])
4467232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(ssat16Iop)
4477232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
4487226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssat16Iop)
4497226Sgblack@eecs.umich.edu
4507226Sgblack@eecs.umich.edu    usat16Code = '''
4517226Sgblack@eecs.umich.edu        int32_t res;
4527226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
4537226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
4547226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
4557232Sgblack@eecs.umich.edu        if (uSatInt(res, argLow, imm))
4568302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4577226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
4587232Sgblack@eecs.umich.edu        if (uSatInt(res, argHigh, imm))
4598302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4607226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4617226Sgblack@eecs.umich.edu        Dest = resTemp;
4627226Sgblack@eecs.umich.edu    '''
4637232Sgblack@eecs.umich.edu    usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
4647226Sgblack@eecs.umich.edu                              { "code": usat16Code,
4658304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(usat16Code) }, [])
4667232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(usat16Iop)
4677232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
4687226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usat16Iop)
4697234Sgblack@eecs.umich.edu
4707234Sgblack@eecs.umich.edu    sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
4717234Sgblack@eecs.umich.edu                            { "code":
4728588Sgblack@eecs.umich.edu                              "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
4737234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
4747234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtbIop)
4757234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
4767234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtbIop)
4777234Sgblack@eecs.umich.edu
4787234Sgblack@eecs.umich.edu    sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
4797234Sgblack@eecs.umich.edu                             { "code":
4807234Sgblack@eecs.umich.edu                               '''
4818588Sgblack@eecs.umich.edu                                   Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
4827234Sgblack@eecs.umich.edu                                          Op1;
4837234Sgblack@eecs.umich.edu                               ''',
4847234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
4857234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
4867234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
4877234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtabIop)
4887234Sgblack@eecs.umich.edu
4897234Sgblack@eecs.umich.edu    sxtb16Code = '''
4907234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
4917234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
4927234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
4937234Sgblack@eecs.umich.edu                sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
4947234Sgblack@eecs.umich.edu    Dest = resTemp;
4957234Sgblack@eecs.umich.edu    '''
4967234Sgblack@eecs.umich.edu    sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
4977234Sgblack@eecs.umich.edu                              { "code": sxtb16Code,
4987234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
4997234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
5007234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
5017234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtb16Iop)
5027234Sgblack@eecs.umich.edu
5037234Sgblack@eecs.umich.edu    sxtab16Code = '''
5047234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5057234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
5067234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
5077234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5087234Sgblack@eecs.umich.edu                sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
5097234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
5107234Sgblack@eecs.umich.edu    Dest = resTemp;
5117234Sgblack@eecs.umich.edu    '''
5127234Sgblack@eecs.umich.edu    sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
5137234Sgblack@eecs.umich.edu                               { "code": sxtab16Code,
5147234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
5157234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
5167234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
5177234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtab16Iop)
5187234Sgblack@eecs.umich.edu
5197234Sgblack@eecs.umich.edu    sxthCode = '''
5207234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
5217234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5227234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated);
5237234Sgblack@eecs.umich.edu    '''
5247234Sgblack@eecs.umich.edu    sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
5257234Sgblack@eecs.umich.edu                              { "code": sxthCode,
5267234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5277234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxthIop)
5287234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxthIop)
5297234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxthIop)
5307234Sgblack@eecs.umich.edu
5317234Sgblack@eecs.umich.edu    sxtahCode = '''
5327234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
5337234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5347234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated) + Op1;
5357234Sgblack@eecs.umich.edu    '''
5367234Sgblack@eecs.umich.edu    sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
5377234Sgblack@eecs.umich.edu                             { "code": sxtahCode,
5387234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5397234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
5407234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
5417234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtahIop)
5427234Sgblack@eecs.umich.edu
5437234Sgblack@eecs.umich.edu    uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
5448588Sgblack@eecs.umich.edu                            { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
5457234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
5467234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtbIop)
5477234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
5487234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtbIop)
5497234Sgblack@eecs.umich.edu
5507234Sgblack@eecs.umich.edu    uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
5517234Sgblack@eecs.umich.edu                             { "code":
5528588Sgblack@eecs.umich.edu                               "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
5537234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5547234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
5557234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
5567234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtabIop)
5577234Sgblack@eecs.umich.edu
5587234Sgblack@eecs.umich.edu    uxtb16Code = '''
5597234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5607234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
5617234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5627234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
5637234Sgblack@eecs.umich.edu    Dest = resTemp;
5647234Sgblack@eecs.umich.edu    '''
5657234Sgblack@eecs.umich.edu    uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
5667234Sgblack@eecs.umich.edu                              { "code": uxtb16Code,
5677234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5687234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
5697234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
5707234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtb16Iop)
5717234Sgblack@eecs.umich.edu
5727234Sgblack@eecs.umich.edu    uxtab16Code = '''
5737234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5747234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
5757234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
5767234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5777234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
5787234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
5797234Sgblack@eecs.umich.edu    Dest = resTemp;
5807234Sgblack@eecs.umich.edu    '''
5817234Sgblack@eecs.umich.edu    uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
5827234Sgblack@eecs.umich.edu                               { "code": uxtab16Code,
5837234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
5847234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
5857234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
5867234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtab16Iop)
5877234Sgblack@eecs.umich.edu
5887234Sgblack@eecs.umich.edu    uxthCode = '''
5897234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
5907234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5917234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated;
5927234Sgblack@eecs.umich.edu    '''
5937234Sgblack@eecs.umich.edu    uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
5947234Sgblack@eecs.umich.edu                              { "code": uxthCode,
5957234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5967234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxthIop)
5977234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxthIop)
5987234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxthIop)
5997234Sgblack@eecs.umich.edu
6007234Sgblack@eecs.umich.edu    uxtahCode = '''
6017234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
6027234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
6037234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated + Op1;
6047234Sgblack@eecs.umich.edu    '''
6057234Sgblack@eecs.umich.edu    uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
6067234Sgblack@eecs.umich.edu                             { "code": uxtahCode,
6077234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
6087234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
6097234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
6107234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtahIop)
6117239Sgblack@eecs.umich.edu
6127239Sgblack@eecs.umich.edu    selCode = '''
6137239Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6147239Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6157239Sgblack@eecs.umich.edu            int low = i * 8;
6167239Sgblack@eecs.umich.edu            int high = low + 7;
6177239Sgblack@eecs.umich.edu            replaceBits(resTemp, high, low,
6188303SAli.Saidi@ARM.com                        bits(CondCodesGE, i) ?
6197239Sgblack@eecs.umich.edu                            bits(Op1, high, low) : bits(Op2, high, low));
6207239Sgblack@eecs.umich.edu        }
6217239Sgblack@eecs.umich.edu        Dest = resTemp;
6227239Sgblack@eecs.umich.edu    '''
6237239Sgblack@eecs.umich.edu    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
6247239Sgblack@eecs.umich.edu                           { "code": selCode,
6258303SAli.Saidi@ARM.com                             "predicate_test": predicateTest }, [])
6267239Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(selIop)
6277239Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(selIop)
6287239Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(selIop)
6297242Sgblack@eecs.umich.edu
6307242Sgblack@eecs.umich.edu    usad8Code = '''
6317242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6327242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6337242Sgblack@eecs.umich.edu            int low = i * 8;
6347242Sgblack@eecs.umich.edu            int high = low + 7;
6357242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
6367242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
6377242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
6387242Sgblack@eecs.umich.edu        }
6397242Sgblack@eecs.umich.edu        Dest = resTemp;
6407242Sgblack@eecs.umich.edu    '''
6417242Sgblack@eecs.umich.edu    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
6427242Sgblack@eecs.umich.edu                             { "code": usad8Code,
6437242Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
6447242Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(usad8Iop)
6457242Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
6467242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usad8Iop)
6477242Sgblack@eecs.umich.edu
6487242Sgblack@eecs.umich.edu    usada8Code = '''
6497242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6507242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6517242Sgblack@eecs.umich.edu            int low = i * 8;
6527242Sgblack@eecs.umich.edu            int high = low + 7;
6537242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
6547242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
6557242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
6567242Sgblack@eecs.umich.edu        }
6577242Sgblack@eecs.umich.edu        Dest = Op3 + resTemp;
6587242Sgblack@eecs.umich.edu    '''
6597242Sgblack@eecs.umich.edu    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
6607242Sgblack@eecs.umich.edu                              { "code": usada8Code,
6617242Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
6627242Sgblack@eecs.umich.edu    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
6637242Sgblack@eecs.umich.edu    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
6647242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usada8Iop)
6657247Sgblack@eecs.umich.edu
66610474Sandreas.hansson@arm.com    bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n'
6677848SAli.Saidi@ARM.com    bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
6687410Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(bkptIop)
6697410Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(bkptIop)
6707410Sgblack@eecs.umich.edu    exec_output += BasicExecute.subst(bkptIop)
6717410Sgblack@eecs.umich.edu
67210037SARM gem5 Developers    nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
6737247Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(nopIop)
67410037SARM gem5 Developers    decoder_output += BasicConstructor64.subst(nopIop)
67510037SARM gem5 Developers    exec_output += BasicExecute.subst(nopIop)
6767408Sgblack@eecs.umich.edu
6777418Sgblack@eecs.umich.edu    yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
6787418Sgblack@eecs.umich.edu            { "code" : "", "predicate_test" : predicateTest })
6797418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(yieldIop)
6807418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(yieldIop)
6817418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(yieldIop)
6827418Sgblack@eecs.umich.edu
6837418Sgblack@eecs.umich.edu    wfeCode = '''
68410037SARM gem5 Developers    CPSR cpsr = Cpsr;
68510037SARM gem5 Developers    SCR  scr  = Scr64;
68610037SARM gem5 Developers
68710037SARM gem5 Developers    // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
68810037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
6898285SPrakash.Ramrakhyani@arm.com    if (SevMailbox == 1) {
6907418Sgblack@eecs.umich.edu        SevMailbox = 0;
69110037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
69211150Smitch.hayenga@arm.com    } else if (tc->getCpuPtr()->getInterruptController(
69311150Smitch.hayenga@arm.com                tc->threadId())->checkInterrupts(tc)) {
69410037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
6958285SPrakash.Ramrakhyani@arm.com    } else {
69612403Sgiacomo.travaglini@arm.com        fault = trapWFx(tc, cpsr, scr, true);
69712403Sgiacomo.travaglini@arm.com        if (fault == NoFault) {
69812403Sgiacomo.travaglini@arm.com            PseudoInst::quiesce(tc);
69912403Sgiacomo.travaglini@arm.com        } else {
70012403Sgiacomo.travaglini@arm.com            PseudoInst::quiesceSkip(tc);
70112403Sgiacomo.travaglini@arm.com        }
7028142SAli.Saidi@ARM.com    }
7037418Sgblack@eecs.umich.edu    '''
7048518Sgeoffrey.blake@arm.com    wfePredFixUpCode = '''
7058518Sgeoffrey.blake@arm.com    // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
7068518Sgeoffrey.blake@arm.com    // and SEV interrupts
7078518Sgeoffrey.blake@arm.com    SevMailbox = 1;
7088518Sgeoffrey.blake@arm.com    '''
7097418Sgblack@eecs.umich.edu    wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
7108518Sgeoffrey.blake@arm.com            { "code" : wfeCode,
7118518Sgeoffrey.blake@arm.com              "pred_fixup" : wfePredFixUpCode,
7128518Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest },
7138733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
7148733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
7157418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfeIop)
7167418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfeIop)
7178518Sgeoffrey.blake@arm.com    exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
7187418Sgblack@eecs.umich.edu
7197418Sgblack@eecs.umich.edu    wfiCode = '''
72010037SARM gem5 Developers    HCR  hcr  = Hcr;
72110037SARM gem5 Developers    CPSR cpsr = Cpsr;
72210037SARM gem5 Developers    SCR  scr  = Scr64;
72310037SARM gem5 Developers
7248285SPrakash.Ramrakhyani@arm.com    // WFI doesn't sleep if interrupts are pending (masked or not)
72510037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
72611150Smitch.hayenga@arm.com    if (tc->getCpuPtr()->getInterruptController(
72711150Smitch.hayenga@arm.com                tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
72810037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
7298285SPrakash.Ramrakhyani@arm.com    } else {
73012403Sgiacomo.travaglini@arm.com        fault = trapWFx(tc, cpsr, scr, false);
73112403Sgiacomo.travaglini@arm.com        if (fault == NoFault) {
73212403Sgiacomo.travaglini@arm.com            PseudoInst::quiesce(tc);
73312403Sgiacomo.travaglini@arm.com        } else {
73412403Sgiacomo.travaglini@arm.com            PseudoInst::quiesceSkip(tc);
73512403Sgiacomo.travaglini@arm.com        }
7368285SPrakash.Ramrakhyani@arm.com    }
73711150Smitch.hayenga@arm.com    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
7387418Sgblack@eecs.umich.edu    '''
7397418Sgblack@eecs.umich.edu    wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
7407418Sgblack@eecs.umich.edu            { "code" : wfiCode, "predicate_test" : predicateTest },
7418733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
7428733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
7437418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfiIop)
7447418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfiIop)
7458142SAli.Saidi@ARM.com    exec_output += QuiescePredOpExecute.subst(wfiIop)
7467418Sgblack@eecs.umich.edu
7477418Sgblack@eecs.umich.edu    sevCode = '''
7488142SAli.Saidi@ARM.com    SevMailbox = 1;
7497418Sgblack@eecs.umich.edu    System *sys = xc->tcBase()->getSystemPtr();
7507418Sgblack@eecs.umich.edu    for (int x = 0; x < sys->numContexts(); x++) {
7517418Sgblack@eecs.umich.edu        ThreadContext *oc = sys->getThreadContext(x);
7528285SPrakash.Ramrakhyani@arm.com        if (oc == xc->tcBase())
7538285SPrakash.Ramrakhyani@arm.com            continue;
7548518Sgeoffrey.blake@arm.com        // Wake CPU with interrupt if they were sleeping
7558285SPrakash.Ramrakhyani@arm.com        if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
7568518Sgeoffrey.blake@arm.com            // Post Interrupt and wake cpu if needed
75711150Smitch.hayenga@arm.com            oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
7588142SAli.Saidi@ARM.com        }
7597418Sgblack@eecs.umich.edu    }
7607418Sgblack@eecs.umich.edu    '''
7617418Sgblack@eecs.umich.edu    sevIop = InstObjParams("sev", "SevInst", "PredOp", \
7627418Sgblack@eecs.umich.edu            { "code" : sevCode, "predicate_test" : predicateTest },
7638733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
7647418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(sevIop)
7657418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(sevIop)
7667418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sevIop)
7677418Sgblack@eecs.umich.edu
76810037SARM gem5 Developers    sevlCode = '''
76910037SARM gem5 Developers    SevMailbox = 1;
77010037SARM gem5 Developers    '''
77110037SARM gem5 Developers    sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
77210037SARM gem5 Developers            { "code" : sevlCode, "predicate_test" : predicateTest },
77310037SARM gem5 Developers            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
77410037SARM gem5 Developers    header_output += BasicDeclare.subst(sevlIop)
77510037SARM gem5 Developers    decoder_output += BasicConstructor.subst(sevlIop)
77610037SARM gem5 Developers    exec_output += BasicExecute.subst(sevlIop)
77710037SARM gem5 Developers
7787408Sgblack@eecs.umich.edu    itIop = InstObjParams("it", "ItInst", "PredOp", \
7798205SAli.Saidi@ARM.com            { "code" : ";",
7808908Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest }, [])
7817408Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(itIop)
7827408Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(itIop)
7837408Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(itIop)
7847409Sgblack@eecs.umich.edu    unknownCode = '''
78510474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, true);
7867409Sgblack@eecs.umich.edu    '''
7877409Sgblack@eecs.umich.edu    unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
7887409Sgblack@eecs.umich.edu                               { "code": unknownCode,
7897409Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest })
7907409Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(unknownIop)
7917409Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(unknownIop)
7927409Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(unknownIop)
7937254Sgblack@eecs.umich.edu
7947254Sgblack@eecs.umich.edu    ubfxCode = '''
7957254Sgblack@eecs.umich.edu        Dest = bits(Op1, imm2, imm1);
7967254Sgblack@eecs.umich.edu    '''
7977254Sgblack@eecs.umich.edu    ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
7987254Sgblack@eecs.umich.edu                            { "code": ubfxCode,
7997254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
8007254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
8017254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
8027254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ubfxIop)
8037254Sgblack@eecs.umich.edu
8047254Sgblack@eecs.umich.edu    sbfxCode = '''
8057254Sgblack@eecs.umich.edu        int32_t resTemp = bits(Op1, imm2, imm1);
8067254Sgblack@eecs.umich.edu        Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
8077254Sgblack@eecs.umich.edu    '''
8087254Sgblack@eecs.umich.edu    sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
8097254Sgblack@eecs.umich.edu                            { "code": sbfxCode,
8107254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
8117254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
8127254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
8137254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sbfxIop)
8147257Sgblack@eecs.umich.edu
8157257Sgblack@eecs.umich.edu    bfcCode = '''
8167257Sgblack@eecs.umich.edu        Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
8177257Sgblack@eecs.umich.edu    '''
8187257Sgblack@eecs.umich.edu    bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
8197257Sgblack@eecs.umich.edu                           { "code": bfcCode,
8207257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8217257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfcIop)
8227257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
8237257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfcIop)
8247257Sgblack@eecs.umich.edu
8257257Sgblack@eecs.umich.edu    bfiCode = '''
8267257Sgblack@eecs.umich.edu        uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
8277257Sgblack@eecs.umich.edu        Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
8287257Sgblack@eecs.umich.edu    '''
8297257Sgblack@eecs.umich.edu    bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
8307257Sgblack@eecs.umich.edu                           { "code": bfiCode,
8317257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8327257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfiIop)
8337257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
8347257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfiIop)
8357262Sgblack@eecs.umich.edu
8368868SMatt.Horsnell@arm.com    mrc14code = '''
83712106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
83812106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, op1)).index();
83911939Snikos.nikoleris@arm.com    bool can_read, undefined;
84011939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
84111939Snikos.nikoleris@arm.com    if (!can_read || undefined) {
84210474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
84310474Sandreas.hansson@arm.com                                                      mnemonic);
84410037SARM gem5 Developers    }
84510037SARM gem5 Developers    if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
84610037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
84710474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
84810474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8498868SMatt.Horsnell@arm.com    }
8508868SMatt.Horsnell@arm.com    Dest = MiscOp1;
8518868SMatt.Horsnell@arm.com    '''
8528868SMatt.Horsnell@arm.com
85310037SARM gem5 Developers    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
8548868SMatt.Horsnell@arm.com                             { "code": mrc14code,
8558868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest }, [])
85610037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mrc14Iop)
85710037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
8588868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mrc14Iop)
8598868SMatt.Horsnell@arm.com
8608868SMatt.Horsnell@arm.com
8618868SMatt.Horsnell@arm.com    mcr14code = '''
86212106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
86312106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, dest)).index();
86411939Snikos.nikoleris@arm.com    bool can_write, undefined;
86511939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
86611939Snikos.nikoleris@arm.com    if (undefined || !can_write) {
86710474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
86810474Sandreas.hansson@arm.com                                                      mnemonic);
86910037SARM gem5 Developers    }
87010037SARM gem5 Developers    if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
87110037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
87210474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
87310474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8748868SMatt.Horsnell@arm.com    }
8758868SMatt.Horsnell@arm.com    MiscDest = Op1;
8768868SMatt.Horsnell@arm.com    '''
87710037SARM gem5 Developers    mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
8788868SMatt.Horsnell@arm.com                             { "code": mcr14code,
8798868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest },
8808868SMatt.Horsnell@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
88110037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mcr14Iop)
88210037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
8838868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mcr14Iop)
8848868SMatt.Horsnell@arm.com
88510037SARM gem5 Developers    mrc15code = '''
88612499Sgiacomo.travaglini@arm.com    int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
88710037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
88812106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
88912106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
89010037SARM gem5 Developers    bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
89110037SARM gem5 Developers                                     Hcptr, imm);
89211939Snikos.nikoleris@arm.com    bool can_read, undefined;
89311939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
89410037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
89510037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
89610037SARM gem5 Developers    // IS accessable.
89711939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
89811939Snikos.nikoleris@arm.com                                    !inSecureState(Scr, Cpsr)))) {
89910474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
90010474Sandreas.hansson@arm.com                                                      mnemonic);
9018782Sgblack@eecs.umich.edu    }
90210037SARM gem5 Developers    if (hypTrap) {
90310474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
90410474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
90510037SARM gem5 Developers    }
90610037SARM gem5 Developers    Dest = MiscNsBankedOp1;
9077347SAli.Saidi@ARM.com    '''
9087347SAli.Saidi@ARM.com
90910418Sandreas.hansson@arm.com    mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp",
9107347SAli.Saidi@ARM.com                             { "code": mrc15code,
9117262Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
91210418Sandreas.hansson@arm.com    header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
91310418Sandreas.hansson@arm.com    decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
9147262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrc15Iop)
9157262Sgblack@eecs.umich.edu
9167347SAli.Saidi@ARM.com
9177347SAli.Saidi@ARM.com    mcr15code = '''
91812499Sgiacomo.travaglini@arm.com    int preFlatDest = snsBankedIndex(dest, xc->tcBase());
91910037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
92012106SRekai.GonzalezAlberquilla@arm.com                       xc->tcBase()->flattenRegId(RegId(MiscRegClass,
92112106SRekai.GonzalezAlberquilla@arm.com                                                  preFlatDest)).index();
92210037SARM gem5 Developers    bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
92310037SARM gem5 Developers                                      Hcptr, imm);
92411939Snikos.nikoleris@arm.com    bool can_write, undefined;
92511939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
92610037SARM gem5 Developers
92710037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
92810037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
92910037SARM gem5 Developers    // IS accessable.
93011939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
93111939Snikos.nikoleris@arm.com                                      !inSecureState(Scr, Cpsr)))) {
93210474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
93310474Sandreas.hansson@arm.com                                                      mnemonic);
9348782Sgblack@eecs.umich.edu    }
93510037SARM gem5 Developers    if (hypTrap) {
93610474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
93710474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
93810037SARM gem5 Developers    }
93910037SARM gem5 Developers    MiscNsBankedDest = Op1;
9407347SAli.Saidi@ARM.com    '''
94110418Sandreas.hansson@arm.com    mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
9427347SAli.Saidi@ARM.com                             { "code": mcr15code,
9437599Sminkyu.jeong@arm.com                               "predicate_test": predicateTest },
9447599Sminkyu.jeong@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
94510418Sandreas.hansson@arm.com    header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
94610418Sandreas.hansson@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
9477262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mcr15Iop)
9487283Sgblack@eecs.umich.edu
9497420Sgblack@eecs.umich.edu
95010037SARM gem5 Developers    mrrc15code = '''
95112499Sgiacomo.travaglini@arm.com    int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
95210037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
95312106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
95412106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
95510037SARM gem5 Developers    bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
95611939Snikos.nikoleris@arm.com    bool can_read, undefined;
95711939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
95810037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
95910037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
96010037SARM gem5 Developers    // IS accessable.
96111939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
96211939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
96310474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
96410474Sandreas.hansson@arm.com                                                      mnemonic);
96510037SARM gem5 Developers    }
96610037SARM gem5 Developers    if (hypTrap) {
96710474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
96810474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
96910037SARM gem5 Developers    }
97010037SARM gem5 Developers    Dest = bits(MiscNsBankedOp164, 63, 32);
97110037SARM gem5 Developers    Dest2 = bits(MiscNsBankedOp164, 31, 0);
97210037SARM gem5 Developers    '''
97310037SARM gem5 Developers    mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
97410037SARM gem5 Developers                              { "code": mrrc15code,
97510037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
97610037SARM gem5 Developers    header_output += MrrcOpDeclare.subst(mrrc15Iop)
97710037SARM gem5 Developers    decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
97810037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrrc15Iop)
97910037SARM gem5 Developers
98010037SARM gem5 Developers
98110037SARM gem5 Developers    mcrr15code = '''
98212499Sgiacomo.travaglini@arm.com    int preFlatDest = snsBankedIndex(dest, xc->tcBase());
98310037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
98412106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
98512106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatDest)).index();
98610037SARM gem5 Developers    bool hypTrap  = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
98711939Snikos.nikoleris@arm.com    bool can_write, undefined;
98811939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
98910037SARM gem5 Developers
99010037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
99110037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
99210037SARM gem5 Developers    // IS accessable.
99311939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
99411939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
99510474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
99610474Sandreas.hansson@arm.com                                                      mnemonic);
99710037SARM gem5 Developers    }
99810037SARM gem5 Developers    if (hypTrap) {
99910474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
100010474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
100110037SARM gem5 Developers    }
100210037SARM gem5 Developers    MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
100310037SARM gem5 Developers    '''
100410037SARM gem5 Developers    mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
100510037SARM gem5 Developers                              { "code": mcrr15code,
100610037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
100710037SARM gem5 Developers    header_output += McrrOpDeclare.subst(mcrr15Iop)
100810037SARM gem5 Developers    decoder_output += McrrOpConstructor.subst(mcrr15Iop)
100910037SARM gem5 Developers    exec_output += PredOpExecute.subst(mcrr15Iop)
101010037SARM gem5 Developers
10117420Sgblack@eecs.umich.edu
10127283Sgblack@eecs.umich.edu    enterxCode = '''
10137797Sgblack@eecs.umich.edu        NextThumb = true;
10147797Sgblack@eecs.umich.edu        NextJazelle = true;
10157283Sgblack@eecs.umich.edu    '''
10167283Sgblack@eecs.umich.edu    enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
10177283Sgblack@eecs.umich.edu                              { "code": enterxCode,
10187283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
10197283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(enterxIop)
10207283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(enterxIop)
10217283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(enterxIop)
10227283Sgblack@eecs.umich.edu
10237283Sgblack@eecs.umich.edu    leavexCode = '''
10247797Sgblack@eecs.umich.edu        NextThumb = true;
10257797Sgblack@eecs.umich.edu        NextJazelle = false;
10267283Sgblack@eecs.umich.edu    '''
10277283Sgblack@eecs.umich.edu    leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
10287283Sgblack@eecs.umich.edu                              { "code": leavexCode,
10297283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
10307283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(leavexIop)
10317283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(leavexIop)
10327283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(leavexIop)
10337307Sgblack@eecs.umich.edu
10347307Sgblack@eecs.umich.edu    setendCode = '''
10357307Sgblack@eecs.umich.edu        CPSR cpsr = Cpsr;
10367307Sgblack@eecs.umich.edu        cpsr.e = imm;
10377307Sgblack@eecs.umich.edu        Cpsr = cpsr;
103812498Sgiacomo.travaglini@arm.com        fault = checkSETENDEnabled(xc->tcBase(), cpsr);
10397307Sgblack@eecs.umich.edu    '''
10407307Sgblack@eecs.umich.edu    setendIop = InstObjParams("setend", "Setend", "ImmOp",
10417307Sgblack@eecs.umich.edu                              { "code": setendCode,
10427648SAli.Saidi@ARM.com                                "predicate_test": predicateTest },
10437648SAli.Saidi@ARM.com                              ["IsSerializeAfter","IsNonSpeculative"])
10447307Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(setendIop)
10457307Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(setendIop)
10467307Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(setendIop)
10477315Sgblack@eecs.umich.edu
10487603SGene.Wu@arm.com    clrexCode = '''
10498209SAli.Saidi@ARM.com        LLSCLock = 0;
10507603SGene.Wu@arm.com    '''
10517603SGene.Wu@arm.com    clrexIop = InstObjParams("clrex", "Clrex","PredOp",
10527603SGene.Wu@arm.com                             { "code": clrexCode,
10537603SGene.Wu@arm.com                               "predicate_test": predicateTest },[])
10548209SAli.Saidi@ARM.com    header_output += BasicDeclare.subst(clrexIop)
10557603SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(clrexIop)
10567603SGene.Wu@arm.com    exec_output += PredOpExecute.subst(clrexIop)
10577603SGene.Wu@arm.com
105812358Snikos.nikoleris@arm.com    McrDcCheckCode = '''
105912499Sgiacomo.travaglini@arm.com        int preFlatDest = snsBankedIndex(dest, xc->tcBase());
106012358Snikos.nikoleris@arm.com        MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
106112358Snikos.nikoleris@arm.com            RegId(MiscRegClass, preFlatDest)).index();
106212358Snikos.nikoleris@arm.com        bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
106312358Snikos.nikoleris@arm.com                                          Hcptr, imm);
106412358Snikos.nikoleris@arm.com        bool can_write, undefined;
106512358Snikos.nikoleris@arm.com        std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
106612358Snikos.nikoleris@arm.com
106712358Snikos.nikoleris@arm.com        // if we're in non secure PL1 mode then we can trap regardless
106812358Snikos.nikoleris@arm.com        // of whether the register is accessible, in other modes we
106912358Snikos.nikoleris@arm.com        // trap if only if the register IS accessible.
107012358Snikos.nikoleris@arm.com        if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
107112358Snikos.nikoleris@arm.com                                         !inSecureState(Scr, Cpsr)))) {
107212358Snikos.nikoleris@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
107312358Snikos.nikoleris@arm.com                                                          mnemonic);
107412358Snikos.nikoleris@arm.com        }
107512358Snikos.nikoleris@arm.com        if (hypTrap) {
107612358Snikos.nikoleris@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
107712358Snikos.nikoleris@arm.com                                                    EC_TRAPPED_CP15_MCR_MRC);
107812358Snikos.nikoleris@arm.com        }
107912358Snikos.nikoleris@arm.com    '''
108012358Snikos.nikoleris@arm.com
108112358Snikos.nikoleris@arm.com    McrDcimvacCode = '''
108212358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
108312358Snikos.nikoleris@arm.com                                            Request::INVALIDATE |
108412358Snikos.nikoleris@arm.com                                            Request::DST_POC);
108512358Snikos.nikoleris@arm.com        EA = Op1;
108612358Snikos.nikoleris@arm.com    '''
108712504Snikos.nikoleris@arm.com    McrDcimvacIop = InstObjParams("mcr", "McrDcimvac",
108812504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
108912358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
109012358Snikos.nikoleris@arm.com                                   "postacc_code": "",
109112358Snikos.nikoleris@arm.com                                   "ea_code": McrDcimvacCode,
109212358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
109312358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
109412358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop)
109512358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop)
109612358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDcimvacIop) + \
109712358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDcimvacIop) + \
109812358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDcimvacIop)
109912358Snikos.nikoleris@arm.com
110012358Snikos.nikoleris@arm.com    McrDccmvacCode = '''
110112358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
110212358Snikos.nikoleris@arm.com                                            Request::CLEAN |
110312358Snikos.nikoleris@arm.com                                            Request::DST_POC);
110412358Snikos.nikoleris@arm.com        EA = Op1;
110512358Snikos.nikoleris@arm.com    '''
110612504Snikos.nikoleris@arm.com    McrDccmvacIop = InstObjParams("mcr", "McrDccmvac",
110712504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
110812358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
110912358Snikos.nikoleris@arm.com                                   "postacc_code": "",
111012358Snikos.nikoleris@arm.com                                   "ea_code": McrDccmvacCode,
111112358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
111212358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
111312358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop)
111412358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop)
111512358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccmvacIop) + \
111612358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccmvacIop) + \
111712358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccmvacIop)
111812358Snikos.nikoleris@arm.com
111912358Snikos.nikoleris@arm.com    McrDccmvauCode = '''
112012358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
112112358Snikos.nikoleris@arm.com                                            Request::CLEAN |
112212358Snikos.nikoleris@arm.com                                            Request::DST_POU);
112312358Snikos.nikoleris@arm.com        EA = Op1;
112412358Snikos.nikoleris@arm.com    '''
112512504Snikos.nikoleris@arm.com    McrDccmvauIop = InstObjParams("mcr", "McrDccmvau",
112612504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
112712358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
112812358Snikos.nikoleris@arm.com                                   "postacc_code": "",
112912358Snikos.nikoleris@arm.com                                   "ea_code": McrDccmvauCode,
113012358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
113112358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
113212358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop)
113312358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop)
113412358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccmvauIop) + \
113512358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccmvauIop) + \
113612358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccmvauIop)
113712358Snikos.nikoleris@arm.com
113812358Snikos.nikoleris@arm.com    McrDccimvacCode = '''
113912358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
114012358Snikos.nikoleris@arm.com                                            Request::CLEAN |
114112358Snikos.nikoleris@arm.com                                            Request::INVALIDATE |
114212358Snikos.nikoleris@arm.com                                            Request::DST_POC);
114312358Snikos.nikoleris@arm.com        EA = Op1;
114412358Snikos.nikoleris@arm.com    '''
114512504Snikos.nikoleris@arm.com    McrDccimvacIop = InstObjParams("mcr", "McrDccimvac",
114612504Snikos.nikoleris@arm.com                                  "MiscRegRegImmOp",
114712358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
114812358Snikos.nikoleris@arm.com                                   "postacc_code": "",
114912358Snikos.nikoleris@arm.com                                   "ea_code": McrDccimvacCode,
115012358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
115112358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
115212358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
115312358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
115412358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
115512358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccimvacIop) + \
115612358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccimvacIop)
115712358Snikos.nikoleris@arm.com
11587605SGene.Wu@arm.com    isbCode = '''
115910037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
116010037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
116110037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
116210474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
116310037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
116410037SARM gem5 Developers        }
11657605SGene.Wu@arm.com    '''
116610037SARM gem5 Developers    isbIop = InstObjParams("isb", "Isb", "ImmOp",
11677605SGene.Wu@arm.com                             {"code": isbCode,
11688068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
116912488Sgiacomo.travaglini@arm.com                                ['IsSquashAfter'])
117010037SARM gem5 Developers    header_output += ImmOpDeclare.subst(isbIop)
117110037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(isbIop)
11727605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(isbIop)
11737605SGene.Wu@arm.com
11747605SGene.Wu@arm.com    dsbCode = '''
117510037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
117610037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr,
117710037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
117810474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
117910037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
118010037SARM gem5 Developers        }
11817605SGene.Wu@arm.com    '''
118210037SARM gem5 Developers    dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
11837605SGene.Wu@arm.com                             {"code": dsbCode,
11848068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
118512261Sgiacomo.travaglini@arm.com                              ['IsMemBarrier', 'IsSerializeAfter'])
118610037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dsbIop)
118710037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dsbIop)
11887605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dsbIop)
11897605SGene.Wu@arm.com
11907605SGene.Wu@arm.com    dmbCode = '''
119110037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
119210037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr,
119310037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
119410474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
119510037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
119610037SARM gem5 Developers        }
11977605SGene.Wu@arm.com    '''
119810037SARM gem5 Developers    dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
11997605SGene.Wu@arm.com                             {"code": dmbCode,
12008068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
12018068SAli.Saidi@ARM.com                               ['IsMemBarrier'])
120210037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dmbIop)
120310037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dmbIop)
12047605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dmbIop)
12057605SGene.Wu@arm.com
12067613SGene.Wu@arm.com    dbgCode = '''
12077613SGene.Wu@arm.com    '''
12087613SGene.Wu@arm.com    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
12097613SGene.Wu@arm.com                             {"code": dbgCode,
12107613SGene.Wu@arm.com                               "predicate_test": predicateTest})
12117613SGene.Wu@arm.com    header_output += BasicDeclare.subst(dbgIop)
12127613SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(dbgIop)
12137613SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dbgIop)
12147613SGene.Wu@arm.com
12157315Sgblack@eecs.umich.edu    cpsCode = '''
12167315Sgblack@eecs.umich.edu    uint32_t mode = bits(imm, 4, 0);
12177315Sgblack@eecs.umich.edu    uint32_t f = bits(imm, 5);
12187315Sgblack@eecs.umich.edu    uint32_t i = bits(imm, 6);
12197315Sgblack@eecs.umich.edu    uint32_t a = bits(imm, 7);
12207315Sgblack@eecs.umich.edu    bool setMode = bits(imm, 8);
12217315Sgblack@eecs.umich.edu    bool enable = bits(imm, 9);
12227315Sgblack@eecs.umich.edu    CPSR cpsr = Cpsr;
12237400SAli.Saidi@ARM.com    SCTLR sctlr = Sctlr;
12247315Sgblack@eecs.umich.edu    if (cpsr.mode != MODE_USER) {
12257315Sgblack@eecs.umich.edu        if (enable) {
12267315Sgblack@eecs.umich.edu            if (f) cpsr.f = 0;
12277315Sgblack@eecs.umich.edu            if (i) cpsr.i = 0;
12287315Sgblack@eecs.umich.edu            if (a) cpsr.a = 0;
12297315Sgblack@eecs.umich.edu        } else {
12307400SAli.Saidi@ARM.com            if (f && !sctlr.nmfi) cpsr.f = 1;
12317315Sgblack@eecs.umich.edu            if (i) cpsr.i = 1;
12327315Sgblack@eecs.umich.edu            if (a) cpsr.a = 1;
12337315Sgblack@eecs.umich.edu        }
12347315Sgblack@eecs.umich.edu        if (setMode) {
12357315Sgblack@eecs.umich.edu            cpsr.mode = mode;
12367315Sgblack@eecs.umich.edu        }
12377315Sgblack@eecs.umich.edu    }
12387315Sgblack@eecs.umich.edu    Cpsr = cpsr;
12397315Sgblack@eecs.umich.edu    '''
12407315Sgblack@eecs.umich.edu    cpsIop = InstObjParams("cps", "Cps", "ImmOp",
12417315Sgblack@eecs.umich.edu                           { "code": cpsCode,
12427599Sminkyu.jeong@arm.com                             "predicate_test": predicateTest },
12437599Sminkyu.jeong@arm.com                           ["IsSerializeAfter","IsNonSpeculative"])
12447315Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(cpsIop)
12457315Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(cpsIop)
12467315Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(cpsIop)
12477202Sgblack@eecs.umich.edu}};
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