misc.isa revision 12403
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*-
27199Sgblack@eecs.umich.edu
311939Snikos.nikoleris@arm.com// Copyright (c) 2010-2013,2017 ARM Limited
47199Sgblack@eecs.umich.edu// All rights reserved
57199Sgblack@eecs.umich.edu//
67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107199Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147199Sgblack@eecs.umich.edu//
157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
247199Sgblack@eecs.umich.edu// this software without specific prior written permission.
257199Sgblack@eecs.umich.edu//
267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
377199Sgblack@eecs.umich.edu//
387199Sgblack@eecs.umich.edu// Authors: Gabe Black
397199Sgblack@eecs.umich.edu
407199Sgblack@eecs.umich.edulet {{
417199Sgblack@eecs.umich.edu
427199Sgblack@eecs.umich.edu    svcCode = '''
4310474Sandreas.hansson@arm.com    fault = std::make_shared<SupervisorCall>(machInst, imm);
4410037SARM gem5 Developers    '''
4510037SARM gem5 Developers
4610037SARM gem5 Developers    svcIop = InstObjParams("svc", "Svc", "ImmOp",
4710037SARM gem5 Developers                           { "code": svcCode,
4810037SARM gem5 Developers                             "predicate_test": predicateTest },
4910037SARM gem5 Developers                           ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
5010037SARM gem5 Developers    header_output = ImmOpDeclare.subst(svcIop)
5110037SARM gem5 Developers    decoder_output = ImmOpConstructor.subst(svcIop)
5210037SARM gem5 Developers    exec_output = PredOpExecute.subst(svcIop)
5310037SARM gem5 Developers
5410037SARM gem5 Developers    smcCode = '''
5510037SARM gem5 Developers    HCR  hcr  = Hcr;
5610037SARM gem5 Developers    CPSR cpsr = Cpsr;
5710037SARM gem5 Developers    SCR  scr  = Scr;
5810037SARM gem5 Developers
5910037SARM gem5 Developers    if ((cpsr.mode != MODE_USER) && FullSystem) {
6010037SARM gem5 Developers        if (ArmSystem::haveVirtualization(xc->tcBase()) &&
6110037SARM gem5 Developers            !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
6210474Sandreas.hansson@arm.com            fault = std::make_shared<HypervisorTrap>(machInst, 0,
6310474Sandreas.hansson@arm.com                                                     EC_SMC_TO_HYP);
6410037SARM gem5 Developers        } else {
6510037SARM gem5 Developers            if (scr.scd) {
6610037SARM gem5 Developers                fault = disabledFault();
6710037SARM gem5 Developers            } else {
6810474Sandreas.hansson@arm.com                fault = std::make_shared<SecureMonitorCall>(machInst);
6910037SARM gem5 Developers            }
7010037SARM gem5 Developers        }
718782Sgblack@eecs.umich.edu    } else {
7210037SARM gem5 Developers        fault = disabledFault();
738782Sgblack@eecs.umich.edu    }
747199Sgblack@eecs.umich.edu    '''
757199Sgblack@eecs.umich.edu
7610037SARM gem5 Developers    smcIop = InstObjParams("smc", "Smc", "PredOp",
7710037SARM gem5 Developers                           { "code": smcCode,
788628SAli.Saidi@ARM.com                             "predicate_test": predicateTest },
7910037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
8010037SARM gem5 Developers    header_output += BasicDeclare.subst(smcIop)
8110037SARM gem5 Developers    decoder_output += BasicConstructor.subst(smcIop)
8210037SARM gem5 Developers    exec_output += PredOpExecute.subst(smcIop)
8310037SARM gem5 Developers
8410037SARM gem5 Developers    hvcCode = '''
8510037SARM gem5 Developers    CPSR cpsr = Cpsr;
8610037SARM gem5 Developers    SCR  scr  = Scr;
8710037SARM gem5 Developers
8810037SARM gem5 Developers    // Filter out the various cases where this instruction isn't defined
8910037SARM gem5 Developers    if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
9010037SARM gem5 Developers        (cpsr.mode == MODE_USER) ||
9110037SARM gem5 Developers        (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
9210037SARM gem5 Developers        fault = disabledFault();
9310037SARM gem5 Developers    } else {
9410474Sandreas.hansson@arm.com        fault = std::make_shared<HypervisorCall>(machInst, imm);
9510037SARM gem5 Developers    }
9610037SARM gem5 Developers    '''
9710037SARM gem5 Developers
9810037SARM gem5 Developers    hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
9910037SARM gem5 Developers                           { "code": hvcCode,
10010037SARM gem5 Developers                             "predicate_test": predicateTest },
10110037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
10210037SARM gem5 Developers    header_output += ImmOpDeclare.subst(hvcIop)
10310037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(hvcIop)
10410037SARM gem5 Developers    exec_output += PredOpExecute.subst(hvcIop)
10510037SARM gem5 Developers
10610037SARM gem5 Developers    eretCode = '''
10710037SARM gem5 Developers        SCTLR sctlr   = Sctlr;
10810037SARM gem5 Developers        CPSR old_cpsr = Cpsr;
10910037SARM gem5 Developers        old_cpsr.nz   = CondCodesNZ;
11010037SARM gem5 Developers        old_cpsr.c    = CondCodesC;
11110037SARM gem5 Developers        old_cpsr.v    = CondCodesV;
11210037SARM gem5 Developers        old_cpsr.ge   = CondCodesGE;
11310037SARM gem5 Developers
11410037SARM gem5 Developers        CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
11510037SARM gem5 Developers                            true, sctlr.nmfi, xc->tcBase());
11610037SARM gem5 Developers        Cpsr        = ~CondCodesMask & new_cpsr;
11710037SARM gem5 Developers        CondCodesNZ = new_cpsr.nz;
11810037SARM gem5 Developers        CondCodesC  = new_cpsr.c;
11910037SARM gem5 Developers        CondCodesV  = new_cpsr.v;
12010037SARM gem5 Developers        CondCodesGE = new_cpsr.ge;
12110037SARM gem5 Developers
12210037SARM gem5 Developers        NextThumb = (new_cpsr).t;
12310037SARM gem5 Developers                    NextJazelle = (new_cpsr).j;
12410037SARM gem5 Developers                    NextItState = (((new_cpsr).it2 << 2) & 0xFC)
12510037SARM gem5 Developers                        | ((new_cpsr).it1 & 0x3);
12610037SARM gem5 Developers
12710037SARM gem5 Developers        NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
12810037SARM gem5 Developers    '''
12910037SARM gem5 Developers
13010037SARM gem5 Developers    eretIop = InstObjParams("eret", "Eret", "PredOp",
13110037SARM gem5 Developers                           { "code": eretCode,
13210037SARM gem5 Developers                             "predicate_test": predicateTest },
13311355Smitch.hayenga@arm.com                           ["IsNonSpeculative", "IsSerializeAfter",
13411355Smitch.hayenga@arm.com                            "IsSquashAfter"])
13510037SARM gem5 Developers    header_output += BasicDeclare.subst(eretIop)
13610037SARM gem5 Developers    decoder_output += BasicConstructor.subst(eretIop)
13710037SARM gem5 Developers    exec_output += PredOpExecute.subst(eretIop)
13810037SARM gem5 Developers
13912258Sgiacomo.travaglini@arm.com    crcCode = '''
14012258Sgiacomo.travaglini@arm.com    constexpr uint8_t size_bytes = %(sz)d;
14112258Sgiacomo.travaglini@arm.com    constexpr uint32_t poly = %(polynom)s;
14210037SARM gem5 Developers
14312258Sgiacomo.travaglini@arm.com    uint32_t data = htole(Op2);
14412258Sgiacomo.travaglini@arm.com    auto data_buffer = reinterpret_cast<uint8_t*>(&data);
14512258Sgiacomo.travaglini@arm.com
14612258Sgiacomo.travaglini@arm.com    Dest = crc32<poly>(
14712258Sgiacomo.travaglini@arm.com        data_buffer,   /* Message Register */
14812258Sgiacomo.travaglini@arm.com        Op1,           /* Initial Value  of the CRC */
14912258Sgiacomo.travaglini@arm.com        size_bytes     /* Size of the original Message */
15012258Sgiacomo.travaglini@arm.com    );
15112258Sgiacomo.travaglini@arm.com    '''
15212258Sgiacomo.travaglini@arm.com
15312258Sgiacomo.travaglini@arm.com    def crc32Emit(mnem, implCode, castagnoli, size):
15412258Sgiacomo.travaglini@arm.com        global header_output, decoder_output, exec_output
15512258Sgiacomo.travaglini@arm.com
15612258Sgiacomo.travaglini@arm.com        if castagnoli:
15712258Sgiacomo.travaglini@arm.com            # crc32c instructions
15812258Sgiacomo.travaglini@arm.com            poly = "0x1EDC6F41"
15912258Sgiacomo.travaglini@arm.com        else:
16012258Sgiacomo.travaglini@arm.com            # crc32 instructions
16112258Sgiacomo.travaglini@arm.com            poly = "0x04C11DB7"
16212258Sgiacomo.travaglini@arm.com
16312258Sgiacomo.travaglini@arm.com        data = {'sz' : size, 'polynom': poly}
16412258Sgiacomo.travaglini@arm.com
16512258Sgiacomo.travaglini@arm.com        instCode = implCode % data
16612258Sgiacomo.travaglini@arm.com
16712258Sgiacomo.travaglini@arm.com        crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
16812258Sgiacomo.travaglini@arm.com                               { "code": instCode,
16912258Sgiacomo.travaglini@arm.com                                 "predicate_test": predicateTest }, [])
17012258Sgiacomo.travaglini@arm.com        header_output += RegRegRegOpDeclare.subst(crcIop)
17112258Sgiacomo.travaglini@arm.com        decoder_output += RegRegRegOpConstructor.subst(crcIop)
17212258Sgiacomo.travaglini@arm.com        exec_output += PredOpExecute.subst(crcIop)
17312258Sgiacomo.travaglini@arm.com
17412258Sgiacomo.travaglini@arm.com    crc32Emit("crc32b", crcCode, False, 1);
17512258Sgiacomo.travaglini@arm.com    crc32Emit("crc32h", crcCode, False, 2);
17612258Sgiacomo.travaglini@arm.com    crc32Emit("crc32w", crcCode, False, 4);
17712258Sgiacomo.travaglini@arm.com    crc32Emit("crc32cb", crcCode, True, 1);
17812258Sgiacomo.travaglini@arm.com    crc32Emit("crc32ch", crcCode, True, 2);
17912258Sgiacomo.travaglini@arm.com    crc32Emit("crc32cw", crcCode, True, 4);
1807199Sgblack@eecs.umich.edu
1817199Sgblack@eecs.umich.edu}};
1827202Sgblack@eecs.umich.edu
1837202Sgblack@eecs.umich.edulet {{
1847202Sgblack@eecs.umich.edu
1857202Sgblack@eecs.umich.edu    header_output = decoder_output = exec_output = ""
1867202Sgblack@eecs.umich.edu
1878301SAli.Saidi@ARM.com    mrsCpsrCode = '''
1888303SAli.Saidi@ARM.com        CPSR cpsr = Cpsr;
1898303SAli.Saidi@ARM.com        cpsr.nz = CondCodesNZ;
1908303SAli.Saidi@ARM.com        cpsr.c = CondCodesC;
1918303SAli.Saidi@ARM.com        cpsr.v = CondCodesV;
1928303SAli.Saidi@ARM.com        cpsr.ge = CondCodesGE;
1938303SAli.Saidi@ARM.com        Dest = cpsr & 0xF8FF03DF
1948301SAli.Saidi@ARM.com    '''
1958301SAli.Saidi@ARM.com
1967202Sgblack@eecs.umich.edu    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
1977202Sgblack@eecs.umich.edu                               { "code": mrsCpsrCode,
1987599Sminkyu.jeong@arm.com                                 "predicate_test": condPredicateTest },
1997783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
2007202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsCpsrIop)
2017202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsCpsrIop)
2027202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsCpsrIop)
2037202Sgblack@eecs.umich.edu
2047202Sgblack@eecs.umich.edu    mrsSpsrCode = "Dest = Spsr"
2057202Sgblack@eecs.umich.edu    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
2067202Sgblack@eecs.umich.edu                               { "code": mrsSpsrCode,
2077599Sminkyu.jeong@arm.com                                 "predicate_test": predicateTest },
2087783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
2097202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsSpsrIop)
2107202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsSpsrIop)
2117202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsSpsrIop)
2127202Sgblack@eecs.umich.edu
21310037SARM gem5 Developers    mrsBankedRegCode = '''
21410037SARM gem5 Developers        bool isIntReg;
21510037SARM gem5 Developers        int  regIdx;
21610037SARM gem5 Developers
21710037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
21810037SARM gem5 Developers            if (isIntReg) {
21910037SARM gem5 Developers                Dest = DecodedBankedIntReg;
22010037SARM gem5 Developers            } else {
22110037SARM gem5 Developers                Dest = xc->readMiscReg(regIdx);
22210037SARM gem5 Developers            }
22310037SARM gem5 Developers        } else {
22410474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
22510474Sandreas.hansson@arm.com                                                          mnemonic);
22610037SARM gem5 Developers        }
22710037SARM gem5 Developers    '''
22810037SARM gem5 Developers    mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
22910037SARM gem5 Developers                                    { "code": mrsBankedRegCode,
23010037SARM gem5 Developers                                      "predicate_test": predicateTest },
23110037SARM gem5 Developers                                    ["IsSerializeBefore"])
23210037SARM gem5 Developers    header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
23310037SARM gem5 Developers    decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
23410037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrsBankedRegIop)
23510037SARM gem5 Developers
23610037SARM gem5 Developers    msrBankedRegCode = '''
23710037SARM gem5 Developers        bool isIntReg;
23810037SARM gem5 Developers        int  regIdx;
23910037SARM gem5 Developers
24010037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
24110037SARM gem5 Developers            if (isIntReg) {
24210037SARM gem5 Developers                // This is a bit nasty, you would have thought that
24310037SARM gem5 Developers                // DecodedBankedIntReg wouldn't be written to unless the
24410037SARM gem5 Developers                // conditions on the IF statements above are met, however if
24510037SARM gem5 Developers                // you look at the generated C code you'll find that they are.
24610037SARM gem5 Developers                // However this is safe as DecodedBankedIntReg (which is used
24710037SARM gem5 Developers                // in operands.isa to get the index of DecodedBankedIntReg)
24810037SARM gem5 Developers                // will return INTREG_DUMMY if its not a valid integer
24910037SARM gem5 Developers                // register, so redirecting the write to somewhere we don't
25010037SARM gem5 Developers                // care about.
25110037SARM gem5 Developers                DecodedBankedIntReg = Op1;
25210037SARM gem5 Developers            } else {
25310037SARM gem5 Developers                xc->setMiscReg(regIdx, Op1);
25410037SARM gem5 Developers            }
25510037SARM gem5 Developers        } else {
25610474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
25710474Sandreas.hansson@arm.com                                                          mnemonic);
25810037SARM gem5 Developers        }
25910037SARM gem5 Developers    '''
26010037SARM gem5 Developers    msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
26110037SARM gem5 Developers                                    { "code": msrBankedRegCode,
26210037SARM gem5 Developers                                      "predicate_test": predicateTest },
26310501Sakash.bagdia@ARM.com                                    ["IsSerializeAfter", "IsNonSpeculative"])
26410037SARM gem5 Developers    header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
26510037SARM gem5 Developers    decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
26610037SARM gem5 Developers    exec_output += PredOpExecute.subst(msrBankedRegIop)
26710037SARM gem5 Developers
2687202Sgblack@eecs.umich.edu    msrCpsrRegCode = '''
2697400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
2708303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
2718303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
2728303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
2738303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
2748303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
2758303SAli.Saidi@ARM.com
2768303SAli.Saidi@ARM.com        CPSR new_cpsr =
27710037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
27810037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
2798303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
2808303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
2818303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
2828303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
2838303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
2847202Sgblack@eecs.umich.edu    '''
2857202Sgblack@eecs.umich.edu    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
2867202Sgblack@eecs.umich.edu                                  { "code": msrCpsrRegCode,
2877599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
2887599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
2897202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
2907202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
2917202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrRegIop)
2927202Sgblack@eecs.umich.edu
2937202Sgblack@eecs.umich.edu    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
2947202Sgblack@eecs.umich.edu    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
2957202Sgblack@eecs.umich.edu                                  { "code": msrSpsrRegCode,
2967599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
2977599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
2987202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
2997202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
3007202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrRegIop)
3017202Sgblack@eecs.umich.edu
3027202Sgblack@eecs.umich.edu    msrCpsrImmCode = '''
3037400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
3048303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
3058303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
3068303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
3078303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
3088303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
3098303SAli.Saidi@ARM.com        CPSR new_cpsr =
31010037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
31110037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
3128303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
3138303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
3148303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
3158303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
3168303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
3177202Sgblack@eecs.umich.edu    '''
3187202Sgblack@eecs.umich.edu    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
3197202Sgblack@eecs.umich.edu                                  { "code": msrCpsrImmCode,
3207599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
3217599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3227202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
3237202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
3247202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrImmIop)
3257202Sgblack@eecs.umich.edu
3267202Sgblack@eecs.umich.edu    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
3277202Sgblack@eecs.umich.edu    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
3287202Sgblack@eecs.umich.edu                                  { "code": msrSpsrImmCode,
3297599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
3307599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
3317202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
3327202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
3337202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrImmIop)
3347209Sgblack@eecs.umich.edu
3357209Sgblack@eecs.umich.edu    revCode = '''
3367209Sgblack@eecs.umich.edu    uint32_t val = Op1;
3377209Sgblack@eecs.umich.edu    Dest = swap_byte(val);
3387209Sgblack@eecs.umich.edu    '''
3397261Sgblack@eecs.umich.edu    revIop = InstObjParams("rev", "Rev", "RegRegOp",
3407209Sgblack@eecs.umich.edu                           { "code": revCode,
3417209Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
3427261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revIop)
3437261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revIop)
3447209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revIop)
3457209Sgblack@eecs.umich.edu
3467209Sgblack@eecs.umich.edu    rev16Code = '''
3477209Sgblack@eecs.umich.edu    uint32_t val = Op1;
3487209Sgblack@eecs.umich.edu    Dest = (bits(val, 15, 8) << 0) |
3497209Sgblack@eecs.umich.edu           (bits(val, 7, 0) << 8) |
3507209Sgblack@eecs.umich.edu           (bits(val, 31, 24) << 16) |
3517209Sgblack@eecs.umich.edu           (bits(val, 23, 16) << 24);
3527209Sgblack@eecs.umich.edu    '''
3537261Sgblack@eecs.umich.edu    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
3547209Sgblack@eecs.umich.edu                             { "code": rev16Code,
3557209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
3567261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rev16Iop)
3577261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rev16Iop)
3587209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rev16Iop)
3597209Sgblack@eecs.umich.edu
3607209Sgblack@eecs.umich.edu    revshCode = '''
3617209Sgblack@eecs.umich.edu    uint16_t val = Op1;
3627209Sgblack@eecs.umich.edu    Dest = sext<16>(swap_byte(val));
3637209Sgblack@eecs.umich.edu    '''
3647261Sgblack@eecs.umich.edu    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
3657209Sgblack@eecs.umich.edu                             { "code": revshCode,
3667209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
3677261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revshIop)
3687261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revshIop)
3697209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revshIop)
3707226Sgblack@eecs.umich.edu
3717249Sgblack@eecs.umich.edu    rbitCode = '''
37212227Sgiacomo.travaglini@arm.com    Dest = reverseBits(Op1);
3737249Sgblack@eecs.umich.edu    '''
3747261Sgblack@eecs.umich.edu    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
3757249Sgblack@eecs.umich.edu                            { "code": rbitCode,
3767249Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
3777261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rbitIop)
3787261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rbitIop)
3797249Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rbitIop)
3807249Sgblack@eecs.umich.edu
3817251Sgblack@eecs.umich.edu    clzCode = '''
3827251Sgblack@eecs.umich.edu        Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
3837251Sgblack@eecs.umich.edu    '''
3847261Sgblack@eecs.umich.edu    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
3857251Sgblack@eecs.umich.edu                           { "code": clzCode,
3867251Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
3877261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(clzIop)
3887261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(clzIop)
3897251Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(clzIop)
3907251Sgblack@eecs.umich.edu
3917226Sgblack@eecs.umich.edu    ssatCode = '''
3927226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
3937226Sgblack@eecs.umich.edu        int32_t res;
3947232Sgblack@eecs.umich.edu        if (satInt(res, operand, imm))
3958302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
3967226Sgblack@eecs.umich.edu        Dest = res;
3977226Sgblack@eecs.umich.edu    '''
3987232Sgblack@eecs.umich.edu    ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
3997226Sgblack@eecs.umich.edu                            { "code": ssatCode,
4008304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(ssatCode) }, [])
4017232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
4027232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
4037226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssatIop)
4047226Sgblack@eecs.umich.edu
4057226Sgblack@eecs.umich.edu    usatCode = '''
4067226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
4077226Sgblack@eecs.umich.edu        int32_t res;
4087232Sgblack@eecs.umich.edu        if (uSatInt(res, operand, imm))
4098302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4107226Sgblack@eecs.umich.edu        Dest = res;
4117226Sgblack@eecs.umich.edu    '''
4127232Sgblack@eecs.umich.edu    usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
4137226Sgblack@eecs.umich.edu                            { "code": usatCode,
4148304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(usatCode) }, [])
4157232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(usatIop)
4167232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
4177226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usatIop)
4187226Sgblack@eecs.umich.edu
4197226Sgblack@eecs.umich.edu    ssat16Code = '''
4207226Sgblack@eecs.umich.edu        int32_t res;
4217226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
4227226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
4237226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
4247232Sgblack@eecs.umich.edu        if (satInt(res, argLow, imm))
4258302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4267226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
4277232Sgblack@eecs.umich.edu        if (satInt(res, argHigh, imm))
4288302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4297226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4307226Sgblack@eecs.umich.edu        Dest = resTemp;
4317226Sgblack@eecs.umich.edu    '''
4327232Sgblack@eecs.umich.edu    ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
4337226Sgblack@eecs.umich.edu                              { "code": ssat16Code,
4348304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(ssat16Code) }, [])
4357232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(ssat16Iop)
4367232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
4377226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssat16Iop)
4387226Sgblack@eecs.umich.edu
4397226Sgblack@eecs.umich.edu    usat16Code = '''
4407226Sgblack@eecs.umich.edu        int32_t res;
4417226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
4427226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
4437226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
4447232Sgblack@eecs.umich.edu        if (uSatInt(res, argLow, imm))
4458302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4467226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
4477232Sgblack@eecs.umich.edu        if (uSatInt(res, argHigh, imm))
4488302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4497226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4507226Sgblack@eecs.umich.edu        Dest = resTemp;
4517226Sgblack@eecs.umich.edu    '''
4527232Sgblack@eecs.umich.edu    usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
4537226Sgblack@eecs.umich.edu                              { "code": usat16Code,
4548304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(usat16Code) }, [])
4557232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(usat16Iop)
4567232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
4577226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usat16Iop)
4587234Sgblack@eecs.umich.edu
4597234Sgblack@eecs.umich.edu    sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
4607234Sgblack@eecs.umich.edu                            { "code":
4618588Sgblack@eecs.umich.edu                              "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
4627234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
4637234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtbIop)
4647234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
4657234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtbIop)
4667234Sgblack@eecs.umich.edu
4677234Sgblack@eecs.umich.edu    sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
4687234Sgblack@eecs.umich.edu                             { "code":
4697234Sgblack@eecs.umich.edu                               '''
4708588Sgblack@eecs.umich.edu                                   Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
4717234Sgblack@eecs.umich.edu                                          Op1;
4727234Sgblack@eecs.umich.edu                               ''',
4737234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
4747234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
4757234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
4767234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtabIop)
4777234Sgblack@eecs.umich.edu
4787234Sgblack@eecs.umich.edu    sxtb16Code = '''
4797234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
4807234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
4817234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
4827234Sgblack@eecs.umich.edu                sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
4837234Sgblack@eecs.umich.edu    Dest = resTemp;
4847234Sgblack@eecs.umich.edu    '''
4857234Sgblack@eecs.umich.edu    sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
4867234Sgblack@eecs.umich.edu                              { "code": sxtb16Code,
4877234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
4887234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
4897234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
4907234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtb16Iop)
4917234Sgblack@eecs.umich.edu
4927234Sgblack@eecs.umich.edu    sxtab16Code = '''
4937234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
4947234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
4957234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
4967234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
4977234Sgblack@eecs.umich.edu                sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
4987234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
4997234Sgblack@eecs.umich.edu    Dest = resTemp;
5007234Sgblack@eecs.umich.edu    '''
5017234Sgblack@eecs.umich.edu    sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
5027234Sgblack@eecs.umich.edu                               { "code": sxtab16Code,
5037234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
5047234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
5057234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
5067234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtab16Iop)
5077234Sgblack@eecs.umich.edu
5087234Sgblack@eecs.umich.edu    sxthCode = '''
5097234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
5107234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5117234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated);
5127234Sgblack@eecs.umich.edu    '''
5137234Sgblack@eecs.umich.edu    sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
5147234Sgblack@eecs.umich.edu                              { "code": sxthCode,
5157234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5167234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxthIop)
5177234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxthIop)
5187234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxthIop)
5197234Sgblack@eecs.umich.edu
5207234Sgblack@eecs.umich.edu    sxtahCode = '''
5217234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
5227234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5237234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated) + Op1;
5247234Sgblack@eecs.umich.edu    '''
5257234Sgblack@eecs.umich.edu    sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
5267234Sgblack@eecs.umich.edu                             { "code": sxtahCode,
5277234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5287234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
5297234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
5307234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtahIop)
5317234Sgblack@eecs.umich.edu
5327234Sgblack@eecs.umich.edu    uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
5338588Sgblack@eecs.umich.edu                            { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
5347234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
5357234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtbIop)
5367234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
5377234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtbIop)
5387234Sgblack@eecs.umich.edu
5397234Sgblack@eecs.umich.edu    uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
5407234Sgblack@eecs.umich.edu                             { "code":
5418588Sgblack@eecs.umich.edu                               "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
5427234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5437234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
5447234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
5457234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtabIop)
5467234Sgblack@eecs.umich.edu
5477234Sgblack@eecs.umich.edu    uxtb16Code = '''
5487234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5497234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
5507234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5517234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
5527234Sgblack@eecs.umich.edu    Dest = resTemp;
5537234Sgblack@eecs.umich.edu    '''
5547234Sgblack@eecs.umich.edu    uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
5557234Sgblack@eecs.umich.edu                              { "code": uxtb16Code,
5567234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5577234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
5587234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
5597234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtb16Iop)
5607234Sgblack@eecs.umich.edu
5617234Sgblack@eecs.umich.edu    uxtab16Code = '''
5627234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5637234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
5647234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
5657234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5667234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
5677234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
5687234Sgblack@eecs.umich.edu    Dest = resTemp;
5697234Sgblack@eecs.umich.edu    '''
5707234Sgblack@eecs.umich.edu    uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
5717234Sgblack@eecs.umich.edu                               { "code": uxtab16Code,
5727234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
5737234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
5747234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
5757234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtab16Iop)
5767234Sgblack@eecs.umich.edu
5777234Sgblack@eecs.umich.edu    uxthCode = '''
5787234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
5797234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5807234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated;
5817234Sgblack@eecs.umich.edu    '''
5827234Sgblack@eecs.umich.edu    uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
5837234Sgblack@eecs.umich.edu                              { "code": uxthCode,
5847234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5857234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxthIop)
5867234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxthIop)
5877234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxthIop)
5887234Sgblack@eecs.umich.edu
5897234Sgblack@eecs.umich.edu    uxtahCode = '''
5907234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
5917234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5927234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated + Op1;
5937234Sgblack@eecs.umich.edu    '''
5947234Sgblack@eecs.umich.edu    uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
5957234Sgblack@eecs.umich.edu                             { "code": uxtahCode,
5967234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5977234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
5987234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
5997234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtahIop)
6007239Sgblack@eecs.umich.edu
6017239Sgblack@eecs.umich.edu    selCode = '''
6027239Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6037239Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6047239Sgblack@eecs.umich.edu            int low = i * 8;
6057239Sgblack@eecs.umich.edu            int high = low + 7;
6067239Sgblack@eecs.umich.edu            replaceBits(resTemp, high, low,
6078303SAli.Saidi@ARM.com                        bits(CondCodesGE, i) ?
6087239Sgblack@eecs.umich.edu                            bits(Op1, high, low) : bits(Op2, high, low));
6097239Sgblack@eecs.umich.edu        }
6107239Sgblack@eecs.umich.edu        Dest = resTemp;
6117239Sgblack@eecs.umich.edu    '''
6127239Sgblack@eecs.umich.edu    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
6137239Sgblack@eecs.umich.edu                           { "code": selCode,
6148303SAli.Saidi@ARM.com                             "predicate_test": predicateTest }, [])
6157239Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(selIop)
6167239Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(selIop)
6177239Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(selIop)
6187242Sgblack@eecs.umich.edu
6197242Sgblack@eecs.umich.edu    usad8Code = '''
6207242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6217242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6227242Sgblack@eecs.umich.edu            int low = i * 8;
6237242Sgblack@eecs.umich.edu            int high = low + 7;
6247242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
6257242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
6267242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
6277242Sgblack@eecs.umich.edu        }
6287242Sgblack@eecs.umich.edu        Dest = resTemp;
6297242Sgblack@eecs.umich.edu    '''
6307242Sgblack@eecs.umich.edu    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
6317242Sgblack@eecs.umich.edu                             { "code": usad8Code,
6327242Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
6337242Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(usad8Iop)
6347242Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
6357242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usad8Iop)
6367242Sgblack@eecs.umich.edu
6377242Sgblack@eecs.umich.edu    usada8Code = '''
6387242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6397242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6407242Sgblack@eecs.umich.edu            int low = i * 8;
6417242Sgblack@eecs.umich.edu            int high = low + 7;
6427242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
6437242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
6447242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
6457242Sgblack@eecs.umich.edu        }
6467242Sgblack@eecs.umich.edu        Dest = Op3 + resTemp;
6477242Sgblack@eecs.umich.edu    '''
6487242Sgblack@eecs.umich.edu    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
6497242Sgblack@eecs.umich.edu                              { "code": usada8Code,
6507242Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
6517242Sgblack@eecs.umich.edu    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
6527242Sgblack@eecs.umich.edu    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
6537242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usada8Iop)
6547247Sgblack@eecs.umich.edu
65510474Sandreas.hansson@arm.com    bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n'
6567848SAli.Saidi@ARM.com    bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
6577410Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(bkptIop)
6587410Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(bkptIop)
6597410Sgblack@eecs.umich.edu    exec_output += BasicExecute.subst(bkptIop)
6607410Sgblack@eecs.umich.edu
66110037SARM gem5 Developers    nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
6627247Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(nopIop)
66310037SARM gem5 Developers    decoder_output += BasicConstructor64.subst(nopIop)
66410037SARM gem5 Developers    exec_output += BasicExecute.subst(nopIop)
6657408Sgblack@eecs.umich.edu
6667418Sgblack@eecs.umich.edu    yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
6677418Sgblack@eecs.umich.edu            { "code" : "", "predicate_test" : predicateTest })
6687418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(yieldIop)
6697418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(yieldIop)
6707418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(yieldIop)
6717418Sgblack@eecs.umich.edu
6727418Sgblack@eecs.umich.edu    wfeCode = '''
67310037SARM gem5 Developers    CPSR cpsr = Cpsr;
67410037SARM gem5 Developers    SCR  scr  = Scr64;
67510037SARM gem5 Developers
67610037SARM gem5 Developers    // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
67710037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
6788285SPrakash.Ramrakhyani@arm.com    if (SevMailbox == 1) {
6797418Sgblack@eecs.umich.edu        SevMailbox = 0;
68010037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
68111150Smitch.hayenga@arm.com    } else if (tc->getCpuPtr()->getInterruptController(
68211150Smitch.hayenga@arm.com                tc->threadId())->checkInterrupts(tc)) {
68310037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
6848285SPrakash.Ramrakhyani@arm.com    } else {
68512403Sgiacomo.travaglini@arm.com        fault = trapWFx(tc, cpsr, scr, true);
68612403Sgiacomo.travaglini@arm.com        if (fault == NoFault) {
68712403Sgiacomo.travaglini@arm.com            PseudoInst::quiesce(tc);
68812403Sgiacomo.travaglini@arm.com        } else {
68912403Sgiacomo.travaglini@arm.com            PseudoInst::quiesceSkip(tc);
69012403Sgiacomo.travaglini@arm.com        }
6918142SAli.Saidi@ARM.com    }
6927418Sgblack@eecs.umich.edu    '''
6938518Sgeoffrey.blake@arm.com    wfePredFixUpCode = '''
6948518Sgeoffrey.blake@arm.com    // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
6958518Sgeoffrey.blake@arm.com    // and SEV interrupts
6968518Sgeoffrey.blake@arm.com    SevMailbox = 1;
6978518Sgeoffrey.blake@arm.com    '''
6987418Sgblack@eecs.umich.edu    wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
6998518Sgeoffrey.blake@arm.com            { "code" : wfeCode,
7008518Sgeoffrey.blake@arm.com              "pred_fixup" : wfePredFixUpCode,
7018518Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest },
7028733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
7038733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
7047418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfeIop)
7057418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfeIop)
7068518Sgeoffrey.blake@arm.com    exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
7077418Sgblack@eecs.umich.edu
7087418Sgblack@eecs.umich.edu    wfiCode = '''
70910037SARM gem5 Developers    HCR  hcr  = Hcr;
71010037SARM gem5 Developers    CPSR cpsr = Cpsr;
71110037SARM gem5 Developers    SCR  scr  = Scr64;
71210037SARM gem5 Developers
7138285SPrakash.Ramrakhyani@arm.com    // WFI doesn't sleep if interrupts are pending (masked or not)
71410037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
71511150Smitch.hayenga@arm.com    if (tc->getCpuPtr()->getInterruptController(
71611150Smitch.hayenga@arm.com                tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
71710037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
7188285SPrakash.Ramrakhyani@arm.com    } else {
71912403Sgiacomo.travaglini@arm.com        fault = trapWFx(tc, cpsr, scr, false);
72012403Sgiacomo.travaglini@arm.com        if (fault == NoFault) {
72112403Sgiacomo.travaglini@arm.com            PseudoInst::quiesce(tc);
72212403Sgiacomo.travaglini@arm.com        } else {
72312403Sgiacomo.travaglini@arm.com            PseudoInst::quiesceSkip(tc);
72412403Sgiacomo.travaglini@arm.com        }
7258285SPrakash.Ramrakhyani@arm.com    }
72611150Smitch.hayenga@arm.com    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
7277418Sgblack@eecs.umich.edu    '''
7287418Sgblack@eecs.umich.edu    wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
7297418Sgblack@eecs.umich.edu            { "code" : wfiCode, "predicate_test" : predicateTest },
7308733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
7318733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
7327418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfiIop)
7337418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfiIop)
7348142SAli.Saidi@ARM.com    exec_output += QuiescePredOpExecute.subst(wfiIop)
7357418Sgblack@eecs.umich.edu
7367418Sgblack@eecs.umich.edu    sevCode = '''
7378142SAli.Saidi@ARM.com    SevMailbox = 1;
7387418Sgblack@eecs.umich.edu    System *sys = xc->tcBase()->getSystemPtr();
7397418Sgblack@eecs.umich.edu    for (int x = 0; x < sys->numContexts(); x++) {
7407418Sgblack@eecs.umich.edu        ThreadContext *oc = sys->getThreadContext(x);
7418285SPrakash.Ramrakhyani@arm.com        if (oc == xc->tcBase())
7428285SPrakash.Ramrakhyani@arm.com            continue;
7438518Sgeoffrey.blake@arm.com        // Wake CPU with interrupt if they were sleeping
7448285SPrakash.Ramrakhyani@arm.com        if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
7458518Sgeoffrey.blake@arm.com            // Post Interrupt and wake cpu if needed
74611150Smitch.hayenga@arm.com            oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
7478142SAli.Saidi@ARM.com        }
7487418Sgblack@eecs.umich.edu    }
7497418Sgblack@eecs.umich.edu    '''
7507418Sgblack@eecs.umich.edu    sevIop = InstObjParams("sev", "SevInst", "PredOp", \
7517418Sgblack@eecs.umich.edu            { "code" : sevCode, "predicate_test" : predicateTest },
7528733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
7537418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(sevIop)
7547418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(sevIop)
7557418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sevIop)
7567418Sgblack@eecs.umich.edu
75710037SARM gem5 Developers    sevlCode = '''
75810037SARM gem5 Developers    SevMailbox = 1;
75910037SARM gem5 Developers    '''
76010037SARM gem5 Developers    sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
76110037SARM gem5 Developers            { "code" : sevlCode, "predicate_test" : predicateTest },
76210037SARM gem5 Developers            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
76310037SARM gem5 Developers    header_output += BasicDeclare.subst(sevlIop)
76410037SARM gem5 Developers    decoder_output += BasicConstructor.subst(sevlIop)
76510037SARM gem5 Developers    exec_output += BasicExecute.subst(sevlIop)
76610037SARM gem5 Developers
7677408Sgblack@eecs.umich.edu    itIop = InstObjParams("it", "ItInst", "PredOp", \
7688205SAli.Saidi@ARM.com            { "code" : ";",
7698908Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest }, [])
7707408Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(itIop)
7717408Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(itIop)
7727408Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(itIop)
7737409Sgblack@eecs.umich.edu    unknownCode = '''
77410474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, true);
7757409Sgblack@eecs.umich.edu    '''
7767409Sgblack@eecs.umich.edu    unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
7777409Sgblack@eecs.umich.edu                               { "code": unknownCode,
7787409Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest })
7797409Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(unknownIop)
7807409Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(unknownIop)
7817409Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(unknownIop)
7827254Sgblack@eecs.umich.edu
7837254Sgblack@eecs.umich.edu    ubfxCode = '''
7847254Sgblack@eecs.umich.edu        Dest = bits(Op1, imm2, imm1);
7857254Sgblack@eecs.umich.edu    '''
7867254Sgblack@eecs.umich.edu    ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
7877254Sgblack@eecs.umich.edu                            { "code": ubfxCode,
7887254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
7897254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
7907254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
7917254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ubfxIop)
7927254Sgblack@eecs.umich.edu
7937254Sgblack@eecs.umich.edu    sbfxCode = '''
7947254Sgblack@eecs.umich.edu        int32_t resTemp = bits(Op1, imm2, imm1);
7957254Sgblack@eecs.umich.edu        Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
7967254Sgblack@eecs.umich.edu    '''
7977254Sgblack@eecs.umich.edu    sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
7987254Sgblack@eecs.umich.edu                            { "code": sbfxCode,
7997254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
8007254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
8017254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
8027254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sbfxIop)
8037257Sgblack@eecs.umich.edu
8047257Sgblack@eecs.umich.edu    bfcCode = '''
8057257Sgblack@eecs.umich.edu        Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
8067257Sgblack@eecs.umich.edu    '''
8077257Sgblack@eecs.umich.edu    bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
8087257Sgblack@eecs.umich.edu                           { "code": bfcCode,
8097257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8107257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfcIop)
8117257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
8127257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfcIop)
8137257Sgblack@eecs.umich.edu
8147257Sgblack@eecs.umich.edu    bfiCode = '''
8157257Sgblack@eecs.umich.edu        uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
8167257Sgblack@eecs.umich.edu        Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
8177257Sgblack@eecs.umich.edu    '''
8187257Sgblack@eecs.umich.edu    bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
8197257Sgblack@eecs.umich.edu                           { "code": bfiCode,
8207257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8217257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfiIop)
8227257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
8237257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfiIop)
8247262Sgblack@eecs.umich.edu
8258868SMatt.Horsnell@arm.com    mrc14code = '''
82612106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
82712106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, op1)).index();
82811939Snikos.nikoleris@arm.com    bool can_read, undefined;
82911939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
83011939Snikos.nikoleris@arm.com    if (!can_read || undefined) {
83110474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
83210474Sandreas.hansson@arm.com                                                      mnemonic);
83310037SARM gem5 Developers    }
83410037SARM gem5 Developers    if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
83510037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
83610474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
83710474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8388868SMatt.Horsnell@arm.com    }
8398868SMatt.Horsnell@arm.com    Dest = MiscOp1;
8408868SMatt.Horsnell@arm.com    '''
8418868SMatt.Horsnell@arm.com
84210037SARM gem5 Developers    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
8438868SMatt.Horsnell@arm.com                             { "code": mrc14code,
8448868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest }, [])
84510037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mrc14Iop)
84610037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
8478868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mrc14Iop)
8488868SMatt.Horsnell@arm.com
8498868SMatt.Horsnell@arm.com
8508868SMatt.Horsnell@arm.com    mcr14code = '''
85112106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
85212106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, dest)).index();
85311939Snikos.nikoleris@arm.com    bool can_write, undefined;
85411939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
85511939Snikos.nikoleris@arm.com    if (undefined || !can_write) {
85610474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
85710474Sandreas.hansson@arm.com                                                      mnemonic);
85810037SARM gem5 Developers    }
85910037SARM gem5 Developers    if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
86010037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
86110474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
86210474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8638868SMatt.Horsnell@arm.com    }
8648868SMatt.Horsnell@arm.com    MiscDest = Op1;
8658868SMatt.Horsnell@arm.com    '''
86610037SARM gem5 Developers    mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
8678868SMatt.Horsnell@arm.com                             { "code": mcr14code,
8688868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest },
8698868SMatt.Horsnell@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
87010037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mcr14Iop)
87110037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
8728868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mcr14Iop)
8738868SMatt.Horsnell@arm.com
87410037SARM gem5 Developers    mrc15code = '''
87510037SARM gem5 Developers    int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
87610037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
87712106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
87812106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
87910037SARM gem5 Developers    bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
88010037SARM gem5 Developers                                     Hcptr, imm);
88111939Snikos.nikoleris@arm.com    bool can_read, undefined;
88211939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
88310037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
88410037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
88510037SARM gem5 Developers    // IS accessable.
88611939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
88711939Snikos.nikoleris@arm.com                                    !inSecureState(Scr, Cpsr)))) {
88810474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
88910474Sandreas.hansson@arm.com                                                      mnemonic);
8908782Sgblack@eecs.umich.edu    }
89110037SARM gem5 Developers    if (hypTrap) {
89210474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
89310474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
89410037SARM gem5 Developers    }
89510037SARM gem5 Developers    Dest = MiscNsBankedOp1;
8967347SAli.Saidi@ARM.com    '''
8977347SAli.Saidi@ARM.com
89810418Sandreas.hansson@arm.com    mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp",
8997347SAli.Saidi@ARM.com                             { "code": mrc15code,
9007262Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
90110418Sandreas.hansson@arm.com    header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
90210418Sandreas.hansson@arm.com    decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
9037262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrc15Iop)
9047262Sgblack@eecs.umich.edu
9057347SAli.Saidi@ARM.com
9067347SAli.Saidi@ARM.com    mcr15code = '''
90710037SARM gem5 Developers    int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
90810037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
90912106SRekai.GonzalezAlberquilla@arm.com                       xc->tcBase()->flattenRegId(RegId(MiscRegClass,
91012106SRekai.GonzalezAlberquilla@arm.com                                                  preFlatDest)).index();
91110037SARM gem5 Developers    bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
91210037SARM gem5 Developers                                      Hcptr, imm);
91311939Snikos.nikoleris@arm.com    bool can_write, undefined;
91411939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
91510037SARM gem5 Developers
91610037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
91710037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
91810037SARM gem5 Developers    // IS accessable.
91911939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
92011939Snikos.nikoleris@arm.com                                      !inSecureState(Scr, Cpsr)))) {
92110474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
92210474Sandreas.hansson@arm.com                                                      mnemonic);
9238782Sgblack@eecs.umich.edu    }
92410037SARM gem5 Developers    if (hypTrap) {
92510474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
92610474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
92710037SARM gem5 Developers    }
92810037SARM gem5 Developers    MiscNsBankedDest = Op1;
9297347SAli.Saidi@ARM.com    '''
93010418Sandreas.hansson@arm.com    mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
9317347SAli.Saidi@ARM.com                             { "code": mcr15code,
9327599Sminkyu.jeong@arm.com                               "predicate_test": predicateTest },
9337599Sminkyu.jeong@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
93410418Sandreas.hansson@arm.com    header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
93510418Sandreas.hansson@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
9367262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mcr15Iop)
9377283Sgblack@eecs.umich.edu
9387420Sgblack@eecs.umich.edu
93910037SARM gem5 Developers    mrrc15code = '''
94010037SARM gem5 Developers    int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
94110037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
94212106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
94312106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
94410037SARM gem5 Developers    bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
94511939Snikos.nikoleris@arm.com    bool can_read, undefined;
94611939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
94710037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
94810037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
94910037SARM gem5 Developers    // IS accessable.
95011939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
95111939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
95210474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
95310474Sandreas.hansson@arm.com                                                      mnemonic);
95410037SARM gem5 Developers    }
95510037SARM gem5 Developers    if (hypTrap) {
95610474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
95710474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
95810037SARM gem5 Developers    }
95910037SARM gem5 Developers    Dest = bits(MiscNsBankedOp164, 63, 32);
96010037SARM gem5 Developers    Dest2 = bits(MiscNsBankedOp164, 31, 0);
96110037SARM gem5 Developers    '''
96210037SARM gem5 Developers    mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
96310037SARM gem5 Developers                              { "code": mrrc15code,
96410037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
96510037SARM gem5 Developers    header_output += MrrcOpDeclare.subst(mrrc15Iop)
96610037SARM gem5 Developers    decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
96710037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrrc15Iop)
96810037SARM gem5 Developers
96910037SARM gem5 Developers
97010037SARM gem5 Developers    mcrr15code = '''
97110037SARM gem5 Developers    int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
97210037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
97312106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
97412106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatDest)).index();
97510037SARM gem5 Developers    bool hypTrap  = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
97611939Snikos.nikoleris@arm.com    bool can_write, undefined;
97711939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
97810037SARM gem5 Developers
97910037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
98010037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
98110037SARM gem5 Developers    // IS accessable.
98211939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
98311939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
98410474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
98510474Sandreas.hansson@arm.com                                                      mnemonic);
98610037SARM gem5 Developers    }
98710037SARM gem5 Developers    if (hypTrap) {
98810474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
98910474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
99010037SARM gem5 Developers    }
99110037SARM gem5 Developers    MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
99210037SARM gem5 Developers    '''
99310037SARM gem5 Developers    mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
99410037SARM gem5 Developers                              { "code": mcrr15code,
99510037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
99610037SARM gem5 Developers    header_output += McrrOpDeclare.subst(mcrr15Iop)
99710037SARM gem5 Developers    decoder_output += McrrOpConstructor.subst(mcrr15Iop)
99810037SARM gem5 Developers    exec_output += PredOpExecute.subst(mcrr15Iop)
99910037SARM gem5 Developers
10007420Sgblack@eecs.umich.edu
10017283Sgblack@eecs.umich.edu    enterxCode = '''
10027797Sgblack@eecs.umich.edu        NextThumb = true;
10037797Sgblack@eecs.umich.edu        NextJazelle = true;
10047283Sgblack@eecs.umich.edu    '''
10057283Sgblack@eecs.umich.edu    enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
10067283Sgblack@eecs.umich.edu                              { "code": enterxCode,
10077283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
10087283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(enterxIop)
10097283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(enterxIop)
10107283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(enterxIop)
10117283Sgblack@eecs.umich.edu
10127283Sgblack@eecs.umich.edu    leavexCode = '''
10137797Sgblack@eecs.umich.edu        NextThumb = true;
10147797Sgblack@eecs.umich.edu        NextJazelle = false;
10157283Sgblack@eecs.umich.edu    '''
10167283Sgblack@eecs.umich.edu    leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
10177283Sgblack@eecs.umich.edu                              { "code": leavexCode,
10187283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
10197283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(leavexIop)
10207283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(leavexIop)
10217283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(leavexIop)
10227307Sgblack@eecs.umich.edu
10237307Sgblack@eecs.umich.edu    setendCode = '''
10247307Sgblack@eecs.umich.edu        CPSR cpsr = Cpsr;
10257307Sgblack@eecs.umich.edu        cpsr.e = imm;
10267307Sgblack@eecs.umich.edu        Cpsr = cpsr;
10277307Sgblack@eecs.umich.edu    '''
10287307Sgblack@eecs.umich.edu    setendIop = InstObjParams("setend", "Setend", "ImmOp",
10297307Sgblack@eecs.umich.edu                              { "code": setendCode,
10307648SAli.Saidi@ARM.com                                "predicate_test": predicateTest },
10317648SAli.Saidi@ARM.com                              ["IsSerializeAfter","IsNonSpeculative"])
10327307Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(setendIop)
10337307Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(setendIop)
10347307Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(setendIop)
10357315Sgblack@eecs.umich.edu
10367603SGene.Wu@arm.com    clrexCode = '''
10378209SAli.Saidi@ARM.com        LLSCLock = 0;
10387603SGene.Wu@arm.com    '''
10397603SGene.Wu@arm.com    clrexIop = InstObjParams("clrex", "Clrex","PredOp",
10407603SGene.Wu@arm.com                             { "code": clrexCode,
10417603SGene.Wu@arm.com                               "predicate_test": predicateTest },[])
10428209SAli.Saidi@ARM.com    header_output += BasicDeclare.subst(clrexIop)
10437603SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(clrexIop)
10447603SGene.Wu@arm.com    exec_output += PredOpExecute.subst(clrexIop)
10457603SGene.Wu@arm.com
104612358Snikos.nikoleris@arm.com    McrDcCheckCode = '''
104712358Snikos.nikoleris@arm.com        int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
104812358Snikos.nikoleris@arm.com        MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
104912358Snikos.nikoleris@arm.com            RegId(MiscRegClass, preFlatDest)).index();
105012358Snikos.nikoleris@arm.com        bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
105112358Snikos.nikoleris@arm.com                                          Hcptr, imm);
105212358Snikos.nikoleris@arm.com        bool can_write, undefined;
105312358Snikos.nikoleris@arm.com        std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
105412358Snikos.nikoleris@arm.com
105512358Snikos.nikoleris@arm.com        // if we're in non secure PL1 mode then we can trap regardless
105612358Snikos.nikoleris@arm.com        // of whether the register is accessible, in other modes we
105712358Snikos.nikoleris@arm.com        // trap if only if the register IS accessible.
105812358Snikos.nikoleris@arm.com        if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
105912358Snikos.nikoleris@arm.com                                         !inSecureState(Scr, Cpsr)))) {
106012358Snikos.nikoleris@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
106112358Snikos.nikoleris@arm.com                                                          mnemonic);
106212358Snikos.nikoleris@arm.com        }
106312358Snikos.nikoleris@arm.com        if (hypTrap) {
106412358Snikos.nikoleris@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
106512358Snikos.nikoleris@arm.com                                                    EC_TRAPPED_CP15_MCR_MRC);
106612358Snikos.nikoleris@arm.com        }
106712358Snikos.nikoleris@arm.com    '''
106812358Snikos.nikoleris@arm.com
106912358Snikos.nikoleris@arm.com    McrDcimvacCode = '''
107012358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
107112358Snikos.nikoleris@arm.com                                            Request::INVALIDATE |
107212358Snikos.nikoleris@arm.com                                            Request::DST_POC);
107312358Snikos.nikoleris@arm.com        EA = Op1;
107412358Snikos.nikoleris@arm.com    '''
107512358Snikos.nikoleris@arm.com    McrDcimvacIop = InstObjParams("mcr dcimvac", "McrDcimvac",
107612358Snikos.nikoleris@arm.com                                  "MiscRegRegImmMemOp",
107712358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
107812358Snikos.nikoleris@arm.com                                   "postacc_code": "",
107912358Snikos.nikoleris@arm.com                                   "ea_code": McrDcimvacCode,
108012358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
108112358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
108212358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop)
108312358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop)
108412358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDcimvacIop) + \
108512358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDcimvacIop) + \
108612358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDcimvacIop)
108712358Snikos.nikoleris@arm.com
108812358Snikos.nikoleris@arm.com    McrDccmvacCode = '''
108912358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
109012358Snikos.nikoleris@arm.com                                            Request::CLEAN |
109112358Snikos.nikoleris@arm.com                                            Request::DST_POC);
109212358Snikos.nikoleris@arm.com        EA = Op1;
109312358Snikos.nikoleris@arm.com    '''
109412358Snikos.nikoleris@arm.com    McrDccmvacIop = InstObjParams("mcr dccmvac", "McrDccmvac",
109512358Snikos.nikoleris@arm.com                                  "MiscRegRegImmMemOp",
109612358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
109712358Snikos.nikoleris@arm.com                                   "postacc_code": "",
109812358Snikos.nikoleris@arm.com                                   "ea_code": McrDccmvacCode,
109912358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
110012358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
110112358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop)
110212358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop)
110312358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccmvacIop) + \
110412358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccmvacIop) + \
110512358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccmvacIop)
110612358Snikos.nikoleris@arm.com
110712358Snikos.nikoleris@arm.com    McrDccmvauCode = '''
110812358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
110912358Snikos.nikoleris@arm.com                                            Request::CLEAN |
111012358Snikos.nikoleris@arm.com                                            Request::DST_POU);
111112358Snikos.nikoleris@arm.com        EA = Op1;
111212358Snikos.nikoleris@arm.com    '''
111312358Snikos.nikoleris@arm.com    McrDccmvauIop = InstObjParams("mcr dccmvau", "McrDccmvau",
111412358Snikos.nikoleris@arm.com                                  "MiscRegRegImmMemOp",
111512358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
111612358Snikos.nikoleris@arm.com                                   "postacc_code": "",
111712358Snikos.nikoleris@arm.com                                   "ea_code": McrDccmvauCode,
111812358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
111912358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
112012358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop)
112112358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop)
112212358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccmvauIop) + \
112312358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccmvauIop) + \
112412358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccmvauIop)
112512358Snikos.nikoleris@arm.com
112612358Snikos.nikoleris@arm.com    McrDccimvacCode = '''
112712358Snikos.nikoleris@arm.com        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
112812358Snikos.nikoleris@arm.com                                            Request::CLEAN |
112912358Snikos.nikoleris@arm.com                                            Request::INVALIDATE |
113012358Snikos.nikoleris@arm.com                                            Request::DST_POC);
113112358Snikos.nikoleris@arm.com        EA = Op1;
113212358Snikos.nikoleris@arm.com    '''
113312358Snikos.nikoleris@arm.com    McrDccimvacIop = InstObjParams("mcr dccimvac", "McrDccimvac",
113412358Snikos.nikoleris@arm.com                                  "MiscRegRegImmMemOp",
113512358Snikos.nikoleris@arm.com                                  {"memacc_code": McrDcCheckCode,
113612358Snikos.nikoleris@arm.com                                   "postacc_code": "",
113712358Snikos.nikoleris@arm.com                                   "ea_code": McrDccimvacCode,
113812358Snikos.nikoleris@arm.com                                   "predicate_test": predicateTest},
113912358Snikos.nikoleris@arm.com                                ['IsMemRef', 'IsStore'])
114012358Snikos.nikoleris@arm.com    header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
114112358Snikos.nikoleris@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
114212358Snikos.nikoleris@arm.com    exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
114312358Snikos.nikoleris@arm.com                   Mcr15InitiateAcc.subst(McrDccimvacIop) + \
114412358Snikos.nikoleris@arm.com                   Mcr15CompleteAcc.subst(McrDccimvacIop)
114512358Snikos.nikoleris@arm.com
11467605SGene.Wu@arm.com    isbCode = '''
114710037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
114810037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
114910037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
115010474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
115110037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
115210037SARM gem5 Developers        }
11537605SGene.Wu@arm.com    '''
115410037SARM gem5 Developers    isbIop = InstObjParams("isb", "Isb", "ImmOp",
11557605SGene.Wu@arm.com                             {"code": isbCode,
11568068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
115712259Sgiacomo.travaglini@arm.com                                ['IsSerializeAfter', 'IsSquashAfter'])
115810037SARM gem5 Developers    header_output += ImmOpDeclare.subst(isbIop)
115910037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(isbIop)
11607605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(isbIop)
11617605SGene.Wu@arm.com
11627605SGene.Wu@arm.com    dsbCode = '''
116310037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
116410037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr,
116510037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
116610474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
116710037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
116810037SARM gem5 Developers        }
11697605SGene.Wu@arm.com    '''
117010037SARM gem5 Developers    dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
11717605SGene.Wu@arm.com                             {"code": dsbCode,
11728068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
117312261Sgiacomo.travaglini@arm.com                              ['IsMemBarrier', 'IsSerializeAfter'])
117410037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dsbIop)
117510037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dsbIop)
11767605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dsbIop)
11777605SGene.Wu@arm.com
11787605SGene.Wu@arm.com    dmbCode = '''
117910037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
118010037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr,
118110037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
118210474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
118310037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
118410037SARM gem5 Developers        }
11857605SGene.Wu@arm.com    '''
118610037SARM gem5 Developers    dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
11877605SGene.Wu@arm.com                             {"code": dmbCode,
11888068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
11898068SAli.Saidi@ARM.com                               ['IsMemBarrier'])
119010037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dmbIop)
119110037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dmbIop)
11927605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dmbIop)
11937605SGene.Wu@arm.com
11947613SGene.Wu@arm.com    dbgCode = '''
11957613SGene.Wu@arm.com    '''
11967613SGene.Wu@arm.com    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
11977613SGene.Wu@arm.com                             {"code": dbgCode,
11987613SGene.Wu@arm.com                               "predicate_test": predicateTest})
11997613SGene.Wu@arm.com    header_output += BasicDeclare.subst(dbgIop)
12007613SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(dbgIop)
12017613SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dbgIop)
12027613SGene.Wu@arm.com
12037315Sgblack@eecs.umich.edu    cpsCode = '''
12047315Sgblack@eecs.umich.edu    uint32_t mode = bits(imm, 4, 0);
12057315Sgblack@eecs.umich.edu    uint32_t f = bits(imm, 5);
12067315Sgblack@eecs.umich.edu    uint32_t i = bits(imm, 6);
12077315Sgblack@eecs.umich.edu    uint32_t a = bits(imm, 7);
12087315Sgblack@eecs.umich.edu    bool setMode = bits(imm, 8);
12097315Sgblack@eecs.umich.edu    bool enable = bits(imm, 9);
12107315Sgblack@eecs.umich.edu    CPSR cpsr = Cpsr;
12117400SAli.Saidi@ARM.com    SCTLR sctlr = Sctlr;
12127315Sgblack@eecs.umich.edu    if (cpsr.mode != MODE_USER) {
12137315Sgblack@eecs.umich.edu        if (enable) {
12147315Sgblack@eecs.umich.edu            if (f) cpsr.f = 0;
12157315Sgblack@eecs.umich.edu            if (i) cpsr.i = 0;
12167315Sgblack@eecs.umich.edu            if (a) cpsr.a = 0;
12177315Sgblack@eecs.umich.edu        } else {
12187400SAli.Saidi@ARM.com            if (f && !sctlr.nmfi) cpsr.f = 1;
12197315Sgblack@eecs.umich.edu            if (i) cpsr.i = 1;
12207315Sgblack@eecs.umich.edu            if (a) cpsr.a = 1;
12217315Sgblack@eecs.umich.edu        }
12227315Sgblack@eecs.umich.edu        if (setMode) {
12237315Sgblack@eecs.umich.edu            cpsr.mode = mode;
12247315Sgblack@eecs.umich.edu        }
12257315Sgblack@eecs.umich.edu    }
12267315Sgblack@eecs.umich.edu    Cpsr = cpsr;
12277315Sgblack@eecs.umich.edu    '''
12287315Sgblack@eecs.umich.edu    cpsIop = InstObjParams("cps", "Cps", "ImmOp",
12297315Sgblack@eecs.umich.edu                           { "code": cpsCode,
12307599Sminkyu.jeong@arm.com                             "predicate_test": predicateTest },
12317599Sminkyu.jeong@arm.com                           ["IsSerializeAfter","IsNonSpeculative"])
12327315Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(cpsIop)
12337315Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(cpsIop)
12347315Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(cpsIop)
12357202Sgblack@eecs.umich.edu}};
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