misc.isa revision 12227
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 311939Snikos.nikoleris@arm.com// Copyright (c) 2010-2013,2017 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 4310474Sandreas.hansson@arm.com fault = std::make_shared<SupervisorCall>(machInst, imm); 4410037SARM gem5 Developers ''' 4510037SARM gem5 Developers 4610037SARM gem5 Developers svcIop = InstObjParams("svc", "Svc", "ImmOp", 4710037SARM gem5 Developers { "code": svcCode, 4810037SARM gem5 Developers "predicate_test": predicateTest }, 4910037SARM gem5 Developers ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"]) 5010037SARM gem5 Developers header_output = ImmOpDeclare.subst(svcIop) 5110037SARM gem5 Developers decoder_output = ImmOpConstructor.subst(svcIop) 5210037SARM gem5 Developers exec_output = PredOpExecute.subst(svcIop) 5310037SARM gem5 Developers 5410037SARM gem5 Developers smcCode = ''' 5510037SARM gem5 Developers HCR hcr = Hcr; 5610037SARM gem5 Developers CPSR cpsr = Cpsr; 5710037SARM gem5 Developers SCR scr = Scr; 5810037SARM gem5 Developers 5910037SARM gem5 Developers if ((cpsr.mode != MODE_USER) && FullSystem) { 6010037SARM gem5 Developers if (ArmSystem::haveVirtualization(xc->tcBase()) && 6110037SARM gem5 Developers !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) { 6210474Sandreas.hansson@arm.com fault = std::make_shared<HypervisorTrap>(machInst, 0, 6310474Sandreas.hansson@arm.com EC_SMC_TO_HYP); 6410037SARM gem5 Developers } else { 6510037SARM gem5 Developers if (scr.scd) { 6610037SARM gem5 Developers fault = disabledFault(); 6710037SARM gem5 Developers } else { 6810474Sandreas.hansson@arm.com fault = std::make_shared<SecureMonitorCall>(machInst); 6910037SARM gem5 Developers } 7010037SARM gem5 Developers } 718782Sgblack@eecs.umich.edu } else { 7210037SARM gem5 Developers fault = disabledFault(); 738782Sgblack@eecs.umich.edu } 747199Sgblack@eecs.umich.edu ''' 757199Sgblack@eecs.umich.edu 7610037SARM gem5 Developers smcIop = InstObjParams("smc", "Smc", "PredOp", 7710037SARM gem5 Developers { "code": smcCode, 788628SAli.Saidi@ARM.com "predicate_test": predicateTest }, 7910037SARM gem5 Developers ["IsNonSpeculative", "IsSerializeAfter"]) 8010037SARM gem5 Developers header_output += BasicDeclare.subst(smcIop) 8110037SARM gem5 Developers decoder_output += BasicConstructor.subst(smcIop) 8210037SARM gem5 Developers exec_output += PredOpExecute.subst(smcIop) 8310037SARM gem5 Developers 8410037SARM gem5 Developers hvcCode = ''' 8510037SARM gem5 Developers CPSR cpsr = Cpsr; 8610037SARM gem5 Developers SCR scr = Scr; 8710037SARM gem5 Developers 8810037SARM gem5 Developers // Filter out the various cases where this instruction isn't defined 8910037SARM gem5 Developers if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) || 9010037SARM gem5 Developers (cpsr.mode == MODE_USER) || 9110037SARM gem5 Developers (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { 9210037SARM gem5 Developers fault = disabledFault(); 9310037SARM gem5 Developers } else { 9410474Sandreas.hansson@arm.com fault = std::make_shared<HypervisorCall>(machInst, imm); 9510037SARM gem5 Developers } 9610037SARM gem5 Developers ''' 9710037SARM gem5 Developers 9810037SARM gem5 Developers hvcIop = InstObjParams("hvc", "Hvc", "ImmOp", 9910037SARM gem5 Developers { "code": hvcCode, 10010037SARM gem5 Developers "predicate_test": predicateTest }, 10110037SARM gem5 Developers ["IsNonSpeculative", "IsSerializeAfter"]) 10210037SARM gem5 Developers header_output += ImmOpDeclare.subst(hvcIop) 10310037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(hvcIop) 10410037SARM gem5 Developers exec_output += PredOpExecute.subst(hvcIop) 10510037SARM gem5 Developers 10610037SARM gem5 Developers eretCode = ''' 10710037SARM gem5 Developers SCTLR sctlr = Sctlr; 10810037SARM gem5 Developers CPSR old_cpsr = Cpsr; 10910037SARM gem5 Developers old_cpsr.nz = CondCodesNZ; 11010037SARM gem5 Developers old_cpsr.c = CondCodesC; 11110037SARM gem5 Developers old_cpsr.v = CondCodesV; 11210037SARM gem5 Developers old_cpsr.ge = CondCodesGE; 11310037SARM gem5 Developers 11410037SARM gem5 Developers CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, 11510037SARM gem5 Developers true, sctlr.nmfi, xc->tcBase()); 11610037SARM gem5 Developers Cpsr = ~CondCodesMask & new_cpsr; 11710037SARM gem5 Developers CondCodesNZ = new_cpsr.nz; 11810037SARM gem5 Developers CondCodesC = new_cpsr.c; 11910037SARM gem5 Developers CondCodesV = new_cpsr.v; 12010037SARM gem5 Developers CondCodesGE = new_cpsr.ge; 12110037SARM gem5 Developers 12210037SARM gem5 Developers NextThumb = (new_cpsr).t; 12310037SARM gem5 Developers NextJazelle = (new_cpsr).j; 12410037SARM gem5 Developers NextItState = (((new_cpsr).it2 << 2) & 0xFC) 12510037SARM gem5 Developers | ((new_cpsr).it1 & 0x3); 12610037SARM gem5 Developers 12710037SARM gem5 Developers NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR; 12810037SARM gem5 Developers ''' 12910037SARM gem5 Developers 13010037SARM gem5 Developers eretIop = InstObjParams("eret", "Eret", "PredOp", 13110037SARM gem5 Developers { "code": eretCode, 13210037SARM gem5 Developers "predicate_test": predicateTest }, 13311355Smitch.hayenga@arm.com ["IsNonSpeculative", "IsSerializeAfter", 13411355Smitch.hayenga@arm.com "IsSquashAfter"]) 13510037SARM gem5 Developers header_output += BasicDeclare.subst(eretIop) 13610037SARM gem5 Developers decoder_output += BasicConstructor.subst(eretIop) 13710037SARM gem5 Developers exec_output += PredOpExecute.subst(eretIop) 13810037SARM gem5 Developers 13910037SARM gem5 Developers 1407199Sgblack@eecs.umich.edu 1417199Sgblack@eecs.umich.edu}}; 1427202Sgblack@eecs.umich.edu 1437202Sgblack@eecs.umich.edulet {{ 1447202Sgblack@eecs.umich.edu 1457202Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 1467202Sgblack@eecs.umich.edu 1478301SAli.Saidi@ARM.com mrsCpsrCode = ''' 1488303SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 1498303SAli.Saidi@ARM.com cpsr.nz = CondCodesNZ; 1508303SAli.Saidi@ARM.com cpsr.c = CondCodesC; 1518303SAli.Saidi@ARM.com cpsr.v = CondCodesV; 1528303SAli.Saidi@ARM.com cpsr.ge = CondCodesGE; 1538303SAli.Saidi@ARM.com Dest = cpsr & 0xF8FF03DF 1548301SAli.Saidi@ARM.com ''' 1558301SAli.Saidi@ARM.com 1567202Sgblack@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 1577202Sgblack@eecs.umich.edu { "code": mrsCpsrCode, 1587599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 1597783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 1607202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsCpsrIop) 1617202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 1627202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 1637202Sgblack@eecs.umich.edu 1647202Sgblack@eecs.umich.edu mrsSpsrCode = "Dest = Spsr" 1657202Sgblack@eecs.umich.edu mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 1667202Sgblack@eecs.umich.edu { "code": mrsSpsrCode, 1677599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1687783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 1697202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsSpsrIop) 1707202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 1717202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsSpsrIop) 1727202Sgblack@eecs.umich.edu 17310037SARM gem5 Developers mrsBankedRegCode = ''' 17410037SARM gem5 Developers bool isIntReg; 17510037SARM gem5 Developers int regIdx; 17610037SARM gem5 Developers 17710037SARM gem5 Developers if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 17810037SARM gem5 Developers if (isIntReg) { 17910037SARM gem5 Developers Dest = DecodedBankedIntReg; 18010037SARM gem5 Developers } else { 18110037SARM gem5 Developers Dest = xc->readMiscReg(regIdx); 18210037SARM gem5 Developers } 18310037SARM gem5 Developers } else { 18410474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 18510474Sandreas.hansson@arm.com mnemonic); 18610037SARM gem5 Developers } 18710037SARM gem5 Developers ''' 18810037SARM gem5 Developers mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp", 18910037SARM gem5 Developers { "code": mrsBankedRegCode, 19010037SARM gem5 Developers "predicate_test": predicateTest }, 19110037SARM gem5 Developers ["IsSerializeBefore"]) 19210037SARM gem5 Developers header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop) 19310037SARM gem5 Developers decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop) 19410037SARM gem5 Developers exec_output += PredOpExecute.subst(mrsBankedRegIop) 19510037SARM gem5 Developers 19610037SARM gem5 Developers msrBankedRegCode = ''' 19710037SARM gem5 Developers bool isIntReg; 19810037SARM gem5 Developers int regIdx; 19910037SARM gem5 Developers 20010037SARM gem5 Developers if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) { 20110037SARM gem5 Developers if (isIntReg) { 20210037SARM gem5 Developers // This is a bit nasty, you would have thought that 20310037SARM gem5 Developers // DecodedBankedIntReg wouldn't be written to unless the 20410037SARM gem5 Developers // conditions on the IF statements above are met, however if 20510037SARM gem5 Developers // you look at the generated C code you'll find that they are. 20610037SARM gem5 Developers // However this is safe as DecodedBankedIntReg (which is used 20710037SARM gem5 Developers // in operands.isa to get the index of DecodedBankedIntReg) 20810037SARM gem5 Developers // will return INTREG_DUMMY if its not a valid integer 20910037SARM gem5 Developers // register, so redirecting the write to somewhere we don't 21010037SARM gem5 Developers // care about. 21110037SARM gem5 Developers DecodedBankedIntReg = Op1; 21210037SARM gem5 Developers } else { 21310037SARM gem5 Developers xc->setMiscReg(regIdx, Op1); 21410037SARM gem5 Developers } 21510037SARM gem5 Developers } else { 21610474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 21710474Sandreas.hansson@arm.com mnemonic); 21810037SARM gem5 Developers } 21910037SARM gem5 Developers ''' 22010037SARM gem5 Developers msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", 22110037SARM gem5 Developers { "code": msrBankedRegCode, 22210037SARM gem5 Developers "predicate_test": predicateTest }, 22310501Sakash.bagdia@ARM.com ["IsSerializeAfter", "IsNonSpeculative"]) 22410037SARM gem5 Developers header_output += MsrBankedRegDeclare.subst(msrBankedRegIop) 22510037SARM gem5 Developers decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop) 22610037SARM gem5 Developers exec_output += PredOpExecute.subst(msrBankedRegIop) 22710037SARM gem5 Developers 2287202Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 2297400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 2308303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 2318303SAli.Saidi@ARM.com old_cpsr.nz = CondCodesNZ; 2328303SAli.Saidi@ARM.com old_cpsr.c = CondCodesC; 2338303SAli.Saidi@ARM.com old_cpsr.v = CondCodesV; 2348303SAli.Saidi@ARM.com old_cpsr.ge = CondCodesGE; 2358303SAli.Saidi@ARM.com 2368303SAli.Saidi@ARM.com CPSR new_cpsr = 23710037SARM gem5 Developers cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false, 23810037SARM gem5 Developers sctlr.nmfi, xc->tcBase()); 2398303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 2408303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 2418303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 2428303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 2438303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 2447202Sgblack@eecs.umich.edu ''' 2457202Sgblack@eecs.umich.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 2467202Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 2477599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 2487599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 2497202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrCpsrRegIop) 2507202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 2517202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrRegIop) 2527202Sgblack@eecs.umich.edu 2537202Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 2547202Sgblack@eecs.umich.edu msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 2557202Sgblack@eecs.umich.edu { "code": msrSpsrRegCode, 2567599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 2577599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 2587202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrSpsrRegIop) 2597202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 2607202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrRegIop) 2617202Sgblack@eecs.umich.edu 2627202Sgblack@eecs.umich.edu msrCpsrImmCode = ''' 2637400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 2648303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 2658303SAli.Saidi@ARM.com old_cpsr.nz = CondCodesNZ; 2668303SAli.Saidi@ARM.com old_cpsr.c = CondCodesC; 2678303SAli.Saidi@ARM.com old_cpsr.v = CondCodesV; 2688303SAli.Saidi@ARM.com old_cpsr.ge = CondCodesGE; 2698303SAli.Saidi@ARM.com CPSR new_cpsr = 27010037SARM gem5 Developers cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false, 27110037SARM gem5 Developers sctlr.nmfi, xc->tcBase()); 2728303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 2738303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 2748303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 2758303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 2768303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 2777202Sgblack@eecs.umich.edu ''' 2787202Sgblack@eecs.umich.edu msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 2797202Sgblack@eecs.umich.edu { "code": msrCpsrImmCode, 2807599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 2817599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 2827202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrCpsrImmIop) 2837202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 2847202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrImmIop) 2857202Sgblack@eecs.umich.edu 2867202Sgblack@eecs.umich.edu msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 2877202Sgblack@eecs.umich.edu msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 2887202Sgblack@eecs.umich.edu { "code": msrSpsrImmCode, 2897599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 2907599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 2917202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrSpsrImmIop) 2927202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 2937202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrImmIop) 2947209Sgblack@eecs.umich.edu 2957209Sgblack@eecs.umich.edu revCode = ''' 2967209Sgblack@eecs.umich.edu uint32_t val = Op1; 2977209Sgblack@eecs.umich.edu Dest = swap_byte(val); 2987209Sgblack@eecs.umich.edu ''' 2997261Sgblack@eecs.umich.edu revIop = InstObjParams("rev", "Rev", "RegRegOp", 3007209Sgblack@eecs.umich.edu { "code": revCode, 3017209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3027261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revIop) 3037261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revIop) 3047209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revIop) 3057209Sgblack@eecs.umich.edu 3067209Sgblack@eecs.umich.edu rev16Code = ''' 3077209Sgblack@eecs.umich.edu uint32_t val = Op1; 3087209Sgblack@eecs.umich.edu Dest = (bits(val, 15, 8) << 0) | 3097209Sgblack@eecs.umich.edu (bits(val, 7, 0) << 8) | 3107209Sgblack@eecs.umich.edu (bits(val, 31, 24) << 16) | 3117209Sgblack@eecs.umich.edu (bits(val, 23, 16) << 24); 3127209Sgblack@eecs.umich.edu ''' 3137261Sgblack@eecs.umich.edu rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 3147209Sgblack@eecs.umich.edu { "code": rev16Code, 3157209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3167261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rev16Iop) 3177261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rev16Iop) 3187209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rev16Iop) 3197209Sgblack@eecs.umich.edu 3207209Sgblack@eecs.umich.edu revshCode = ''' 3217209Sgblack@eecs.umich.edu uint16_t val = Op1; 3227209Sgblack@eecs.umich.edu Dest = sext<16>(swap_byte(val)); 3237209Sgblack@eecs.umich.edu ''' 3247261Sgblack@eecs.umich.edu revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 3257209Sgblack@eecs.umich.edu { "code": revshCode, 3267209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3277261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revshIop) 3287261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revshIop) 3297209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revshIop) 3307226Sgblack@eecs.umich.edu 3317249Sgblack@eecs.umich.edu rbitCode = ''' 33212227Sgiacomo.travaglini@arm.com Dest = reverseBits(Op1); 3337249Sgblack@eecs.umich.edu ''' 3347261Sgblack@eecs.umich.edu rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 3357249Sgblack@eecs.umich.edu { "code": rbitCode, 3367249Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3377261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rbitIop) 3387261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rbitIop) 3397249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rbitIop) 3407249Sgblack@eecs.umich.edu 3417251Sgblack@eecs.umich.edu clzCode = ''' 3427251Sgblack@eecs.umich.edu Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 3437251Sgblack@eecs.umich.edu ''' 3447261Sgblack@eecs.umich.edu clzIop = InstObjParams("clz", "Clz", "RegRegOp", 3457251Sgblack@eecs.umich.edu { "code": clzCode, 3467251Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3477261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(clzIop) 3487261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(clzIop) 3497251Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clzIop) 3507251Sgblack@eecs.umich.edu 3517226Sgblack@eecs.umich.edu ssatCode = ''' 3527226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 3537226Sgblack@eecs.umich.edu int32_t res; 3547232Sgblack@eecs.umich.edu if (satInt(res, operand, imm)) 3558302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 3567226Sgblack@eecs.umich.edu Dest = res; 3577226Sgblack@eecs.umich.edu ''' 3587232Sgblack@eecs.umich.edu ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 3597226Sgblack@eecs.umich.edu { "code": ssatCode, 3608304SAli.Saidi@ARM.com "predicate_test": pickPredicate(ssatCode) }, []) 3617232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 3627232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 3637226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssatIop) 3647226Sgblack@eecs.umich.edu 3657226Sgblack@eecs.umich.edu usatCode = ''' 3667226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 3677226Sgblack@eecs.umich.edu int32_t res; 3687232Sgblack@eecs.umich.edu if (uSatInt(res, operand, imm)) 3698302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 3707226Sgblack@eecs.umich.edu Dest = res; 3717226Sgblack@eecs.umich.edu ''' 3727232Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 3737226Sgblack@eecs.umich.edu { "code": usatCode, 3748304SAli.Saidi@ARM.com "predicate_test": pickPredicate(usatCode) }, []) 3757232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(usatIop) 3767232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 3777226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usatIop) 3787226Sgblack@eecs.umich.edu 3797226Sgblack@eecs.umich.edu ssat16Code = ''' 3807226Sgblack@eecs.umich.edu int32_t res; 3817226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3827226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 3837226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 3847232Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 3858302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 3867226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 3877232Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 3888302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 3897226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 3907226Sgblack@eecs.umich.edu Dest = resTemp; 3917226Sgblack@eecs.umich.edu ''' 3927232Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 3937226Sgblack@eecs.umich.edu { "code": ssat16Code, 3948304SAli.Saidi@ARM.com "predicate_test": pickPredicate(ssat16Code) }, []) 3957232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(ssat16Iop) 3967232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 3977226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssat16Iop) 3987226Sgblack@eecs.umich.edu 3997226Sgblack@eecs.umich.edu usat16Code = ''' 4007226Sgblack@eecs.umich.edu int32_t res; 4017226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4027226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 4037226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 4047232Sgblack@eecs.umich.edu if (uSatInt(res, argLow, imm)) 4058302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4067226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 4077232Sgblack@eecs.umich.edu if (uSatInt(res, argHigh, imm)) 4088302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 4097226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 4107226Sgblack@eecs.umich.edu Dest = resTemp; 4117226Sgblack@eecs.umich.edu ''' 4127232Sgblack@eecs.umich.edu usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 4137226Sgblack@eecs.umich.edu { "code": usat16Code, 4148304SAli.Saidi@ARM.com "predicate_test": pickPredicate(usat16Code) }, []) 4157232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(usat16Iop) 4167232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 4177226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usat16Iop) 4187234Sgblack@eecs.umich.edu 4197234Sgblack@eecs.umich.edu sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 4207234Sgblack@eecs.umich.edu { "code": 4218588Sgblack@eecs.umich.edu "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", 4227234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4237234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtbIop) 4247234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 4257234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtbIop) 4267234Sgblack@eecs.umich.edu 4277234Sgblack@eecs.umich.edu sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 4287234Sgblack@eecs.umich.edu { "code": 4297234Sgblack@eecs.umich.edu ''' 4308588Sgblack@eecs.umich.edu Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + 4317234Sgblack@eecs.umich.edu Op1; 4327234Sgblack@eecs.umich.edu ''', 4337234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4347234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 4357234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 4367234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtabIop) 4377234Sgblack@eecs.umich.edu 4387234Sgblack@eecs.umich.edu sxtb16Code = ''' 4397234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4407234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 4417234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 4427234Sgblack@eecs.umich.edu sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 4437234Sgblack@eecs.umich.edu Dest = resTemp; 4447234Sgblack@eecs.umich.edu ''' 4457234Sgblack@eecs.umich.edu sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 4467234Sgblack@eecs.umich.edu { "code": sxtb16Code, 4477234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4487234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 4497234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 4507234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtb16Iop) 4517234Sgblack@eecs.umich.edu 4527234Sgblack@eecs.umich.edu sxtab16Code = ''' 4537234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4547234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 4557234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 4567234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 4577234Sgblack@eecs.umich.edu sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 4587234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 4597234Sgblack@eecs.umich.edu Dest = resTemp; 4607234Sgblack@eecs.umich.edu ''' 4617234Sgblack@eecs.umich.edu sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 4627234Sgblack@eecs.umich.edu { "code": sxtab16Code, 4637234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4647234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 4657234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 4667234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtab16Iop) 4677234Sgblack@eecs.umich.edu 4687234Sgblack@eecs.umich.edu sxthCode = ''' 4697234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 4707234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4717234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 4727234Sgblack@eecs.umich.edu ''' 4737234Sgblack@eecs.umich.edu sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 4747234Sgblack@eecs.umich.edu { "code": sxthCode, 4757234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4767234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 4777234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 4787234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 4797234Sgblack@eecs.umich.edu 4807234Sgblack@eecs.umich.edu sxtahCode = ''' 4817234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 4827234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4837234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated) + Op1; 4847234Sgblack@eecs.umich.edu ''' 4857234Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 4867234Sgblack@eecs.umich.edu { "code": sxtahCode, 4877234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4887234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 4897234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 4907234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtahIop) 4917234Sgblack@eecs.umich.edu 4927234Sgblack@eecs.umich.edu uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 4938588Sgblack@eecs.umich.edu { "code": "Dest = (uint8_t)(Op1_ud >> imm);", 4947234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4957234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtbIop) 4967234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 4977234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtbIop) 4987234Sgblack@eecs.umich.edu 4997234Sgblack@eecs.umich.edu uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 5007234Sgblack@eecs.umich.edu { "code": 5018588Sgblack@eecs.umich.edu "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", 5027234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5037234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 5047234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 5057234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 5067234Sgblack@eecs.umich.edu 5077234Sgblack@eecs.umich.edu uxtb16Code = ''' 5087234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5097234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 5107234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5117234Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 5127234Sgblack@eecs.umich.edu Dest = resTemp; 5137234Sgblack@eecs.umich.edu ''' 5147234Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 5157234Sgblack@eecs.umich.edu { "code": uxtb16Code, 5167234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5177234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 5187234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 5197234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtb16Iop) 5207234Sgblack@eecs.umich.edu 5217234Sgblack@eecs.umich.edu uxtab16Code = ''' 5227234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5237234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 5247234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 5257234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 5267234Sgblack@eecs.umich.edu (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 5277234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 5287234Sgblack@eecs.umich.edu Dest = resTemp; 5297234Sgblack@eecs.umich.edu ''' 5307234Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 5317234Sgblack@eecs.umich.edu { "code": uxtab16Code, 5327234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5337234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 5347234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 5357234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 5367234Sgblack@eecs.umich.edu 5377234Sgblack@eecs.umich.edu uxthCode = ''' 5387234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 5397234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 5407234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated; 5417234Sgblack@eecs.umich.edu ''' 5427234Sgblack@eecs.umich.edu uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 5437234Sgblack@eecs.umich.edu { "code": uxthCode, 5447234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5457234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxthIop) 5467234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxthIop) 5477234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxthIop) 5487234Sgblack@eecs.umich.edu 5497234Sgblack@eecs.umich.edu uxtahCode = ''' 5507234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 5517234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 5527234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 5537234Sgblack@eecs.umich.edu ''' 5547234Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 5557234Sgblack@eecs.umich.edu { "code": uxtahCode, 5567234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5577234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 5587234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 5597234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 5607239Sgblack@eecs.umich.edu 5617239Sgblack@eecs.umich.edu selCode = ''' 5627239Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5637239Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 5647239Sgblack@eecs.umich.edu int low = i * 8; 5657239Sgblack@eecs.umich.edu int high = low + 7; 5667239Sgblack@eecs.umich.edu replaceBits(resTemp, high, low, 5678303SAli.Saidi@ARM.com bits(CondCodesGE, i) ? 5687239Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 5697239Sgblack@eecs.umich.edu } 5707239Sgblack@eecs.umich.edu Dest = resTemp; 5717239Sgblack@eecs.umich.edu ''' 5727239Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 5737239Sgblack@eecs.umich.edu { "code": selCode, 5748303SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 5757239Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 5767239Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 5777239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 5787242Sgblack@eecs.umich.edu 5797242Sgblack@eecs.umich.edu usad8Code = ''' 5807242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5817242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 5827242Sgblack@eecs.umich.edu int low = i * 8; 5837242Sgblack@eecs.umich.edu int high = low + 7; 5847242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 5857242Sgblack@eecs.umich.edu bits(Op2, high, low); 5867242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 5877242Sgblack@eecs.umich.edu } 5887242Sgblack@eecs.umich.edu Dest = resTemp; 5897242Sgblack@eecs.umich.edu ''' 5907242Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 5917242Sgblack@eecs.umich.edu { "code": usad8Code, 5927242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5937242Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 5947242Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 5957242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usad8Iop) 5967242Sgblack@eecs.umich.edu 5977242Sgblack@eecs.umich.edu usada8Code = ''' 5987242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 5997242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 6007242Sgblack@eecs.umich.edu int low = i * 8; 6017242Sgblack@eecs.umich.edu int high = low + 7; 6027242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 6037242Sgblack@eecs.umich.edu bits(Op2, high, low); 6047242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 6057242Sgblack@eecs.umich.edu } 6067242Sgblack@eecs.umich.edu Dest = Op3 + resTemp; 6077242Sgblack@eecs.umich.edu ''' 6087242Sgblack@eecs.umich.edu usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 6097242Sgblack@eecs.umich.edu { "code": usada8Code, 6107242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6117242Sgblack@eecs.umich.edu header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 6127242Sgblack@eecs.umich.edu decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 6137242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usada8Iop) 6147247Sgblack@eecs.umich.edu 61510474Sandreas.hansson@arm.com bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n' 6167848SAli.Saidi@ARM.com bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 6177410Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(bkptIop) 6187410Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(bkptIop) 6197410Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(bkptIop) 6207410Sgblack@eecs.umich.edu 62110037SARM gem5 Developers nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop']) 6227247Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(nopIop) 62310037SARM gem5 Developers decoder_output += BasicConstructor64.subst(nopIop) 62410037SARM gem5 Developers exec_output += BasicExecute.subst(nopIop) 6257408Sgblack@eecs.umich.edu 6267418Sgblack@eecs.umich.edu yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 6277418Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 6287418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(yieldIop) 6297418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(yieldIop) 6307418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(yieldIop) 6317418Sgblack@eecs.umich.edu 6327418Sgblack@eecs.umich.edu wfeCode = ''' 63310037SARM gem5 Developers HCR hcr = Hcr; 63410037SARM gem5 Developers CPSR cpsr = Cpsr; 63510037SARM gem5 Developers SCR scr = Scr64; 63610037SARM gem5 Developers SCTLR sctlr = Sctlr; 63710037SARM gem5 Developers 63810037SARM gem5 Developers // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending, 63910037SARM gem5 Developers ThreadContext *tc = xc->tcBase(); 6408285SPrakash.Ramrakhyani@arm.com if (SevMailbox == 1) { 6417418Sgblack@eecs.umich.edu SevMailbox = 0; 64210037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 64311150Smitch.hayenga@arm.com } else if (tc->getCpuPtr()->getInterruptController( 64411150Smitch.hayenga@arm.com tc->threadId())->checkInterrupts(tc)) { 64510037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 64610037SARM gem5 Developers } else if (cpsr.el == EL0 && !sctlr.ntwe) { 64710037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 64810474Sandreas.hansson@arm.com fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00001, 64910474Sandreas.hansson@arm.com EC_TRAPPED_WFI_WFE); 65010037SARM gem5 Developers } else if (ArmSystem::haveVirtualization(tc) && 65110037SARM gem5 Developers !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && 65210037SARM gem5 Developers hcr.twe) { 65310037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 65410474Sandreas.hansson@arm.com fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00001, 65510474Sandreas.hansson@arm.com EC_TRAPPED_WFI_WFE); 65610037SARM gem5 Developers } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twe) { 65710037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 65810474Sandreas.hansson@arm.com fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00001, 65910474Sandreas.hansson@arm.com EC_TRAPPED_WFI_WFE); 6608285SPrakash.Ramrakhyani@arm.com } else { 66110037SARM gem5 Developers PseudoInst::quiesce(tc); 6628142SAli.Saidi@ARM.com } 6637418Sgblack@eecs.umich.edu ''' 6648518Sgeoffrey.blake@arm.com wfePredFixUpCode = ''' 6658518Sgeoffrey.blake@arm.com // WFE is predicated false, reset SevMailbox to reduce spurious sleeps 6668518Sgeoffrey.blake@arm.com // and SEV interrupts 6678518Sgeoffrey.blake@arm.com SevMailbox = 1; 6688518Sgeoffrey.blake@arm.com ''' 6697418Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 6708518Sgeoffrey.blake@arm.com { "code" : wfeCode, 6718518Sgeoffrey.blake@arm.com "pred_fixup" : wfePredFixUpCode, 6728518Sgeoffrey.blake@arm.com "predicate_test" : predicateTest }, 6738733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsQuiesce", 6748733Sgeoffrey.blake@arm.com "IsSerializeAfter", "IsUnverifiable"]) 6757418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 6767418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfeIop) 6778518Sgeoffrey.blake@arm.com exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) 6787418Sgblack@eecs.umich.edu 6797418Sgblack@eecs.umich.edu wfiCode = ''' 68010037SARM gem5 Developers HCR hcr = Hcr; 68110037SARM gem5 Developers CPSR cpsr = Cpsr; 68210037SARM gem5 Developers SCR scr = Scr64; 68310037SARM gem5 Developers SCTLR sctlr = Sctlr; 68410037SARM gem5 Developers 6858285SPrakash.Ramrakhyani@arm.com // WFI doesn't sleep if interrupts are pending (masked or not) 68610037SARM gem5 Developers ThreadContext *tc = xc->tcBase(); 68711150Smitch.hayenga@arm.com if (tc->getCpuPtr()->getInterruptController( 68811150Smitch.hayenga@arm.com tc->threadId())->checkWfiWake(hcr, cpsr, scr)) { 68910037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 69010037SARM gem5 Developers } else if (cpsr.el == EL0 && !sctlr.ntwi) { 69110037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 69210474Sandreas.hansson@arm.com fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00000, 69310474Sandreas.hansson@arm.com EC_TRAPPED_WFI_WFE); 69410037SARM gem5 Developers } else if (ArmSystem::haveVirtualization(tc) && hcr.twi && 69510037SARM gem5 Developers (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) { 69610037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 69710474Sandreas.hansson@arm.com fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00000, 69810474Sandreas.hansson@arm.com EC_TRAPPED_WFI_WFE); 69910037SARM gem5 Developers } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) { 70010037SARM gem5 Developers PseudoInst::quiesceSkip(tc); 70110474Sandreas.hansson@arm.com fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000, 70210474Sandreas.hansson@arm.com EC_TRAPPED_WFI_WFE); 7038285SPrakash.Ramrakhyani@arm.com } else { 70410037SARM gem5 Developers PseudoInst::quiesce(tc); 7058285SPrakash.Ramrakhyani@arm.com } 70611150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 7077418Sgblack@eecs.umich.edu ''' 7087418Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 7097418Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 7108733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsQuiesce", 7118733Sgeoffrey.blake@arm.com "IsSerializeAfter", "IsUnverifiable"]) 7127418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfiIop) 7137418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfiIop) 7148142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(wfiIop) 7157418Sgblack@eecs.umich.edu 7167418Sgblack@eecs.umich.edu sevCode = ''' 7178142SAli.Saidi@ARM.com SevMailbox = 1; 7187418Sgblack@eecs.umich.edu System *sys = xc->tcBase()->getSystemPtr(); 7197418Sgblack@eecs.umich.edu for (int x = 0; x < sys->numContexts(); x++) { 7207418Sgblack@eecs.umich.edu ThreadContext *oc = sys->getThreadContext(x); 7218285SPrakash.Ramrakhyani@arm.com if (oc == xc->tcBase()) 7228285SPrakash.Ramrakhyani@arm.com continue; 7238518Sgeoffrey.blake@arm.com // Wake CPU with interrupt if they were sleeping 7248285SPrakash.Ramrakhyani@arm.com if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 7258518Sgeoffrey.blake@arm.com // Post Interrupt and wake cpu if needed 72611150Smitch.hayenga@arm.com oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0); 7278142SAli.Saidi@ARM.com } 7287418Sgblack@eecs.umich.edu } 7297418Sgblack@eecs.umich.edu ''' 7307418Sgblack@eecs.umich.edu sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 7317418Sgblack@eecs.umich.edu { "code" : sevCode, "predicate_test" : predicateTest }, 7328733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 7337418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sevIop) 7347418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sevIop) 7357418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sevIop) 7367418Sgblack@eecs.umich.edu 73710037SARM gem5 Developers sevlCode = ''' 73810037SARM gem5 Developers SevMailbox = 1; 73910037SARM gem5 Developers ''' 74010037SARM gem5 Developers sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \ 74110037SARM gem5 Developers { "code" : sevlCode, "predicate_test" : predicateTest }, 74210037SARM gem5 Developers ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 74310037SARM gem5 Developers header_output += BasicDeclare.subst(sevlIop) 74410037SARM gem5 Developers decoder_output += BasicConstructor.subst(sevlIop) 74510037SARM gem5 Developers exec_output += BasicExecute.subst(sevlIop) 74610037SARM gem5 Developers 7477408Sgblack@eecs.umich.edu itIop = InstObjParams("it", "ItInst", "PredOp", \ 7488205SAli.Saidi@ARM.com { "code" : ";", 7498908Sgeoffrey.blake@arm.com "predicate_test" : predicateTest }, []) 7507408Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(itIop) 7517408Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(itIop) 7527408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(itIop) 7537409Sgblack@eecs.umich.edu unknownCode = ''' 75410474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, true); 7557409Sgblack@eecs.umich.edu ''' 7567409Sgblack@eecs.umich.edu unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 7577409Sgblack@eecs.umich.edu { "code": unknownCode, 7587409Sgblack@eecs.umich.edu "predicate_test": predicateTest }) 7597409Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(unknownIop) 7607409Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(unknownIop) 7617409Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(unknownIop) 7627254Sgblack@eecs.umich.edu 7637254Sgblack@eecs.umich.edu ubfxCode = ''' 7647254Sgblack@eecs.umich.edu Dest = bits(Op1, imm2, imm1); 7657254Sgblack@eecs.umich.edu ''' 7667254Sgblack@eecs.umich.edu ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 7677254Sgblack@eecs.umich.edu { "code": ubfxCode, 7687254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7697254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 7707254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 7717254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ubfxIop) 7727254Sgblack@eecs.umich.edu 7737254Sgblack@eecs.umich.edu sbfxCode = ''' 7747254Sgblack@eecs.umich.edu int32_t resTemp = bits(Op1, imm2, imm1); 7757254Sgblack@eecs.umich.edu Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 7767254Sgblack@eecs.umich.edu ''' 7777254Sgblack@eecs.umich.edu sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 7787254Sgblack@eecs.umich.edu { "code": sbfxCode, 7797254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7807254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 7817254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 7827254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sbfxIop) 7837257Sgblack@eecs.umich.edu 7847257Sgblack@eecs.umich.edu bfcCode = ''' 7857257Sgblack@eecs.umich.edu Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 7867257Sgblack@eecs.umich.edu ''' 7877257Sgblack@eecs.umich.edu bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 7887257Sgblack@eecs.umich.edu { "code": bfcCode, 7897257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7907257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfcIop) 7917257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 7927257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfcIop) 7937257Sgblack@eecs.umich.edu 7947257Sgblack@eecs.umich.edu bfiCode = ''' 7957257Sgblack@eecs.umich.edu uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 7967257Sgblack@eecs.umich.edu Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 7977257Sgblack@eecs.umich.edu ''' 7987257Sgblack@eecs.umich.edu bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 7997257Sgblack@eecs.umich.edu { "code": bfiCode, 8007257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8017257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfiIop) 8027257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 8037257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfiIop) 8047262Sgblack@eecs.umich.edu 8058868SMatt.Horsnell@arm.com mrc14code = ''' 80612106SRekai.GonzalezAlberquilla@arm.com MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 80712106SRekai.GonzalezAlberquilla@arm.com RegId(MiscRegClass, op1)).index(); 80811939Snikos.nikoleris@arm.com bool can_read, undefined; 80911939Snikos.nikoleris@arm.com std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 81011939Snikos.nikoleris@arm.com if (!can_read || undefined) { 81110474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 81210474Sandreas.hansson@arm.com mnemonic); 81310037SARM gem5 Developers } 81410037SARM gem5 Developers if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr, 81510037SARM gem5 Developers Hstr, Hcptr, imm)) { 81610474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 81710474Sandreas.hansson@arm.com EC_TRAPPED_CP14_MCR_MRC); 8188868SMatt.Horsnell@arm.com } 8198868SMatt.Horsnell@arm.com Dest = MiscOp1; 8208868SMatt.Horsnell@arm.com ''' 8218868SMatt.Horsnell@arm.com 82210037SARM gem5 Developers mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp", 8238868SMatt.Horsnell@arm.com { "code": mrc14code, 8248868SMatt.Horsnell@arm.com "predicate_test": predicateTest }, []) 82510037SARM gem5 Developers header_output += RegRegImmOpDeclare.subst(mrc14Iop) 82610037SARM gem5 Developers decoder_output += RegRegImmOpConstructor.subst(mrc14Iop) 8278868SMatt.Horsnell@arm.com exec_output += PredOpExecute.subst(mrc14Iop) 8288868SMatt.Horsnell@arm.com 8298868SMatt.Horsnell@arm.com 8308868SMatt.Horsnell@arm.com mcr14code = ''' 83112106SRekai.GonzalezAlberquilla@arm.com MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( 83212106SRekai.GonzalezAlberquilla@arm.com RegId(MiscRegClass, dest)).index(); 83311939Snikos.nikoleris@arm.com bool can_write, undefined; 83411939Snikos.nikoleris@arm.com std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 83511939Snikos.nikoleris@arm.com if (undefined || !can_write) { 83610474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 83710474Sandreas.hansson@arm.com mnemonic); 83810037SARM gem5 Developers } 83910037SARM gem5 Developers if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, 84010037SARM gem5 Developers Hstr, Hcptr, imm)) { 84110474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 84210474Sandreas.hansson@arm.com EC_TRAPPED_CP14_MCR_MRC); 8438868SMatt.Horsnell@arm.com } 8448868SMatt.Horsnell@arm.com MiscDest = Op1; 8458868SMatt.Horsnell@arm.com ''' 84610037SARM gem5 Developers mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp", 8478868SMatt.Horsnell@arm.com { "code": mcr14code, 8488868SMatt.Horsnell@arm.com "predicate_test": predicateTest }, 8498868SMatt.Horsnell@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 85010037SARM gem5 Developers header_output += RegRegImmOpDeclare.subst(mcr14Iop) 85110037SARM gem5 Developers decoder_output += RegRegImmOpConstructor.subst(mcr14Iop) 8528868SMatt.Horsnell@arm.com exec_output += PredOpExecute.subst(mcr14Iop) 8538868SMatt.Horsnell@arm.com 85410037SARM gem5 Developers mrc15code = ''' 85510037SARM gem5 Developers int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase()); 85610037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 85712106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 85812106SRekai.GonzalezAlberquilla@arm.com preFlatOp1)).index(); 85910037SARM gem5 Developers bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 86010037SARM gem5 Developers Hcptr, imm); 86111939Snikos.nikoleris@arm.com bool can_read, undefined; 86211939Snikos.nikoleris@arm.com std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 86310037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 86410037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 86510037SARM gem5 Developers // IS accessable. 86611939Snikos.nikoleris@arm.com if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 86711939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 86810474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 86910474Sandreas.hansson@arm.com mnemonic); 8708782Sgblack@eecs.umich.edu } 87110037SARM gem5 Developers if (hypTrap) { 87210474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 87310474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCR_MRC); 87410037SARM gem5 Developers } 87510037SARM gem5 Developers Dest = MiscNsBankedOp1; 8767347SAli.Saidi@ARM.com ''' 8777347SAli.Saidi@ARM.com 87810418Sandreas.hansson@arm.com mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", 8797347SAli.Saidi@ARM.com { "code": mrc15code, 8807262Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 88110418Sandreas.hansson@arm.com header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop) 88210418Sandreas.hansson@arm.com decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop) 8837262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15Iop) 8847262Sgblack@eecs.umich.edu 8857347SAli.Saidi@ARM.com 8867347SAli.Saidi@ARM.com mcr15code = ''' 88710037SARM gem5 Developers int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase()); 88810037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 88912106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 89012106SRekai.GonzalezAlberquilla@arm.com preFlatDest)).index(); 89110037SARM gem5 Developers bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, 89210037SARM gem5 Developers Hcptr, imm); 89311939Snikos.nikoleris@arm.com bool can_write, undefined; 89411939Snikos.nikoleris@arm.com std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 89510037SARM gem5 Developers 89610037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 89710037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 89810037SARM gem5 Developers // IS accessable. 89911939Snikos.nikoleris@arm.com if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 90011939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 90110474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 90210474Sandreas.hansson@arm.com mnemonic); 9038782Sgblack@eecs.umich.edu } 90410037SARM gem5 Developers if (hypTrap) { 90510474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 90610474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCR_MRC); 90710037SARM gem5 Developers } 90810037SARM gem5 Developers MiscNsBankedDest = Op1; 9097347SAli.Saidi@ARM.com ''' 91010418Sandreas.hansson@arm.com mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", 9117347SAli.Saidi@ARM.com { "code": mcr15code, 9127599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 9137599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 91410418Sandreas.hansson@arm.com header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop) 91510418Sandreas.hansson@arm.com decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop) 9167262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15Iop) 9177283Sgblack@eecs.umich.edu 9187420Sgblack@eecs.umich.edu 91910037SARM gem5 Developers mrrc15code = ''' 92010037SARM gem5 Developers int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase()); 92110037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 92212106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 92312106SRekai.GonzalezAlberquilla@arm.com preFlatOp1)).index(); 92410037SARM gem5 Developers bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 92511939Snikos.nikoleris@arm.com bool can_read, undefined; 92611939Snikos.nikoleris@arm.com std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); 92710037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 92810037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 92910037SARM gem5 Developers // IS accessable. 93011939Snikos.nikoleris@arm.com if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) && 93111939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 93210474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 93310474Sandreas.hansson@arm.com mnemonic); 93410037SARM gem5 Developers } 93510037SARM gem5 Developers if (hypTrap) { 93610474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 93710474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCRR_MRRC); 93810037SARM gem5 Developers } 93910037SARM gem5 Developers Dest = bits(MiscNsBankedOp164, 63, 32); 94010037SARM gem5 Developers Dest2 = bits(MiscNsBankedOp164, 31, 0); 94110037SARM gem5 Developers ''' 94210037SARM gem5 Developers mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp", 94310037SARM gem5 Developers { "code": mrrc15code, 94410037SARM gem5 Developers "predicate_test": predicateTest }, []) 94510037SARM gem5 Developers header_output += MrrcOpDeclare.subst(mrrc15Iop) 94610037SARM gem5 Developers decoder_output += MrrcOpConstructor.subst(mrrc15Iop) 94710037SARM gem5 Developers exec_output += PredOpExecute.subst(mrrc15Iop) 94810037SARM gem5 Developers 94910037SARM gem5 Developers 95010037SARM gem5 Developers mcrr15code = ''' 95110037SARM gem5 Developers int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase()); 95210037SARM gem5 Developers MiscRegIndex miscReg = (MiscRegIndex) 95312106SRekai.GonzalezAlberquilla@arm.com xc->tcBase()->flattenRegId(RegId(MiscRegClass, 95412106SRekai.GonzalezAlberquilla@arm.com preFlatDest)).index(); 95510037SARM gem5 Developers bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm); 95611939Snikos.nikoleris@arm.com bool can_write, undefined; 95711939Snikos.nikoleris@arm.com std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); 95810037SARM gem5 Developers 95910037SARM gem5 Developers // if we're in non secure PL1 mode then we can trap regargless of whether 96010037SARM gem5 Developers // the register is accessable, in other modes we trap if only if the register 96110037SARM gem5 Developers // IS accessable. 96211939Snikos.nikoleris@arm.com if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) && 96311939Snikos.nikoleris@arm.com !inSecureState(Scr, Cpsr)))) { 96410474Sandreas.hansson@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 96510474Sandreas.hansson@arm.com mnemonic); 96610037SARM gem5 Developers } 96710037SARM gem5 Developers if (hypTrap) { 96810474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 96910474Sandreas.hansson@arm.com EC_TRAPPED_CP15_MCRR_MRRC); 97010037SARM gem5 Developers } 97110037SARM gem5 Developers MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2; 97210037SARM gem5 Developers ''' 97310037SARM gem5 Developers mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp", 97410037SARM gem5 Developers { "code": mcrr15code, 97510037SARM gem5 Developers "predicate_test": predicateTest }, []) 97610037SARM gem5 Developers header_output += McrrOpDeclare.subst(mcrr15Iop) 97710037SARM gem5 Developers decoder_output += McrrOpConstructor.subst(mcrr15Iop) 97810037SARM gem5 Developers exec_output += PredOpExecute.subst(mcrr15Iop) 97910037SARM gem5 Developers 9807420Sgblack@eecs.umich.edu 9817283Sgblack@eecs.umich.edu enterxCode = ''' 9827797Sgblack@eecs.umich.edu NextThumb = true; 9837797Sgblack@eecs.umich.edu NextJazelle = true; 9847283Sgblack@eecs.umich.edu ''' 9857283Sgblack@eecs.umich.edu enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 9867283Sgblack@eecs.umich.edu { "code": enterxCode, 9877283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9887283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(enterxIop) 9897283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(enterxIop) 9907283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(enterxIop) 9917283Sgblack@eecs.umich.edu 9927283Sgblack@eecs.umich.edu leavexCode = ''' 9937797Sgblack@eecs.umich.edu NextThumb = true; 9947797Sgblack@eecs.umich.edu NextJazelle = false; 9957283Sgblack@eecs.umich.edu ''' 9967283Sgblack@eecs.umich.edu leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 9977283Sgblack@eecs.umich.edu { "code": leavexCode, 9987283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9997283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(leavexIop) 10007283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(leavexIop) 10017283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(leavexIop) 10027307Sgblack@eecs.umich.edu 10037307Sgblack@eecs.umich.edu setendCode = ''' 10047307Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 10057307Sgblack@eecs.umich.edu cpsr.e = imm; 10067307Sgblack@eecs.umich.edu Cpsr = cpsr; 10077307Sgblack@eecs.umich.edu ''' 10087307Sgblack@eecs.umich.edu setendIop = InstObjParams("setend", "Setend", "ImmOp", 10097307Sgblack@eecs.umich.edu { "code": setendCode, 10107648SAli.Saidi@ARM.com "predicate_test": predicateTest }, 10117648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 10127307Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(setendIop) 10137307Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(setendIop) 10147307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(setendIop) 10157315Sgblack@eecs.umich.edu 10167603SGene.Wu@arm.com clrexCode = ''' 10178209SAli.Saidi@ARM.com LLSCLock = 0; 10187603SGene.Wu@arm.com ''' 10197603SGene.Wu@arm.com clrexIop = InstObjParams("clrex", "Clrex","PredOp", 10207603SGene.Wu@arm.com { "code": clrexCode, 10217603SGene.Wu@arm.com "predicate_test": predicateTest },[]) 10228209SAli.Saidi@ARM.com header_output += BasicDeclare.subst(clrexIop) 10237603SGene.Wu@arm.com decoder_output += BasicConstructor.subst(clrexIop) 10247603SGene.Wu@arm.com exec_output += PredOpExecute.subst(clrexIop) 10257603SGene.Wu@arm.com 10267605SGene.Wu@arm.com isbCode = ''' 102710037SARM gem5 Developers // If the barrier is due to a CP15 access check for hyp traps 102810037SARM gem5 Developers if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr, 102910037SARM gem5 Developers Hdcr, Hstr, Hcptr, imm)) { 103010474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 103110037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC); 103210037SARM gem5 Developers } 103310474Sandreas.hansson@arm.com fault = std::make_shared<FlushPipe>(); 10347605SGene.Wu@arm.com ''' 103510037SARM gem5 Developers isbIop = InstObjParams("isb", "Isb", "ImmOp", 10367605SGene.Wu@arm.com {"code": isbCode, 10378068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 10388068SAli.Saidi@ARM.com ['IsSerializeAfter']) 103910037SARM gem5 Developers header_output += ImmOpDeclare.subst(isbIop) 104010037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(isbIop) 10417605SGene.Wu@arm.com exec_output += PredOpExecute.subst(isbIop) 10427605SGene.Wu@arm.com 10437605SGene.Wu@arm.com dsbCode = ''' 104410037SARM gem5 Developers // If the barrier is due to a CP15 access check for hyp traps 104510037SARM gem5 Developers if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr, 104610037SARM gem5 Developers Hdcr, Hstr, Hcptr, imm)) { 104710474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 104810037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC); 104910037SARM gem5 Developers } 105010474Sandreas.hansson@arm.com fault = std::make_shared<FlushPipe>(); 10517605SGene.Wu@arm.com ''' 105210037SARM gem5 Developers dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", 10537605SGene.Wu@arm.com {"code": dsbCode, 10548068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 10558068SAli.Saidi@ARM.com ['IsMemBarrier', 'IsSerializeAfter']) 105610037SARM gem5 Developers header_output += ImmOpDeclare.subst(dsbIop) 105710037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(dsbIop) 10587605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dsbIop) 10597605SGene.Wu@arm.com 10607605SGene.Wu@arm.com dmbCode = ''' 106110037SARM gem5 Developers // If the barrier is due to a CP15 access check for hyp traps 106210037SARM gem5 Developers if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr, 106310037SARM gem5 Developers Hdcr, Hstr, Hcptr, imm)) { 106410474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 106510037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC); 106610037SARM gem5 Developers } 10677605SGene.Wu@arm.com ''' 106810037SARM gem5 Developers dmbIop = InstObjParams("dmb", "Dmb", "ImmOp", 10697605SGene.Wu@arm.com {"code": dmbCode, 10708068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 10718068SAli.Saidi@ARM.com ['IsMemBarrier']) 107210037SARM gem5 Developers header_output += ImmOpDeclare.subst(dmbIop) 107310037SARM gem5 Developers decoder_output += ImmOpConstructor.subst(dmbIop) 10747605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dmbIop) 10757605SGene.Wu@arm.com 10767613SGene.Wu@arm.com dbgCode = ''' 10777613SGene.Wu@arm.com ''' 10787613SGene.Wu@arm.com dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 10797613SGene.Wu@arm.com {"code": dbgCode, 10807613SGene.Wu@arm.com "predicate_test": predicateTest}) 10817613SGene.Wu@arm.com header_output += BasicDeclare.subst(dbgIop) 10827613SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dbgIop) 10837613SGene.Wu@arm.com exec_output += PredOpExecute.subst(dbgIop) 10847613SGene.Wu@arm.com 10857315Sgblack@eecs.umich.edu cpsCode = ''' 10867315Sgblack@eecs.umich.edu uint32_t mode = bits(imm, 4, 0); 10877315Sgblack@eecs.umich.edu uint32_t f = bits(imm, 5); 10887315Sgblack@eecs.umich.edu uint32_t i = bits(imm, 6); 10897315Sgblack@eecs.umich.edu uint32_t a = bits(imm, 7); 10907315Sgblack@eecs.umich.edu bool setMode = bits(imm, 8); 10917315Sgblack@eecs.umich.edu bool enable = bits(imm, 9); 10927315Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 10937400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 10947315Sgblack@eecs.umich.edu if (cpsr.mode != MODE_USER) { 10957315Sgblack@eecs.umich.edu if (enable) { 10967315Sgblack@eecs.umich.edu if (f) cpsr.f = 0; 10977315Sgblack@eecs.umich.edu if (i) cpsr.i = 0; 10987315Sgblack@eecs.umich.edu if (a) cpsr.a = 0; 10997315Sgblack@eecs.umich.edu } else { 11007400SAli.Saidi@ARM.com if (f && !sctlr.nmfi) cpsr.f = 1; 11017315Sgblack@eecs.umich.edu if (i) cpsr.i = 1; 11027315Sgblack@eecs.umich.edu if (a) cpsr.a = 1; 11037315Sgblack@eecs.umich.edu } 11047315Sgblack@eecs.umich.edu if (setMode) { 11057315Sgblack@eecs.umich.edu cpsr.mode = mode; 11067315Sgblack@eecs.umich.edu } 11077315Sgblack@eecs.umich.edu } 11087315Sgblack@eecs.umich.edu Cpsr = cpsr; 11097315Sgblack@eecs.umich.edu ''' 11107315Sgblack@eecs.umich.edu cpsIop = InstObjParams("cps", "Cps", "ImmOp", 11117315Sgblack@eecs.umich.edu { "code": cpsCode, 11127599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 11137599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 11147315Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(cpsIop) 11157315Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(cpsIop) 11167315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(cpsIop) 11177202Sgblack@eecs.umich.edu}}; 1118