misc.isa revision 12106
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*-
27199Sgblack@eecs.umich.edu
311939Snikos.nikoleris@arm.com// Copyright (c) 2010-2013,2017 ARM Limited
47199Sgblack@eecs.umich.edu// All rights reserved
57199Sgblack@eecs.umich.edu//
67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
107199Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
147199Sgblack@eecs.umich.edu//
157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
247199Sgblack@eecs.umich.edu// this software without specific prior written permission.
257199Sgblack@eecs.umich.edu//
267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
377199Sgblack@eecs.umich.edu//
387199Sgblack@eecs.umich.edu// Authors: Gabe Black
397199Sgblack@eecs.umich.edu
407199Sgblack@eecs.umich.edulet {{
417199Sgblack@eecs.umich.edu
427199Sgblack@eecs.umich.edu    svcCode = '''
4310474Sandreas.hansson@arm.com    fault = std::make_shared<SupervisorCall>(machInst, imm);
4410037SARM gem5 Developers    '''
4510037SARM gem5 Developers
4610037SARM gem5 Developers    svcIop = InstObjParams("svc", "Svc", "ImmOp",
4710037SARM gem5 Developers                           { "code": svcCode,
4810037SARM gem5 Developers                             "predicate_test": predicateTest },
4910037SARM gem5 Developers                           ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
5010037SARM gem5 Developers    header_output = ImmOpDeclare.subst(svcIop)
5110037SARM gem5 Developers    decoder_output = ImmOpConstructor.subst(svcIop)
5210037SARM gem5 Developers    exec_output = PredOpExecute.subst(svcIop)
5310037SARM gem5 Developers
5410037SARM gem5 Developers    smcCode = '''
5510037SARM gem5 Developers    HCR  hcr  = Hcr;
5610037SARM gem5 Developers    CPSR cpsr = Cpsr;
5710037SARM gem5 Developers    SCR  scr  = Scr;
5810037SARM gem5 Developers
5910037SARM gem5 Developers    if ((cpsr.mode != MODE_USER) && FullSystem) {
6010037SARM gem5 Developers        if (ArmSystem::haveVirtualization(xc->tcBase()) &&
6110037SARM gem5 Developers            !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
6210474Sandreas.hansson@arm.com            fault = std::make_shared<HypervisorTrap>(machInst, 0,
6310474Sandreas.hansson@arm.com                                                     EC_SMC_TO_HYP);
6410037SARM gem5 Developers        } else {
6510037SARM gem5 Developers            if (scr.scd) {
6610037SARM gem5 Developers                fault = disabledFault();
6710037SARM gem5 Developers            } else {
6810474Sandreas.hansson@arm.com                fault = std::make_shared<SecureMonitorCall>(machInst);
6910037SARM gem5 Developers            }
7010037SARM gem5 Developers        }
718782Sgblack@eecs.umich.edu    } else {
7210037SARM gem5 Developers        fault = disabledFault();
738782Sgblack@eecs.umich.edu    }
747199Sgblack@eecs.umich.edu    '''
757199Sgblack@eecs.umich.edu
7610037SARM gem5 Developers    smcIop = InstObjParams("smc", "Smc", "PredOp",
7710037SARM gem5 Developers                           { "code": smcCode,
788628SAli.Saidi@ARM.com                             "predicate_test": predicateTest },
7910037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
8010037SARM gem5 Developers    header_output += BasicDeclare.subst(smcIop)
8110037SARM gem5 Developers    decoder_output += BasicConstructor.subst(smcIop)
8210037SARM gem5 Developers    exec_output += PredOpExecute.subst(smcIop)
8310037SARM gem5 Developers
8410037SARM gem5 Developers    hvcCode = '''
8510037SARM gem5 Developers    CPSR cpsr = Cpsr;
8610037SARM gem5 Developers    SCR  scr  = Scr;
8710037SARM gem5 Developers
8810037SARM gem5 Developers    // Filter out the various cases where this instruction isn't defined
8910037SARM gem5 Developers    if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
9010037SARM gem5 Developers        (cpsr.mode == MODE_USER) ||
9110037SARM gem5 Developers        (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
9210037SARM gem5 Developers        fault = disabledFault();
9310037SARM gem5 Developers    } else {
9410474Sandreas.hansson@arm.com        fault = std::make_shared<HypervisorCall>(machInst, imm);
9510037SARM gem5 Developers    }
9610037SARM gem5 Developers    '''
9710037SARM gem5 Developers
9810037SARM gem5 Developers    hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
9910037SARM gem5 Developers                           { "code": hvcCode,
10010037SARM gem5 Developers                             "predicate_test": predicateTest },
10110037SARM gem5 Developers                           ["IsNonSpeculative", "IsSerializeAfter"])
10210037SARM gem5 Developers    header_output += ImmOpDeclare.subst(hvcIop)
10310037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(hvcIop)
10410037SARM gem5 Developers    exec_output += PredOpExecute.subst(hvcIop)
10510037SARM gem5 Developers
10610037SARM gem5 Developers    eretCode = '''
10710037SARM gem5 Developers        SCTLR sctlr   = Sctlr;
10810037SARM gem5 Developers        CPSR old_cpsr = Cpsr;
10910037SARM gem5 Developers        old_cpsr.nz   = CondCodesNZ;
11010037SARM gem5 Developers        old_cpsr.c    = CondCodesC;
11110037SARM gem5 Developers        old_cpsr.v    = CondCodesV;
11210037SARM gem5 Developers        old_cpsr.ge   = CondCodesGE;
11310037SARM gem5 Developers
11410037SARM gem5 Developers        CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
11510037SARM gem5 Developers                            true, sctlr.nmfi, xc->tcBase());
11610037SARM gem5 Developers        Cpsr        = ~CondCodesMask & new_cpsr;
11710037SARM gem5 Developers        CondCodesNZ = new_cpsr.nz;
11810037SARM gem5 Developers        CondCodesC  = new_cpsr.c;
11910037SARM gem5 Developers        CondCodesV  = new_cpsr.v;
12010037SARM gem5 Developers        CondCodesGE = new_cpsr.ge;
12110037SARM gem5 Developers
12210037SARM gem5 Developers        NextThumb = (new_cpsr).t;
12310037SARM gem5 Developers                    NextJazelle = (new_cpsr).j;
12410037SARM gem5 Developers                    NextItState = (((new_cpsr).it2 << 2) & 0xFC)
12510037SARM gem5 Developers                        | ((new_cpsr).it1 & 0x3);
12610037SARM gem5 Developers
12710037SARM gem5 Developers        NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
12810037SARM gem5 Developers    '''
12910037SARM gem5 Developers
13010037SARM gem5 Developers    eretIop = InstObjParams("eret", "Eret", "PredOp",
13110037SARM gem5 Developers                           { "code": eretCode,
13210037SARM gem5 Developers                             "predicate_test": predicateTest },
13311355Smitch.hayenga@arm.com                           ["IsNonSpeculative", "IsSerializeAfter",
13411355Smitch.hayenga@arm.com                            "IsSquashAfter"])
13510037SARM gem5 Developers    header_output += BasicDeclare.subst(eretIop)
13610037SARM gem5 Developers    decoder_output += BasicConstructor.subst(eretIop)
13710037SARM gem5 Developers    exec_output += PredOpExecute.subst(eretIop)
13810037SARM gem5 Developers
13910037SARM gem5 Developers
1407199Sgblack@eecs.umich.edu
1417199Sgblack@eecs.umich.edu}};
1427202Sgblack@eecs.umich.edu
1437202Sgblack@eecs.umich.edulet {{
1447202Sgblack@eecs.umich.edu
1457202Sgblack@eecs.umich.edu    header_output = decoder_output = exec_output = ""
1467202Sgblack@eecs.umich.edu
1478301SAli.Saidi@ARM.com    mrsCpsrCode = '''
1488303SAli.Saidi@ARM.com        CPSR cpsr = Cpsr;
1498303SAli.Saidi@ARM.com        cpsr.nz = CondCodesNZ;
1508303SAli.Saidi@ARM.com        cpsr.c = CondCodesC;
1518303SAli.Saidi@ARM.com        cpsr.v = CondCodesV;
1528303SAli.Saidi@ARM.com        cpsr.ge = CondCodesGE;
1538303SAli.Saidi@ARM.com        Dest = cpsr & 0xF8FF03DF
1548301SAli.Saidi@ARM.com    '''
1558301SAli.Saidi@ARM.com
1567202Sgblack@eecs.umich.edu    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
1577202Sgblack@eecs.umich.edu                               { "code": mrsCpsrCode,
1587599Sminkyu.jeong@arm.com                                 "predicate_test": condPredicateTest },
1597783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
1607202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsCpsrIop)
1617202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsCpsrIop)
1627202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsCpsrIop)
1637202Sgblack@eecs.umich.edu
1647202Sgblack@eecs.umich.edu    mrsSpsrCode = "Dest = Spsr"
1657202Sgblack@eecs.umich.edu    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
1667202Sgblack@eecs.umich.edu                               { "code": mrsSpsrCode,
1677599Sminkyu.jeong@arm.com                                 "predicate_test": predicateTest },
1687783SGiacomo.Gabrielli@arm.com                               ["IsSerializeBefore"])
1697202Sgblack@eecs.umich.edu    header_output += MrsDeclare.subst(mrsSpsrIop)
1707202Sgblack@eecs.umich.edu    decoder_output += MrsConstructor.subst(mrsSpsrIop)
1717202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrsSpsrIop)
1727202Sgblack@eecs.umich.edu
17310037SARM gem5 Developers    mrsBankedRegCode = '''
17410037SARM gem5 Developers        bool isIntReg;
17510037SARM gem5 Developers        int  regIdx;
17610037SARM gem5 Developers
17710037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
17810037SARM gem5 Developers            if (isIntReg) {
17910037SARM gem5 Developers                Dest = DecodedBankedIntReg;
18010037SARM gem5 Developers            } else {
18110037SARM gem5 Developers                Dest = xc->readMiscReg(regIdx);
18210037SARM gem5 Developers            }
18310037SARM gem5 Developers        } else {
18410474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
18510474Sandreas.hansson@arm.com                                                          mnemonic);
18610037SARM gem5 Developers        }
18710037SARM gem5 Developers    '''
18810037SARM gem5 Developers    mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
18910037SARM gem5 Developers                                    { "code": mrsBankedRegCode,
19010037SARM gem5 Developers                                      "predicate_test": predicateTest },
19110037SARM gem5 Developers                                    ["IsSerializeBefore"])
19210037SARM gem5 Developers    header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
19310037SARM gem5 Developers    decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
19410037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrsBankedRegIop)
19510037SARM gem5 Developers
19610037SARM gem5 Developers    msrBankedRegCode = '''
19710037SARM gem5 Developers        bool isIntReg;
19810037SARM gem5 Developers        int  regIdx;
19910037SARM gem5 Developers
20010037SARM gem5 Developers        if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
20110037SARM gem5 Developers            if (isIntReg) {
20210037SARM gem5 Developers                // This is a bit nasty, you would have thought that
20310037SARM gem5 Developers                // DecodedBankedIntReg wouldn't be written to unless the
20410037SARM gem5 Developers                // conditions on the IF statements above are met, however if
20510037SARM gem5 Developers                // you look at the generated C code you'll find that they are.
20610037SARM gem5 Developers                // However this is safe as DecodedBankedIntReg (which is used
20710037SARM gem5 Developers                // in operands.isa to get the index of DecodedBankedIntReg)
20810037SARM gem5 Developers                // will return INTREG_DUMMY if its not a valid integer
20910037SARM gem5 Developers                // register, so redirecting the write to somewhere we don't
21010037SARM gem5 Developers                // care about.
21110037SARM gem5 Developers                DecodedBankedIntReg = Op1;
21210037SARM gem5 Developers            } else {
21310037SARM gem5 Developers                xc->setMiscReg(regIdx, Op1);
21410037SARM gem5 Developers            }
21510037SARM gem5 Developers        } else {
21610474Sandreas.hansson@arm.com            return std::make_shared<UndefinedInstruction>(machInst, false,
21710474Sandreas.hansson@arm.com                                                          mnemonic);
21810037SARM gem5 Developers        }
21910037SARM gem5 Developers    '''
22010037SARM gem5 Developers    msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
22110037SARM gem5 Developers                                    { "code": msrBankedRegCode,
22210037SARM gem5 Developers                                      "predicate_test": predicateTest },
22310501Sakash.bagdia@ARM.com                                    ["IsSerializeAfter", "IsNonSpeculative"])
22410037SARM gem5 Developers    header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
22510037SARM gem5 Developers    decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
22610037SARM gem5 Developers    exec_output += PredOpExecute.subst(msrBankedRegIop)
22710037SARM gem5 Developers
2287202Sgblack@eecs.umich.edu    msrCpsrRegCode = '''
2297400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
2308303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
2318303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
2328303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
2338303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
2348303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
2358303SAli.Saidi@ARM.com
2368303SAli.Saidi@ARM.com        CPSR new_cpsr =
23710037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
23810037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
2398303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
2408303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
2418303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
2428303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
2438303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
2447202Sgblack@eecs.umich.edu    '''
2457202Sgblack@eecs.umich.edu    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
2467202Sgblack@eecs.umich.edu                                  { "code": msrCpsrRegCode,
2477599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
2487599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
2497202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
2507202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
2517202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrRegIop)
2527202Sgblack@eecs.umich.edu
2537202Sgblack@eecs.umich.edu    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
2547202Sgblack@eecs.umich.edu    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
2557202Sgblack@eecs.umich.edu                                  { "code": msrSpsrRegCode,
2567599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
2577599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
2587202Sgblack@eecs.umich.edu    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
2597202Sgblack@eecs.umich.edu    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
2607202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrRegIop)
2617202Sgblack@eecs.umich.edu
2627202Sgblack@eecs.umich.edu    msrCpsrImmCode = '''
2637400SAli.Saidi@ARM.com        SCTLR sctlr = Sctlr;
2648303SAli.Saidi@ARM.com        CPSR old_cpsr = Cpsr;
2658303SAli.Saidi@ARM.com        old_cpsr.nz = CondCodesNZ;
2668303SAli.Saidi@ARM.com        old_cpsr.c = CondCodesC;
2678303SAli.Saidi@ARM.com        old_cpsr.v = CondCodesV;
2688303SAli.Saidi@ARM.com        old_cpsr.ge = CondCodesGE;
2698303SAli.Saidi@ARM.com        CPSR new_cpsr =
27010037SARM gem5 Developers            cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
27110037SARM gem5 Developers                             sctlr.nmfi, xc->tcBase());
2728303SAli.Saidi@ARM.com        Cpsr = ~CondCodesMask & new_cpsr;
2738303SAli.Saidi@ARM.com        CondCodesNZ = new_cpsr.nz;
2748303SAli.Saidi@ARM.com        CondCodesC = new_cpsr.c;
2758303SAli.Saidi@ARM.com        CondCodesV = new_cpsr.v;
2768303SAli.Saidi@ARM.com        CondCodesGE = new_cpsr.ge;
2777202Sgblack@eecs.umich.edu    '''
2787202Sgblack@eecs.umich.edu    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
2797202Sgblack@eecs.umich.edu                                  { "code": msrCpsrImmCode,
2807599Sminkyu.jeong@arm.com                                    "predicate_test": condPredicateTest },
2817599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
2827202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
2837202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
2847202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrCpsrImmIop)
2857202Sgblack@eecs.umich.edu
2867202Sgblack@eecs.umich.edu    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
2877202Sgblack@eecs.umich.edu    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
2887202Sgblack@eecs.umich.edu                                  { "code": msrSpsrImmCode,
2897599Sminkyu.jeong@arm.com                                    "predicate_test": predicateTest },
2907599Sminkyu.jeong@arm.com                                  ["IsSerializeAfter","IsNonSpeculative"])
2917202Sgblack@eecs.umich.edu    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
2927202Sgblack@eecs.umich.edu    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
2937202Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(msrSpsrImmIop)
2947209Sgblack@eecs.umich.edu
2957209Sgblack@eecs.umich.edu    revCode = '''
2967209Sgblack@eecs.umich.edu    uint32_t val = Op1;
2977209Sgblack@eecs.umich.edu    Dest = swap_byte(val);
2987209Sgblack@eecs.umich.edu    '''
2997261Sgblack@eecs.umich.edu    revIop = InstObjParams("rev", "Rev", "RegRegOp",
3007209Sgblack@eecs.umich.edu                           { "code": revCode,
3017209Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
3027261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revIop)
3037261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revIop)
3047209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revIop)
3057209Sgblack@eecs.umich.edu
3067209Sgblack@eecs.umich.edu    rev16Code = '''
3077209Sgblack@eecs.umich.edu    uint32_t val = Op1;
3087209Sgblack@eecs.umich.edu    Dest = (bits(val, 15, 8) << 0) |
3097209Sgblack@eecs.umich.edu           (bits(val, 7, 0) << 8) |
3107209Sgblack@eecs.umich.edu           (bits(val, 31, 24) << 16) |
3117209Sgblack@eecs.umich.edu           (bits(val, 23, 16) << 24);
3127209Sgblack@eecs.umich.edu    '''
3137261Sgblack@eecs.umich.edu    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
3147209Sgblack@eecs.umich.edu                             { "code": rev16Code,
3157209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
3167261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rev16Iop)
3177261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rev16Iop)
3187209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rev16Iop)
3197209Sgblack@eecs.umich.edu
3207209Sgblack@eecs.umich.edu    revshCode = '''
3217209Sgblack@eecs.umich.edu    uint16_t val = Op1;
3227209Sgblack@eecs.umich.edu    Dest = sext<16>(swap_byte(val));
3237209Sgblack@eecs.umich.edu    '''
3247261Sgblack@eecs.umich.edu    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
3257209Sgblack@eecs.umich.edu                             { "code": revshCode,
3267209Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
3277261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(revshIop)
3287261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(revshIop)
3297209Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(revshIop)
3307226Sgblack@eecs.umich.edu
3317249Sgblack@eecs.umich.edu    rbitCode = '''
3327249Sgblack@eecs.umich.edu    uint8_t *opBytes = (uint8_t *)&Op1;
3337249Sgblack@eecs.umich.edu    uint32_t resTemp;
3347249Sgblack@eecs.umich.edu    uint8_t *destBytes = (uint8_t *)&resTemp;
3357249Sgblack@eecs.umich.edu    // This reverses the bytes and bits of the input, or so says the
3367249Sgblack@eecs.umich.edu    // internet.
3377249Sgblack@eecs.umich.edu    for (int i = 0; i < 4; i++) {
3387249Sgblack@eecs.umich.edu        uint32_t temp = opBytes[i];
3397249Sgblack@eecs.umich.edu        temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
3407249Sgblack@eecs.umich.edu        destBytes[3 - i] = (temp * 0x10101) >> 16;
3417249Sgblack@eecs.umich.edu    }
3427249Sgblack@eecs.umich.edu    Dest = resTemp;
3437249Sgblack@eecs.umich.edu    '''
3447261Sgblack@eecs.umich.edu    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
3457249Sgblack@eecs.umich.edu                            { "code": rbitCode,
3467249Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
3477261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(rbitIop)
3487261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(rbitIop)
3497249Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(rbitIop)
3507249Sgblack@eecs.umich.edu
3517251Sgblack@eecs.umich.edu    clzCode = '''
3527251Sgblack@eecs.umich.edu        Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
3537251Sgblack@eecs.umich.edu    '''
3547261Sgblack@eecs.umich.edu    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
3557251Sgblack@eecs.umich.edu                           { "code": clzCode,
3567251Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
3577261Sgblack@eecs.umich.edu    header_output += RegRegOpDeclare.subst(clzIop)
3587261Sgblack@eecs.umich.edu    decoder_output += RegRegOpConstructor.subst(clzIop)
3597251Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(clzIop)
3607251Sgblack@eecs.umich.edu
3617226Sgblack@eecs.umich.edu    ssatCode = '''
3627226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
3637226Sgblack@eecs.umich.edu        int32_t res;
3647232Sgblack@eecs.umich.edu        if (satInt(res, operand, imm))
3658302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
3667226Sgblack@eecs.umich.edu        Dest = res;
3677226Sgblack@eecs.umich.edu    '''
3687232Sgblack@eecs.umich.edu    ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
3697226Sgblack@eecs.umich.edu                            { "code": ssatCode,
3708304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(ssatCode) }, [])
3717232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
3727232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
3737226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssatIop)
3747226Sgblack@eecs.umich.edu
3757226Sgblack@eecs.umich.edu    usatCode = '''
3767226Sgblack@eecs.umich.edu        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
3777226Sgblack@eecs.umich.edu        int32_t res;
3787232Sgblack@eecs.umich.edu        if (uSatInt(res, operand, imm))
3798302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
3807226Sgblack@eecs.umich.edu        Dest = res;
3817226Sgblack@eecs.umich.edu    '''
3827232Sgblack@eecs.umich.edu    usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
3837226Sgblack@eecs.umich.edu                            { "code": usatCode,
3848304SAli.Saidi@ARM.com                              "predicate_test": pickPredicate(usatCode) }, [])
3857232Sgblack@eecs.umich.edu    header_output += RegImmRegShiftOpDeclare.subst(usatIop)
3867232Sgblack@eecs.umich.edu    decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
3877226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usatIop)
3887226Sgblack@eecs.umich.edu
3897226Sgblack@eecs.umich.edu    ssat16Code = '''
3907226Sgblack@eecs.umich.edu        int32_t res;
3917226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
3927226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
3937226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
3947232Sgblack@eecs.umich.edu        if (satInt(res, argLow, imm))
3958302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
3967226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
3977232Sgblack@eecs.umich.edu        if (satInt(res, argHigh, imm))
3988302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
3997226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4007226Sgblack@eecs.umich.edu        Dest = resTemp;
4017226Sgblack@eecs.umich.edu    '''
4027232Sgblack@eecs.umich.edu    ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
4037226Sgblack@eecs.umich.edu                              { "code": ssat16Code,
4048304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(ssat16Code) }, [])
4057232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(ssat16Iop)
4067232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
4077226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ssat16Iop)
4087226Sgblack@eecs.umich.edu
4097226Sgblack@eecs.umich.edu    usat16Code = '''
4107226Sgblack@eecs.umich.edu        int32_t res;
4117226Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
4127226Sgblack@eecs.umich.edu        int32_t argLow = sext<16>(bits(Op1, 15, 0));
4137226Sgblack@eecs.umich.edu        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
4147232Sgblack@eecs.umich.edu        if (uSatInt(res, argLow, imm))
4158302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4167226Sgblack@eecs.umich.edu        replaceBits(resTemp, 15, 0, res);
4177232Sgblack@eecs.umich.edu        if (uSatInt(res, argHigh, imm))
4188302SAli.Saidi@ARM.com            CpsrQ = 1 << 27;
4197226Sgblack@eecs.umich.edu        replaceBits(resTemp, 31, 16, res);
4207226Sgblack@eecs.umich.edu        Dest = resTemp;
4217226Sgblack@eecs.umich.edu    '''
4227232Sgblack@eecs.umich.edu    usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
4237226Sgblack@eecs.umich.edu                              { "code": usat16Code,
4248304SAli.Saidi@ARM.com                                "predicate_test": pickPredicate(usat16Code) }, [])
4257232Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(usat16Iop)
4267232Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
4277226Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usat16Iop)
4287234Sgblack@eecs.umich.edu
4297234Sgblack@eecs.umich.edu    sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
4307234Sgblack@eecs.umich.edu                            { "code":
4318588Sgblack@eecs.umich.edu                              "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
4327234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
4337234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtbIop)
4347234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
4357234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtbIop)
4367234Sgblack@eecs.umich.edu
4377234Sgblack@eecs.umich.edu    sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
4387234Sgblack@eecs.umich.edu                             { "code":
4397234Sgblack@eecs.umich.edu                               '''
4408588Sgblack@eecs.umich.edu                                   Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
4417234Sgblack@eecs.umich.edu                                          Op1;
4427234Sgblack@eecs.umich.edu                               ''',
4437234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
4447234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
4457234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
4467234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtabIop)
4477234Sgblack@eecs.umich.edu
4487234Sgblack@eecs.umich.edu    sxtb16Code = '''
4497234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
4507234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
4517234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
4527234Sgblack@eecs.umich.edu                sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
4537234Sgblack@eecs.umich.edu    Dest = resTemp;
4547234Sgblack@eecs.umich.edu    '''
4557234Sgblack@eecs.umich.edu    sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
4567234Sgblack@eecs.umich.edu                              { "code": sxtb16Code,
4577234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
4587234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
4597234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
4607234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtb16Iop)
4617234Sgblack@eecs.umich.edu
4627234Sgblack@eecs.umich.edu    sxtab16Code = '''
4637234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
4647234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
4657234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
4667234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
4677234Sgblack@eecs.umich.edu                sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
4687234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
4697234Sgblack@eecs.umich.edu    Dest = resTemp;
4707234Sgblack@eecs.umich.edu    '''
4717234Sgblack@eecs.umich.edu    sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
4727234Sgblack@eecs.umich.edu                               { "code": sxtab16Code,
4737234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
4747234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
4757234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
4767234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtab16Iop)
4777234Sgblack@eecs.umich.edu
4787234Sgblack@eecs.umich.edu    sxthCode = '''
4797234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
4807234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
4817234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated);
4827234Sgblack@eecs.umich.edu    '''
4837234Sgblack@eecs.umich.edu    sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
4847234Sgblack@eecs.umich.edu                              { "code": sxthCode,
4857234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
4867234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(sxthIop)
4877234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(sxthIop)
4887234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxthIop)
4897234Sgblack@eecs.umich.edu
4907234Sgblack@eecs.umich.edu    sxtahCode = '''
4917234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
4927234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
4937234Sgblack@eecs.umich.edu    Dest = sext<16>((uint16_t)rotated) + Op1;
4947234Sgblack@eecs.umich.edu    '''
4957234Sgblack@eecs.umich.edu    sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
4967234Sgblack@eecs.umich.edu                             { "code": sxtahCode,
4977234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
4987234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
4997234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
5007234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sxtahIop)
5017234Sgblack@eecs.umich.edu
5027234Sgblack@eecs.umich.edu    uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
5038588Sgblack@eecs.umich.edu                            { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
5047234Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
5057234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtbIop)
5067234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
5077234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtbIop)
5087234Sgblack@eecs.umich.edu
5097234Sgblack@eecs.umich.edu    uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
5107234Sgblack@eecs.umich.edu                             { "code":
5118588Sgblack@eecs.umich.edu                               "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
5127234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5137234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
5147234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
5157234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtabIop)
5167234Sgblack@eecs.umich.edu
5177234Sgblack@eecs.umich.edu    uxtb16Code = '''
5187234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5197234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
5207234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5217234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
5227234Sgblack@eecs.umich.edu    Dest = resTemp;
5237234Sgblack@eecs.umich.edu    '''
5247234Sgblack@eecs.umich.edu    uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
5257234Sgblack@eecs.umich.edu                              { "code": uxtb16Code,
5267234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5277234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
5287234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
5297234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtb16Iop)
5307234Sgblack@eecs.umich.edu
5317234Sgblack@eecs.umich.edu    uxtab16Code = '''
5327234Sgblack@eecs.umich.edu    uint32_t resTemp = 0;
5337234Sgblack@eecs.umich.edu    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
5347234Sgblack@eecs.umich.edu                                        bits(Op1, 15, 0));
5357234Sgblack@eecs.umich.edu    replaceBits(resTemp, 31, 16,
5367234Sgblack@eecs.umich.edu                (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
5377234Sgblack@eecs.umich.edu                bits(Op1, 31, 16));
5387234Sgblack@eecs.umich.edu    Dest = resTemp;
5397234Sgblack@eecs.umich.edu    '''
5407234Sgblack@eecs.umich.edu    uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
5417234Sgblack@eecs.umich.edu                               { "code": uxtab16Code,
5427234Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest }, [])
5437234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
5447234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
5457234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtab16Iop)
5467234Sgblack@eecs.umich.edu
5477234Sgblack@eecs.umich.edu    uxthCode = '''
5487234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op1;
5497234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5507234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated;
5517234Sgblack@eecs.umich.edu    '''
5527234Sgblack@eecs.umich.edu    uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
5537234Sgblack@eecs.umich.edu                              { "code": uxthCode,
5547234Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
5557234Sgblack@eecs.umich.edu    header_output += RegImmRegOpDeclare.subst(uxthIop)
5567234Sgblack@eecs.umich.edu    decoder_output += RegImmRegOpConstructor.subst(uxthIop)
5577234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxthIop)
5587234Sgblack@eecs.umich.edu
5597234Sgblack@eecs.umich.edu    uxtahCode = '''
5607234Sgblack@eecs.umich.edu    uint64_t rotated = (uint32_t)Op2;
5617234Sgblack@eecs.umich.edu    rotated = (rotated | (rotated << 32)) >> imm;
5627234Sgblack@eecs.umich.edu    Dest = (uint16_t)rotated + Op1;
5637234Sgblack@eecs.umich.edu    '''
5647234Sgblack@eecs.umich.edu    uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
5657234Sgblack@eecs.umich.edu                             { "code": uxtahCode,
5667234Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
5677234Sgblack@eecs.umich.edu    header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
5687234Sgblack@eecs.umich.edu    decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
5697234Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(uxtahIop)
5707239Sgblack@eecs.umich.edu
5717239Sgblack@eecs.umich.edu    selCode = '''
5727239Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
5737239Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
5747239Sgblack@eecs.umich.edu            int low = i * 8;
5757239Sgblack@eecs.umich.edu            int high = low + 7;
5767239Sgblack@eecs.umich.edu            replaceBits(resTemp, high, low,
5778303SAli.Saidi@ARM.com                        bits(CondCodesGE, i) ?
5787239Sgblack@eecs.umich.edu                            bits(Op1, high, low) : bits(Op2, high, low));
5797239Sgblack@eecs.umich.edu        }
5807239Sgblack@eecs.umich.edu        Dest = resTemp;
5817239Sgblack@eecs.umich.edu    '''
5827239Sgblack@eecs.umich.edu    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
5837239Sgblack@eecs.umich.edu                           { "code": selCode,
5848303SAli.Saidi@ARM.com                             "predicate_test": predicateTest }, [])
5857239Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(selIop)
5867239Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(selIop)
5877239Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(selIop)
5887242Sgblack@eecs.umich.edu
5897242Sgblack@eecs.umich.edu    usad8Code = '''
5907242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
5917242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
5927242Sgblack@eecs.umich.edu            int low = i * 8;
5937242Sgblack@eecs.umich.edu            int high = low + 7;
5947242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
5957242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
5967242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
5977242Sgblack@eecs.umich.edu        }
5987242Sgblack@eecs.umich.edu        Dest = resTemp;
5997242Sgblack@eecs.umich.edu    '''
6007242Sgblack@eecs.umich.edu    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
6017242Sgblack@eecs.umich.edu                             { "code": usad8Code,
6027242Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
6037242Sgblack@eecs.umich.edu    header_output += RegRegRegOpDeclare.subst(usad8Iop)
6047242Sgblack@eecs.umich.edu    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
6057242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usad8Iop)
6067242Sgblack@eecs.umich.edu
6077242Sgblack@eecs.umich.edu    usada8Code = '''
6087242Sgblack@eecs.umich.edu        uint32_t resTemp = 0;
6097242Sgblack@eecs.umich.edu        for (unsigned i = 0; i < 4; i++) {
6107242Sgblack@eecs.umich.edu            int low = i * 8;
6117242Sgblack@eecs.umich.edu            int high = low + 7;
6127242Sgblack@eecs.umich.edu            int32_t diff = bits(Op1, high, low) -
6137242Sgblack@eecs.umich.edu                           bits(Op2, high, low);
6147242Sgblack@eecs.umich.edu            resTemp += ((diff < 0) ? -diff : diff);
6157242Sgblack@eecs.umich.edu        }
6167242Sgblack@eecs.umich.edu        Dest = Op3 + resTemp;
6177242Sgblack@eecs.umich.edu    '''
6187242Sgblack@eecs.umich.edu    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
6197242Sgblack@eecs.umich.edu                              { "code": usada8Code,
6207242Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
6217242Sgblack@eecs.umich.edu    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
6227242Sgblack@eecs.umich.edu    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
6237242Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(usada8Iop)
6247247Sgblack@eecs.umich.edu
62510474Sandreas.hansson@arm.com    bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n'
6267848SAli.Saidi@ARM.com    bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
6277410Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(bkptIop)
6287410Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(bkptIop)
6297410Sgblack@eecs.umich.edu    exec_output += BasicExecute.subst(bkptIop)
6307410Sgblack@eecs.umich.edu
63110037SARM gem5 Developers    nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
6327247Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(nopIop)
63310037SARM gem5 Developers    decoder_output += BasicConstructor64.subst(nopIop)
63410037SARM gem5 Developers    exec_output += BasicExecute.subst(nopIop)
6357408Sgblack@eecs.umich.edu
6367418Sgblack@eecs.umich.edu    yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
6377418Sgblack@eecs.umich.edu            { "code" : "", "predicate_test" : predicateTest })
6387418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(yieldIop)
6397418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(yieldIop)
6407418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(yieldIop)
6417418Sgblack@eecs.umich.edu
6427418Sgblack@eecs.umich.edu    wfeCode = '''
64310037SARM gem5 Developers    HCR  hcr  = Hcr;
64410037SARM gem5 Developers    CPSR cpsr = Cpsr;
64510037SARM gem5 Developers    SCR  scr  = Scr64;
64610037SARM gem5 Developers    SCTLR sctlr = Sctlr;
64710037SARM gem5 Developers
64810037SARM gem5 Developers    // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
64910037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
6508285SPrakash.Ramrakhyani@arm.com    if (SevMailbox == 1) {
6517418Sgblack@eecs.umich.edu        SevMailbox = 0;
65210037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
65311150Smitch.hayenga@arm.com    } else if (tc->getCpuPtr()->getInterruptController(
65411150Smitch.hayenga@arm.com                tc->threadId())->checkInterrupts(tc)) {
65510037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
65610037SARM gem5 Developers    } else if (cpsr.el == EL0 && !sctlr.ntwe) {
65710037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
65810474Sandreas.hansson@arm.com        fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00001,
65910474Sandreas.hansson@arm.com                                                 EC_TRAPPED_WFI_WFE);
66010037SARM gem5 Developers    } else if (ArmSystem::haveVirtualization(tc) &&
66110037SARM gem5 Developers               !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) &&
66210037SARM gem5 Developers               hcr.twe) {
66310037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
66410474Sandreas.hansson@arm.com        fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00001,
66510474Sandreas.hansson@arm.com                                                 EC_TRAPPED_WFI_WFE);
66610037SARM gem5 Developers    } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twe) {
66710037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
66810474Sandreas.hansson@arm.com        fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00001,
66910474Sandreas.hansson@arm.com                                                    EC_TRAPPED_WFI_WFE);
6708285SPrakash.Ramrakhyani@arm.com    } else {
67110037SARM gem5 Developers        PseudoInst::quiesce(tc);
6728142SAli.Saidi@ARM.com    }
6737418Sgblack@eecs.umich.edu    '''
6748518Sgeoffrey.blake@arm.com    wfePredFixUpCode = '''
6758518Sgeoffrey.blake@arm.com    // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
6768518Sgeoffrey.blake@arm.com    // and SEV interrupts
6778518Sgeoffrey.blake@arm.com    SevMailbox = 1;
6788518Sgeoffrey.blake@arm.com    '''
6797418Sgblack@eecs.umich.edu    wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
6808518Sgeoffrey.blake@arm.com            { "code" : wfeCode,
6818518Sgeoffrey.blake@arm.com              "pred_fixup" : wfePredFixUpCode,
6828518Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest },
6838733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
6848733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
6857418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfeIop)
6867418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfeIop)
6878518Sgeoffrey.blake@arm.com    exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
6887418Sgblack@eecs.umich.edu
6897418Sgblack@eecs.umich.edu    wfiCode = '''
69010037SARM gem5 Developers    HCR  hcr  = Hcr;
69110037SARM gem5 Developers    CPSR cpsr = Cpsr;
69210037SARM gem5 Developers    SCR  scr  = Scr64;
69310037SARM gem5 Developers    SCTLR sctlr = Sctlr;
69410037SARM gem5 Developers
6958285SPrakash.Ramrakhyani@arm.com    // WFI doesn't sleep if interrupts are pending (masked or not)
69610037SARM gem5 Developers    ThreadContext *tc = xc->tcBase();
69711150Smitch.hayenga@arm.com    if (tc->getCpuPtr()->getInterruptController(
69811150Smitch.hayenga@arm.com                tc->threadId())->checkWfiWake(hcr, cpsr, scr)) {
69910037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
70010037SARM gem5 Developers    } else if (cpsr.el == EL0 && !sctlr.ntwi) {
70110037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
70210474Sandreas.hansson@arm.com        fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
70310474Sandreas.hansson@arm.com                                                 EC_TRAPPED_WFI_WFE);
70410037SARM gem5 Developers    } else if (ArmSystem::haveVirtualization(tc) && hcr.twi &&
70510037SARM gem5 Developers               (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) {
70610037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
70710474Sandreas.hansson@arm.com        fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00000,
70810474Sandreas.hansson@arm.com                                                 EC_TRAPPED_WFI_WFE);
70910037SARM gem5 Developers    } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) {
71010037SARM gem5 Developers        PseudoInst::quiesceSkip(tc);
71110474Sandreas.hansson@arm.com        fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000,
71210474Sandreas.hansson@arm.com                                                    EC_TRAPPED_WFI_WFE);
7138285SPrakash.Ramrakhyani@arm.com    } else {
71410037SARM gem5 Developers        PseudoInst::quiesce(tc);
7158285SPrakash.Ramrakhyani@arm.com    }
71611150Smitch.hayenga@arm.com    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
7177418Sgblack@eecs.umich.edu    '''
7187418Sgblack@eecs.umich.edu    wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
7197418Sgblack@eecs.umich.edu            { "code" : wfiCode, "predicate_test" : predicateTest },
7208733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsQuiesce",
7218733Sgeoffrey.blake@arm.com             "IsSerializeAfter", "IsUnverifiable"])
7227418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(wfiIop)
7237418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(wfiIop)
7248142SAli.Saidi@ARM.com    exec_output += QuiescePredOpExecute.subst(wfiIop)
7257418Sgblack@eecs.umich.edu
7267418Sgblack@eecs.umich.edu    sevCode = '''
7278142SAli.Saidi@ARM.com    SevMailbox = 1;
7287418Sgblack@eecs.umich.edu    System *sys = xc->tcBase()->getSystemPtr();
7297418Sgblack@eecs.umich.edu    for (int x = 0; x < sys->numContexts(); x++) {
7307418Sgblack@eecs.umich.edu        ThreadContext *oc = sys->getThreadContext(x);
7318285SPrakash.Ramrakhyani@arm.com        if (oc == xc->tcBase())
7328285SPrakash.Ramrakhyani@arm.com            continue;
7338518Sgeoffrey.blake@arm.com        // Wake CPU with interrupt if they were sleeping
7348285SPrakash.Ramrakhyani@arm.com        if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
7358518Sgeoffrey.blake@arm.com            // Post Interrupt and wake cpu if needed
73611150Smitch.hayenga@arm.com            oc->getCpuPtr()->postInterrupt(oc->threadId(), INT_SEV, 0);
7378142SAli.Saidi@ARM.com        }
7387418Sgblack@eecs.umich.edu    }
7397418Sgblack@eecs.umich.edu    '''
7407418Sgblack@eecs.umich.edu    sevIop = InstObjParams("sev", "SevInst", "PredOp", \
7417418Sgblack@eecs.umich.edu            { "code" : sevCode, "predicate_test" : predicateTest },
7428733Sgeoffrey.blake@arm.com            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
7437418Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(sevIop)
7447418Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(sevIop)
7457418Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sevIop)
7467418Sgblack@eecs.umich.edu
74710037SARM gem5 Developers    sevlCode = '''
74810037SARM gem5 Developers    SevMailbox = 1;
74910037SARM gem5 Developers    '''
75010037SARM gem5 Developers    sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
75110037SARM gem5 Developers            { "code" : sevlCode, "predicate_test" : predicateTest },
75210037SARM gem5 Developers            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
75310037SARM gem5 Developers    header_output += BasicDeclare.subst(sevlIop)
75410037SARM gem5 Developers    decoder_output += BasicConstructor.subst(sevlIop)
75510037SARM gem5 Developers    exec_output += BasicExecute.subst(sevlIop)
75610037SARM gem5 Developers
7577408Sgblack@eecs.umich.edu    itIop = InstObjParams("it", "ItInst", "PredOp", \
7588205SAli.Saidi@ARM.com            { "code" : ";",
7598908Sgeoffrey.blake@arm.com              "predicate_test" : predicateTest }, [])
7607408Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(itIop)
7617408Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(itIop)
7627408Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(itIop)
7637409Sgblack@eecs.umich.edu    unknownCode = '''
76410474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, true);
7657409Sgblack@eecs.umich.edu    '''
7667409Sgblack@eecs.umich.edu    unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
7677409Sgblack@eecs.umich.edu                               { "code": unknownCode,
7687409Sgblack@eecs.umich.edu                                 "predicate_test": predicateTest })
7697409Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(unknownIop)
7707409Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(unknownIop)
7717409Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(unknownIop)
7727254Sgblack@eecs.umich.edu
7737254Sgblack@eecs.umich.edu    ubfxCode = '''
7747254Sgblack@eecs.umich.edu        Dest = bits(Op1, imm2, imm1);
7757254Sgblack@eecs.umich.edu    '''
7767254Sgblack@eecs.umich.edu    ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
7777254Sgblack@eecs.umich.edu                            { "code": ubfxCode,
7787254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
7797254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
7807254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
7817254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(ubfxIop)
7827254Sgblack@eecs.umich.edu
7837254Sgblack@eecs.umich.edu    sbfxCode = '''
7847254Sgblack@eecs.umich.edu        int32_t resTemp = bits(Op1, imm2, imm1);
7857254Sgblack@eecs.umich.edu        Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
7867254Sgblack@eecs.umich.edu    '''
7877254Sgblack@eecs.umich.edu    sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
7887254Sgblack@eecs.umich.edu                            { "code": sbfxCode,
7897254Sgblack@eecs.umich.edu                              "predicate_test": predicateTest }, [])
7907254Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
7917254Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
7927254Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(sbfxIop)
7937257Sgblack@eecs.umich.edu
7947257Sgblack@eecs.umich.edu    bfcCode = '''
7957257Sgblack@eecs.umich.edu        Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
7967257Sgblack@eecs.umich.edu    '''
7977257Sgblack@eecs.umich.edu    bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
7987257Sgblack@eecs.umich.edu                           { "code": bfcCode,
7997257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8007257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfcIop)
8017257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
8027257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfcIop)
8037257Sgblack@eecs.umich.edu
8047257Sgblack@eecs.umich.edu    bfiCode = '''
8057257Sgblack@eecs.umich.edu        uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
8067257Sgblack@eecs.umich.edu        Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
8077257Sgblack@eecs.umich.edu    '''
8087257Sgblack@eecs.umich.edu    bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
8097257Sgblack@eecs.umich.edu                           { "code": bfiCode,
8107257Sgblack@eecs.umich.edu                             "predicate_test": predicateTest }, [])
8117257Sgblack@eecs.umich.edu    header_output += RegRegImmImmOpDeclare.subst(bfiIop)
8127257Sgblack@eecs.umich.edu    decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
8137257Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(bfiIop)
8147262Sgblack@eecs.umich.edu
8158868SMatt.Horsnell@arm.com    mrc14code = '''
81612106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
81712106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, op1)).index();
81811939Snikos.nikoleris@arm.com    bool can_read, undefined;
81911939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
82011939Snikos.nikoleris@arm.com    if (!can_read || undefined) {
82110474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
82210474Sandreas.hansson@arm.com                                                      mnemonic);
82310037SARM gem5 Developers    }
82410037SARM gem5 Developers    if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
82510037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
82610474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
82710474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8288868SMatt.Horsnell@arm.com    }
8298868SMatt.Horsnell@arm.com    Dest = MiscOp1;
8308868SMatt.Horsnell@arm.com    '''
8318868SMatt.Horsnell@arm.com
83210037SARM gem5 Developers    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
8338868SMatt.Horsnell@arm.com                             { "code": mrc14code,
8348868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest }, [])
83510037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mrc14Iop)
83610037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
8378868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mrc14Iop)
8388868SMatt.Horsnell@arm.com
8398868SMatt.Horsnell@arm.com
8408868SMatt.Horsnell@arm.com    mcr14code = '''
84112106SRekai.GonzalezAlberquilla@arm.com    MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
84212106SRekai.GonzalezAlberquilla@arm.com                               RegId(MiscRegClass, dest)).index();
84311939Snikos.nikoleris@arm.com    bool can_write, undefined;
84411939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
84511939Snikos.nikoleris@arm.com    if (undefined || !can_write) {
84610474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
84710474Sandreas.hansson@arm.com                                                      mnemonic);
84810037SARM gem5 Developers    }
84910037SARM gem5 Developers    if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
85010037SARM gem5 Developers                          Hstr, Hcptr, imm)) {
85110474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
85210474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP14_MCR_MRC);
8538868SMatt.Horsnell@arm.com    }
8548868SMatt.Horsnell@arm.com    MiscDest = Op1;
8558868SMatt.Horsnell@arm.com    '''
85610037SARM gem5 Developers    mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
8578868SMatt.Horsnell@arm.com                             { "code": mcr14code,
8588868SMatt.Horsnell@arm.com                               "predicate_test": predicateTest },
8598868SMatt.Horsnell@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
86010037SARM gem5 Developers    header_output += RegRegImmOpDeclare.subst(mcr14Iop)
86110037SARM gem5 Developers    decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
8628868SMatt.Horsnell@arm.com    exec_output += PredOpExecute.subst(mcr14Iop)
8638868SMatt.Horsnell@arm.com
86410037SARM gem5 Developers    mrc15code = '''
86510037SARM gem5 Developers    int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
86610037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
86712106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
86812106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
86910037SARM gem5 Developers    bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
87010037SARM gem5 Developers                                     Hcptr, imm);
87111939Snikos.nikoleris@arm.com    bool can_read, undefined;
87211939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
87310037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
87410037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
87510037SARM gem5 Developers    // IS accessable.
87611939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
87711939Snikos.nikoleris@arm.com                                    !inSecureState(Scr, Cpsr)))) {
87810474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
87910474Sandreas.hansson@arm.com                                                      mnemonic);
8808782Sgblack@eecs.umich.edu    }
88110037SARM gem5 Developers    if (hypTrap) {
88210474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
88310474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
88410037SARM gem5 Developers    }
88510037SARM gem5 Developers    Dest = MiscNsBankedOp1;
8867347SAli.Saidi@ARM.com    '''
8877347SAli.Saidi@ARM.com
88810418Sandreas.hansson@arm.com    mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp",
8897347SAli.Saidi@ARM.com                             { "code": mrc15code,
8907262Sgblack@eecs.umich.edu                               "predicate_test": predicateTest }, [])
89110418Sandreas.hansson@arm.com    header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
89210418Sandreas.hansson@arm.com    decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
8937262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mrc15Iop)
8947262Sgblack@eecs.umich.edu
8957347SAli.Saidi@ARM.com
8967347SAli.Saidi@ARM.com    mcr15code = '''
89710037SARM gem5 Developers    int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
89810037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
89912106SRekai.GonzalezAlberquilla@arm.com                       xc->tcBase()->flattenRegId(RegId(MiscRegClass,
90012106SRekai.GonzalezAlberquilla@arm.com                                                  preFlatDest)).index();
90110037SARM gem5 Developers    bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
90210037SARM gem5 Developers                                      Hcptr, imm);
90311939Snikos.nikoleris@arm.com    bool can_write, undefined;
90411939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
90510037SARM gem5 Developers
90610037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
90710037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
90810037SARM gem5 Developers    // IS accessable.
90911939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
91011939Snikos.nikoleris@arm.com                                      !inSecureState(Scr, Cpsr)))) {
91110474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
91210474Sandreas.hansson@arm.com                                                      mnemonic);
9138782Sgblack@eecs.umich.edu    }
91410037SARM gem5 Developers    if (hypTrap) {
91510474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
91610474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCR_MRC);
91710037SARM gem5 Developers    }
91810037SARM gem5 Developers    MiscNsBankedDest = Op1;
9197347SAli.Saidi@ARM.com    '''
92010418Sandreas.hansson@arm.com    mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
9217347SAli.Saidi@ARM.com                             { "code": mcr15code,
9227599Sminkyu.jeong@arm.com                               "predicate_test": predicateTest },
9237599Sminkyu.jeong@arm.com                               ["IsSerializeAfter","IsNonSpeculative"])
92410418Sandreas.hansson@arm.com    header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
92510418Sandreas.hansson@arm.com    decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
9267262Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(mcr15Iop)
9277283Sgblack@eecs.umich.edu
9287420Sgblack@eecs.umich.edu
92910037SARM gem5 Developers    mrrc15code = '''
93010037SARM gem5 Developers    int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
93110037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
93212106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
93312106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatOp1)).index();
93410037SARM gem5 Developers    bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
93511939Snikos.nikoleris@arm.com    bool can_read, undefined;
93611939Snikos.nikoleris@arm.com    std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
93710037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
93810037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
93910037SARM gem5 Developers    // IS accessable.
94011939Snikos.nikoleris@arm.com    if (undefined || (!can_read && !(hypTrap && !inUserMode(Cpsr) &&
94111939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
94210474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
94310474Sandreas.hansson@arm.com                                                      mnemonic);
94410037SARM gem5 Developers    }
94510037SARM gem5 Developers    if (hypTrap) {
94610474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
94710474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
94810037SARM gem5 Developers    }
94910037SARM gem5 Developers    Dest = bits(MiscNsBankedOp164, 63, 32);
95010037SARM gem5 Developers    Dest2 = bits(MiscNsBankedOp164, 31, 0);
95110037SARM gem5 Developers    '''
95210037SARM gem5 Developers    mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
95310037SARM gem5 Developers                              { "code": mrrc15code,
95410037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
95510037SARM gem5 Developers    header_output += MrrcOpDeclare.subst(mrrc15Iop)
95610037SARM gem5 Developers    decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
95710037SARM gem5 Developers    exec_output += PredOpExecute.subst(mrrc15Iop)
95810037SARM gem5 Developers
95910037SARM gem5 Developers
96010037SARM gem5 Developers    mcrr15code = '''
96110037SARM gem5 Developers    int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
96210037SARM gem5 Developers    MiscRegIndex miscReg = (MiscRegIndex)
96312106SRekai.GonzalezAlberquilla@arm.com                           xc->tcBase()->flattenRegId(RegId(MiscRegClass,
96412106SRekai.GonzalezAlberquilla@arm.com                                                      preFlatDest)).index();
96510037SARM gem5 Developers    bool hypTrap  = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
96611939Snikos.nikoleris@arm.com    bool can_write, undefined;
96711939Snikos.nikoleris@arm.com    std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
96810037SARM gem5 Developers
96910037SARM gem5 Developers    // if we're in non secure PL1 mode then we can trap regargless of whether
97010037SARM gem5 Developers    // the register is accessable, in other modes we trap if only if the register
97110037SARM gem5 Developers    // IS accessable.
97211939Snikos.nikoleris@arm.com    if (undefined || (!can_write && !(hypTrap && !inUserMode(Cpsr) &&
97311939Snikos.nikoleris@arm.com                                     !inSecureState(Scr, Cpsr)))) {
97410474Sandreas.hansson@arm.com        return std::make_shared<UndefinedInstruction>(machInst, false,
97510474Sandreas.hansson@arm.com                                                      mnemonic);
97610037SARM gem5 Developers    }
97710037SARM gem5 Developers    if (hypTrap) {
97810474Sandreas.hansson@arm.com        return std::make_shared<HypervisorTrap>(machInst, imm,
97910474Sandreas.hansson@arm.com                                                EC_TRAPPED_CP15_MCRR_MRRC);
98010037SARM gem5 Developers    }
98110037SARM gem5 Developers    MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
98210037SARM gem5 Developers    '''
98310037SARM gem5 Developers    mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
98410037SARM gem5 Developers                              { "code": mcrr15code,
98510037SARM gem5 Developers                                "predicate_test": predicateTest }, [])
98610037SARM gem5 Developers    header_output += McrrOpDeclare.subst(mcrr15Iop)
98710037SARM gem5 Developers    decoder_output += McrrOpConstructor.subst(mcrr15Iop)
98810037SARM gem5 Developers    exec_output += PredOpExecute.subst(mcrr15Iop)
98910037SARM gem5 Developers
9907420Sgblack@eecs.umich.edu
9917283Sgblack@eecs.umich.edu    enterxCode = '''
9927797Sgblack@eecs.umich.edu        NextThumb = true;
9937797Sgblack@eecs.umich.edu        NextJazelle = true;
9947283Sgblack@eecs.umich.edu    '''
9957283Sgblack@eecs.umich.edu    enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
9967283Sgblack@eecs.umich.edu                              { "code": enterxCode,
9977283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
9987283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(enterxIop)
9997283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(enterxIop)
10007283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(enterxIop)
10017283Sgblack@eecs.umich.edu
10027283Sgblack@eecs.umich.edu    leavexCode = '''
10037797Sgblack@eecs.umich.edu        NextThumb = true;
10047797Sgblack@eecs.umich.edu        NextJazelle = false;
10057283Sgblack@eecs.umich.edu    '''
10067283Sgblack@eecs.umich.edu    leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
10077283Sgblack@eecs.umich.edu                              { "code": leavexCode,
10087283Sgblack@eecs.umich.edu                                "predicate_test": predicateTest }, [])
10097283Sgblack@eecs.umich.edu    header_output += BasicDeclare.subst(leavexIop)
10107283Sgblack@eecs.umich.edu    decoder_output += BasicConstructor.subst(leavexIop)
10117283Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(leavexIop)
10127307Sgblack@eecs.umich.edu
10137307Sgblack@eecs.umich.edu    setendCode = '''
10147307Sgblack@eecs.umich.edu        CPSR cpsr = Cpsr;
10157307Sgblack@eecs.umich.edu        cpsr.e = imm;
10167307Sgblack@eecs.umich.edu        Cpsr = cpsr;
10177307Sgblack@eecs.umich.edu    '''
10187307Sgblack@eecs.umich.edu    setendIop = InstObjParams("setend", "Setend", "ImmOp",
10197307Sgblack@eecs.umich.edu                              { "code": setendCode,
10207648SAli.Saidi@ARM.com                                "predicate_test": predicateTest },
10217648SAli.Saidi@ARM.com                              ["IsSerializeAfter","IsNonSpeculative"])
10227307Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(setendIop)
10237307Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(setendIop)
10247307Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(setendIop)
10257315Sgblack@eecs.umich.edu
10267603SGene.Wu@arm.com    clrexCode = '''
10278209SAli.Saidi@ARM.com        LLSCLock = 0;
10287603SGene.Wu@arm.com    '''
10297603SGene.Wu@arm.com    clrexIop = InstObjParams("clrex", "Clrex","PredOp",
10307603SGene.Wu@arm.com                             { "code": clrexCode,
10317603SGene.Wu@arm.com                               "predicate_test": predicateTest },[])
10328209SAli.Saidi@ARM.com    header_output += BasicDeclare.subst(clrexIop)
10337603SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(clrexIop)
10347603SGene.Wu@arm.com    exec_output += PredOpExecute.subst(clrexIop)
10357603SGene.Wu@arm.com
10367605SGene.Wu@arm.com    isbCode = '''
103710037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
103810037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr,
103910037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
104010474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
104110037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
104210037SARM gem5 Developers        }
104310474Sandreas.hansson@arm.com        fault = std::make_shared<FlushPipe>();
10447605SGene.Wu@arm.com    '''
104510037SARM gem5 Developers    isbIop = InstObjParams("isb", "Isb", "ImmOp",
10467605SGene.Wu@arm.com                             {"code": isbCode,
10478068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
10488068SAli.Saidi@ARM.com                                ['IsSerializeAfter'])
104910037SARM gem5 Developers    header_output += ImmOpDeclare.subst(isbIop)
105010037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(isbIop)
10517605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(isbIop)
10527605SGene.Wu@arm.com
10537605SGene.Wu@arm.com    dsbCode = '''
105410037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
105510037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr,
105610037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
105710474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
105810037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
105910037SARM gem5 Developers        }
106010474Sandreas.hansson@arm.com        fault = std::make_shared<FlushPipe>();
10617605SGene.Wu@arm.com    '''
106210037SARM gem5 Developers    dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
10637605SGene.Wu@arm.com                             {"code": dsbCode,
10648068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
10658068SAli.Saidi@ARM.com                              ['IsMemBarrier', 'IsSerializeAfter'])
106610037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dsbIop)
106710037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dsbIop)
10687605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dsbIop)
10697605SGene.Wu@arm.com
10707605SGene.Wu@arm.com    dmbCode = '''
107110037SARM gem5 Developers        // If the barrier is due to a CP15 access check for hyp traps
107210037SARM gem5 Developers        if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr,
107310037SARM gem5 Developers            Hdcr, Hstr, Hcptr, imm)) {
107410474Sandreas.hansson@arm.com            return std::make_shared<HypervisorTrap>(machInst, imm,
107510037SARM gem5 Developers                EC_TRAPPED_CP15_MCR_MRC);
107610037SARM gem5 Developers        }
10777605SGene.Wu@arm.com    '''
107810037SARM gem5 Developers    dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
10797605SGene.Wu@arm.com                             {"code": dmbCode,
10808068SAli.Saidi@ARM.com                               "predicate_test": predicateTest},
10818068SAli.Saidi@ARM.com                               ['IsMemBarrier'])
108210037SARM gem5 Developers    header_output += ImmOpDeclare.subst(dmbIop)
108310037SARM gem5 Developers    decoder_output += ImmOpConstructor.subst(dmbIop)
10847605SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dmbIop)
10857605SGene.Wu@arm.com
10867613SGene.Wu@arm.com    dbgCode = '''
10877613SGene.Wu@arm.com    '''
10887613SGene.Wu@arm.com    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
10897613SGene.Wu@arm.com                             {"code": dbgCode,
10907613SGene.Wu@arm.com                               "predicate_test": predicateTest})
10917613SGene.Wu@arm.com    header_output += BasicDeclare.subst(dbgIop)
10927613SGene.Wu@arm.com    decoder_output += BasicConstructor.subst(dbgIop)
10937613SGene.Wu@arm.com    exec_output += PredOpExecute.subst(dbgIop)
10947613SGene.Wu@arm.com
10957315Sgblack@eecs.umich.edu    cpsCode = '''
10967315Sgblack@eecs.umich.edu    uint32_t mode = bits(imm, 4, 0);
10977315Sgblack@eecs.umich.edu    uint32_t f = bits(imm, 5);
10987315Sgblack@eecs.umich.edu    uint32_t i = bits(imm, 6);
10997315Sgblack@eecs.umich.edu    uint32_t a = bits(imm, 7);
11007315Sgblack@eecs.umich.edu    bool setMode = bits(imm, 8);
11017315Sgblack@eecs.umich.edu    bool enable = bits(imm, 9);
11027315Sgblack@eecs.umich.edu    CPSR cpsr = Cpsr;
11037400SAli.Saidi@ARM.com    SCTLR sctlr = Sctlr;
11047315Sgblack@eecs.umich.edu    if (cpsr.mode != MODE_USER) {
11057315Sgblack@eecs.umich.edu        if (enable) {
11067315Sgblack@eecs.umich.edu            if (f) cpsr.f = 0;
11077315Sgblack@eecs.umich.edu            if (i) cpsr.i = 0;
11087315Sgblack@eecs.umich.edu            if (a) cpsr.a = 0;
11097315Sgblack@eecs.umich.edu        } else {
11107400SAli.Saidi@ARM.com            if (f && !sctlr.nmfi) cpsr.f = 1;
11117315Sgblack@eecs.umich.edu            if (i) cpsr.i = 1;
11127315Sgblack@eecs.umich.edu            if (a) cpsr.a = 1;
11137315Sgblack@eecs.umich.edu        }
11147315Sgblack@eecs.umich.edu        if (setMode) {
11157315Sgblack@eecs.umich.edu            cpsr.mode = mode;
11167315Sgblack@eecs.umich.edu        }
11177315Sgblack@eecs.umich.edu    }
11187315Sgblack@eecs.umich.edu    Cpsr = cpsr;
11197315Sgblack@eecs.umich.edu    '''
11207315Sgblack@eecs.umich.edu    cpsIop = InstObjParams("cps", "Cps", "ImmOp",
11217315Sgblack@eecs.umich.edu                           { "code": cpsCode,
11227599Sminkyu.jeong@arm.com                             "predicate_test": predicateTest },
11237599Sminkyu.jeong@arm.com                           ["IsSerializeAfter","IsNonSpeculative"])
11247315Sgblack@eecs.umich.edu    header_output += ImmOpDeclare.subst(cpsIop)
11257315Sgblack@eecs.umich.edu    decoder_output += ImmOpConstructor.subst(cpsIop)
11267315Sgblack@eecs.umich.edu    exec_output += PredOpExecute.subst(cpsIop)
11277202Sgblack@eecs.umich.edu}};
1128