mem.isa revision 8140:7449084b1612
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 class LoadStoreInst(object): 43 def __init__(self): 44 self.fullExecTemplate = eval(self.execBase + 'Execute') 45 self.initiateAccTemplate = eval(self.execBase + 'InitiateAcc') 46 self.completeAccTemplate = eval(self.execBase + 'CompleteAcc') 47 self.declareTemplate = eval(self.decConstBase + 'Declare') 48 self.constructTemplate = eval(self.decConstBase + 'Constructor') 49 50 def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags, 51 base = 'Memory', wbDecl = None, pcDecl = None): 52 # Make sure flags are in lists (convert to lists if not). 53 memFlags = makeList(memFlags) 54 instFlags = makeList(instFlags) 55 56 eaCode = codeBlobs["ea_code"] 57 58 # This shouldn't be part of the eaCode, but until the exec templates 59 # are converted over it's the easiest place to put it. 60 eaCode += '\n unsigned memAccessFlags = ' 61 eaCode += (string.join(memFlags, '|') + ';') 62 63 codeBlobs["ea_code"] = eaCode 64 65 macroName = Name 66 instFlagsCopy = list(instFlags) 67 codeBlobsCopy = dict(codeBlobs) 68 69 use_uops = 0 70 if wbDecl is not None or pcDecl is not None: 71 instFlagsCopy.append('IsMicroop') 72 Name = Name + 'Acc' 73 use_uops = 1 74 75 use_wb = 0 76 use_pc = 0 77 if wbDecl is not None: 78 use_wb = 1 79 if pcDecl is not None: 80 use_pc = 1 81 82 codeBlobsCopy['acc_name'] = Name 83 codeBlobsCopy['wb_decl'] = wbDecl 84 codeBlobsCopy['pc_decl'] = pcDecl 85 codeBlobsCopy['use_uops'] = 0 86 codeBlobsCopy['use_wb'] = 0 87 codeBlobsCopy['use_pc'] = 0 88 89 iop = InstObjParams(name, Name, base, 90 codeBlobsCopy, instFlagsCopy) 91 92 header_output = self.declareTemplate.subst(iop) 93 decoder_output = self.constructTemplate.subst(iop) 94 exec_output = self.fullExecTemplate.subst(iop) + \ 95 self.initiateAccTemplate.subst(iop) + \ 96 self.completeAccTemplate.subst(iop) 97 98 if wbDecl is not None or pcDecl is not None: 99 iop = InstObjParams(name, macroName, base, 100 { "wb_decl" : wbDecl, 101 "pc_decl" : pcDecl, 102 "acc_name" : Name, 103 "use_uops" : use_uops, 104 "use_pc" : use_pc, 105 "use_wb" : use_wb }, 106 ['IsMacroop']) 107 header_output += self.declareTemplate.subst(iop) 108 decoder_output += self.constructTemplate.subst(iop) 109 exec_output += PanicExecute.subst(iop) + \ 110 PanicInitiateAcc.subst(iop) + \ 111 PanicCompleteAcc.subst(iop) 112 113 return (header_output, decoder_output, exec_output) 114 115 def pickPredicate(blobs): 116 for val in blobs.values(): 117 if re.search('(?<!Opt)CondCodes', val): 118 return condPredicateTest 119 return predicateTest 120 121 def memClassName(base, post, add, writeback, \ 122 size=4, sign=False, user=False): 123 Name = base 124 125 parts = { "P" : post, "A" : add, "W" : writeback, 126 "S" : sign, "U" : user } 127 128 for (letter, val) in parts.items(): 129 if val: 130 Name += "_%sY" % letter 131 else: 132 Name += "_%sN" % letter 133 134 Name += ('_SZ%d' % size) 135 136 return Name 137 138 def buildMemSuffix(sign, size): 139 if size == 4: 140 memSuffix = '' 141 elif size == 2: 142 if sign: 143 memSuffix = '.sh' 144 else: 145 memSuffix = '.uh' 146 elif size == 1: 147 if sign: 148 memSuffix = '.sb' 149 else: 150 memSuffix = '.ub' 151 else: 152 raise Exception, "Unrecognized size for access %d" % size 153 154 return memSuffix 155 156 def buildMemBase(base, post, writeback): 157 if post and writeback: 158 base = "MemoryPostIndex<%s>" % base 159 elif not post and writeback: 160 base = "MemoryPreIndex<%s>" % base 161 elif not post and not writeback: 162 base = "MemoryOffset<%s>" % base 163 else: 164 raise Exception, "Illegal combination of post and writeback" 165 return base 166}}; 167 168