mem.isa revision 7292:f4d99c45743e 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41    def loadStoreBaseWork(name, Name, imm, swp, rfe, codeBlobs, memFlags,
42                          instFlags, double, base = 'Memory',
43                          execTemplateBase = ''):
44        # Make sure flags are in lists (convert to lists if not).
45        memFlags = makeList(memFlags)
46        instFlags = makeList(instFlags)
47
48        eaCode = codeBlobs["ea_code"]
49
50        # This shouldn't be part of the eaCode, but until the exec templates
51        # are converted over it's the easiest place to put it.
52        eaCode += '\n    unsigned memAccessFlags = '
53        if memFlags:
54            eaCode += (string.join(memFlags, '|') + ';')
55        else:
56            eaCode += '0;'
57
58        codeBlobs["ea_code"] = eaCode
59
60        iop = InstObjParams(name, Name, base, codeBlobs, instFlags)
61
62        fullExecTemplate = eval(execTemplateBase + 'Execute')
63        initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc')
64        completeAccTemplate = eval(execTemplateBase + 'CompleteAcc')
65
66        if swp:
67            declareTemplate = SwapDeclare
68            constructTemplate = SwapConstructor
69        elif rfe:
70            declareTemplate = RfeDeclare
71            constructTemplate = RfeConstructor
72        elif imm:
73            if double:
74                declareTemplate = LoadStoreDImmDeclare
75                constructTemplate = LoadStoreDImmConstructor
76            else:
77                declareTemplate = LoadStoreImmDeclare
78                constructTemplate = LoadStoreImmConstructor
79        else:
80            if double:
81                declareTemplate = LoadStoreDRegDeclare
82                constructTemplate = LoadStoreDRegConstructor
83            else:
84                declareTemplate = LoadStoreRegDeclare
85                constructTemplate = LoadStoreRegConstructor
86
87        # (header_output, decoder_output, decode_block, exec_output)
88        return (declareTemplate.subst(iop),
89                constructTemplate.subst(iop),
90                fullExecTemplate.subst(iop)
91                + initiateAccTemplate.subst(iop)
92                + completeAccTemplate.subst(iop))
93
94    def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags,
95                      instFlags, double, base = 'Memory',
96                      execTemplateBase = ''):
97        codeBlobs = { "ea_code": eaCode,
98                      "memacc_code": accCode,
99                      "predicate_test": predicateTest }
100        return loadStoreBaseWork(name, Name, imm, False, False, codeBlobs,
101                                 memFlags, instFlags, double, base,
102                                 execTemplateBase)
103
104    def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags):
105        codeBlobs = { "ea_code": eaCode,
106                      "memacc_code": accCode,
107                      "predicate_test": predicateTest }
108        return loadStoreBaseWork(name, Name, False, False, True, codeBlobs,
109                                 memFlags, instFlags, False, 'RfeOp', 'Load')
110
111    def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
112                 instFlags):
113        codeBlobs = { "ea_code": eaCode,
114                      "preacc_code": preAccCode,
115                      "postacc_code": postAccCode,
116                      "predicate_test": predicateTest }
117        return loadStoreBaseWork(name, Name, False, True, False, codeBlobs,
118                                 memFlags, instFlags, False, 'Swap', 'Swap')
119
120    def memClassName(base, post, add, writeback, \
121                     size=4, sign=False, user=False):
122        Name = base
123
124        if post:
125            Name += '_PY'
126        else:
127            Name += '_PN'
128
129        if add:
130            Name += '_AY'
131        else:
132            Name += '_AN'
133
134        if writeback:
135            Name += '_WY'
136        else:
137            Name += '_WN'
138
139        Name += ('_SZ%d' % size)
140
141        if sign:
142            Name += '_SY'
143        else:
144            Name += '_SN'
145
146        if user:
147            Name += '_UY'
148        else:
149            Name += '_UN'
150
151        return Name
152
153    def buildMemSuffix(sign, size):
154        if size == 4:
155            memSuffix = ''
156        elif size == 2:
157            if sign:
158                memSuffix = '.sh'
159            else:
160                memSuffix = '.uh'
161        elif size == 1:
162            if sign:
163                memSuffix = '.sb'
164            else:
165                memSuffix = '.ub'
166        else:
167            raise Exception, "Unrecognized size for load %d" % size
168
169        return memSuffix
170
171    def buildMemBase(base, post, writeback):
172        if post and writeback:
173            base = "MemoryPostIndex<%s>" % base
174        elif not post and writeback:
175            base = "MemoryPreIndex<%s>" % base
176        elif not post and not writeback:
177            base = "MemoryOffset<%s>" % base
178        else:
179            raise Exception, "Illegal combination of post and writeback"
180        return base
181}};
182
183