mem.isa revision 8442
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37119Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47119Sgblack@eecs.umich.edu// All rights reserved 57119Sgblack@eecs.umich.edu// 67119Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77119Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87119Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97119Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107119Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117119Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127119Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137119Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147119Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247119Sgblack@eecs.umich.edu// this software without specific prior written permission. 257119Sgblack@eecs.umich.edu// 267119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119Sgblack@eecs.umich.edu// 387119Sgblack@eecs.umich.edu// Authors: Gabe Black 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.edulet {{ 417119Sgblack@eecs.umich.edu 427590Sgblack@eecs.umich.edu class LoadStoreInst(object): 437590Sgblack@eecs.umich.edu def __init__(self): 447590Sgblack@eecs.umich.edu self.fullExecTemplate = eval(self.execBase + 'Execute') 457590Sgblack@eecs.umich.edu self.initiateAccTemplate = eval(self.execBase + 'InitiateAcc') 467590Sgblack@eecs.umich.edu self.completeAccTemplate = eval(self.execBase + 'CompleteAcc') 477590Sgblack@eecs.umich.edu self.declareTemplate = eval(self.decConstBase + 'Declare') 487590Sgblack@eecs.umich.edu self.constructTemplate = eval(self.decConstBase + 'Constructor') 497205Sgblack@eecs.umich.edu 507590Sgblack@eecs.umich.edu def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags, 518203SAli.Saidi@ARM.com base = 'Memory', wbDecl = None, pcDecl = None, 528203SAli.Saidi@ARM.com rasPop = False): 537590Sgblack@eecs.umich.edu # Make sure flags are in lists (convert to lists if not). 547590Sgblack@eecs.umich.edu memFlags = makeList(memFlags) 557590Sgblack@eecs.umich.edu instFlags = makeList(instFlags) 567119Sgblack@eecs.umich.edu 577590Sgblack@eecs.umich.edu eaCode = codeBlobs["ea_code"] 587205Sgblack@eecs.umich.edu 597590Sgblack@eecs.umich.edu # This shouldn't be part of the eaCode, but until the exec templates 607590Sgblack@eecs.umich.edu # are converted over it's the easiest place to put it. 617590Sgblack@eecs.umich.edu eaCode += '\n unsigned memAccessFlags = ' 627590Sgblack@eecs.umich.edu eaCode += (string.join(memFlags, '|') + ';') 637119Sgblack@eecs.umich.edu 647590Sgblack@eecs.umich.edu codeBlobs["ea_code"] = eaCode 657119Sgblack@eecs.umich.edu 667646Sgene.wu@arm.com macroName = Name 677646Sgene.wu@arm.com instFlagsCopy = list(instFlags) 687646Sgene.wu@arm.com codeBlobsCopy = dict(codeBlobs) 698140SMatt.Horsnell@arm.com 708140SMatt.Horsnell@arm.com use_uops = 0 718140SMatt.Horsnell@arm.com if wbDecl is not None or pcDecl is not None: 727646Sgene.wu@arm.com instFlagsCopy.append('IsMicroop') 737646Sgene.wu@arm.com Name = Name + 'Acc' 748140SMatt.Horsnell@arm.com use_uops = 1 758140SMatt.Horsnell@arm.com 768140SMatt.Horsnell@arm.com use_wb = 0 778140SMatt.Horsnell@arm.com use_pc = 0 788140SMatt.Horsnell@arm.com if wbDecl is not None: 798140SMatt.Horsnell@arm.com use_wb = 1 808140SMatt.Horsnell@arm.com if pcDecl is not None: 818140SMatt.Horsnell@arm.com use_pc = 1 828140SMatt.Horsnell@arm.com 837646Sgene.wu@arm.com codeBlobsCopy['acc_name'] = Name 847646Sgene.wu@arm.com codeBlobsCopy['wb_decl'] = wbDecl 858140SMatt.Horsnell@arm.com codeBlobsCopy['pc_decl'] = pcDecl 867646Sgene.wu@arm.com codeBlobsCopy['use_uops'] = 0 878140SMatt.Horsnell@arm.com codeBlobsCopy['use_wb'] = 0 888140SMatt.Horsnell@arm.com codeBlobsCopy['use_pc'] = 0 898203SAli.Saidi@ARM.com is_ras_pop = "0" 908203SAli.Saidi@ARM.com if rasPop: 918203SAli.Saidi@ARM.com is_ras_pop = "1" 928203SAli.Saidi@ARM.com codeBlobsCopy['is_ras_pop'] = is_ras_pop 937119Sgblack@eecs.umich.edu 947646Sgene.wu@arm.com iop = InstObjParams(name, Name, base, 957646Sgene.wu@arm.com codeBlobsCopy, instFlagsCopy) 967646Sgene.wu@arm.com 977646Sgene.wu@arm.com header_output = self.declareTemplate.subst(iop) 987646Sgene.wu@arm.com decoder_output = self.constructTemplate.subst(iop) 997646Sgene.wu@arm.com exec_output = self.fullExecTemplate.subst(iop) + \ 1007646Sgene.wu@arm.com self.initiateAccTemplate.subst(iop) + \ 1017646Sgene.wu@arm.com self.completeAccTemplate.subst(iop) 1027646Sgene.wu@arm.com 1038140SMatt.Horsnell@arm.com if wbDecl is not None or pcDecl is not None: 1047646Sgene.wu@arm.com iop = InstObjParams(name, macroName, base, 1057646Sgene.wu@arm.com { "wb_decl" : wbDecl, 1068140SMatt.Horsnell@arm.com "pc_decl" : pcDecl, 1077646Sgene.wu@arm.com "acc_name" : Name, 1088140SMatt.Horsnell@arm.com "use_uops" : use_uops, 1098140SMatt.Horsnell@arm.com "use_pc" : use_pc, 1108203SAli.Saidi@ARM.com "use_wb" : use_wb, 1118203SAli.Saidi@ARM.com "is_ras_pop" : is_ras_pop }, 1127646Sgene.wu@arm.com ['IsMacroop']) 1137646Sgene.wu@arm.com header_output += self.declareTemplate.subst(iop) 1147646Sgene.wu@arm.com decoder_output += self.constructTemplate.subst(iop) 1157646Sgene.wu@arm.com exec_output += PanicExecute.subst(iop) + \ 1167646Sgene.wu@arm.com PanicInitiateAcc.subst(iop) + \ 1177646Sgene.wu@arm.com PanicCompleteAcc.subst(iop) 1187646Sgene.wu@arm.com 1197646Sgene.wu@arm.com return (header_output, decoder_output, exec_output) 1207119Sgblack@eecs.umich.edu 1217422Sgblack@eecs.umich.edu def pickPredicate(blobs): 1228303SAli.Saidi@ARM.com opt_nz = True 1238304SAli.Saidi@ARM.com opt_c = 'opt' 1248303SAli.Saidi@ARM.com opt_v = True 1258304SAli.Saidi@ARM.com 1268304SAli.Saidi@ARM.com if not isinstance(blobs, dict): 1278304SAli.Saidi@ARM.com vals = [blobs] 1288304SAli.Saidi@ARM.com else: 1298304SAli.Saidi@ARM.com vals = blobs.values() 1308304SAli.Saidi@ARM.com for val in vals: 1318304SAli.Saidi@ARM.com if re.search('(?<!Opt)CondCodesNZ(?!.*=)', val): 1328303SAli.Saidi@ARM.com opt_nz = False 1338304SAli.Saidi@ARM.com if re.search('OptShiftRmCondCodesC(?!.*=)', val): 1348304SAli.Saidi@ARM.com opt_c = 'opt_shift_rm' 1358304SAli.Saidi@ARM.com elif re.search('(?<!Opt)CondCodesC(?!.*=)', val): 1368304SAli.Saidi@ARM.com opt_c = 'none' 1378304SAli.Saidi@ARM.com if re.search('(?<!Opt)CondCodesV(?!.*=)', val): 1388303SAli.Saidi@ARM.com opt_v = False 1398303SAli.Saidi@ARM.com 1408303SAli.Saidi@ARM.com # Build up the predicate piece by piece depending on which 1418303SAli.Saidi@ARM.com # flags the instruction needs 1428303SAli.Saidi@ARM.com predicate = 'testPredicate(' 1438303SAli.Saidi@ARM.com if opt_nz: 1448303SAli.Saidi@ARM.com predicate += 'OptCondCodesNZ, ' 1458303SAli.Saidi@ARM.com else: 1468303SAli.Saidi@ARM.com predicate += 'CondCodesNZ, ' 1478304SAli.Saidi@ARM.com if opt_c == 'opt': 1488303SAli.Saidi@ARM.com predicate += 'OptCondCodesC, ' 1498304SAli.Saidi@ARM.com elif opt_c == 'opt_shift_rm': 1508304SAli.Saidi@ARM.com predicate += 'OptShiftRmCondCodesC, ' 1518303SAli.Saidi@ARM.com else: 1528303SAli.Saidi@ARM.com predicate += 'CondCodesC, ' 1538303SAli.Saidi@ARM.com if opt_v: 1548303SAli.Saidi@ARM.com predicate += 'OptCondCodesV, ' 1558303SAli.Saidi@ARM.com else: 1568303SAli.Saidi@ARM.com predicate += 'CondCodesV, ' 1578303SAli.Saidi@ARM.com predicate += 'condCode)' 1588304SAli.Saidi@ARM.com predicate += '/*auto*/' 1598303SAli.Saidi@ARM.com return predicate 1607422Sgblack@eecs.umich.edu 1617119Sgblack@eecs.umich.edu def memClassName(base, post, add, writeback, \ 1627119Sgblack@eecs.umich.edu size=4, sign=False, user=False): 1637119Sgblack@eecs.umich.edu Name = base 1647119Sgblack@eecs.umich.edu 1657590Sgblack@eecs.umich.edu parts = { "P" : post, "A" : add, "W" : writeback, 1667590Sgblack@eecs.umich.edu "S" : sign, "U" : user } 1677119Sgblack@eecs.umich.edu 1687590Sgblack@eecs.umich.edu for (letter, val) in parts.items(): 1697590Sgblack@eecs.umich.edu if val: 1707590Sgblack@eecs.umich.edu Name += "_%sY" % letter 1717590Sgblack@eecs.umich.edu else: 1727590Sgblack@eecs.umich.edu Name += "_%sN" % letter 1737119Sgblack@eecs.umich.edu 1747119Sgblack@eecs.umich.edu Name += ('_SZ%d' % size) 1757119Sgblack@eecs.umich.edu 1767119Sgblack@eecs.umich.edu return Name 1777119Sgblack@eecs.umich.edu 1787119Sgblack@eecs.umich.edu def buildMemSuffix(sign, size): 1797119Sgblack@eecs.umich.edu if size == 4: 1807119Sgblack@eecs.umich.edu memSuffix = '' 1817119Sgblack@eecs.umich.edu elif size == 2: 1827119Sgblack@eecs.umich.edu if sign: 1837119Sgblack@eecs.umich.edu memSuffix = '.sh' 1847119Sgblack@eecs.umich.edu else: 1857119Sgblack@eecs.umich.edu memSuffix = '.uh' 1867119Sgblack@eecs.umich.edu elif size == 1: 1877119Sgblack@eecs.umich.edu if sign: 1887119Sgblack@eecs.umich.edu memSuffix = '.sb' 1897119Sgblack@eecs.umich.edu else: 1907119Sgblack@eecs.umich.edu memSuffix = '.ub' 1917119Sgblack@eecs.umich.edu else: 1927590Sgblack@eecs.umich.edu raise Exception, "Unrecognized size for access %d" % size 1937119Sgblack@eecs.umich.edu 1947119Sgblack@eecs.umich.edu return memSuffix 1957119Sgblack@eecs.umich.edu 1967119Sgblack@eecs.umich.edu def buildMemBase(base, post, writeback): 1977119Sgblack@eecs.umich.edu if post and writeback: 1987132Sgblack@eecs.umich.edu base = "MemoryPostIndex<%s>" % base 1997119Sgblack@eecs.umich.edu elif not post and writeback: 2007132Sgblack@eecs.umich.edu base = "MemoryPreIndex<%s>" % base 2017119Sgblack@eecs.umich.edu elif not post and not writeback: 2027132Sgblack@eecs.umich.edu base = "MemoryOffset<%s>" % base 2037119Sgblack@eecs.umich.edu else: 2047119Sgblack@eecs.umich.edu raise Exception, "Illegal combination of post and writeback" 2057119Sgblack@eecs.umich.edu return base 2067119Sgblack@eecs.umich.edu}}; 2077119Sgblack@eecs.umich.edu 208