ldr64.isa revision 13759:9941fca869a9
1// -*- mode:c++ -*- 2 3// Copyright (c) 2011-2014, 2017 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 class LoadInst64(LoadStoreInst): 47 execBase = 'Load64' 48 micro = False 49 50 def __init__(self, mnem, Name, size=4, sign=False, user=False, 51 literal=False, flavor="normal", top=False): 52 super(LoadInst64, self).__init__() 53 54 self.name = mnem 55 self.Name = Name 56 self.size = size 57 self.sign = sign 58 self.user = user 59 self.literal = literal 60 self.flavor = flavor 61 self.top = top 62 63 self.memFlags = ["ArmISA::TLB::MustBeOne"] 64 self.instFlags = [] 65 self.codeBlobs = {"postacc_code" : ""} 66 67 # Add memory request flags where necessary 68 if self.user: 69 self.memFlags.append("ArmISA::TLB::UserMode") 70 71 if self.flavor == "dprefetch": 72 self.memFlags.append("Request::PREFETCH") 73 self.instFlags = ['IsDataPrefetch'] 74 elif self.flavor == "iprefetch": 75 self.memFlags.append("Request::PREFETCH") 76 self.instFlags = ['IsInstPrefetch'] 77 elif self.flavor == "mprefetch": 78 self.memFlags.append("((((dest>>3)&3)==2)? \ 79 (Request::PF_EXCLUSIVE):(Request::PREFETCH))") 80 self.instFlags = ['IsDataPrefetch'] 81 if self.micro: 82 self.instFlags.append("IsMicroop") 83 84 if self.flavor in ("acexp", "exp"): 85 # For exclusive pair ops alignment check is based on total size 86 self.memFlags.append("%d" % int(math.log(self.size, 2) + 1)) 87 elif not (self.size == 16 and self.top): 88 # Only the first microop should perform alignment checking. 89 self.memFlags.append("%d" % int(math.log(self.size, 2))) 90 91 if self.flavor not in ("acquire", "acex", "exclusive", 92 "acexp", "exp"): 93 self.memFlags.append("ArmISA::TLB::AllowUnaligned") 94 95 if self.flavor in ("acquire", "acex", "acexp"): 96 self.instFlags.extend(["IsMemBarrier", 97 "IsWriteBarrier", 98 "IsReadBarrier"]) 99 if self.flavor in ("acex", "exclusive", "exp", "acexp"): 100 self.memFlags.append("Request::LLSC") 101 102 def buildEACode(self): 103 # Address computation code 104 eaCode = "" 105 if self.flavor == "fp": 106 eaCode += vfp64EnabledCheckCode 107 108 if self.literal: 109 eaCode += "EA = RawPC" 110 else: 111 eaCode += SPAlignmentCheckCode + "EA = XBase" 112 113 if self.size == 16: 114 if self.top: 115 eaCode += " + (isBigEndian64(xc->tcBase()) ? 0 : 8)" 116 else: 117 eaCode += " + (isBigEndian64(xc->tcBase()) ? 8 : 0)" 118 if not self.post: 119 eaCode += self.offset 120 eaCode += ";" 121 122 self.codeBlobs["ea_code"] = eaCode 123 124 def emitHelper(self, base='Memory64', wbDecl=None): 125 global header_output, decoder_output, exec_output 126 127 # If this is a microop itself, don't allow anything that would 128 # require further microcoding. 129 if self.micro: 130 assert not wbDecl 131 132 fa_code = None 133 if not self.micro and self.flavor in ("normal", "widen", "acquire"): 134 fa_code = ''' 135 fault->annotate(ArmFault::SAS, %s); 136 fault->annotate(ArmFault::SSE, %s); 137 fault->annotate(ArmFault::SRT, dest); 138 fault->annotate(ArmFault::SF, %s); 139 fault->annotate(ArmFault::AR, %s); 140 ''' % ("0" if self.size == 1 else 141 "1" if self.size == 2 else 142 "2" if self.size == 4 else "3", 143 "true" if self.sign else "false", 144 "true" if (self.size == 8 or 145 self.flavor == "widen") else "false", 146 "true" if self.flavor == "acquire" else "false") 147 148 (newHeader, newDecoder, newExec) = \ 149 self.fillTemplates(self.name, self.Name, self.codeBlobs, 150 self.memFlags, self.instFlags, 151 base, wbDecl, faCode=fa_code) 152 153 header_output += newHeader 154 decoder_output += newDecoder 155 exec_output += newExec 156 157 class LoadImmInst64(LoadInst64): 158 def __init__(self, *args, **kargs): 159 super(LoadImmInst64, self).__init__(*args, **kargs) 160 self.offset = " + imm" 161 162 self.wbDecl = "MicroAddXiUop(machInst, base, base, imm);" 163 164 class LoadRegInst64(LoadInst64): 165 def __init__(self, *args, **kargs): 166 super(LoadRegInst64, self).__init__(*args, **kargs) 167 self.offset = " + extendReg64(XOffset, type, shiftAmt, 64)" 168 169 self.wbDecl = \ 170 "MicroAddXERegUop(machInst, base, base, " + \ 171 " offset, type, shiftAmt);" 172 173 class LoadRawRegInst64(LoadInst64): 174 def __init__(self, *args, **kargs): 175 super(LoadRawRegInst64, self).__init__(*args, **kargs) 176 self.offset = "" 177 178 class LoadSingle64(LoadInst64): 179 def emit(self): 180 self.buildEACode() 181 182 accEpilogCode = None 183 # Code that actually handles the access 184 if self.flavor in ("dprefetch", "iprefetch", "mprefetch"): 185 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;' 186 elif self.flavor == "fp": 187 accEpilogCode = ''' 188 TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest, 189 ArmStaticInst::getCurSveVecLen<uint64_t>( 190 xc->tcBase())); 191 ''' 192 if self.size in (1, 2, 4): 193 accCode = ''' 194 AA64FpDestP0_uw = cSwap(Mem%s, 195 isBigEndian64(xc->tcBase())); 196 AA64FpDestP1_uw = 0; 197 AA64FpDestP2_uw = 0; 198 AA64FpDestP3_uw = 0; 199 ''' 200 elif self.size == 8: 201 accCode = ''' 202 uint64_t data = cSwap(Mem%s, 203 isBigEndian64(xc->tcBase())); 204 AA64FpDestP0_uw = (uint32_t)data; 205 AA64FpDestP1_uw = (data >> 32); 206 AA64FpDestP2_uw = 0; 207 AA64FpDestP3_uw = 0; 208 ''' 209 elif self.size == 16: 210 accCode = ''' 211 auto data = cSwap(Mem%s, isBigEndian64(xc->tcBase())); 212 AA64FpDestP0_uw = (uint32_t)data[0]; 213 AA64FpDestP1_uw = (data[0] >> 32); 214 AA64FpDestP2_uw = (uint32_t)data[1]; 215 AA64FpDestP3_uw = (data[1] >> 32); 216 ''' 217 elif self.flavor == "widen" or self.size == 8: 218 accCode = "XDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));" 219 else: 220 accCode = "WDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));" 221 222 accCode = accCode % buildMemSuffix(self.sign, self.size) 223 224 self.codeBlobs["memacc_code"] = accCode 225 if accEpilogCode: 226 self.codeBlobs["memacc_epilog_code"] = accEpilogCode 227 228 # Push it out to the output files 229 wbDecl = None 230 if self.writeback and not self.micro: 231 wbDecl = self.wbDecl 232 self.emitHelper(self.base, wbDecl) 233 234 class LoadDouble64(LoadInst64): 235 def emit(self): 236 self.buildEACode() 237 238 accEpilogCode = None 239 # Code that actually handles the access 240 if self.flavor == "fp": 241 accEpilogCode = ''' 242 TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest, 243 ArmStaticInst::getCurSveVecLen<uint64_t>( 244 xc->tcBase())); 245 TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2, 246 ArmStaticInst::getCurSveVecLen<uint64_t>( 247 xc->tcBase())); 248 ''' 249 if self.size == 4: 250 accCode = ''' 251 uint64_t data = cSwap(Mem_ud, isBigEndian64(xc->tcBase())); 252 AA64FpDestP0_uw = isBigEndian64(xc->tcBase()) 253 ? (data >> 32) 254 : (uint32_t)data; 255 AA64FpDestP1_uw = 0; 256 AA64FpDestP2_uw = 0; 257 AA64FpDestP3_uw = 0; 258 AA64FpDest2P0_uw = isBigEndian64(xc->tcBase()) 259 ? (uint32_t)data 260 : (data >> 32); 261 AA64FpDest2P1_uw = 0; 262 AA64FpDest2P2_uw = 0; 263 AA64FpDest2P3_uw = 0; 264 ''' 265 elif self.size == 8: 266 accCode = ''' 267 uint64_t data_a = cSwap(Mem_tud[0], 268 isBigEndian64(xc->tcBase())); 269 uint64_t data_b = cSwap(Mem_tud[1], 270 isBigEndian64(xc->tcBase())); 271 AA64FpDestP0_uw = (uint32_t)data_a; 272 AA64FpDestP1_uw = (uint32_t)(data_a >> 32); 273 AA64FpDestP2_uw = 0; 274 AA64FpDestP3_uw = 0; 275 AA64FpDest2P0_uw = (uint32_t)data_b; 276 AA64FpDest2P1_uw = (uint32_t)(data_b >> 32); 277 AA64FpDest2P2_uw = 0; 278 AA64FpDest2P3_uw = 0; 279 ''' 280 else: 281 if self.sign: 282 if self.size == 4: 283 accCode = ''' 284 uint64_t data = cSwap(Mem_ud, 285 isBigEndian64(xc->tcBase())); 286 XDest = isBigEndian64(xc->tcBase()) 287 ? sext<32>(data >> 32) 288 : sext<32>((uint32_t)data); 289 XDest2 = isBigEndian64(xc->tcBase()) 290 ? sext<32>((uint32_t)data) 291 : sext<32>(data >> 32); 292 ''' 293 elif self.size == 8: 294 accCode = ''' 295 XDest = cSwap(Mem_tud[0], 296 isBigEndian64(xc->tcBase())); 297 XDest2 = cSwap(Mem_tud[1], 298 isBigEndian64(xc->tcBase())); 299 ''' 300 else: 301 if self.size == 4: 302 accCode = ''' 303 uint64_t data = cSwap(Mem_ud, 304 isBigEndian64(xc->tcBase())); 305 XDest = isBigEndian64(xc->tcBase()) 306 ? (data >> 32) 307 : (uint32_t)data; 308 XDest2 = isBigEndian64(xc->tcBase()) 309 ? (uint32_t)data 310 : (data >> 32); 311 ''' 312 elif self.size == 8: 313 accCode = ''' 314 XDest = cSwap(Mem_tud[0], 315 isBigEndian64(xc->tcBase())); 316 XDest2 = cSwap(Mem_tud[1], 317 isBigEndian64(xc->tcBase())); 318 ''' 319 self.codeBlobs["memacc_code"] = accCode 320 if accEpilogCode: 321 self.codeBlobs["memacc_epilog_code"] = accEpilogCode 322 323 # Push it out to the output files 324 wbDecl = None 325 if self.writeback and not self.micro: 326 wbDecl = self.wbDecl 327 self.emitHelper(self.base, wbDecl) 328 329 class LoadImm64(LoadImmInst64, LoadSingle64): 330 decConstBase = 'LoadStoreImm64' 331 base = 'ArmISA::MemoryImm64' 332 writeback = False 333 post = False 334 335 class LoadPre64(LoadImmInst64, LoadSingle64): 336 decConstBase = 'LoadStoreImm64' 337 base = 'ArmISA::MemoryPreIndex64' 338 writeback = True 339 post = False 340 341 class LoadPost64(LoadImmInst64, LoadSingle64): 342 decConstBase = 'LoadStoreImm64' 343 base = 'ArmISA::MemoryPostIndex64' 344 writeback = True 345 post = True 346 347 class LoadReg64(LoadRegInst64, LoadSingle64): 348 decConstBase = 'LoadStoreReg64' 349 base = 'ArmISA::MemoryReg64' 350 writeback = False 351 post = False 352 353 class LoadRaw64(LoadRawRegInst64, LoadSingle64): 354 decConstBase = 'LoadStoreRaw64' 355 base = 'ArmISA::MemoryRaw64' 356 writeback = False 357 post = False 358 359 class LoadEx64(LoadRawRegInst64, LoadSingle64): 360 decConstBase = 'LoadStoreEx64' 361 base = 'ArmISA::MemoryEx64' 362 writeback = False 363 post = False 364 365 class LoadLit64(LoadImmInst64, LoadSingle64): 366 decConstBase = 'LoadStoreLit64' 367 base = 'ArmISA::MemoryLiteral64' 368 writeback = False 369 post = False 370 371 def buildLoads64(mnem, NameBase, size, sign, flavor="normal"): 372 LoadImm64(mnem, NameBase + "_IMM", size, sign, flavor=flavor).emit() 373 LoadPre64(mnem, NameBase + "_PRE", size, sign, flavor=flavor).emit() 374 LoadPost64(mnem, NameBase + "_POST", size, sign, flavor=flavor).emit() 375 LoadReg64(mnem, NameBase + "_REG", size, sign, flavor=flavor).emit() 376 377 buildLoads64("ldrb", "LDRB64", 1, False) 378 buildLoads64("ldrsb", "LDRSBW64", 1, True) 379 buildLoads64("ldrsb", "LDRSBX64", 1, True, flavor="widen") 380 buildLoads64("ldrh", "LDRH64", 2, False) 381 buildLoads64("ldrsh", "LDRSHW64", 2, True) 382 buildLoads64("ldrsh", "LDRSHX64", 2, True, flavor="widen") 383 buildLoads64("ldrsw", "LDRSW64", 4, True, flavor="widen") 384 buildLoads64("ldr", "LDRW64", 4, False) 385 buildLoads64("ldr", "LDRX64", 8, False) 386 buildLoads64("ldr", "LDRBFP64", 1, False, flavor="fp") 387 buildLoads64("ldr", "LDRHFP64", 2, False, flavor="fp") 388 buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp") 389 buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp") 390 391 LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit() 392 LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit() 393 LoadLit64("prfm", "PRFM64_LIT", 8, literal=True, 394 flavor="mprefetch").emit() 395 LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit() 396 397 LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit() 398 LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit() 399 LoadImm64("ldursb", "LDURSBX64_IMM", 1, True, flavor="widen").emit() 400 LoadImm64("ldurh", "LDURH64_IMM", 2, False).emit() 401 LoadImm64("ldursh", "LDURSHW64_IMM", 2, True).emit() 402 LoadImm64("ldursh", "LDURSHX64_IMM", 2, True, flavor="widen").emit() 403 LoadImm64("ldursw", "LDURSW64_IMM", 4, True, flavor="widen").emit() 404 LoadImm64("ldur", "LDURW64_IMM", 4, False).emit() 405 LoadImm64("ldur", "LDURX64_IMM", 8, False).emit() 406 LoadImm64("ldur", "LDURBFP64_IMM", 1, flavor="fp").emit() 407 LoadImm64("ldur", "LDURHFP64_IMM", 2, flavor="fp").emit() 408 LoadImm64("ldur", "LDURSFP64_IMM", 4, flavor="fp").emit() 409 LoadImm64("ldur", "LDURDFP64_IMM", 8, flavor="fp").emit() 410 411 LoadImm64("ldtrb", "LDTRB64_IMM", 1, False, True).emit() 412 LoadImm64("ldtrsb", "LDTRSBW64_IMM", 1, True, True).emit() 413 LoadImm64("ldtrsb", "LDTRSBX64_IMM", 1, True, True, flavor="widen").emit() 414 LoadImm64("ldtrh", "LDTRH64_IMM", 2, False, True).emit() 415 LoadImm64("ldtrsh", "LDTRSHW64_IMM", 2, True, True).emit() 416 LoadImm64("ldtrsh", "LDTRSHX64_IMM", 2, True, True, flavor="widen").emit() 417 LoadImm64("ldtrsw", "LDTRSW64_IMM", 4, True, flavor="widen").emit() 418 LoadImm64("ldtr", "LDTRW64_IMM", 4, False, True).emit() 419 LoadImm64("ldtr", "LDTRX64_IMM", 8, False, True).emit() 420 421 LoadLit64("ldrsw", "LDRSWL64_LIT", 4, True, \ 422 literal=True, flavor="widen").emit() 423 LoadLit64("ldr", "LDRWL64_LIT", 4, False, literal=True).emit() 424 LoadLit64("ldr", "LDRXL64_LIT", 8, False, literal=True).emit() 425 LoadLit64("ldr", "LDRSFP64_LIT", 4, literal=True, flavor="fp").emit() 426 LoadLit64("ldr", "LDRDFP64_LIT", 8, literal=True, flavor="fp").emit() 427 428 LoadRaw64("ldar", "LDARX64", 8, flavor="acquire").emit() 429 LoadRaw64("ldar", "LDARW64", 4, flavor="acquire").emit() 430 LoadRaw64("ldarh", "LDARH64", 2, flavor="acquire").emit() 431 LoadRaw64("ldarb", "LDARB64", 1, flavor="acquire").emit() 432 433 LoadEx64("ldaxr", "LDAXRX64", 8, flavor="acex").emit() 434 LoadEx64("ldaxr", "LDAXRW64", 4, flavor="acex").emit() 435 LoadEx64("ldaxrh", "LDAXRH64", 2, flavor="acex").emit() 436 LoadEx64("ldaxrb", "LDAXRB64", 1, flavor="acex").emit() 437 438 LoadEx64("ldxr", "LDXRX64", 8, flavor="exclusive").emit() 439 LoadEx64("ldxr", "LDXRW64", 4, flavor="exclusive").emit() 440 LoadEx64("ldxrh", "LDXRH64", 2, flavor="exclusive").emit() 441 LoadEx64("ldxrb", "LDXRB64", 1, flavor="exclusive").emit() 442 443 LoadRaw64("ldapr", "LDAPRX64", 8, flavor="acquire").emit() 444 LoadRaw64("ldapr", "LDAPRW64", 4, flavor="acquire").emit() 445 LoadRaw64("ldaprh", "LDAPRH64", 2, flavor="acquire").emit() 446 LoadRaw64("ldaprb", "LDAPRB64", 1, flavor="acquire").emit() 447 448 class LoadImmU64(LoadImm64): 449 decConstBase = 'LoadStoreImmU64' 450 micro = True 451 452 class LoadImmDU64(LoadImmInst64, LoadDouble64): 453 decConstBase = 'LoadStoreImmDU64' 454 base = 'ArmISA::MemoryDImm64' 455 micro = True 456 post = False 457 writeback = False 458 459 class LoadImmDouble64(LoadImmInst64, LoadDouble64): 460 decConstBase = 'LoadStoreImmDU64' 461 base = 'ArmISA::MemoryDImm64' 462 micro = False 463 post = False 464 writeback = False 465 466 class LoadRegU64(LoadReg64): 467 decConstBase = 'LoadStoreRegU64' 468 micro = True 469 470 class LoadLitU64(LoadLit64): 471 decConstBase = 'LoadStoreLitU64' 472 micro = True 473 474 LoadImmDU64("ldp_uop", "MicroLdPairUop", 8).emit() 475 LoadImmDU64("ldp_fp8_uop", "MicroLdPairFp8Uop", 8, flavor="fp").emit() 476 LoadImmU64("ldfp16_uop", "MicroLdFp16Uop", 16, flavor="fp").emit() 477 LoadReg64("ldfp16reg_uop", "MicroLdFp16RegUop", 16, flavor="fp").emit() 478 479 LoadImmDouble64("ldaxp", "LDAXPW64", 4, flavor="acexp").emit() 480 LoadImmDouble64("ldaxp", "LDAXPX64", 8, flavor="acexp").emit() 481 LoadImmDouble64("ldxp", "LDXPW64", 4, flavor="exp").emit() 482 LoadImmDouble64("ldxp", "LDXPX64", 8, flavor="exp").emit() 483 484 LoadImmU64("ldrxi_uop", "MicroLdrXImmUop", 8).emit() 485 LoadRegU64("ldrxr_uop", "MicroLdrXRegUop", 8).emit() 486 LoadLitU64("ldrxl_uop", "MicroLdrXLitUop", 8, literal=True).emit() 487 LoadImmU64("ldrfpxi_uop", "MicroLdrFpXImmUop", 8, flavor="fp").emit() 488 LoadRegU64("ldrfpxr_uop", "MicroLdrFpXRegUop", 8, flavor="fp").emit() 489 LoadLitU64("ldrfpxl_uop", "MicroLdrFpXLitUop", 8, literal=True, 490 flavor="fp").emit() 491 LoadLitU64("ldfp16_lit__uop", "MicroLdFp16LitUop", 492 16, literal=True, flavor="fp").emit() 493 LoadImmDU64("ldrduxi_uop", "MicroLdrDUXImmUop", 4, sign=False).emit() 494 LoadImmDU64("ldrdsxi_uop", "MicroLdrDSXImmUop", 4, sign=True).emit() 495 LoadImmDU64("ldrdfpxi_uop", "MicroLdrDFpXImmUop", 4, flavor="fp").emit() 496}}; 497