fp.isa revision 7366:4efa4733e66e
16691Stjones1@inf.ed.ac.uk// -*- mode:c++ -*- 26691Stjones1@inf.ed.ac.uk 36691Stjones1@inf.ed.ac.uk// Copyright (c) 2010 ARM Limited 46691Stjones1@inf.ed.ac.uk// All rights reserved 56691Stjones1@inf.ed.ac.uk// 66691Stjones1@inf.ed.ac.uk// The license below extends only to copyright in the software and shall 76691Stjones1@inf.ed.ac.uk// not be construed as granting a license to any other intellectual 86691Stjones1@inf.ed.ac.uk// property including but not limited to intellectual property relating 96691Stjones1@inf.ed.ac.uk// to a hardware implementation of the functionality of the software 106691Stjones1@inf.ed.ac.uk// licensed hereunder. You may use the software subject to the license 116691Stjones1@inf.ed.ac.uk// terms below provided that you ensure that this notice is replicated 126691Stjones1@inf.ed.ac.uk// unmodified and in its entirety in all distributions of the software, 136691Stjones1@inf.ed.ac.uk// modified or unmodified, in source code or in binary form. 146691Stjones1@inf.ed.ac.uk// 156691Stjones1@inf.ed.ac.uk// Redistribution and use in source and binary forms, with or without 166691Stjones1@inf.ed.ac.uk// modification, are permitted provided that the following conditions are 176691Stjones1@inf.ed.ac.uk// met: redistributions of source code must retain the above copyright 186691Stjones1@inf.ed.ac.uk// notice, this list of conditions and the following disclaimer; 196691Stjones1@inf.ed.ac.uk// redistributions in binary form must reproduce the above copyright 206691Stjones1@inf.ed.ac.uk// notice, this list of conditions and the following disclaimer in the 216691Stjones1@inf.ed.ac.uk// documentation and/or other materials provided with the distribution; 226691Stjones1@inf.ed.ac.uk// neither the name of the copyright holders nor the names of its 236691Stjones1@inf.ed.ac.uk// contributors may be used to endorse or promote products derived from 246691Stjones1@inf.ed.ac.uk// this software without specific prior written permission. 256691Stjones1@inf.ed.ac.uk// 266691Stjones1@inf.ed.ac.uk// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 276691Stjones1@inf.ed.ac.uk// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 286691Stjones1@inf.ed.ac.uk// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 296691Stjones1@inf.ed.ac.uk// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 306691Stjones1@inf.ed.ac.uk// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 316691Stjones1@inf.ed.ac.uk// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 326691Stjones1@inf.ed.ac.uk// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 336691Stjones1@inf.ed.ac.uk// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 346691Stjones1@inf.ed.ac.uk// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 356691Stjones1@inf.ed.ac.uk// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 366691Stjones1@inf.ed.ac.uk// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 376691Stjones1@inf.ed.ac.uk// 386691Stjones1@inf.ed.ac.uk// Authors: Gabe Black 396691Stjones1@inf.ed.ac.uk 406691Stjones1@inf.ed.ac.uklet {{ 416691Stjones1@inf.ed.ac.uk 426691Stjones1@inf.ed.ac.uk header_output = "" 436691Stjones1@inf.ed.ac.uk decoder_output = "" 446691Stjones1@inf.ed.ac.uk exec_output = "" 456691Stjones1@inf.ed.ac.uk 466691Stjones1@inf.ed.ac.uk vmsrIop = InstObjParams("vmsr", "Vmsr", "RegRegOp", 476691Stjones1@inf.ed.ac.uk { "code": "MiscDest = Op1;", 486691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 496691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vmsrIop); 506691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vmsrIop); 516691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmsrIop); 526691Stjones1@inf.ed.ac.uk 536691Stjones1@inf.ed.ac.uk vmrsIop = InstObjParams("vmrs", "Vmrs", "RegRegOp", 546691Stjones1@inf.ed.ac.uk { "code": "Dest = MiscOp1;", 556691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 566691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vmrsIop); 576691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vmrsIop); 586691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmrsIop); 596691Stjones1@inf.ed.ac.uk 606691Stjones1@inf.ed.ac.uk vmovImmSCode = ''' 616691Stjones1@inf.ed.ac.uk FpDest.uw = bits(imm, 31, 0); 626691Stjones1@inf.ed.ac.uk ''' 636691Stjones1@inf.ed.ac.uk vmovImmSIop = InstObjParams("vmov", "VmovImmS", "RegImmOp", 646691Stjones1@inf.ed.ac.uk { "code": vmovImmSCode, 656691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 666691Stjones1@inf.ed.ac.uk header_output += RegImmOpDeclare.subst(vmovImmSIop); 676691Stjones1@inf.ed.ac.uk decoder_output += RegImmOpConstructor.subst(vmovImmSIop); 686691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovImmSIop); 696691Stjones1@inf.ed.ac.uk 706691Stjones1@inf.ed.ac.uk vmovImmDCode = ''' 716691Stjones1@inf.ed.ac.uk FpDestP0.uw = bits(imm, 31, 0); 726691Stjones1@inf.ed.ac.uk FpDestP1.uw = bits(imm, 63, 32); 736691Stjones1@inf.ed.ac.uk ''' 746691Stjones1@inf.ed.ac.uk vmovImmDIop = InstObjParams("vmov", "VmovImmD", "RegImmOp", 756691Stjones1@inf.ed.ac.uk { "code": vmovImmDCode, 766691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 776691Stjones1@inf.ed.ac.uk header_output += RegImmOpDeclare.subst(vmovImmDIop); 786691Stjones1@inf.ed.ac.uk decoder_output += RegImmOpConstructor.subst(vmovImmDIop); 796691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovImmDIop); 806691Stjones1@inf.ed.ac.uk 816691Stjones1@inf.ed.ac.uk vmovImmQCode = ''' 826691Stjones1@inf.ed.ac.uk FpDestP0.uw = bits(imm, 31, 0); 836691Stjones1@inf.ed.ac.uk FpDestP1.uw = bits(imm, 63, 32); 846691Stjones1@inf.ed.ac.uk FpDestP2.uw = bits(imm, 31, 0); 856691Stjones1@inf.ed.ac.uk FpDestP3.uw = bits(imm, 63, 32); 866691Stjones1@inf.ed.ac.uk ''' 878442Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "RegImmOp", 886691Stjones1@inf.ed.ac.uk { "code": vmovImmQCode, 896691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 906691Stjones1@inf.ed.ac.uk header_output += RegImmOpDeclare.subst(vmovImmQIop); 916691Stjones1@inf.ed.ac.uk decoder_output += RegImmOpConstructor.subst(vmovImmQIop); 926691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovImmQIop); 936691Stjones1@inf.ed.ac.uk 946691Stjones1@inf.ed.ac.uk vmovRegSCode = ''' 956691Stjones1@inf.ed.ac.uk FpDest.uw = FpOp1.uw; 966691Stjones1@inf.ed.ac.uk ''' 976691Stjones1@inf.ed.ac.uk vmovRegSIop = InstObjParams("vmov", "VmovRegS", "RegRegOp", 986691Stjones1@inf.ed.ac.uk { "code": vmovRegSCode, 996691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1006691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vmovRegSIop); 1016691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vmovRegSIop); 1026691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovRegSIop); 1036691Stjones1@inf.ed.ac.uk 1046691Stjones1@inf.ed.ac.uk vmovRegDCode = ''' 1056691Stjones1@inf.ed.ac.uk FpDestP0.uw = FpOp1P0.uw; 1066691Stjones1@inf.ed.ac.uk FpDestP1.uw = FpOp1P1.uw; 1076691Stjones1@inf.ed.ac.uk ''' 1086691Stjones1@inf.ed.ac.uk vmovRegDIop = InstObjParams("vmov", "VmovRegD", "RegRegOp", 1096691Stjones1@inf.ed.ac.uk { "code": vmovRegDCode, 1106691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1116691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vmovRegDIop); 1128442Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmovRegDIop); 1136691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovRegDIop); 1146691Stjones1@inf.ed.ac.uk 1156691Stjones1@inf.ed.ac.uk vmovRegQCode = ''' 1166691Stjones1@inf.ed.ac.uk FpDestP0.uw = FpOp1P0.uw; 1176691Stjones1@inf.ed.ac.uk FpDestP1.uw = FpOp1P1.uw; 1186691Stjones1@inf.ed.ac.uk FpDestP2.uw = FpOp1P2.uw; 1196691Stjones1@inf.ed.ac.uk FpDestP3.uw = FpOp1P3.uw; 1206691Stjones1@inf.ed.ac.uk ''' 1216691Stjones1@inf.ed.ac.uk vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "RegRegOp", 1226691Stjones1@inf.ed.ac.uk { "code": vmovRegQCode, 1236691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1246691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vmovRegQIop); 1256691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vmovRegQIop); 1266691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovRegQIop); 1276691Stjones1@inf.ed.ac.uk 1286691Stjones1@inf.ed.ac.uk vmovCoreRegBCode = ''' 1296691Stjones1@inf.ed.ac.uk FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 1306691Stjones1@inf.ed.ac.uk ''' 1316691Stjones1@inf.ed.ac.uk vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "RegRegImmOp", 1326691Stjones1@inf.ed.ac.uk { "code": vmovCoreRegBCode, 1336691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1346691Stjones1@inf.ed.ac.uk header_output += RegRegImmOpDeclare.subst(vmovCoreRegBIop); 1358442Sgblack@eecs.umich.edu decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegBIop); 1366691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovCoreRegBIop); 1376691Stjones1@inf.ed.ac.uk 1386691Stjones1@inf.ed.ac.uk vmovCoreRegHCode = ''' 1396691Stjones1@inf.ed.ac.uk FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 1406691Stjones1@inf.ed.ac.uk ''' 1416691Stjones1@inf.ed.ac.uk vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "RegRegImmOp", 1426691Stjones1@inf.ed.ac.uk { "code": vmovCoreRegHCode, 1436691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1446691Stjones1@inf.ed.ac.uk header_output += RegRegImmOpDeclare.subst(vmovCoreRegHIop); 1456691Stjones1@inf.ed.ac.uk decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegHIop); 1466691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovCoreRegHIop); 1476691Stjones1@inf.ed.ac.uk 1486691Stjones1@inf.ed.ac.uk vmovCoreRegWCode = ''' 1496691Stjones1@inf.ed.ac.uk FpDest.uw = Op1.uw; 1506691Stjones1@inf.ed.ac.uk ''' 1516691Stjones1@inf.ed.ac.uk vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "RegRegOp", 1526691Stjones1@inf.ed.ac.uk { "code": vmovCoreRegWCode, 1536691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1546691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vmovCoreRegWIop); 1556691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vmovCoreRegWIop); 1566691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovCoreRegWIop); 1576691Stjones1@inf.ed.ac.uk 1586691Stjones1@inf.ed.ac.uk vmovRegCoreUBCode = ''' 1596691Stjones1@inf.ed.ac.uk Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 1606691Stjones1@inf.ed.ac.uk ''' 1616691Stjones1@inf.ed.ac.uk vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "RegRegImmOp", 1626691Stjones1@inf.ed.ac.uk { "code": vmovRegCoreUBCode, 1636691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1646691Stjones1@inf.ed.ac.uk header_output += RegRegImmOpDeclare.subst(vmovRegCoreUBIop); 1656691Stjones1@inf.ed.ac.uk decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUBIop); 1666691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 1678442Sgblack@eecs.umich.edu 1688442Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 1696691Stjones1@inf.ed.ac.uk Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 1706691Stjones1@inf.ed.ac.uk ''' 1716691Stjones1@inf.ed.ac.uk vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "RegRegImmOp", 1726691Stjones1@inf.ed.ac.uk { "code": vmovRegCoreUHCode, 1736691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1746691Stjones1@inf.ed.ac.uk header_output += RegRegImmOpDeclare.subst(vmovRegCoreUHIop); 1756691Stjones1@inf.ed.ac.uk decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUHIop); 1766691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 1776691Stjones1@inf.ed.ac.uk 1786691Stjones1@inf.ed.ac.uk vmovRegCoreSBCode = ''' 1796691Stjones1@inf.ed.ac.uk Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 1806691Stjones1@inf.ed.ac.uk ''' 1816691Stjones1@inf.ed.ac.uk vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "RegRegImmOp", 1826691Stjones1@inf.ed.ac.uk { "code": vmovRegCoreSBCode, 1836691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1846691Stjones1@inf.ed.ac.uk header_output += RegRegImmOpDeclare.subst(vmovRegCoreSBIop); 1856691Stjones1@inf.ed.ac.uk decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSBIop); 1866691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 1876691Stjones1@inf.ed.ac.uk 1886691Stjones1@inf.ed.ac.uk vmovRegCoreSHCode = ''' 1896691Stjones1@inf.ed.ac.uk Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 1906691Stjones1@inf.ed.ac.uk ''' 1916691Stjones1@inf.ed.ac.uk vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "RegRegImmOp", 1926691Stjones1@inf.ed.ac.uk { "code": vmovRegCoreSHCode, 1936691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 1946691Stjones1@inf.ed.ac.uk header_output += RegRegImmOpDeclare.subst(vmovRegCoreSHIop); 1956691Stjones1@inf.ed.ac.uk decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSHIop); 1968442Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 1978442Sgblack@eecs.umich.edu 1986691Stjones1@inf.ed.ac.uk vmovRegCoreWCode = ''' 1996691Stjones1@inf.ed.ac.uk Dest = FpOp1.uw; 2006691Stjones1@inf.ed.ac.uk ''' 2016691Stjones1@inf.ed.ac.uk vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "RegRegOp", 2026691Stjones1@inf.ed.ac.uk { "code": vmovRegCoreWCode, 2036691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2046691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vmovRegCoreWIop); 2056691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vmovRegCoreWIop); 2066691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmovRegCoreWIop); 2076691Stjones1@inf.ed.ac.uk 2086691Stjones1@inf.ed.ac.uk vmov2Reg2CoreCode = ''' 2096691Stjones1@inf.ed.ac.uk FpDestP0.uw = Op1.uw; 2106691Stjones1@inf.ed.ac.uk FpDestP1.uw = Op2.uw; 2116691Stjones1@inf.ed.ac.uk ''' 2126691Stjones1@inf.ed.ac.uk vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "RegRegRegOp", 2136691Stjones1@inf.ed.ac.uk { "code": vmov2Reg2CoreCode, 2146691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2157712Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 2166691Stjones1@inf.ed.ac.uk decoder_output += RegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 2176691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 2186691Stjones1@inf.ed.ac.uk 2196691Stjones1@inf.ed.ac.uk vmov2Core2RegCode = ''' 2206691Stjones1@inf.ed.ac.uk Dest.uw = FpOp2P0.uw; 2216691Stjones1@inf.ed.ac.uk Op1.uw = FpOp2P1.uw; 2226691Stjones1@inf.ed.ac.uk ''' 2236691Stjones1@inf.ed.ac.uk vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp", 2246691Stjones1@inf.ed.ac.uk { "code": vmov2Core2RegCode, 2256691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2266691Stjones1@inf.ed.ac.uk header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop); 2276691Stjones1@inf.ed.ac.uk decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop); 2286691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmov2Core2RegIop); 2296691Stjones1@inf.ed.ac.uk 2306691Stjones1@inf.ed.ac.uk vmulSCode = ''' 2316691Stjones1@inf.ed.ac.uk FpDest = FpOp1 * FpOp2; 2326691Stjones1@inf.ed.ac.uk if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 2336691Stjones1@inf.ed.ac.uk FpDest = NAN; 2346691Stjones1@inf.ed.ac.uk } 2356691Stjones1@inf.ed.ac.uk ''' 2366691Stjones1@inf.ed.ac.uk vmulSIop = InstObjParams("vmuls", "VmulS", "RegRegRegOp", 2376691Stjones1@inf.ed.ac.uk { "code": vmulSCode, 2386691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2396691Stjones1@inf.ed.ac.uk header_output += RegRegRegOpDeclare.subst(vmulSIop); 2406691Stjones1@inf.ed.ac.uk decoder_output += RegRegRegOpConstructor.subst(vmulSIop); 2416691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmulSIop); 2426691Stjones1@inf.ed.ac.uk 2436691Stjones1@inf.ed.ac.uk vmulDCode = ''' 2446691Stjones1@inf.ed.ac.uk IntDoubleUnion cOp1, cOp2, cDest; 2456691Stjones1@inf.ed.ac.uk cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 2466691Stjones1@inf.ed.ac.uk cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 2476691Stjones1@inf.ed.ac.uk cDest.fp = cOp1.fp * cOp2.fp; 2486691Stjones1@inf.ed.ac.uk if ((isinf(cOp1.fp) && cOp2.fp == 0) || 2496691Stjones1@inf.ed.ac.uk (isinf(cOp2.fp) && cOp1.fp == 0)) { 2506691Stjones1@inf.ed.ac.uk cDest.fp = NAN; 2516691Stjones1@inf.ed.ac.uk } 2526691Stjones1@inf.ed.ac.uk FpDestP0.uw = cDest.bits; 2536691Stjones1@inf.ed.ac.uk FpDestP1.uw = cDest.bits >> 32; 2546691Stjones1@inf.ed.ac.uk ''' 2556691Stjones1@inf.ed.ac.uk vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp", 2566691Stjones1@inf.ed.ac.uk { "code": vmulDCode, 2576691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2586691Stjones1@inf.ed.ac.uk header_output += RegRegRegOpDeclare.subst(vmulDIop); 2596691Stjones1@inf.ed.ac.uk decoder_output += RegRegRegOpConstructor.subst(vmulDIop); 2606691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vmulDIop); 2616691Stjones1@inf.ed.ac.uk 2626691Stjones1@inf.ed.ac.uk vnegSCode = ''' 2636691Stjones1@inf.ed.ac.uk FpDest = -FpOp1; 2646691Stjones1@inf.ed.ac.uk ''' 2656691Stjones1@inf.ed.ac.uk vnegSIop = InstObjParams("vnegs", "VnegS", "RegRegOp", 2666691Stjones1@inf.ed.ac.uk { "code": vnegSCode, 2676691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2686691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vnegSIop); 2696691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vnegSIop); 2706691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vnegSIop); 2716691Stjones1@inf.ed.ac.uk 2726691Stjones1@inf.ed.ac.uk vnegDCode = ''' 2736691Stjones1@inf.ed.ac.uk IntDoubleUnion cOp1, cDest; 2746691Stjones1@inf.ed.ac.uk cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 2756691Stjones1@inf.ed.ac.uk cDest.fp = -cOp1.fp; 2766691Stjones1@inf.ed.ac.uk FpDestP0.uw = cDest.bits; 2776691Stjones1@inf.ed.ac.uk FpDestP1.uw = cDest.bits >> 32; 2786691Stjones1@inf.ed.ac.uk ''' 2796691Stjones1@inf.ed.ac.uk vnegDIop = InstObjParams("vnegd", "VnegD", "RegRegOp", 2806691Stjones1@inf.ed.ac.uk { "code": vnegDCode, 2816691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2826691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vnegDIop); 2836691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vnegDIop); 2846691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vnegDIop); 2856691Stjones1@inf.ed.ac.uk 2866691Stjones1@inf.ed.ac.uk vabsSCode = ''' 2876691Stjones1@inf.ed.ac.uk FpDest = fabsf(FpOp1); 2886691Stjones1@inf.ed.ac.uk ''' 2896691Stjones1@inf.ed.ac.uk vabsSIop = InstObjParams("vabss", "VabsS", "RegRegOp", 2906691Stjones1@inf.ed.ac.uk { "code": vabsSCode, 2916691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 2926691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vabsSIop); 2936691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vabsSIop); 2946691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vabsSIop); 2956691Stjones1@inf.ed.ac.uk 2966691Stjones1@inf.ed.ac.uk vabsDCode = ''' 2976691Stjones1@inf.ed.ac.uk IntDoubleUnion cOp1, cDest; 2986691Stjones1@inf.ed.ac.uk cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 2996691Stjones1@inf.ed.ac.uk cDest.fp = fabs(cOp1.fp); 3006691Stjones1@inf.ed.ac.uk FpDestP0.uw = cDest.bits; 3016691Stjones1@inf.ed.ac.uk FpDestP1.uw = cDest.bits >> 32; 3026691Stjones1@inf.ed.ac.uk ''' 3036691Stjones1@inf.ed.ac.uk vabsDIop = InstObjParams("vabsd", "VabsD", "RegRegOp", 3046691Stjones1@inf.ed.ac.uk { "code": vabsDCode, 3056691Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 3066691Stjones1@inf.ed.ac.uk header_output += RegRegOpDeclare.subst(vabsDIop); 3076691Stjones1@inf.ed.ac.uk decoder_output += RegRegOpConstructor.subst(vabsDIop); 3086691Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vabsDIop); 3096691Stjones1@inf.ed.ac.uk}}; 3106691Stjones1@inf.ed.ac.uk