fp.isa revision 8607
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947396Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1957644Sali.saidi@arm.com { "code": vmsrEnabledCheckCode + \ 1967640Sgblack@eecs.umich.edu "MiscDest = Op1;", 1977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 1987760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 1997648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 2007396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrIop); 2017396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 2027322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2037324Sgblack@eecs.umich.edu 2047644Sali.saidi@arm.com vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2057643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2067643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2077643Sgblack@eecs.umich.edu ''' 2087643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2097643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2107760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2117783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2128070SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative", 2138070SAli.Saidi@ARM.com "IsSquashAfter"]) 2147643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2157643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2167643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2177643Sgblack@eecs.umich.edu 2187396Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2197644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2207760SGiacomo.Gabrielli@arm.com "Dest = MiscOp1;", 2217760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2227783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2237783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2247396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2257396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2267324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2277333Sgblack@eecs.umich.edu 2287643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2297644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2307643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2327783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2337783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2347643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2357643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2367643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2377643Sgblack@eecs.umich.edu 2388303SAli.Saidi@ARM.com vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + ''' 2398303SAli.Saidi@ARM.com FPSCR fpscr = FpCondCodes; 2408303SAli.Saidi@ARM.com CondCodesNZ = (fpscr.n << 1) | fpscr.z; 2418303SAli.Saidi@ARM.com CondCodesC = fpscr.c; 2428303SAli.Saidi@ARM.com CondCodesV = fpscr.v; 2437643Sgblack@eecs.umich.edu ''' 2448303SAli.Saidi@ARM.com vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", 2457643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2478303SAli.Saidi@ARM.com "op_class": "SimdFloatMiscOp" }) 2488303SAli.Saidi@ARM.com header_output += BasicDeclare.subst(vmrsApsrFpscrIop); 2498303SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); 2507643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2517643Sgblack@eecs.umich.edu 2527640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2538588Sgblack@eecs.umich.edu FpDest_uw = bits(imm, 31, 0); 2547333Sgblack@eecs.umich.edu ''' 2557396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2567333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2597396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2607396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2617333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2627333Sgblack@eecs.umich.edu 2637640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2648588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2658588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2667333Sgblack@eecs.umich.edu ''' 2677396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2687333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2697760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2707760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2717396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2727396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2737333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2747333Sgblack@eecs.umich.edu 2757640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 2768588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2778588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2788588Sgblack@eecs.umich.edu FpDestP2_uw = bits(imm, 31, 0); 2798588Sgblack@eecs.umich.edu FpDestP3_uw = bits(imm, 63, 32); 2807333Sgblack@eecs.umich.edu ''' 2817396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2827333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2857396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2867396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2877333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2887333Sgblack@eecs.umich.edu 2897640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 2908588Sgblack@eecs.umich.edu FpDest_uw = FpOp1_uw; 2917333Sgblack@eecs.umich.edu ''' 2927396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 2937333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2967396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 2977396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 2987333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2997333Sgblack@eecs.umich.edu 3007640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 3018588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3028588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3037333Sgblack@eecs.umich.edu ''' 3047396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3057333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3087396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3097396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3107333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3117333Sgblack@eecs.umich.edu 3127640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3138588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3148588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3158588Sgblack@eecs.umich.edu FpDestP2_uw = FpOp1P2_uw; 3168588Sgblack@eecs.umich.edu FpDestP3_uw = FpOp1P3_uw; 3177333Sgblack@eecs.umich.edu ''' 3187396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3197333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3227396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3237396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3247333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3257333Sgblack@eecs.umich.edu 3267640Sgblack@eecs.umich.edu vmovCoreRegBCode = vfpEnabledCheckCode + ''' 3278588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); 3287333Sgblack@eecs.umich.edu ''' 3297396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3307333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3327760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3337396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3347396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3357333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3367333Sgblack@eecs.umich.edu 3377640Sgblack@eecs.umich.edu vmovCoreRegHCode = vfpEnabledCheckCode + ''' 3388588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); 3397333Sgblack@eecs.umich.edu ''' 3407396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3417333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3427760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3437760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3447396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3457396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3467333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3477333Sgblack@eecs.umich.edu 3487640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3498588Sgblack@eecs.umich.edu FpDest_uw = Op1_uw; 3507333Sgblack@eecs.umich.edu ''' 3517396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3527333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3537760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3547760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3557396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3567396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3577333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3587333Sgblack@eecs.umich.edu 3597640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3607639Sgblack@eecs.umich.edu assert(imm < 4); 3618588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8); 3627333Sgblack@eecs.umich.edu ''' 3637396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3647333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3657760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3667760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3677396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3687396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3697333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3707333Sgblack@eecs.umich.edu 3717640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3727639Sgblack@eecs.umich.edu assert(imm < 2); 3738588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16); 3747333Sgblack@eecs.umich.edu ''' 3757396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3767333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3777760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3787760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3797396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3807396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3817333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3827333Sgblack@eecs.umich.edu 3837640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 3847639Sgblack@eecs.umich.edu assert(imm < 4); 3858588Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8)); 3867333Sgblack@eecs.umich.edu ''' 3877396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3887333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3897760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3907760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3917396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3927396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3937333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3947333Sgblack@eecs.umich.edu 3957640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 3967639Sgblack@eecs.umich.edu assert(imm < 2); 3978588Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16)); 3987333Sgblack@eecs.umich.edu ''' 3997396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 4007333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 4017760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4027760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4037396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 4047396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 4057333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 4067333Sgblack@eecs.umich.edu 4077640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 4088588Sgblack@eecs.umich.edu Dest = FpOp1_uw; 4097333Sgblack@eecs.umich.edu ''' 4107396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 4117333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 4127760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4137760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4147396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4157396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4167333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4177333Sgblack@eecs.umich.edu 4187640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4198588Sgblack@eecs.umich.edu FpDestP0_uw = Op1_uw; 4208588Sgblack@eecs.umich.edu FpDestP1_uw = Op2_uw; 4217333Sgblack@eecs.umich.edu ''' 4227396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4237333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4247760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4257760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4267396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4277396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4287333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4297333Sgblack@eecs.umich.edu 4307640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4318588Sgblack@eecs.umich.edu Dest_uw = FpOp2P0_uw; 4328588Sgblack@eecs.umich.edu Op1_uw = FpOp2P1_uw; 4337333Sgblack@eecs.umich.edu ''' 4347396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4357333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4367760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4377760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4387396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4397396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4407333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4417381Sgblack@eecs.umich.edu}}; 4427381Sgblack@eecs.umich.edu 4437381Sgblack@eecs.umich.edulet {{ 4447381Sgblack@eecs.umich.edu 4457381Sgblack@eecs.umich.edu header_output = "" 4467381Sgblack@eecs.umich.edu decoder_output = "" 4477381Sgblack@eecs.umich.edu exec_output = "" 4487364Sgblack@eecs.umich.edu 4497783SGiacomo.Gabrielli@arm.com singleSimpleCode = vfpEnabledCheckCode + ''' 4508607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4517396Sgblack@eecs.umich.edu FpDest = %(op)s; 4527783SGiacomo.Gabrielli@arm.com ''' 4537783SGiacomo.Gabrielli@arm.com singleCode = singleSimpleCode + ''' 4547783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4557364Sgblack@eecs.umich.edu ''' 4567396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4577639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4587396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4597640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4608607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4617396Sgblack@eecs.umich.edu double dest = %(op)s; 4628588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 4638588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 4647783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4657396Sgblack@eecs.umich.edu ''' 4667396Sgblack@eecs.umich.edu doubleBinOp = ''' 4678588Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 4688588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 4697639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 4707396Sgblack@eecs.umich.edu ''' 4717396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 4728588Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s, 4737396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 4747396Sgblack@eecs.umich.edu ''' 4757364Sgblack@eecs.umich.edu 4767760SGiacomo.Gabrielli@arm.com def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 4777396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4787365Sgblack@eecs.umich.edu 4797396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4807396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4817396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4827760SGiacomo.Gabrielli@arm.com { "code": code, 4837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4847760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 4857396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4867396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4877396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4887760SGiacomo.Gabrielli@arm.com { "code": code, 4897760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4907760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 4917365Sgblack@eecs.umich.edu 4927396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4937396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4947366Sgblack@eecs.umich.edu 4957396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4967396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4977396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4987396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4997366Sgblack@eecs.umich.edu 5007760SGiacomo.Gabrielli@arm.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS", 5017760SGiacomo.Gabrielli@arm.com "fpAddD") 5027760SGiacomo.Gabrielli@arm.com buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS", 5037760SGiacomo.Gabrielli@arm.com "fpSubD") 5047760SGiacomo.Gabrielli@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS", 5057760SGiacomo.Gabrielli@arm.com "fpDivD") 5067760SGiacomo.Gabrielli@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS", 5077760SGiacomo.Gabrielli@arm.com "fpMulD") 5087367Sgblack@eecs.umich.edu 5097760SGiacomo.Gabrielli@arm.com def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 5107396Sgblack@eecs.umich.edu if doubleOp is None: 5117396Sgblack@eecs.umich.edu doubleOp = singleOp 5127396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5137367Sgblack@eecs.umich.edu 5147396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 5157396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5167396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5177760SGiacomo.Gabrielli@arm.com { "code": code, 5187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5197760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5207396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 5217396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5227396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5237760SGiacomo.Gabrielli@arm.com { "code": code, 5247760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5257760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5267368Sgblack@eecs.umich.edu 5277396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5287396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5297368Sgblack@eecs.umich.edu 5307396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5317396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5327396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5337396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5347369Sgblack@eecs.umich.edu 5357760SGiacomo.Gabrielli@arm.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "SimdFloatSqrtOp", "sqrtf", 5367760SGiacomo.Gabrielli@arm.com "sqrt") 5377369Sgblack@eecs.umich.edu 5387760SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 5397760SGiacomo.Gabrielli@arm.com doubleOp = None): 5407396Sgblack@eecs.umich.edu if doubleOp is None: 5417396Sgblack@eecs.umich.edu doubleOp = singleOp 5427396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5437369Sgblack@eecs.umich.edu 5447396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5457783SGiacomo.Gabrielli@arm.com { "code": singleSimpleCode % { "op": singleOp }, 5467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5477760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5487396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5497396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 5507760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5517760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5527369Sgblack@eecs.umich.edu 5537396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5547396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5557396Sgblack@eecs.umich.edu 5567396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5577396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5587396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5597396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5607396Sgblack@eecs.umich.edu 5617760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", 5628588Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)") 5637760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", 5648588Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))") 5657381Sgblack@eecs.umich.edu}}; 5667381Sgblack@eecs.umich.edu 5677381Sgblack@eecs.umich.edulet {{ 5687381Sgblack@eecs.umich.edu 5697381Sgblack@eecs.umich.edu header_output = "" 5707381Sgblack@eecs.umich.edu decoder_output = "" 5717381Sgblack@eecs.umich.edu exec_output = "" 5727370Sgblack@eecs.umich.edu 5737640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 5747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 5757396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5767639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5777639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 5787639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 5807370Sgblack@eecs.umich.edu ''' 5817396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5827370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 5857396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5867396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5877370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5887370Sgblack@eecs.umich.edu 5897640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 5907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 5918588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 5928588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 5937639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5948588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 5957639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 5967639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5978588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 5988588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 5997783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6007370Sgblack@eecs.umich.edu ''' 6017396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 6027370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6037760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6047760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6057396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 6067396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 6077370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6087370Sgblack@eecs.umich.edu 6097640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 6107783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6117396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6127639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6137639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 6147639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6167370Sgblack@eecs.umich.edu ''' 6177396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 6187370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6217396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 6227396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 6237370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 6247370Sgblack@eecs.umich.edu 6257640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 6267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6278588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 6288588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 6297639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6308588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 6317639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 6327639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6338588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 6348588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 6357783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6367370Sgblack@eecs.umich.edu ''' 6377396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 6387370Sgblack@eecs.umich.edu { "code": vmlsDCode, 6397760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6407760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6417396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 6427396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 6437370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 6447371Sgblack@eecs.umich.edu 6457640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 6467783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6477396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6487639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6497639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 6507639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6517783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6527371Sgblack@eecs.umich.edu ''' 6537396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 6547371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 6557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6567760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6577396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 6587396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 6597371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 6607371Sgblack@eecs.umich.edu 6617640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 6627783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6638588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 6648588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 6657639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6668588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 6677639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 6687639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6698588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 6708588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 6717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6727371Sgblack@eecs.umich.edu ''' 6737396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 6747371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6757760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6767760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6777396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 6787396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 6797371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6807371Sgblack@eecs.umich.edu 6817640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 6827783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6837396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6847639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6857639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 6867639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6877783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6887371Sgblack@eecs.umich.edu ''' 6897396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 6907760SGiacomo.Gabrielli@arm.com { "code": vnmlsSCode, 6917760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6927760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6937396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 6947396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 6957371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 6967371Sgblack@eecs.umich.edu 6977640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 6987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6998588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7008588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7017639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7028588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 7037639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 7047639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7058588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7068588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7077783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7087371Sgblack@eecs.umich.edu ''' 7097396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 7107760SGiacomo.Gabrielli@arm.com { "code": vnmlsDCode, 7117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7127760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7137396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 7147396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 7157371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 7167371Sgblack@eecs.umich.edu 7177640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 7187783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7197639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 7207639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7217783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7227371Sgblack@eecs.umich.edu ''' 7237396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 7247760SGiacomo.Gabrielli@arm.com { "code": vnmulSCode, 7257760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7267760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 7277396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 7287396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 7297371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 7307371Sgblack@eecs.umich.edu 7317640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 7327783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7338588Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7348588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7357639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 7367639Sgblack@eecs.umich.edu fpscr.rMode); 7378588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7388588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7407371Sgblack@eecs.umich.edu ''' 7417396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 7427371Sgblack@eecs.umich.edu { "code": vnmulDCode, 7437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 7457396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 7467396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 7477371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 7487381Sgblack@eecs.umich.edu}}; 7497381Sgblack@eecs.umich.edu 7507381Sgblack@eecs.umich.edulet {{ 7517381Sgblack@eecs.umich.edu 7527381Sgblack@eecs.umich.edu header_output = "" 7537381Sgblack@eecs.umich.edu decoder_output = "" 7547381Sgblack@eecs.umich.edu exec_output = "" 7557373Sgblack@eecs.umich.edu 7567640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 7577783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7587397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7598588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 7608588Sgblack@eecs.umich.edu FpDest = FpOp1_uw; 7617381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7627639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7637783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7647373Sgblack@eecs.umich.edu ''' 7657396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 7667373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 7677760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7687760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 7697396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 7707396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 7717373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 7727373Sgblack@eecs.umich.edu 7737640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 7747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7757397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7768588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_uw) : "m" (FpOp1P0_uw)); 7778588Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0_uw; 7787397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7797639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7808588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 7818588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 7827783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7837373Sgblack@eecs.umich.edu ''' 7847396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 7857373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 7867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 7887396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 7897396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 7907373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 7917373Sgblack@eecs.umich.edu 7927640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 7937783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7947397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7958588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 7968588Sgblack@eecs.umich.edu FpDest = FpOp1_sw; 7977381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7987639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7997783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8007373Sgblack@eecs.umich.edu ''' 8017396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 8027373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 8037760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8047760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8057396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 8067396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 8077373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 8087373Sgblack@eecs.umich.edu 8097640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 8107783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8117397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8128588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_sw) : "m" (FpOp1P0_sw)); 8138588Sgblack@eecs.umich.edu double cDest = FpOp1P0_sw; 8147397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8168588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 8178588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 8187783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8197373Sgblack@eecs.umich.edu ''' 8207396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 8217373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 8227760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8237760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8247396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 8257396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 8267373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 8277373Sgblack@eecs.umich.edu 8287640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 8297783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8317397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8327381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8338588Sgblack@eecs.umich.edu FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 8348588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 8357639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8367783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8377380Sgblack@eecs.umich.edu ''' 8387396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 8397380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 8407760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8417760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8427396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 8437396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 8447380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 8457380Sgblack@eecs.umich.edu 8467640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 8477783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8488588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 8497397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8507397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8517397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8527397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 8537381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8547639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8558588Sgblack@eecs.umich.edu FpDestP0_uw = result; 8567783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8577380Sgblack@eecs.umich.edu ''' 8587396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 8597380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 8607760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8617760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8627396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 8637396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 8647380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 8657380Sgblack@eecs.umich.edu 8667640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 8677783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8687397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8697397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8707381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8718588Sgblack@eecs.umich.edu FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 8728588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 8737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8757380Sgblack@eecs.umich.edu ''' 8767396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 8777380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 8787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 8817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 8827380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 8837380Sgblack@eecs.umich.edu 8847640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 8857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8868588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 8877397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8887397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8897397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8907397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 8917381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8927639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8938588Sgblack@eecs.umich.edu FpDestP0_uw = result; 8947783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8957380Sgblack@eecs.umich.edu ''' 8967396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 8977380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 8987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9007396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 9017396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 9027380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 9037380Sgblack@eecs.umich.edu 9047640Sgblack@eecs.umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 9057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9067397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9077397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9087380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9097381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9108588Sgblack@eecs.umich.edu FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0); 9118588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 9127639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9147373Sgblack@eecs.umich.edu ''' 9157396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 9167373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 9177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9197396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 9207396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 9217373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 9227373Sgblack@eecs.umich.edu 9237640Sgblack@eecs.umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 9247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9258588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9267397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9277397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9287380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9297397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9307397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 9317381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9327639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9338588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9357373Sgblack@eecs.umich.edu ''' 9367396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 9377373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 9387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9397760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9407396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 9417396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 9427373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 9437373Sgblack@eecs.umich.edu 9447640Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 9457783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9467397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9477397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9487380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9497381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9508588Sgblack@eecs.umich.edu FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0); 9518588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 9527639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9537783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9547373Sgblack@eecs.umich.edu ''' 9557396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 9567373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 9577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9597396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 9607396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 9617373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 9627373Sgblack@eecs.umich.edu 9637640Sgblack@eecs.umich.edu vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 9647783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9658588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9677397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9687380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9697397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9707397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 9717381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9727639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9738588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9757373Sgblack@eecs.umich.edu ''' 9767396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 9777373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 9787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 9817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 9827373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 9837374Sgblack@eecs.umich.edu 9847640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 9857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9867397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9877397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9887381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9897783SGiacomo.Gabrielli@arm.com double cDest = fixFpSFpDDest(FpscrExc, FpOp1); 9907397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9917639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9928588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 9938588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 9947783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9957374Sgblack@eecs.umich.edu ''' 9967396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 9977374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 9987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10007396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 10017396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 10027374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 10037374Sgblack@eecs.umich.edu 10047640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 10057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10068588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10077397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10087397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10097397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 10107783SGiacomo.Gabrielli@arm.com FpDest = fixFpDFpSDest(FpscrExc, cOp1); 10117381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10127639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10147374Sgblack@eecs.umich.edu ''' 10157396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 10167374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 10177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10197396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 10207396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 10217374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 10227377Sgblack@eecs.umich.edu 10237640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 10247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10257398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10267398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10277398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10287639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 10297639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 10307398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10317639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10327783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10337398Sgblack@eecs.umich.edu ''' 10347398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 10357398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 10367760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10377760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10387398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 10397398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 10407398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 10417398Sgblack@eecs.umich.edu 10427640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 10437783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10447398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10457398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10467639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 10477639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 10487398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10497639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10507783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10517398Sgblack@eecs.umich.edu ''' 10527398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 10537398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 10547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10557760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10567398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 10577398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 10587398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 10597398Sgblack@eecs.umich.edu 10607640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 10617783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10627398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10637398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10648588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 10658588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 10668588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 31, 16,, 10677639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10687639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 10698588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 10707639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10727398Sgblack@eecs.umich.edu ''' 10737398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 10747398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 10757760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10767760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10777398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 10787398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 10797398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 10807398Sgblack@eecs.umich.edu 10817640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 10827783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10837398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10847398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10858588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 10868588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 10878588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 15, 0, 10887639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10897639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 10908588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 10917639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10927783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10937398Sgblack@eecs.umich.edu ''' 10947398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 10957398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 10967760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10977760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10987398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 10997398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 11007398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 11017398Sgblack@eecs.umich.edu 11027640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 11037783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11047397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 11057377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11067377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11077377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11087377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11097377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11107377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11117377Sgblack@eecs.umich.edu } else { 11127389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11137389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 11147396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 11157389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 11167396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 11177389Sgblack@eecs.umich.edu if (signal1 || signal2) 11187389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11197377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11207377Sgblack@eecs.umich.edu } 11217643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11227783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11237377Sgblack@eecs.umich.edu ''' 11247396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 11257377Sgblack@eecs.umich.edu { "code": vcmpSCode, 11267760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11277760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11287396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 11297396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 11307377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 11317377Sgblack@eecs.umich.edu 11327640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 11338588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 11348588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 11357783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11367397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 11377397Sgblack@eecs.umich.edu if (cDest == cOp1) { 11387377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11397397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 11407377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11417397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 11427377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11437377Sgblack@eecs.umich.edu } else { 11447389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 11457397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 11467397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 11477397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 11487397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 11497389Sgblack@eecs.umich.edu if (signal1 || signal2) 11507389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11517377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11527377Sgblack@eecs.umich.edu } 11537643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11547783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11557377Sgblack@eecs.umich.edu ''' 11567396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 11577377Sgblack@eecs.umich.edu { "code": vcmpDCode, 11587760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11597760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11607396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 11617396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 11627377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 11637377Sgblack@eecs.umich.edu 11647640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 11657783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 11677389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11687389Sgblack@eecs.umich.edu assert(imm == 0); 11697377Sgblack@eecs.umich.edu if (FpDest == imm) { 11707377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11717377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11727377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11737377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11747377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11757377Sgblack@eecs.umich.edu } else { 11767389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11777389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 11787396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 11797389Sgblack@eecs.umich.edu if (signal) 11807389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11817377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11827377Sgblack@eecs.umich.edu } 11837643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11847783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11857377Sgblack@eecs.umich.edu ''' 11867396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 11877377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 11887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11897760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11907396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 11917396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 11927377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 11937377Sgblack@eecs.umich.edu 11947640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 11957389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11967389Sgblack@eecs.umich.edu assert(imm == 0); 11978588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 11987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11997397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 12007397Sgblack@eecs.umich.edu if (cDest == imm) { 12017377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12027397Sgblack@eecs.umich.edu } else if (cDest < imm) { 12037377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12047397Sgblack@eecs.umich.edu } else if (cDest > imm) { 12057377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12067377Sgblack@eecs.umich.edu } else { 12077389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12087397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 12097397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 12107389Sgblack@eecs.umich.edu if (signal) 12117389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12127377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12137377Sgblack@eecs.umich.edu } 12147643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12167377Sgblack@eecs.umich.edu ''' 12177396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 12187377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 12197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12217396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 12227396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 12237377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 12247389Sgblack@eecs.umich.edu 12257640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 12267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12277397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 12287389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12297389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12307389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12317389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12327389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12337389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12347389Sgblack@eecs.umich.edu } else { 12357389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12367389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12377389Sgblack@eecs.umich.edu } 12387643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12407389Sgblack@eecs.umich.edu ''' 12417396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 12427389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 12437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12457396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 12467396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 12477389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 12487389Sgblack@eecs.umich.edu 12497640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 12508588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 12518588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 12527783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12537397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 12547397Sgblack@eecs.umich.edu if (cDest == cOp1) { 12557389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12567397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 12577389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12587397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 12597389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12607389Sgblack@eecs.umich.edu } else { 12617389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12627389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12637389Sgblack@eecs.umich.edu } 12647643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12657783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12667389Sgblack@eecs.umich.edu ''' 12677396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 12687389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 12697760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12707760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12717396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 12727396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 12737389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 12747389Sgblack@eecs.umich.edu 12757640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 12767783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12777397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 12787389Sgblack@eecs.umich.edu if (FpDest == imm) { 12797389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12807389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12817389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12827389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12837389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12847389Sgblack@eecs.umich.edu } else { 12857389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12867389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12877389Sgblack@eecs.umich.edu } 12887643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12897783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12907389Sgblack@eecs.umich.edu ''' 12917396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 12927389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 12937760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12947760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12957396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 12967396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 12977389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 12987389Sgblack@eecs.umich.edu 12997640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 13008588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 13017783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13027397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 13037397Sgblack@eecs.umich.edu if (cDest == imm) { 13047389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13057397Sgblack@eecs.umich.edu } else if (cDest < imm) { 13067389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13077397Sgblack@eecs.umich.edu } else if (cDest > imm) { 13087389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13097389Sgblack@eecs.umich.edu } else { 13107389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13117389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13127389Sgblack@eecs.umich.edu } 13137643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13147783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13157389Sgblack@eecs.umich.edu ''' 13167396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 13177389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 13187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13197760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13207396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 13217396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 13227389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 13237322Sgblack@eecs.umich.edu}}; 13247379Sgblack@eecs.umich.edu 13257379Sgblack@eecs.umich.edulet {{ 13267379Sgblack@eecs.umich.edu 13277379Sgblack@eecs.umich.edu header_output = "" 13287379Sgblack@eecs.umich.edu decoder_output = "" 13297379Sgblack@eecs.umich.edu exec_output = "" 13307379Sgblack@eecs.umich.edu 13317640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 13327783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13337397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13347397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13357381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13368588Sgblack@eecs.umich.edu FpDest_sw = vfpFpSToFixed(FpOp1, true, false, imm); 13378588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 13387639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13407379Sgblack@eecs.umich.edu ''' 13417396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 13427379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 13437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13457396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 13467396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 13477379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 13487379Sgblack@eecs.umich.edu 13497640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 13507783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13518588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 13527397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13537397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13547397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13557397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 13567381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13577639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13588588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 13598588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 13607783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13617379Sgblack@eecs.umich.edu ''' 13627396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 13637379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 13647760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13657760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13667396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 13677396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 13687379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 13697379Sgblack@eecs.umich.edu 13707640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 13717783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13727397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13737397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13747381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13758588Sgblack@eecs.umich.edu FpDest_uw = vfpFpSToFixed(FpOp1, false, false, imm); 13768588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 13777639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13787783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13797379Sgblack@eecs.umich.edu ''' 13807396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 13817379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 13827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13837760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13847396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 13857396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 13867379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 13877379Sgblack@eecs.umich.edu 13887640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 13897783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13908588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 13917397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13927397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13937397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13947397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 13957381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13967639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13978588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 13988588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 13997783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14007379Sgblack@eecs.umich.edu ''' 14017396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 14027379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 14037760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14047760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14057396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 14067396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 14077379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 14087379Sgblack@eecs.umich.edu 14097640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 14107783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14117397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14128588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 14138588Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, false, imm); 14147381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14167783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14177379Sgblack@eecs.umich.edu ''' 14187396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 14197379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 14207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14227396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 14237396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 14247379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 14257379Sgblack@eecs.umich.edu 14267640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 14277783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14288588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 14297397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14307381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14317639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 14327397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14337639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14348588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 14358588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 14367783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14377379Sgblack@eecs.umich.edu ''' 14387396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 14397379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 14407760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14417760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14427396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 14437396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 14447379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 14457379Sgblack@eecs.umich.edu 14467640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 14477783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14487397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14498588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 14508588Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, false, imm); 14517381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14527639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14537783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14547379Sgblack@eecs.umich.edu ''' 14557396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 14567379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 14577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14597396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 14607396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 14617379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 14627379Sgblack@eecs.umich.edu 14637640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 14647783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14658588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 14667397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14677381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14687639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 14697397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14707639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14718588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 14728588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 14737783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14747379Sgblack@eecs.umich.edu ''' 14757396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 14767379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 14777760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14787760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14797396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 14807396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 14817379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 14827379Sgblack@eecs.umich.edu 14837640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 14847783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14857397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14867397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14877381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14888588Sgblack@eecs.umich.edu FpDest_sh = vfpFpSToFixed(FpOp1, true, true, imm); 14898588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sh)); 14907639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14917783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14927379Sgblack@eecs.umich.edu ''' 14937379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 14947396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14957379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 14967760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14977760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14987396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 14997396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 15007379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 15017379Sgblack@eecs.umich.edu 15027640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 15037783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15048588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 15057397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15067397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15077397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 15087397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 15097381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 15107639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15118588Sgblack@eecs.umich.edu FpDestP0_uw = result; 15128588Sgblack@eecs.umich.edu FpDestP1_uw = result >> 32; 15137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15147379Sgblack@eecs.umich.edu ''' 15157379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 15167396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15177379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 15187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15197760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15207396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 15217396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 15227379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 15237379Sgblack@eecs.umich.edu 15247640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 15257783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15267397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15277397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15287381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 15298588Sgblack@eecs.umich.edu FpDest_uh = vfpFpSToFixed(FpOp1, false, true, imm); 15308588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uh)); 15317639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15327783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15337379Sgblack@eecs.umich.edu ''' 15347379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 15357396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15367379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 15377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15397396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 15407396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 15417379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 15427379Sgblack@eecs.umich.edu 15437640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 15447783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15458588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 15467397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15477397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15487397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 15497397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 15507381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15517639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15528588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 15538588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 15547783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15557379Sgblack@eecs.umich.edu ''' 15567379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 15577396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15587379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 15597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15617396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 15627396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 15637379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 15647379Sgblack@eecs.umich.edu 15657640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 15667783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15677397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15688588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh)); 15698588Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, true, imm); 15707381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15717639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15727783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15737379Sgblack@eecs.umich.edu ''' 15747379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 15757396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15767379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 15777760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15787760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15797396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 15807396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 15817379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 15827379Sgblack@eecs.umich.edu 15837640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 15847783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15858588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 15867397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15877381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15887639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 15897397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15907639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15918588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 15928588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 15937783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15947379Sgblack@eecs.umich.edu ''' 15957379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 15967396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15977379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 15987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16007396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 16017396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 16027379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 16037379Sgblack@eecs.umich.edu 16047640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 16057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16067397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16078588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh)); 16088588Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, true, imm); 16097381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 16107639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16117783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16127379Sgblack@eecs.umich.edu ''' 16137379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 16147396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16157379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 16167760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16177760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16187396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 16197396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 16207379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 16217379Sgblack@eecs.umich.edu 16227640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 16237783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16248588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 16257397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16267381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 16277639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 16287397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16297639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16308588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 16318588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 16327783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16337379Sgblack@eecs.umich.edu ''' 16347379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 16357396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16367379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 16377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16397396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 16407396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 16417379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 16427379Sgblack@eecs.umich.edu}}; 1643