fp.isa revision 8070
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947396Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1957644Sali.saidi@arm.com { "code": vmsrEnabledCheckCode + \ 1967640Sgblack@eecs.umich.edu "MiscDest = Op1;", 1977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 1987760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 1997648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 2007396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrIop); 2017396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 2027322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2037324Sgblack@eecs.umich.edu 2047644Sali.saidi@arm.com vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2057643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2067643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2077643Sgblack@eecs.umich.edu ''' 2087643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2097643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2107760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2117783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2128070SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative", 2138070SAli.Saidi@ARM.com "IsSquashAfter"]) 2147643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2157643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2167643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2177643Sgblack@eecs.umich.edu 2187396Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2197644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2207760SGiacomo.Gabrielli@arm.com "Dest = MiscOp1;", 2217760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2227783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2237783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2247396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2257396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2267324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2277333Sgblack@eecs.umich.edu 2287643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2297644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2307643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2327783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2337783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2347643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2357643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2367643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2377643Sgblack@eecs.umich.edu 2387644Sali.saidi@arm.com vmrsApsrCode = vmrsEnabledCheckCode + ''' 2397643Sgblack@eecs.umich.edu Dest = (MiscOp1 & imm) | (Dest & ~imm); 2407643Sgblack@eecs.umich.edu ''' 2417396Sgblack@eecs.umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 2427392Sgblack@eecs.umich.edu { "code": vmrsApsrCode, 2437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2447783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2457783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2467396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 2477396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 2487392Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrIop); 2497392Sgblack@eecs.umich.edu 2507644Sali.saidi@arm.com vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' 2517643Sgblack@eecs.umich.edu assert((imm & ~FpCondCodesMask) == 0); 2527643Sgblack@eecs.umich.edu Dest = (FpCondCodes & imm) | (Dest & ~imm); 2537643Sgblack@eecs.umich.edu ''' 2547643Sgblack@eecs.umich.edu vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", 2557643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2577783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2587783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2597643Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); 2607643Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); 2617643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2627643Sgblack@eecs.umich.edu 2637640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2647333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2657333Sgblack@eecs.umich.edu ''' 2667396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2677333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2687760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2697760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2707396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2717396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2727333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2737333Sgblack@eecs.umich.edu 2747640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2757333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2767333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2777333Sgblack@eecs.umich.edu ''' 2787396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2797333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2827396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2837396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2857333Sgblack@eecs.umich.edu 2867640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 2877333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2887333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2897333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2907333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2917333Sgblack@eecs.umich.edu ''' 2927396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2937333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2967396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2977396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2987333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2997333Sgblack@eecs.umich.edu 3007640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 3017333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 3027333Sgblack@eecs.umich.edu ''' 3037396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 3047333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 3057760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3067760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3077396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 3087396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 3097333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 3107333Sgblack@eecs.umich.edu 3117640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 3127333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 3137333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 3147333Sgblack@eecs.umich.edu ''' 3157396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3167333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3197396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3207396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3217333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3227333Sgblack@eecs.umich.edu 3237640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3247333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 3257333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 3267333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 3277333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 3287333Sgblack@eecs.umich.edu ''' 3297396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3307333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3327760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3337396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3347396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3357333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3367333Sgblack@eecs.umich.edu 3377640Sgblack@eecs.umich.edu vmovCoreRegBCode = vfpEnabledCheckCode + ''' 3387639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub); 3397333Sgblack@eecs.umich.edu ''' 3407396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3417333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3427760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3437760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3447396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3457396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3467333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3477333Sgblack@eecs.umich.edu 3487640Sgblack@eecs.umich.edu vmovCoreRegHCode = vfpEnabledCheckCode + ''' 3497639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh); 3507333Sgblack@eecs.umich.edu ''' 3517396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3527333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3537760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3547760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3557396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3567396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3577333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3587333Sgblack@eecs.umich.edu 3597640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3607333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 3617333Sgblack@eecs.umich.edu ''' 3627396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3637333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3647760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3657760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3667396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3677396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3687333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3697333Sgblack@eecs.umich.edu 3707640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3717639Sgblack@eecs.umich.edu assert(imm < 4); 3727639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8); 3737333Sgblack@eecs.umich.edu ''' 3747396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3757333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3767760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3777760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3787396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3797396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3807333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3817333Sgblack@eecs.umich.edu 3827640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3837639Sgblack@eecs.umich.edu assert(imm < 2); 3847639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16); 3857333Sgblack@eecs.umich.edu ''' 3867396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3877333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3897760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3907396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3917396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3927333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3937333Sgblack@eecs.umich.edu 3947640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 3957639Sgblack@eecs.umich.edu assert(imm < 4); 3967639Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8)); 3977333Sgblack@eecs.umich.edu ''' 3987396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3997333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 4007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4017760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4027396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 4037396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 4047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 4057333Sgblack@eecs.umich.edu 4067640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 4077639Sgblack@eecs.umich.edu assert(imm < 2); 4087639Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16)); 4097333Sgblack@eecs.umich.edu ''' 4107396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 4117333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 4127760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4137760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4147396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 4157396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 4167333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 4177333Sgblack@eecs.umich.edu 4187640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 4197333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 4207333Sgblack@eecs.umich.edu ''' 4217396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 4227333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 4237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4247760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4257396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4267396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4277333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4287333Sgblack@eecs.umich.edu 4297640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4307333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 4317333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 4327333Sgblack@eecs.umich.edu ''' 4337396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4347333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4357760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4367760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4377396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4387396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4397333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4407333Sgblack@eecs.umich.edu 4417640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4427333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 4437333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 4447333Sgblack@eecs.umich.edu ''' 4457396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4467333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4477760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4487760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4497396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4507396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4517333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4527381Sgblack@eecs.umich.edu}}; 4537381Sgblack@eecs.umich.edu 4547381Sgblack@eecs.umich.edulet {{ 4557381Sgblack@eecs.umich.edu 4567381Sgblack@eecs.umich.edu header_output = "" 4577381Sgblack@eecs.umich.edu decoder_output = "" 4587381Sgblack@eecs.umich.edu exec_output = "" 4597364Sgblack@eecs.umich.edu 4607783SGiacomo.Gabrielli@arm.com singleSimpleCode = vfpEnabledCheckCode + ''' 4617783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 4627396Sgblack@eecs.umich.edu FpDest = %(op)s; 4637783SGiacomo.Gabrielli@arm.com ''' 4647783SGiacomo.Gabrielli@arm.com singleCode = singleSimpleCode + ''' 4657783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4667364Sgblack@eecs.umich.edu ''' 4677396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4687639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4697396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4707640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4717783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 4727396Sgblack@eecs.umich.edu double dest = %(op)s; 4737396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 4747396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 4757783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4767396Sgblack@eecs.umich.edu ''' 4777396Sgblack@eecs.umich.edu doubleBinOp = ''' 4787396Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 4797396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 4807639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 4817396Sgblack@eecs.umich.edu ''' 4827396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 4837396Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, 4847396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 4857396Sgblack@eecs.umich.edu ''' 4867364Sgblack@eecs.umich.edu 4877760SGiacomo.Gabrielli@arm.com def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 4887396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4897365Sgblack@eecs.umich.edu 4907396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4917396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4927396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4937760SGiacomo.Gabrielli@arm.com { "code": code, 4947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4957760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 4967396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4977396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4987396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4997760SGiacomo.Gabrielli@arm.com { "code": code, 5007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5017760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5027365Sgblack@eecs.umich.edu 5037396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5047396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5057366Sgblack@eecs.umich.edu 5067396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5077396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5087396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5097396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5107366Sgblack@eecs.umich.edu 5117760SGiacomo.Gabrielli@arm.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS", 5127760SGiacomo.Gabrielli@arm.com "fpAddD") 5137760SGiacomo.Gabrielli@arm.com buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS", 5147760SGiacomo.Gabrielli@arm.com "fpSubD") 5157760SGiacomo.Gabrielli@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS", 5167760SGiacomo.Gabrielli@arm.com "fpDivD") 5177760SGiacomo.Gabrielli@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS", 5187760SGiacomo.Gabrielli@arm.com "fpMulD") 5197367Sgblack@eecs.umich.edu 5207760SGiacomo.Gabrielli@arm.com def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 5217396Sgblack@eecs.umich.edu if doubleOp is None: 5227396Sgblack@eecs.umich.edu doubleOp = singleOp 5237396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5247367Sgblack@eecs.umich.edu 5257396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 5267396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5277396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5287760SGiacomo.Gabrielli@arm.com { "code": code, 5297760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5307760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5317396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 5327396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5337396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5347760SGiacomo.Gabrielli@arm.com { "code": code, 5357760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5367760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5377368Sgblack@eecs.umich.edu 5387396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5397396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5407368Sgblack@eecs.umich.edu 5417396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5427396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5437396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5447396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5457369Sgblack@eecs.umich.edu 5467760SGiacomo.Gabrielli@arm.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "SimdFloatSqrtOp", "sqrtf", 5477760SGiacomo.Gabrielli@arm.com "sqrt") 5487369Sgblack@eecs.umich.edu 5497760SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 5507760SGiacomo.Gabrielli@arm.com doubleOp = None): 5517396Sgblack@eecs.umich.edu if doubleOp is None: 5527396Sgblack@eecs.umich.edu doubleOp = singleOp 5537396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5547369Sgblack@eecs.umich.edu 5557396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5567783SGiacomo.Gabrielli@arm.com { "code": singleSimpleCode % { "op": singleOp }, 5577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5587760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5597396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5607396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 5617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5627760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5637369Sgblack@eecs.umich.edu 5647396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5657396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5667396Sgblack@eecs.umich.edu 5677396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5687396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5697396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5707396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5717396Sgblack@eecs.umich.edu 5727760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", 5737396Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") 5747760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", 5757396Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") 5767381Sgblack@eecs.umich.edu}}; 5777381Sgblack@eecs.umich.edu 5787381Sgblack@eecs.umich.edulet {{ 5797381Sgblack@eecs.umich.edu 5807381Sgblack@eecs.umich.edu header_output = "" 5817381Sgblack@eecs.umich.edu decoder_output = "" 5827381Sgblack@eecs.umich.edu exec_output = "" 5837370Sgblack@eecs.umich.edu 5847640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 5857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 5867396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5877639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5887639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 5897639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5907783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 5917370Sgblack@eecs.umich.edu ''' 5927396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5937370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 5967396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5977396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5987370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5997370Sgblack@eecs.umich.edu 6007640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 6017783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6027396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6037396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6047639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6057396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 6067639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 6077639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6087396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6097396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6107783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6117370Sgblack@eecs.umich.edu ''' 6127396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 6137370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6147760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6157760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6167396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 6177396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 6187370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6197370Sgblack@eecs.umich.edu 6207640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 6217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6227396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6237639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6247639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 6257639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6267783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6277370Sgblack@eecs.umich.edu ''' 6287396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 6297370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6307760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6317760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6327396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 6337396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 6347370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 6357370Sgblack@eecs.umich.edu 6367640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 6377783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6387396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6397396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6407639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6417396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 6427639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 6437639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6447396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6457396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6467783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6477370Sgblack@eecs.umich.edu ''' 6487396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 6497370Sgblack@eecs.umich.edu { "code": vmlsDCode, 6507760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6517760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6527396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 6537396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 6547370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 6557371Sgblack@eecs.umich.edu 6567640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 6577783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6587396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6597639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6607639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 6617639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6627783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6637371Sgblack@eecs.umich.edu ''' 6647396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 6657371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 6667760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6677760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6687396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 6697396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 6707371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 6717371Sgblack@eecs.umich.edu 6727640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 6737783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6747396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6757396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6767639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6777396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6787639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 6797639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6807396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6817396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6827783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6837371Sgblack@eecs.umich.edu ''' 6847396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 6857371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6887396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 6897396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 6907371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6917371Sgblack@eecs.umich.edu 6927640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 6937783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6947396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6957639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6967639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 6977639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6987783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6997371Sgblack@eecs.umich.edu ''' 7007396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 7017760SGiacomo.Gabrielli@arm.com { "code": vnmlsSCode, 7027760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7037760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7047396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 7057396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 7067371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7077371Sgblack@eecs.umich.edu 7087640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 7097783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7107396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 7117396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 7127639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7137396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 7147639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 7157639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7167396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 7177396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 7187783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7197371Sgblack@eecs.umich.edu ''' 7207396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 7217760SGiacomo.Gabrielli@arm.com { "code": vnmlsDCode, 7227760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7237760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7247396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 7257396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 7267371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 7277371Sgblack@eecs.umich.edu 7287640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 7297783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7307639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 7317639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7327783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7337371Sgblack@eecs.umich.edu ''' 7347396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 7357760SGiacomo.Gabrielli@arm.com { "code": vnmulSCode, 7367760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7377760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 7387396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 7397396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 7407371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 7417371Sgblack@eecs.umich.edu 7427640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 7437783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7447396Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 7457396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 7467639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 7477639Sgblack@eecs.umich.edu fpscr.rMode); 7487396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 7497396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 7507783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7517371Sgblack@eecs.umich.edu ''' 7527396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 7537371Sgblack@eecs.umich.edu { "code": vnmulDCode, 7547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7557760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 7567396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 7577396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 7587371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 7597381Sgblack@eecs.umich.edu}}; 7607381Sgblack@eecs.umich.edu 7617381Sgblack@eecs.umich.edulet {{ 7627381Sgblack@eecs.umich.edu 7637381Sgblack@eecs.umich.edu header_output = "" 7647381Sgblack@eecs.umich.edu decoder_output = "" 7657381Sgblack@eecs.umich.edu exec_output = "" 7667373Sgblack@eecs.umich.edu 7677640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 7687783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7697397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7707381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 7717373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 7727381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7757373Sgblack@eecs.umich.edu ''' 7767396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 7777373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 7787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 7807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 7817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 7827373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 7837373Sgblack@eecs.umich.edu 7847640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 7857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7867397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7877381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 7887397Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0.uw; 7897397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7907639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7917397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7927397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7937783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7947373Sgblack@eecs.umich.edu ''' 7957396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 7967373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 7977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7987760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 7997396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 8007396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 8017373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 8027373Sgblack@eecs.umich.edu 8037640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 8047783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8057397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8067381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 8077373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 8087381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8097639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8107783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8117373Sgblack@eecs.umich.edu ''' 8127396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 8137373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 8147760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8157760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8167396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 8177396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 8187373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 8197373Sgblack@eecs.umich.edu 8207640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 8217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8227397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8237381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 8247397Sgblack@eecs.umich.edu double cDest = FpOp1P0.sw; 8257397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8267639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8277397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 8287397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 8297783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8307373Sgblack@eecs.umich.edu ''' 8317396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 8327373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 8337760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8347760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8357396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 8367396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 8377373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 8387373Sgblack@eecs.umich.edu 8397640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 8407783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8417397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8427397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8437381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8447388Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 8457381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 8467639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8477783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8487380Sgblack@eecs.umich.edu ''' 8497396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 8507380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 8517760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8527760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8537396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 8547396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 8557380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 8567380Sgblack@eecs.umich.edu 8577640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 8587783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8597397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8607397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8617397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8627397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8637397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 8647381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8657639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8667380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8677783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8687380Sgblack@eecs.umich.edu ''' 8697396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 8707380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 8717760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8727760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8737396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 8747396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 8757380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 8767380Sgblack@eecs.umich.edu 8777640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 8787783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8797397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8807397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8817381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8827388Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 8837381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 8847639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8857783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8867380Sgblack@eecs.umich.edu ''' 8877396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 8887380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 8897760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8907760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8917396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 8927396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 8937380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 8947380Sgblack@eecs.umich.edu 8957640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 8967783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8977397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8987397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8997397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9007397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9017397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 9027381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9037639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9047380Sgblack@eecs.umich.edu FpDestP0.uw = result; 9057783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9067380Sgblack@eecs.umich.edu ''' 9077396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 9087380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 9097760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9107760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9117396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 9127396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 9137380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 9147380Sgblack@eecs.umich.edu 9157640Sgblack@eecs.umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 9167783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9177397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9187397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9197380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9207381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9217387Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 9227381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 9237639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9247783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9257373Sgblack@eecs.umich.edu ''' 9267396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 9277373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 9287760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9297760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9307396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 9317396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 9327373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 9337373Sgblack@eecs.umich.edu 9347640Sgblack@eecs.umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 9357783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9367397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9377397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9387397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9397380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9407397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9417397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 9427381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9437639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9447373Sgblack@eecs.umich.edu FpDestP0.uw = result; 9457783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9467373Sgblack@eecs.umich.edu ''' 9477396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 9487373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 9497760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9507760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9517396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 9527396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 9537373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 9547373Sgblack@eecs.umich.edu 9557640Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 9567783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9577397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9587397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9597380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9607381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9617387Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 9627381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 9637639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9647783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9657373Sgblack@eecs.umich.edu ''' 9667396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 9677373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 9687760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9697760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9707396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 9717396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 9727373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 9737373Sgblack@eecs.umich.edu 9747640Sgblack@eecs.umich.edu vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 9757783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9767397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9777397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9787397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9797380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9807397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9817397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 9827381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9837639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9847373Sgblack@eecs.umich.edu FpDestP0.uw = result; 9857783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9867373Sgblack@eecs.umich.edu ''' 9877396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 9887373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 9897760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9907760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9917396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 9927396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 9937373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 9947374Sgblack@eecs.umich.edu 9957640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 9967783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9977397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9987397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9997381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10007783SGiacomo.Gabrielli@arm.com double cDest = fixFpSFpDDest(FpscrExc, FpOp1); 10017397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 10027639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10037397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 10047397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 10057783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10067374Sgblack@eecs.umich.edu ''' 10077396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 10087374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 10097760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10107760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10117396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 10127396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 10137374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 10147374Sgblack@eecs.umich.edu 10157640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 10167783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10177397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 10187397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10197397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10207397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 10217783SGiacomo.Gabrielli@arm.com FpDest = fixFpDFpSDest(FpscrExc, cOp1); 10227381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10237639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10247783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10257374Sgblack@eecs.umich.edu ''' 10267396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 10277374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 10287760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10297760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10307396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 10317396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 10327374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 10337377Sgblack@eecs.umich.edu 10347640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 10357783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10367398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10377398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10387398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10397639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 10407639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 10417398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10427639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10437783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10447398Sgblack@eecs.umich.edu ''' 10457398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 10467398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 10477760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10487760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10497398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 10507398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 10517398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 10527398Sgblack@eecs.umich.edu 10537640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 10547783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10557398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10567398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10577639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 10587639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 10597398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10607639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10617783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10627398Sgblack@eecs.umich.edu ''' 10637398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 10647398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 10657760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10667760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10677398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 10687398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 10697398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 10707398Sgblack@eecs.umich.edu 10717640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 10727783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10737398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10747398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10757639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10767639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 10777639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 31, 16,, 10787639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10797639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 10807639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10817639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10827783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10837398Sgblack@eecs.umich.edu ''' 10847398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 10857398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 10867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10887398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 10897398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 10907398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 10917398Sgblack@eecs.umich.edu 10927640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 10937783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10947398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10957398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10967639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10977639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 10987639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 15, 0, 10997639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 11007639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 11017639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 11027639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11037783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11047398Sgblack@eecs.umich.edu ''' 11057398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 11067398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 11077760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11087760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11097398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 11107398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 11117398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 11127398Sgblack@eecs.umich.edu 11137640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 11147783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11157397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 11167377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11177377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11187377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11197377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11207377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11217377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11227377Sgblack@eecs.umich.edu } else { 11237389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11247389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 11257396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 11267389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 11277396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 11287389Sgblack@eecs.umich.edu if (signal1 || signal2) 11297389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11307377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11317377Sgblack@eecs.umich.edu } 11327643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11337783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11347377Sgblack@eecs.umich.edu ''' 11357396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 11367377Sgblack@eecs.umich.edu { "code": vcmpSCode, 11377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11397396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 11407396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 11417377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 11427377Sgblack@eecs.umich.edu 11437640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 11447397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 11457397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11467783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11477397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 11487397Sgblack@eecs.umich.edu if (cDest == cOp1) { 11497377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11507397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 11517377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11527397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 11537377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11547377Sgblack@eecs.umich.edu } else { 11557389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 11567397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 11577397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 11587397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 11597397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 11607389Sgblack@eecs.umich.edu if (signal1 || signal2) 11617389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11627377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11637377Sgblack@eecs.umich.edu } 11647643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11657783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11667377Sgblack@eecs.umich.edu ''' 11677396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 11687377Sgblack@eecs.umich.edu { "code": vcmpDCode, 11697760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11707760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11717396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 11727396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 11737377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 11747377Sgblack@eecs.umich.edu 11757640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 11767783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11777397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 11787389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11797389Sgblack@eecs.umich.edu assert(imm == 0); 11807377Sgblack@eecs.umich.edu if (FpDest == imm) { 11817377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11827377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11837377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11847377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11857377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11867377Sgblack@eecs.umich.edu } else { 11877389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11887389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 11897396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 11907389Sgblack@eecs.umich.edu if (signal) 11917389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11927377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11937377Sgblack@eecs.umich.edu } 11947643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11957783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11967377Sgblack@eecs.umich.edu ''' 11977396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 11987377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 11997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12017396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 12027396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 12037377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 12047377Sgblack@eecs.umich.edu 12057640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 12067389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12077389Sgblack@eecs.umich.edu assert(imm == 0); 12087397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 12097783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12107397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 12117397Sgblack@eecs.umich.edu if (cDest == imm) { 12127377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12137397Sgblack@eecs.umich.edu } else if (cDest < imm) { 12147377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12157397Sgblack@eecs.umich.edu } else if (cDest > imm) { 12167377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12177377Sgblack@eecs.umich.edu } else { 12187389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12197397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 12207397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 12217389Sgblack@eecs.umich.edu if (signal) 12227389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12237377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12247377Sgblack@eecs.umich.edu } 12257643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12267783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12277377Sgblack@eecs.umich.edu ''' 12287396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 12297377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 12307760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12317760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12327396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 12337396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 12347377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 12357389Sgblack@eecs.umich.edu 12367640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 12377783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12387397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 12397389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12407389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12417389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12427389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12437389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12447389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12457389Sgblack@eecs.umich.edu } else { 12467389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12477389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12487389Sgblack@eecs.umich.edu } 12497643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12507783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12517389Sgblack@eecs.umich.edu ''' 12527396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 12537389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 12547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12557760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12567396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 12577396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 12587389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 12597389Sgblack@eecs.umich.edu 12607640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 12617397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12627397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 12637783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12647397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 12657397Sgblack@eecs.umich.edu if (cDest == cOp1) { 12667389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12677397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 12687389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12697397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 12707389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12717389Sgblack@eecs.umich.edu } else { 12727389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12737389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12747389Sgblack@eecs.umich.edu } 12757643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12767783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12777389Sgblack@eecs.umich.edu ''' 12787396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 12797389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 12807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12827396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 12837396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 12847389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 12857389Sgblack@eecs.umich.edu 12867640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 12877783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12887397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 12897389Sgblack@eecs.umich.edu if (FpDest == imm) { 12907389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12917389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12927389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12937389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12947389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12957389Sgblack@eecs.umich.edu } else { 12967389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12977389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12987389Sgblack@eecs.umich.edu } 12997643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13007783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13017389Sgblack@eecs.umich.edu ''' 13027396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 13037389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 13047760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13057760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13067396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 13077396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 13087389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 13097389Sgblack@eecs.umich.edu 13107640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 13117397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 13127783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13137397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 13147397Sgblack@eecs.umich.edu if (cDest == imm) { 13157389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13167397Sgblack@eecs.umich.edu } else if (cDest < imm) { 13177389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13187397Sgblack@eecs.umich.edu } else if (cDest > imm) { 13197389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13207389Sgblack@eecs.umich.edu } else { 13217389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13227389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13237389Sgblack@eecs.umich.edu } 13247643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13257783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13267389Sgblack@eecs.umich.edu ''' 13277396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 13287389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 13297760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13307760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13317396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 13327396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 13337389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 13347322Sgblack@eecs.umich.edu}}; 13357379Sgblack@eecs.umich.edu 13367379Sgblack@eecs.umich.edulet {{ 13377379Sgblack@eecs.umich.edu 13387379Sgblack@eecs.umich.edu header_output = "" 13397379Sgblack@eecs.umich.edu decoder_output = "" 13407379Sgblack@eecs.umich.edu exec_output = "" 13417379Sgblack@eecs.umich.edu 13427640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 13437783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13447397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13457397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13467381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13477379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 13487381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 13497639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13507783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13517379Sgblack@eecs.umich.edu ''' 13527396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 13537379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 13547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13557760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13567396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 13577396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 13587379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 13597379Sgblack@eecs.umich.edu 13607640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 13617783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13627397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 13637397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13647397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13657397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13667397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 13677381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13687639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13697379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13707379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13727379Sgblack@eecs.umich.edu ''' 13737396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 13747379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 13757760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13767760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13777396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 13787396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 13797379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 13807379Sgblack@eecs.umich.edu 13817640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 13827783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13837397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13847397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13857381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13867379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 13877381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 13887639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13897783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13907379Sgblack@eecs.umich.edu ''' 13917396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 13927379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 13937760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13947760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13957396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 13967396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 13977379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 13987379Sgblack@eecs.umich.edu 13997640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 14007783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14017397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 14027397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14037397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14047397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 14057397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 14067381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 14077639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14087379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 14097379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 14107783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14117379Sgblack@eecs.umich.edu ''' 14127396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 14137379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 14147760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14157760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14167396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 14177396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 14187379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 14197379Sgblack@eecs.umich.edu 14207640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 14217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14227397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14237381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 14247639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 14257381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14267639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14277783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14287379Sgblack@eecs.umich.edu ''' 14297396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 14307379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 14317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14327760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14337396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 14347396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 14357379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 14367379Sgblack@eecs.umich.edu 14377640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 14387783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14397379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14407397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14417381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14427639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 14437397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14447639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14457397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 14467397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 14477783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14487379Sgblack@eecs.umich.edu ''' 14497396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 14507379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 14517760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14527760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14537396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 14547396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 14557379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 14567379Sgblack@eecs.umich.edu 14577640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 14587783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14597397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14607381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 14617639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 14627381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14637639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14647783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14657379Sgblack@eecs.umich.edu ''' 14667396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 14677379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 14687760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14697760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14707396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 14717396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 14727379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 14737379Sgblack@eecs.umich.edu 14747640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 14757783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14767379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14777397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14787381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14797639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 14807397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14817639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14827397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 14837397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 14847783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14857379Sgblack@eecs.umich.edu ''' 14867396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 14877379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 14887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14897760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14907396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 14917396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 14927379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 14937379Sgblack@eecs.umich.edu 14947640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 14957783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14967397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14977397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14997379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 15007381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 15017639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15027783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15037379Sgblack@eecs.umich.edu ''' 15047379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 15057396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15067379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 15077760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15087760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15097396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 15107396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 15117379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 15127379Sgblack@eecs.umich.edu 15137640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 15147783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15157397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 15167397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15177397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15187397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 15197397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 15207381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 15217639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15227379Sgblack@eecs.umich.edu FpDestP0.uw = result; 15237379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 15247783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15257379Sgblack@eecs.umich.edu ''' 15267379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 15277396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15287379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 15297760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15307760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15317396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 15327396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 15337379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 15347379Sgblack@eecs.umich.edu 15357640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 15367783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15377397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15387397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15397381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 15407379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 15417381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 15427639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15437783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15447379Sgblack@eecs.umich.edu ''' 15457379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 15467396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15477379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 15487760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15497760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15507396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 15517396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 15527379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 15537379Sgblack@eecs.umich.edu 15547640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 15557783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15567397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 15577397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15587397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15597397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 15607397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 15617381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15627639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15637379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 15647379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 15657783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15667379Sgblack@eecs.umich.edu ''' 15677379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 15687396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15697379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 15707760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15717760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15727396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 15737396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 15747379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 15757379Sgblack@eecs.umich.edu 15767640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 15777783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15787397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15797381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 15807639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 15817381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15827639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15837783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15847379Sgblack@eecs.umich.edu ''' 15857379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 15867396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15877379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 15887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15897760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15907396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 15917396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 15927379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 15937379Sgblack@eecs.umich.edu 15947640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 15957783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15967379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15977397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15997639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 16007397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16017639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16027397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 16037397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 16047783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16057379Sgblack@eecs.umich.edu ''' 16067379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 16077396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16087379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 16097760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16107760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16117396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 16127396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 16137379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 16147379Sgblack@eecs.umich.edu 16157640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 16167783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16177397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16187381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 16197639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 16207381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 16217639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16227783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16237379Sgblack@eecs.umich.edu ''' 16247379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 16257396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16267379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 16277760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16287760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16297396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 16307396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 16317379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 16327379Sgblack@eecs.umich.edu 16337640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 16347783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16357379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 16367397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16377381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 16387639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 16397397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16407639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16417397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 16427397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 16437783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16447379Sgblack@eecs.umich.edu ''' 16457379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 16467396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16477379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 16487760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16497760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16507396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 16517396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 16527379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 16537379Sgblack@eecs.umich.edu}}; 1654