fp.isa revision 7760
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947396Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1957644Sali.saidi@arm.com { "code": vmsrEnabledCheckCode + \ 1967640Sgblack@eecs.umich.edu "MiscDest = Op1;", 1977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 1987760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 1997648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 2007396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrIop); 2017396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 2027322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2037324Sgblack@eecs.umich.edu 2047644Sali.saidi@arm.com vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2057643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2067643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2077643Sgblack@eecs.umich.edu ''' 2087643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2097643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2107760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2117760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2127643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2137643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2147643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2157643Sgblack@eecs.umich.edu 2167396Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2177644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2187760SGiacomo.Gabrielli@arm.com "Dest = MiscOp1;", 2197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2217396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2227396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2237324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2247333Sgblack@eecs.umich.edu 2257643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2267644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2277643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2287760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2297760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2307643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2317643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2327643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2337643Sgblack@eecs.umich.edu 2347644Sali.saidi@arm.com vmrsApsrCode = vmrsEnabledCheckCode + ''' 2357643Sgblack@eecs.umich.edu Dest = (MiscOp1 & imm) | (Dest & ~imm); 2367643Sgblack@eecs.umich.edu ''' 2377396Sgblack@eecs.umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 2387392Sgblack@eecs.umich.edu { "code": vmrsApsrCode, 2397760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2407760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2417396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 2427396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 2437392Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrIop); 2447392Sgblack@eecs.umich.edu 2457644Sali.saidi@arm.com vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' 2467643Sgblack@eecs.umich.edu assert((imm & ~FpCondCodesMask) == 0); 2477643Sgblack@eecs.umich.edu Dest = (FpCondCodes & imm) | (Dest & ~imm); 2487643Sgblack@eecs.umich.edu ''' 2497643Sgblack@eecs.umich.edu vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", 2507643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2517760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2527760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2537643Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); 2547643Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); 2557643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2567643Sgblack@eecs.umich.edu 2577640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2587333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2597333Sgblack@eecs.umich.edu ''' 2607396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2617333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2627760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2637760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2647396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2657396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2667333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2677333Sgblack@eecs.umich.edu 2687640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2697333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2707333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2717333Sgblack@eecs.umich.edu ''' 2727396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2737333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2747760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2757760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2767396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2777396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2787333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2797333Sgblack@eecs.umich.edu 2807640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 2817333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2827333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2837333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2847333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2857333Sgblack@eecs.umich.edu ''' 2867396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2877333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2897760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2907396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2917396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2927333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2937333Sgblack@eecs.umich.edu 2947640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 2957333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2967333Sgblack@eecs.umich.edu ''' 2977396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 2987333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3017396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 3027396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 3037333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 3047333Sgblack@eecs.umich.edu 3057640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 3067333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 3077333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 3087333Sgblack@eecs.umich.edu ''' 3097396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3107333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3127760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3137396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3147396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3157333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3167333Sgblack@eecs.umich.edu 3177640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3187333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 3197333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 3207333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 3217333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 3227333Sgblack@eecs.umich.edu ''' 3237396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3247333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3257760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3267760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3277396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3287396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3297333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3307333Sgblack@eecs.umich.edu 3317640Sgblack@eecs.umich.edu vmovCoreRegBCode = vfpEnabledCheckCode + ''' 3327639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub); 3337333Sgblack@eecs.umich.edu ''' 3347396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3357333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3367760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3377760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3387396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3397396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3407333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3417333Sgblack@eecs.umich.edu 3427640Sgblack@eecs.umich.edu vmovCoreRegHCode = vfpEnabledCheckCode + ''' 3437639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh); 3447333Sgblack@eecs.umich.edu ''' 3457396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3467333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3477760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3487760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3497396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3507396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3517333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3527333Sgblack@eecs.umich.edu 3537640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3547333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 3557333Sgblack@eecs.umich.edu ''' 3567396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3577333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3587760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3597760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3607396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3617396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3627333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3637333Sgblack@eecs.umich.edu 3647640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3657639Sgblack@eecs.umich.edu assert(imm < 4); 3667639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8); 3677333Sgblack@eecs.umich.edu ''' 3687396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3697333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3707760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3717760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3727396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3737396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3747333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3757333Sgblack@eecs.umich.edu 3767640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3777639Sgblack@eecs.umich.edu assert(imm < 2); 3787639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16); 3797333Sgblack@eecs.umich.edu ''' 3807396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3817333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3837760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3847396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3857396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3867333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3877333Sgblack@eecs.umich.edu 3887640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 3897639Sgblack@eecs.umich.edu assert(imm < 4); 3907639Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8)); 3917333Sgblack@eecs.umich.edu ''' 3927396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3937333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3967396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3977396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3987333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3997333Sgblack@eecs.umich.edu 4007640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 4017639Sgblack@eecs.umich.edu assert(imm < 2); 4027639Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16)); 4037333Sgblack@eecs.umich.edu ''' 4047396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 4057333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 4067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4087396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 4097396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 4107333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 4117333Sgblack@eecs.umich.edu 4127640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 4137333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 4147333Sgblack@eecs.umich.edu ''' 4157396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 4167333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 4177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4197396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4207396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4217333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4227333Sgblack@eecs.umich.edu 4237640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4247333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 4257333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 4267333Sgblack@eecs.umich.edu ''' 4277396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4287333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4297760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4307760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4317396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4327396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4337333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4347333Sgblack@eecs.umich.edu 4357640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4367333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 4377333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 4387333Sgblack@eecs.umich.edu ''' 4397396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4407333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4417760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4427760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4437396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4447396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4457333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4467381Sgblack@eecs.umich.edu}}; 4477381Sgblack@eecs.umich.edu 4487381Sgblack@eecs.umich.edulet {{ 4497381Sgblack@eecs.umich.edu 4507381Sgblack@eecs.umich.edu header_output = "" 4517381Sgblack@eecs.umich.edu decoder_output = "" 4527381Sgblack@eecs.umich.edu exec_output = "" 4537364Sgblack@eecs.umich.edu 4547640Sgblack@eecs.umich.edu singleCode = vfpEnabledCheckCode + ''' 4557643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 4567396Sgblack@eecs.umich.edu FpDest = %(op)s; 4577643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 4587364Sgblack@eecs.umich.edu ''' 4597396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4607639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4617396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4627640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4637643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 4647396Sgblack@eecs.umich.edu double dest = %(op)s; 4657643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 4667396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 4677396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 4687396Sgblack@eecs.umich.edu ''' 4697396Sgblack@eecs.umich.edu doubleBinOp = ''' 4707396Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 4717396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 4727639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 4737396Sgblack@eecs.umich.edu ''' 4747396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 4757396Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, 4767396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 4777396Sgblack@eecs.umich.edu ''' 4787364Sgblack@eecs.umich.edu 4797760SGiacomo.Gabrielli@arm.com def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 4807396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4817365Sgblack@eecs.umich.edu 4827396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4837396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4847396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4857760SGiacomo.Gabrielli@arm.com { "code": code, 4867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4877760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 4887396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4897396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4907396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4917760SGiacomo.Gabrielli@arm.com { "code": code, 4927760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4937760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 4947365Sgblack@eecs.umich.edu 4957396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4967396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4977366Sgblack@eecs.umich.edu 4987396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4997396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5007396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5017396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5027366Sgblack@eecs.umich.edu 5037760SGiacomo.Gabrielli@arm.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS", 5047760SGiacomo.Gabrielli@arm.com "fpAddD") 5057760SGiacomo.Gabrielli@arm.com buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS", 5067760SGiacomo.Gabrielli@arm.com "fpSubD") 5077760SGiacomo.Gabrielli@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS", 5087760SGiacomo.Gabrielli@arm.com "fpDivD") 5097760SGiacomo.Gabrielli@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS", 5107760SGiacomo.Gabrielli@arm.com "fpMulD") 5117367Sgblack@eecs.umich.edu 5127760SGiacomo.Gabrielli@arm.com def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 5137396Sgblack@eecs.umich.edu if doubleOp is None: 5147396Sgblack@eecs.umich.edu doubleOp = singleOp 5157396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5167367Sgblack@eecs.umich.edu 5177396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 5187396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5197396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5207760SGiacomo.Gabrielli@arm.com { "code": code, 5217760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5227760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5237396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 5247396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5257396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5267760SGiacomo.Gabrielli@arm.com { "code": code, 5277760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5287760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5297368Sgblack@eecs.umich.edu 5307396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5317396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5327368Sgblack@eecs.umich.edu 5337396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5347396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5357396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5367396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5377369Sgblack@eecs.umich.edu 5387760SGiacomo.Gabrielli@arm.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "SimdFloatSqrtOp", "sqrtf", 5397760SGiacomo.Gabrielli@arm.com "sqrt") 5407369Sgblack@eecs.umich.edu 5417760SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 5427760SGiacomo.Gabrielli@arm.com doubleOp = None): 5437396Sgblack@eecs.umich.edu if doubleOp is None: 5447396Sgblack@eecs.umich.edu doubleOp = singleOp 5457396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5467369Sgblack@eecs.umich.edu 5477396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5487396Sgblack@eecs.umich.edu { "code": singleCode % { "op": singleOp }, 5497760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5507760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5517396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5527396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 5537760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5547760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5557369Sgblack@eecs.umich.edu 5567396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5577396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5587396Sgblack@eecs.umich.edu 5597396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5607396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5617396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5627396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5637396Sgblack@eecs.umich.edu 5647760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", 5657396Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") 5667760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", 5677396Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") 5687381Sgblack@eecs.umich.edu}}; 5697381Sgblack@eecs.umich.edu 5707381Sgblack@eecs.umich.edulet {{ 5717381Sgblack@eecs.umich.edu 5727381Sgblack@eecs.umich.edu header_output = "" 5737381Sgblack@eecs.umich.edu decoder_output = "" 5747381Sgblack@eecs.umich.edu exec_output = "" 5757370Sgblack@eecs.umich.edu 5767640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 5777643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5787396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5797639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5807639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 5817639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5827643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 5837370Sgblack@eecs.umich.edu ''' 5847396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5857370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 5887396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5897396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5907370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5917370Sgblack@eecs.umich.edu 5927640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 5937643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5947396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5957396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5967639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5977396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5987639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 5997639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6007643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6017396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6027396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6037370Sgblack@eecs.umich.edu ''' 6047396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 6057370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6087396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 6097396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 6107370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6117370Sgblack@eecs.umich.edu 6127640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 6137643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6147396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6157639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6167639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 6177639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6187643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6197370Sgblack@eecs.umich.edu ''' 6207396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 6217370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6227760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6237760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6247396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 6257396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 6267370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 6277370Sgblack@eecs.umich.edu 6287640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 6297643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6307396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6317396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6327639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6337396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 6347639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 6357639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6367643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6377396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6387396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6397370Sgblack@eecs.umich.edu ''' 6407396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 6417370Sgblack@eecs.umich.edu { "code": vmlsDCode, 6427760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6437760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6447396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 6457396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 6467370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 6477371Sgblack@eecs.umich.edu 6487640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 6497643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6507396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6517639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6527639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 6537639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6547643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6557371Sgblack@eecs.umich.edu ''' 6567396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 6577371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 6587760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6597760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6607396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 6617396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 6627371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 6637371Sgblack@eecs.umich.edu 6647640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 6657643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6667396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6677396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6687639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6697396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6707639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 6717639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6727643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6737396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6747396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6757371Sgblack@eecs.umich.edu ''' 6767396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 6777371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6807396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 6817396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 6827371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6837371Sgblack@eecs.umich.edu 6847640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 6857643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6867396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6877639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6887639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 6897639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6907643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6917371Sgblack@eecs.umich.edu ''' 6927396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 6937760SGiacomo.Gabrielli@arm.com { "code": vnmlsSCode, 6947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6967396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 6977396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 6987371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 6997371Sgblack@eecs.umich.edu 7007640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 7017643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7027396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 7037396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 7047639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7057396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 7067639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 7077639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7087643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7097396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 7107396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 7117371Sgblack@eecs.umich.edu ''' 7127396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 7137760SGiacomo.Gabrielli@arm.com { "code": vnmlsDCode, 7147760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7157760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7167396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 7177396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 7187371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 7197371Sgblack@eecs.umich.edu 7207640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 7217643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7227639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 7237639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7247643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7257371Sgblack@eecs.umich.edu ''' 7267396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 7277760SGiacomo.Gabrielli@arm.com { "code": vnmulSCode, 7287760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7297760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 7307396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 7317396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 7327371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 7337371Sgblack@eecs.umich.edu 7347640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 7357643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7367396Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 7377396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 7387639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 7397639Sgblack@eecs.umich.edu fpscr.rMode); 7407643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7417396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 7427396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 7437371Sgblack@eecs.umich.edu ''' 7447396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 7457371Sgblack@eecs.umich.edu { "code": vnmulDCode, 7467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7477760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 7487396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 7497396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 7507371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 7517381Sgblack@eecs.umich.edu}}; 7527381Sgblack@eecs.umich.edu 7537381Sgblack@eecs.umich.edulet {{ 7547381Sgblack@eecs.umich.edu 7557381Sgblack@eecs.umich.edu header_output = "" 7567381Sgblack@eecs.umich.edu decoder_output = "" 7577381Sgblack@eecs.umich.edu exec_output = "" 7587373Sgblack@eecs.umich.edu 7597640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 7607643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7617397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7627381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 7637373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 7647381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7657639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7667643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7677373Sgblack@eecs.umich.edu ''' 7687396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 7697373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 7707760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7717760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 7727396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 7737396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 7747373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 7757373Sgblack@eecs.umich.edu 7767640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 7777643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7787397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7797381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 7807397Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0.uw; 7817397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7827639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7837643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7847397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7857397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7867373Sgblack@eecs.umich.edu ''' 7877396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 7887373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 7897760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7907760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 7917396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 7927396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 7937373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 7947373Sgblack@eecs.umich.edu 7957640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 7967643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7977397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 7997373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 8007381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8017639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8027643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8037373Sgblack@eecs.umich.edu ''' 8047396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 8057373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 8067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8087396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 8097396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 8107373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 8117373Sgblack@eecs.umich.edu 8127640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 8137643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8147397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8157381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 8167397Sgblack@eecs.umich.edu double cDest = FpOp1P0.sw; 8177397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8187639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8197643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8207397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 8217397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 8227373Sgblack@eecs.umich.edu ''' 8237396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 8247373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 8257760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8267760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8277396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 8287396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 8297373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 8307373Sgblack@eecs.umich.edu 8317640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 8327643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8337397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8347397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8357381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8367388Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 8377381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 8387639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8397643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8407380Sgblack@eecs.umich.edu ''' 8417396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 8427380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 8437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8457396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 8467396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 8477380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 8487380Sgblack@eecs.umich.edu 8497640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 8507643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8517397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8527397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8537397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8547397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8557397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 8567381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8577639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8587643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8597380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8607380Sgblack@eecs.umich.edu ''' 8617396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 8627380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 8637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8647760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8657396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 8667396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 8677380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 8687380Sgblack@eecs.umich.edu 8697640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 8707643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8717397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8727397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8737381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8747388Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 8757381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 8767639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8777643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8787380Sgblack@eecs.umich.edu ''' 8797396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 8807380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 8817760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8827760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8837396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 8847396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 8857380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 8867380Sgblack@eecs.umich.edu 8877640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 8887643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8897397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8907397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8917397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8927397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8937397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 8947381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8957639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8967643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8977380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8987380Sgblack@eecs.umich.edu ''' 8997396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 9007380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 9017760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9027760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9037396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 9047396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 9057380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 9067380Sgblack@eecs.umich.edu 9077640Sgblack@eecs.umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 9087643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9097397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9107397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9117380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9127381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9137387Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 9147381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 9157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9167643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9177373Sgblack@eecs.umich.edu ''' 9187396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 9197373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 9207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9227396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 9237396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 9247373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 9257373Sgblack@eecs.umich.edu 9267640Sgblack@eecs.umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 9277643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9287397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9297397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9317380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9327397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9337397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 9347381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9357639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9367643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9377373Sgblack@eecs.umich.edu FpDestP0.uw = result; 9387373Sgblack@eecs.umich.edu ''' 9397396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 9407373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 9417760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9427760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9437396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 9447396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 9457373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 9467373Sgblack@eecs.umich.edu 9477640Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 9487643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9497397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9507397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9517380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9527381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9537387Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 9547381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 9557639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9567643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9577373Sgblack@eecs.umich.edu ''' 9587396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 9597373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 9607760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9617760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9627396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 9637396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 9647373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 9657373Sgblack@eecs.umich.edu 9667640Sgblack@eecs.umich.edu vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 9677643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9687397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9697397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9707397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9717380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9727397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9737397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 9747381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9757639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9767643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9777373Sgblack@eecs.umich.edu FpDestP0.uw = result; 9787373Sgblack@eecs.umich.edu ''' 9797396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 9807373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 9817760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9827760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9837396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 9847396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 9857373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 9867374Sgblack@eecs.umich.edu 9877640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 9887643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9897397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9907397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9917381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9927397Sgblack@eecs.umich.edu double cDest = fixFpSFpDDest(Fpscr, FpOp1); 9937397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9947639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9957643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9967397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 9977397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 9987374Sgblack@eecs.umich.edu ''' 9997396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 10007374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 10017760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10027760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10037396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 10047396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 10057374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 10067374Sgblack@eecs.umich.edu 10077640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 10087643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10097397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 10107397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10117397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10127397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 10137397Sgblack@eecs.umich.edu FpDest = fixFpDFpSDest(Fpscr, cOp1); 10147381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10167643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10177374Sgblack@eecs.umich.edu ''' 10187396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 10197374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 10207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10227396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 10237396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 10247374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 10257377Sgblack@eecs.umich.edu 10267640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 10277643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10287398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10297398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10307398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10317639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 10327639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 10337398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10347639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10357643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10367398Sgblack@eecs.umich.edu ''' 10377398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 10387398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 10397760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10407760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10417398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 10427398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 10437398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 10447398Sgblack@eecs.umich.edu 10457640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 10467643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10477398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10487398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10497639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 10507639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 10517398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10527639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10537643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10547398Sgblack@eecs.umich.edu ''' 10557398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 10567398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 10577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10597398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 10607398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 10617398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 10627398Sgblack@eecs.umich.edu 10637640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 10647643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10657398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10667398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10677639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10687639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 10697639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 31, 16,, 10707639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10717639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 10727639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10747643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10757398Sgblack@eecs.umich.edu ''' 10767398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 10777398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 10787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10807398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 10817398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 10827398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 10837398Sgblack@eecs.umich.edu 10847640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 10857643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10867398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10877398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10887639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10897639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 10907639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 15, 0, 10917639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10927639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 10937639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10947639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10957643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10967398Sgblack@eecs.umich.edu ''' 10977398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 10987398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 10997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11017398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 11027398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 11037398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 11047398Sgblack@eecs.umich.edu 11057640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 11067643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 11077397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 11087377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11097377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11107377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11117377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11127377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11137377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11147377Sgblack@eecs.umich.edu } else { 11157389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11167389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 11177396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 11187389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 11197396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 11207389Sgblack@eecs.umich.edu if (signal1 || signal2) 11217389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11227377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11237377Sgblack@eecs.umich.edu } 11247643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11257377Sgblack@eecs.umich.edu ''' 11267396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 11277377Sgblack@eecs.umich.edu { "code": vcmpSCode, 11287760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11297760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11307396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 11317396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 11327377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 11337377Sgblack@eecs.umich.edu 11347640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 11357397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 11367397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11377643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 11387397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 11397397Sgblack@eecs.umich.edu if (cDest == cOp1) { 11407377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11417397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 11427377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11437397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 11447377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11457377Sgblack@eecs.umich.edu } else { 11467389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 11477397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 11487397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 11497397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 11507397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 11517389Sgblack@eecs.umich.edu if (signal1 || signal2) 11527389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11537377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11547377Sgblack@eecs.umich.edu } 11557643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11567377Sgblack@eecs.umich.edu ''' 11577396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 11587377Sgblack@eecs.umich.edu { "code": vcmpDCode, 11597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11617396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 11627396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 11637377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 11647377Sgblack@eecs.umich.edu 11657640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 11667643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 11677397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 11687389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11697389Sgblack@eecs.umich.edu assert(imm == 0); 11707377Sgblack@eecs.umich.edu if (FpDest == imm) { 11717377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11727377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11737377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11747377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11757377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11767377Sgblack@eecs.umich.edu } else { 11777389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11787389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 11797396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 11807389Sgblack@eecs.umich.edu if (signal) 11817389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11827377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11837377Sgblack@eecs.umich.edu } 11847643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11857377Sgblack@eecs.umich.edu ''' 11867396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 11877377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 11887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11897760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 11907396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 11917396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 11927377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 11937377Sgblack@eecs.umich.edu 11947640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 11957389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11967389Sgblack@eecs.umich.edu assert(imm == 0); 11977397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11987643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 11997397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 12007397Sgblack@eecs.umich.edu if (cDest == imm) { 12017377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12027397Sgblack@eecs.umich.edu } else if (cDest < imm) { 12037377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12047397Sgblack@eecs.umich.edu } else if (cDest > imm) { 12057377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12067377Sgblack@eecs.umich.edu } else { 12077389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12087397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 12097397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 12107389Sgblack@eecs.umich.edu if (signal) 12117389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12127377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12137377Sgblack@eecs.umich.edu } 12147643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12157377Sgblack@eecs.umich.edu ''' 12167396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 12177377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 12187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12197760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12207396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 12217396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 12227377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 12237389Sgblack@eecs.umich.edu 12247640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 12257643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12267397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 12277389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12287389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12297389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12307389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12317389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12327389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12337389Sgblack@eecs.umich.edu } else { 12347389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12357389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12367389Sgblack@eecs.umich.edu } 12377643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12387389Sgblack@eecs.umich.edu ''' 12397396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 12407389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 12417760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12427760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12437396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 12447396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 12457389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 12467389Sgblack@eecs.umich.edu 12477640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 12487397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12497397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 12507643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12517397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 12527397Sgblack@eecs.umich.edu if (cDest == cOp1) { 12537389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12547397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 12557389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12567397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 12577389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12587389Sgblack@eecs.umich.edu } else { 12597389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12607389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12617389Sgblack@eecs.umich.edu } 12627643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12637389Sgblack@eecs.umich.edu ''' 12647396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 12657389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 12667760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12677760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12687396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 12697396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 12707389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 12717389Sgblack@eecs.umich.edu 12727640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 12737643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12747397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 12757389Sgblack@eecs.umich.edu if (FpDest == imm) { 12767389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12777389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12787389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12797389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12807389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12817389Sgblack@eecs.umich.edu } else { 12827389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12837389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12847389Sgblack@eecs.umich.edu } 12857643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12867389Sgblack@eecs.umich.edu ''' 12877396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 12887389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 12897760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12907760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12917396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 12927396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 12937389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 12947389Sgblack@eecs.umich.edu 12957640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 12967397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 12977643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12987397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 12997397Sgblack@eecs.umich.edu if (cDest == imm) { 13007389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13017397Sgblack@eecs.umich.edu } else if (cDest < imm) { 13027389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13037397Sgblack@eecs.umich.edu } else if (cDest > imm) { 13047389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13057389Sgblack@eecs.umich.edu } else { 13067389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13077389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13087389Sgblack@eecs.umich.edu } 13097643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13107389Sgblack@eecs.umich.edu ''' 13117396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 13127389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 13137760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13147760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13157396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 13167396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 13177389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 13187322Sgblack@eecs.umich.edu}}; 13197379Sgblack@eecs.umich.edu 13207379Sgblack@eecs.umich.edulet {{ 13217379Sgblack@eecs.umich.edu 13227379Sgblack@eecs.umich.edu header_output = "" 13237379Sgblack@eecs.umich.edu decoder_output = "" 13247379Sgblack@eecs.umich.edu exec_output = "" 13257379Sgblack@eecs.umich.edu 13267640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 13277643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13287397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13297397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13307381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13317379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 13327381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 13337639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13347643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13357379Sgblack@eecs.umich.edu ''' 13367396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 13377379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 13387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13397760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13407396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 13417396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 13427379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 13437379Sgblack@eecs.umich.edu 13447640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 13457643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13467397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 13477397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13487397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13497397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13507397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 13517381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13527639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13537643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13547379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13557379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13567379Sgblack@eecs.umich.edu ''' 13577396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 13587379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 13597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13617396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 13627396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 13637379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 13647379Sgblack@eecs.umich.edu 13657640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 13667643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13677397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13687397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13697381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13707379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 13717381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 13727639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13737643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13747379Sgblack@eecs.umich.edu ''' 13757396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 13767379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 13777760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13787760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 13797396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 13807396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 13817379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 13827379Sgblack@eecs.umich.edu 13837640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 13847643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13857397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 13867397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13877397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13887397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13897397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 13907381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13917639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13927643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13937379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13947379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13957379Sgblack@eecs.umich.edu ''' 13967396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 13977379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 13987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14007396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 14017396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 14027379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 14037379Sgblack@eecs.umich.edu 14047640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 14057643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14067397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14077381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 14087639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 14097381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14107639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14117643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14127379Sgblack@eecs.umich.edu ''' 14137396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 14147379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 14157760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14167760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14177396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 14187396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 14197379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 14207379Sgblack@eecs.umich.edu 14217640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 14227643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14237379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14247397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14257381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14267639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 14277397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14287639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14297643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14307397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 14317397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 14327379Sgblack@eecs.umich.edu ''' 14337396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 14347379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 14357760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14367760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14377396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 14387396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 14397379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 14407379Sgblack@eecs.umich.edu 14417640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 14427643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14437397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14447381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 14457639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 14467381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14477639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14487643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14497379Sgblack@eecs.umich.edu ''' 14507396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 14517379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 14527760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14537760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14547396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 14557396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 14567379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 14577379Sgblack@eecs.umich.edu 14587640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 14597643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14607379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14617397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14627381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14637639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 14647397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14657639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14667643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14677397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 14687397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 14697379Sgblack@eecs.umich.edu ''' 14707396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 14717379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 14727760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14737760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14747396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 14757396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 14767379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 14777379Sgblack@eecs.umich.edu 14787640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 14797643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14807397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14817397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14827381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14837379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 14847381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 14857639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14867643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14877379Sgblack@eecs.umich.edu ''' 14887379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 14897396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14907379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 14917760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14927760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14937396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 14947396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 14957379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 14967379Sgblack@eecs.umich.edu 14977640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 14987643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14997397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 15007397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15017397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15027397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 15037397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 15047381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 15057639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15067643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 15077379Sgblack@eecs.umich.edu FpDestP0.uw = result; 15087379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 15097379Sgblack@eecs.umich.edu ''' 15107379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 15117396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15127379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 15137760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15147760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15157396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 15167396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 15177379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 15187379Sgblack@eecs.umich.edu 15197640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 15207643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 15217397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15227397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15237381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 15247379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 15257381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 15267639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15277643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 15287379Sgblack@eecs.umich.edu ''' 15297379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 15307396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15317379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 15327760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15337760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15347396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 15357396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 15367379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 15377379Sgblack@eecs.umich.edu 15387640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 15397643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 15407397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 15417397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15427397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15437397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 15447397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 15457381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15467639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15477643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 15487379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 15497379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 15507379Sgblack@eecs.umich.edu ''' 15517379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 15527396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15537379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 15547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15557760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15567396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 15577396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 15587379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 15597379Sgblack@eecs.umich.edu 15607640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 15617643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 15627397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15637381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 15647639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 15657381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15667639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15677643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 15687379Sgblack@eecs.umich.edu ''' 15697379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 15707396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15717379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 15727760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15737760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15747396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 15757396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 15767379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 15777379Sgblack@eecs.umich.edu 15787640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 15797643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 15807379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15817397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15827381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15837639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 15847397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15857639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15867643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 15877397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 15887397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 15897379Sgblack@eecs.umich.edu ''' 15907379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 15917396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15927379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 15937760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15947760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15957396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 15967396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 15977379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 15987379Sgblack@eecs.umich.edu 15997640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 16007643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 16017397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16027381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 16037639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 16047381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 16057639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16067643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 16077379Sgblack@eecs.umich.edu ''' 16087379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 16097396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16107379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 16117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16127760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16137396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 16147396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 16157379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 16167379Sgblack@eecs.umich.edu 16177640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 16187643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 16197379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 16207397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16217381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 16227639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 16237397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16247639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16257643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 16267397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 16277397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 16287379Sgblack@eecs.umich.edu ''' 16297379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 16307396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16317379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 16327760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16337760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16347396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 16357396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 16367379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 16377379Sgblack@eecs.umich.edu}}; 1638