fp.isa revision 7648
19814Sandreas.hansson@arm.com// -*- mode:c++ -*- 22292SN/A 39383SAli.Saidi@ARM.com// Copyright (c) 2010 ARM Limited 47597Sminkyu.jeong@arm.com// All rights reserved 57597Sminkyu.jeong@arm.com// 67597Sminkyu.jeong@arm.com// The license below extends only to copyright in the software and shall 77597Sminkyu.jeong@arm.com// not be construed as granting a license to any other intellectual 87597Sminkyu.jeong@arm.com// property including but not limited to intellectual property relating 97597Sminkyu.jeong@arm.com// to a hardware implementation of the functionality of the software 107597Sminkyu.jeong@arm.com// licensed hereunder. You may use the software subject to the license 117597Sminkyu.jeong@arm.com// terms below provided that you ensure that this notice is replicated 127597Sminkyu.jeong@arm.com// unmodified and in its entirety in all distributions of the software, 137597Sminkyu.jeong@arm.com// modified or unmodified, in source code or in binary form. 147597Sminkyu.jeong@arm.com// 152292SN/A// Redistribution and use in source and binary forms, with or without 162292SN/A// modification, are permitted provided that the following conditions are 172292SN/A// met: redistributions of source code must retain the above copyright 182292SN/A// notice, this list of conditions and the following disclaimer; 192292SN/A// redistributions in binary form must reproduce the above copyright 202292SN/A// notice, this list of conditions and the following disclaimer in the 212292SN/A// documentation and/or other materials provided with the distribution; 222292SN/A// neither the name of the copyright holders nor the names of its 232292SN/A// contributors may be used to endorse or promote products derived from 242292SN/A// this software without specific prior written permission. 252292SN/A// 262292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272292SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282292SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 302292SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 312292SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 322292SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 332292SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 342292SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 352292SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 362292SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 372292SN/A// 382292SN/A// Authors: Gabe Black 392292SN/A 402689Sktlim@umich.eduoutput header {{ 412689Sktlim@umich.edu 422689Sktlim@umich.edutemplate <class Micro> 432292SN/Aclass VfpMacroRegRegOp : public VfpMacroOp 442292SN/A{ 459944Smatt.horsnell@ARM.com public: 469944Smatt.horsnell@ARM.com VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 479944Smatt.horsnell@ARM.com IntRegIndex _op1, bool _wide) : 488591Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 493326Sktlim@umich.edu { 508229Snate@binkert.org numMicroops = machInst.fpscrLen + 1; 516658Snate@binkert.org assert(numMicroops > 1); 528887Sgeoffrey.blake@arm.com microOps = new StaticInstPtr[numMicroops]; 532907Sktlim@umich.edu for (unsigned i = 0; i < numMicroops; i++) { 542292SN/A VfpMicroMode mode = VfpMicroop; 558232Snate@binkert.org if (i == 0) 568232Snate@binkert.org mode = VfpFirstMicroop; 578232Snate@binkert.org else if (i == numMicroops - 1) 589527SMatt.Horsnell@arm.com mode = VfpLastMicroop; 592722Sktlim@umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 602669Sktlim@umich.edu nextIdxs(_dest, _op1); 612292SN/A } 622669Sktlim@umich.edu } 632678Sktlim@umich.edu 642678Sktlim@umich.edu %(BasicExecPanic)s 658581Ssteve.reinhardt@amd.com}; 668581Ssteve.reinhardt@amd.com 672292SN/Atemplate <class VfpOp> 682292SN/Astatic StaticInstPtr 692292SN/AdecodeVfpRegRegOp(ExtMachInst machInst, 702669Sktlim@umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 712292SN/A{ 722678Sktlim@umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 732292SN/A return new VfpOp(machInst, dest, op1); 749444SAndreas.Sandberg@ARM.com } else { 759444SAndreas.Sandberg@ARM.com return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 769444SAndreas.Sandberg@ARM.com } 774319Sktlim@umich.edu} 784319Sktlim@umich.edu 794319Sktlim@umich.edutemplate <class Micro> 804319Sktlim@umich.educlass VfpMacroRegImmOp : public VfpMacroOp 814319Sktlim@umich.edu{ 822678Sktlim@umich.edu public: 832678Sktlim@umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 842292SN/A bool _wide) : 852678Sktlim@umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 862678Sktlim@umich.edu { 875336Shines@cs.fsu.edu numMicroops = machInst.fpscrLen + 1; 882678Sktlim@umich.edu microOps = new StaticInstPtr[numMicroops]; 894873Sstever@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 902678Sktlim@umich.edu VfpMicroMode mode = VfpMicroop; 912292SN/A if (i == 0) 922678Sktlim@umich.edu mode = VfpFirstMicroop; 932678Sktlim@umich.edu else if (i == numMicroops - 1) 942678Sktlim@umich.edu mode = VfpLastMicroop; 952678Sktlim@umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 962678Sktlim@umich.edu nextIdxs(_dest); 972678Sktlim@umich.edu } 987852SMatt.Horsnell@arm.com } 997852SMatt.Horsnell@arm.com 1002344SN/A %(BasicExecPanic)s 1012678Sktlim@umich.edu}; 1022678Sktlim@umich.edu 1036974Stjones1@inf.ed.ac.uktemplate <class VfpOp> 1046974Stjones1@inf.ed.ac.ukstatic StaticInstPtr 1056974Stjones1@inf.ed.ac.ukdecodeVfpRegImmOp(ExtMachInst machInst, 1066974Stjones1@inf.ed.ac.uk IntRegIndex dest, uint64_t imm, bool wide) 1076974Stjones1@inf.ed.ac.uk{ 1086974Stjones1@inf.ed.ac.uk if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1096974Stjones1@inf.ed.ac.uk return new VfpOp(machInst, dest, imm); 1109444SAndreas.Sandberg@ARM.com } else { 1119444SAndreas.Sandberg@ARM.com return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1122820Sktlim@umich.edu } 1132678Sktlim@umich.edu} 1142678Sktlim@umich.edu 1156974Stjones1@inf.ed.ac.uktemplate <class Micro> 1166974Stjones1@inf.ed.ac.ukclass VfpMacroRegRegImmOp : public VfpMacroOp 1176974Stjones1@inf.ed.ac.uk{ 1186974Stjones1@inf.ed.ac.uk public: 1196974Stjones1@inf.ed.ac.uk VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1206974Stjones1@inf.ed.ac.uk IntRegIndex _op1, uint64_t _imm, bool _wide) : 1212678Sktlim@umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1222678Sktlim@umich.edu { 1232678Sktlim@umich.edu numMicroops = machInst.fpscrLen + 1; 1242678Sktlim@umich.edu microOps = new StaticInstPtr[numMicroops]; 1252678Sktlim@umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1262344SN/A VfpMicroMode mode = VfpMicroop; 1272307SN/A if (i == 0) 1286974Stjones1@inf.ed.ac.uk mode = VfpFirstMicroop; 1296974Stjones1@inf.ed.ac.uk else if (i == numMicroops - 1) 1306974Stjones1@inf.ed.ac.uk mode = VfpLastMicroop; 1316974Stjones1@inf.ed.ac.uk microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1322678Sktlim@umich.edu nextIdxs(_dest, _op1); 1334032Sktlim@umich.edu } 1342678Sktlim@umich.edu } 1352292SN/A 1362292SN/A %(BasicExecPanic)s 1372292SN/A}; 1382292SN/A 1398545Ssaidi@eecs.umich.edutemplate <class VfpOp> 1402678Sktlim@umich.edustatic StaticInstPtr 1418727Snilay@cs.wisc.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1422292SN/A IntRegIndex op1, uint64_t imm, bool wide) 1432292SN/A{ 1442292SN/A if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1452292SN/A return new VfpOp(machInst, dest, op1, imm); 1462292SN/A } else { 1475529Snate@binkert.org return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1485529Snate@binkert.org } 1495529Snate@binkert.org} 1502292SN/A 1514329Sktlim@umich.edutemplate <class Micro> 1524329Sktlim@umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1534329Sktlim@umich.edu{ 1544329Sktlim@umich.edu public: 1552292SN/A VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1562907Sktlim@umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1572907Sktlim@umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1582292SN/A { 1592292SN/A numMicroops = machInst.fpscrLen + 1; 1602329SN/A microOps = new StaticInstPtr[numMicroops]; 1612329SN/A for (unsigned i = 0; i < numMicroops; i++) { 1622329SN/A VfpMicroMode mode = VfpMicroop; 1632292SN/A if (i == 0) 1649936SFaissal.Sleiman@arm.com mode = VfpFirstMicroop; 1659936SFaissal.Sleiman@arm.com else if (i == numMicroops - 1) 1669936SFaissal.Sleiman@arm.com mode = VfpLastMicroop; 1679936SFaissal.Sleiman@arm.com microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1682292SN/A nextIdxs(_dest, _op1, _op2); 1692292SN/A } 1702292SN/A } 1718199SAli.Saidi@ARM.com 1728199SAli.Saidi@ARM.com %(BasicExecPanic)s 1739444SAndreas.Sandberg@ARM.com}; 1749444SAndreas.Sandberg@ARM.com 1759444SAndreas.Sandberg@ARM.comtemplate <class VfpOp> 1769444SAndreas.Sandberg@ARM.comstatic StaticInstPtr 1779444SAndreas.Sandberg@ARM.comdecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1789444SAndreas.Sandberg@ARM.com IntRegIndex op1, IntRegIndex op2, bool wide) 1799444SAndreas.Sandberg@ARM.com{ 1809444SAndreas.Sandberg@ARM.com if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1819444SAndreas.Sandberg@ARM.com return new VfpOp(machInst, dest, op1, op2); 1829444SAndreas.Sandberg@ARM.com } else { 1839444SAndreas.Sandberg@ARM.com return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1849444SAndreas.Sandberg@ARM.com } 1858199SAli.Saidi@ARM.com} 1862292SN/A}}; 1872292SN/A 1882292SN/Alet {{ 1892292SN/A 1902292SN/A header_output = "" 1912292SN/A decoder_output = "" 1923492Sktlim@umich.edu exec_output = "" 1932329SN/A 1942292SN/A vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1952292SN/A { "code": vmsrEnabledCheckCode + \ 1969444SAndreas.Sandberg@ARM.com "MiscDest = Op1;", 1979444SAndreas.Sandberg@ARM.com "predicate_test": predicateTest }, 1989444SAndreas.Sandberg@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 1999444SAndreas.Sandberg@ARM.com header_output += FpRegRegOpDeclare.subst(vmsrIop); 2009444SAndreas.Sandberg@ARM.com decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 2019814Sandreas.hansson@arm.com exec_output += PredOpExecute.subst(vmsrIop); 2022292SN/A 2032292SN/A vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2042292SN/A Fpscr = Op1 & ~FpCondCodesMask; 2052292SN/A FpCondCodes = Op1 & FpCondCodesMask; 2062292SN/A ''' 2072292SN/A vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2082292SN/A { "code": vmsrFpscrCode, 2092292SN/A "predicate_test": predicateTest }, []) 2102292SN/A header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2118247Snate@binkert.org decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2122292SN/A exec_output += PredOpExecute.subst(vmsrFpscrIop); 2132292SN/A 2142292SN/A vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2152292SN/A { "code": vmrsEnabledCheckCode + \ 2162292SN/A "Dest = MiscOp1;", 2172727Sktlim@umich.edu "predicate_test": predicateTest }, []) 2182727Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2192727Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2202727Sktlim@umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2212727Sktlim@umich.edu 2222727Sktlim@umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2232727Sktlim@umich.edu { "code": vmrsEnabledCheckCode + \ 2242727Sktlim@umich.edu "Dest = Fpscr | FpCondCodes;", 2252727Sktlim@umich.edu "predicate_test": predicateTest }, []) 2262727Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2272727Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2282727Sktlim@umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2292727Sktlim@umich.edu 2302727Sktlim@umich.edu vmrsApsrCode = vmrsEnabledCheckCode + ''' 2312727Sktlim@umich.edu Dest = (MiscOp1 & imm) | (Dest & ~imm); 2322727Sktlim@umich.edu ''' 2332727Sktlim@umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 2342727Sktlim@umich.edu { "code": vmrsApsrCode, 2352361SN/A "predicate_test": predicateTest }, []) 2362361SN/A header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 2372361SN/A decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 2382361SN/A exec_output += PredOpExecute.subst(vmrsApsrIop); 2392727Sktlim@umich.edu 2402727Sktlim@umich.edu vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' 2412727Sktlim@umich.edu assert((imm & ~FpCondCodesMask) == 0); 2422727Sktlim@umich.edu Dest = (FpCondCodes & imm) | (Dest & ~imm); 2432727Sktlim@umich.edu ''' 2442727Sktlim@umich.edu vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", 2452727Sktlim@umich.edu { "code": vmrsApsrFpscrCode, 2462727Sktlim@umich.edu "predicate_test": predicateTest }, []) 2472727Sktlim@umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); 2482727Sktlim@umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); 2492727Sktlim@umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2502727Sktlim@umich.edu 2512727Sktlim@umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2522727Sktlim@umich.edu FpDest.uw = bits(imm, 31, 0); 2532727Sktlim@umich.edu ''' 2542727Sktlim@umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2552727Sktlim@umich.edu { "code": vmovImmSCode, 2562727Sktlim@umich.edu "predicate_test": predicateTest }, []) 2572727Sktlim@umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2582727Sktlim@umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2592727Sktlim@umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2602727Sktlim@umich.edu 2612727Sktlim@umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2628922Swilliam.wang@arm.com FpDestP0.uw = bits(imm, 31, 0); 2634329Sktlim@umich.edu FpDestP1.uw = bits(imm, 63, 32); 2644329Sktlim@umich.edu ''' 2654329Sktlim@umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2664329Sktlim@umich.edu { "code": vmovImmDCode, 2674329Sktlim@umich.edu "predicate_test": predicateTest }, []) 2684329Sktlim@umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2692292SN/A decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2702292SN/A exec_output += PredOpExecute.subst(vmovImmDIop); 2712292SN/A 2722292SN/A vmovImmQCode = vfpEnabledCheckCode + ''' 2732292SN/A FpDestP0.uw = bits(imm, 31, 0); 2742292SN/A FpDestP1.uw = bits(imm, 63, 32); 2752292SN/A FpDestP2.uw = bits(imm, 31, 0); 2762292SN/A FpDestP3.uw = bits(imm, 63, 32); 2772292SN/A ''' 2782292SN/A vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2792292SN/A { "code": vmovImmQCode, 2802292SN/A "predicate_test": predicateTest }, []) 2812292SN/A header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2822292SN/A decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2839444SAndreas.Sandberg@ARM.com exec_output += PredOpExecute.subst(vmovImmQIop); 2842307SN/A 2859444SAndreas.Sandberg@ARM.com vmovRegSCode = vfpEnabledCheckCode + ''' 2862367SN/A FpDest.uw = FpOp1.uw; 2872307SN/A ''' 2882329SN/A vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 2899444SAndreas.Sandberg@ARM.com { "code": vmovRegSCode, 2902307SN/A "predicate_test": predicateTest }, []) 2912307SN/A header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 2922307SN/A decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 2932307SN/A exec_output += PredOpExecute.subst(vmovRegSIop); 2942307SN/A 2952307SN/A vmovRegDCode = vfpEnabledCheckCode + ''' 2969444SAndreas.Sandberg@ARM.com FpDestP0.uw = FpOp1P0.uw; 2972307SN/A FpDestP1.uw = FpOp1P1.uw; 2982307SN/A ''' 2992307SN/A vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3002307SN/A { "code": vmovRegDCode, 3012292SN/A "predicate_test": predicateTest }, []) 3022292SN/A header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3032329SN/A decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3042329SN/A exec_output += PredOpExecute.subst(vmovRegDIop); 3052292SN/A 3062329SN/A vmovRegQCode = vfpEnabledCheckCode + ''' 3072329SN/A FpDestP0.uw = FpOp1P0.uw; 3082292SN/A FpDestP1.uw = FpOp1P1.uw; 3092292SN/A FpDestP2.uw = FpOp1P2.uw; 3102292SN/A FpDestP3.uw = FpOp1P3.uw; 3112292SN/A ''' 3122292SN/A vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3132329SN/A { "code": vmovRegQCode, 3142292SN/A "predicate_test": predicateTest }, []) 3152292SN/A header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3169936SFaissal.Sleiman@arm.com decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3172292SN/A exec_output += PredOpExecute.subst(vmovRegQIop); 3182292SN/A 3192292SN/A vmovCoreRegBCode = vfpEnabledCheckCode + ''' 3202292SN/A FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub); 3212292SN/A ''' 3222292SN/A vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3232329SN/A { "code": vmovCoreRegBCode, 3242329SN/A "predicate_test": predicateTest }, []) 3252329SN/A header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3262292SN/A decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3272292SN/A exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3282292SN/A 3292292SN/A vmovCoreRegHCode = vfpEnabledCheckCode + ''' 3302292SN/A FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh); 3312329SN/A ''' 3322292SN/A vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3339936SFaissal.Sleiman@arm.com { "code": vmovCoreRegHCode, 3349936SFaissal.Sleiman@arm.com "predicate_test": predicateTest }, []) 3352292SN/A header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3362292SN/A decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3372292SN/A exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3382292SN/A 3392292SN/A vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3402292SN/A FpDest.uw = Op1.uw; 3412292SN/A ''' 3422292SN/A vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3432292SN/A { "code": vmovCoreRegWCode, 3442292SN/A "predicate_test": predicateTest }, []) 3452292SN/A header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3462292SN/A decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3472292SN/A exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3482292SN/A 3492292SN/A vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3502292SN/A assert(imm < 4); 3512292SN/A Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8); 3522292SN/A ''' 3532292SN/A vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3542292SN/A { "code": vmovRegCoreUBCode, 3552292SN/A "predicate_test": predicateTest }, []) 3562292SN/A header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3572292SN/A decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3582329SN/A exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3592329SN/A 3602292SN/A vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3617720Sgblack@eecs.umich.edu assert(imm < 2); 3627720Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16); 3632292SN/A ''' 3642292SN/A vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3652292SN/A { "code": vmovRegCoreUHCode, 3662292SN/A "predicate_test": predicateTest }, []) 3672292SN/A header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3682292SN/A decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3692292SN/A exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3702292SN/A 3712292SN/A vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 3722292SN/A assert(imm < 4); 3732292SN/A Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8)); 3742292SN/A ''' 3752292SN/A vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3762292SN/A { "code": vmovRegCoreSBCode, 3772292SN/A "predicate_test": predicateTest }, []) 3782292SN/A header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3792292SN/A decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3802292SN/A exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3812292SN/A 3822292SN/A vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 3832292SN/A assert(imm < 2); 3842292SN/A Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16)); 3852292SN/A ''' 3862292SN/A vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 3877720Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3887720Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3892292SN/A header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3902292SN/A decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3912292SN/A exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3922292SN/A 3932292SN/A vmovRegCoreWCode = vfpEnabledCheckCode + ''' 3942292SN/A Dest = FpOp1.uw; 3952292SN/A ''' 3962292SN/A vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 3972292SN/A { "code": vmovRegCoreWCode, 3982292SN/A "predicate_test": predicateTest }, []) 3992292SN/A header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4002292SN/A decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4012292SN/A exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4022292SN/A 4032292SN/A vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4042292SN/A FpDestP0.uw = Op1.uw; 4052292SN/A FpDestP1.uw = Op2.uw; 4062292SN/A ''' 4072292SN/A vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4082292SN/A { "code": vmov2Reg2CoreCode, 4092292SN/A "predicate_test": predicateTest }, []) 4102292SN/A header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4112292SN/A decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4122292SN/A exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4132292SN/A 4142292SN/A vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4152292SN/A Dest.uw = FpOp2P0.uw; 4162292SN/A Op1.uw = FpOp2P1.uw; 4172292SN/A ''' 4182292SN/A vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4192292SN/A { "code": vmov2Core2RegCode, 4202292SN/A "predicate_test": predicateTest }, []) 4212292SN/A header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4222292SN/A decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4232292SN/A exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4242292SN/A}}; 4252292SN/A 4262292SN/Alet {{ 4272292SN/A 4288545Ssaidi@eecs.umich.edu header_output = "" 4298545Ssaidi@eecs.umich.edu decoder_output = "" 4308545Ssaidi@eecs.umich.edu exec_output = "" 4318545Ssaidi@eecs.umich.edu 4328545Ssaidi@eecs.umich.edu singleCode = vfpEnabledCheckCode + ''' 4339383SAli.Saidi@ARM.com FPSCR fpscr = Fpscr | FpCondCodes; 4349383SAli.Saidi@ARM.com FpDest = %(op)s; 4359383SAli.Saidi@ARM.com FpCondCodes = fpscr & FpCondCodesMask; 4369383SAli.Saidi@ARM.com ''' 4379383SAli.Saidi@ARM.com singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4389383SAli.Saidi@ARM.com "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4399383SAli.Saidi@ARM.com singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4409383SAli.Saidi@ARM.com doubleCode = vfpEnabledCheckCode + ''' 4419383SAli.Saidi@ARM.com FPSCR fpscr = Fpscr | FpCondCodes; 4429383SAli.Saidi@ARM.com double dest = %(op)s; 4439383SAli.Saidi@ARM.com FpCondCodes = fpscr & FpCondCodesMask; 4449383SAli.Saidi@ARM.com FpDestP0.uw = dblLow(dest); 4458545Ssaidi@eecs.umich.edu FpDestP1.uw = dblHi(dest); 4468545Ssaidi@eecs.umich.edu ''' 4478545Ssaidi@eecs.umich.edu doubleBinOp = ''' 4488545Ssaidi@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 4498545Ssaidi@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 4508545Ssaidi@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 4518545Ssaidi@eecs.umich.edu ''' 4528545Ssaidi@eecs.umich.edu doubleUnaryOp = ''' 4538545Ssaidi@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, 4548545Ssaidi@eecs.umich.edu fpscr.fz, fpscr.rMode) 4559046SAli.Saidi@ARM.com ''' 4568545Ssaidi@eecs.umich.edu 4578545Ssaidi@eecs.umich.edu def buildBinFpOp(name, Name, base, singleOp, doubleOp): 4588545Ssaidi@eecs.umich.edu global header_output, decoder_output, exec_output 4598545Ssaidi@eecs.umich.edu 4608545Ssaidi@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4618545Ssaidi@eecs.umich.edu code = code % { "func": singleOp } 4628545Ssaidi@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4638545Ssaidi@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4648545Ssaidi@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4659046SAli.Saidi@ARM.com code = code % { "func": doubleOp } 4668545Ssaidi@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4678545Ssaidi@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4688545Ssaidi@eecs.umich.edu 4698545Ssaidi@eecs.umich.edu declareTempl = eval(base + "Declare"); 4708545Ssaidi@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4718545Ssaidi@eecs.umich.edu 4728545Ssaidi@eecs.umich.edu for iop in sIop, dIop: 4738545Ssaidi@eecs.umich.edu header_output += declareTempl.subst(iop) 4748545Ssaidi@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4759046SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(iop) 4768545Ssaidi@eecs.umich.edu 4778545Ssaidi@eecs.umich.edu buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "fpAddS", "fpAddD") 4788545Ssaidi@eecs.umich.edu buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "fpSubS", "fpSubD") 4798545Ssaidi@eecs.umich.edu buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "fpDivS", "fpDivD") 4808545Ssaidi@eecs.umich.edu buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "fpMulS", "fpMulD") 4818545Ssaidi@eecs.umich.edu 4828545Ssaidi@eecs.umich.edu def buildUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4838545Ssaidi@eecs.umich.edu if doubleOp is None: 4842292SN/A doubleOp = singleOp 4858199SAli.Saidi@ARM.com global header_output, decoder_output, exec_output 4868199SAli.Saidi@ARM.com 4878199SAli.Saidi@ARM.com code = singleCode % { "op": singleUnaryOp } 4888199SAli.Saidi@ARM.com code = code % { "func": singleOp } 4898199SAli.Saidi@ARM.com sIop = InstObjParams(name + "s", Name + "S", base, 4908199SAli.Saidi@ARM.com { "code": code, "predicate_test": predicateTest }, []) 4918199SAli.Saidi@ARM.com code = doubleCode % { "op": doubleUnaryOp } 4928199SAli.Saidi@ARM.com code = code % { "func": doubleOp } 4938199SAli.Saidi@ARM.com dIop = InstObjParams(name + "d", Name + "D", base, 4948199SAli.Saidi@ARM.com { "code": code, "predicate_test": predicateTest }, []) 4958199SAli.Saidi@ARM.com 4968199SAli.Saidi@ARM.com declareTempl = eval(base + "Declare"); 4979046SAli.Saidi@ARM.com constructorTempl = eval(base + "Constructor"); 4988199SAli.Saidi@ARM.com 4998199SAli.Saidi@ARM.com for iop in sIop, dIop: 5008199SAli.Saidi@ARM.com header_output += declareTempl.subst(iop) 5018199SAli.Saidi@ARM.com decoder_output += constructorTempl.subst(iop) 5028199SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(iop) 5038199SAli.Saidi@ARM.com 5048199SAli.Saidi@ARM.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "sqrtf", "sqrt") 5058199SAli.Saidi@ARM.com 5068272SAli.Saidi@ARM.com def buildSimpleUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 5078545Ssaidi@eecs.umich.edu if doubleOp is None: 5088545Ssaidi@eecs.umich.edu doubleOp = singleOp 5098545Ssaidi@eecs.umich.edu global header_output, decoder_output, exec_output 5108545Ssaidi@eecs.umich.edu 5119046SAli.Saidi@ARM.com sIop = InstObjParams(name + "s", Name + "S", base, 5128545Ssaidi@eecs.umich.edu { "code": singleCode % { "op": singleOp }, 5138545Ssaidi@eecs.umich.edu "predicate_test": predicateTest }, []) 5148545Ssaidi@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5158592Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 5168592Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5178545Ssaidi@eecs.umich.edu 5188199SAli.Saidi@ARM.com declareTempl = eval(base + "Declare"); 5198545Ssaidi@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5208199SAli.Saidi@ARM.com 5218591Sgblack@eecs.umich.edu for iop in sIop, dIop: 5228591Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5238591Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5248591Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5258545Ssaidi@eecs.umich.edu 5268545Ssaidi@eecs.umich.edu buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", 5278199SAli.Saidi@ARM.com "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") 5288545Ssaidi@eecs.umich.edu buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", 5298545Ssaidi@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") 5309046SAli.Saidi@ARM.com}}; 5318545Ssaidi@eecs.umich.edu 5328545Ssaidi@eecs.umich.edulet {{ 5338545Ssaidi@eecs.umich.edu 5348545Ssaidi@eecs.umich.edu header_output = "" 5358545Ssaidi@eecs.umich.edu decoder_output = "" 5368545Ssaidi@eecs.umich.edu exec_output = "" 5378545Ssaidi@eecs.umich.edu 5388545Ssaidi@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 5398545Ssaidi@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5408545Ssaidi@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5418592Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5428592Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 5438592Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5448545Ssaidi@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 5458545Ssaidi@eecs.umich.edu ''' 5468545Ssaidi@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5478545Ssaidi@eecs.umich.edu { "code": vmlaSCode, 5488591Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5498591Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5508591Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5518545Ssaidi@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5528199SAli.Saidi@ARM.com 5538199SAli.Saidi@ARM.com vmlaDCode = vfpEnabledCheckCode + ''' 5548199SAli.Saidi@ARM.com FPSCR fpscr = Fpscr | FpCondCodes; 5558199SAli.Saidi@ARM.com double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5568199SAli.Saidi@ARM.com dbl(FpOp2P0.uw, FpOp2P1.uw), 5578199SAli.Saidi@ARM.com fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5588199SAli.Saidi@ARM.com double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5598199SAli.Saidi@ARM.com mid, fpAddD, fpscr.fz, 5608199SAli.Saidi@ARM.com fpscr.dn, fpscr.rMode); 5618199SAli.Saidi@ARM.com FpCondCodes = fpscr & FpCondCodesMask; 5628199SAli.Saidi@ARM.com FpDestP0.uw = dblLow(dest); 5638199SAli.Saidi@ARM.com FpDestP1.uw = dblHi(dest); 5642292SN/A ''' 5652292SN/A vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 5664032Sktlim@umich.edu { "code": vmlaDCode, 5672292SN/A "predicate_test": predicateTest }, []) 5682292SN/A header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 5692292SN/A decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 5707720Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 5717944SGiacomo.Gabrielli@arm.com 5722292SN/A vmlsSCode = vfpEnabledCheckCode + ''' 5734032Sktlim@umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5744032Sktlim@umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5752669Sktlim@umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5762292SN/A FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 5777944SGiacomo.Gabrielli@arm.com fpscr.fz, fpscr.dn, fpscr.rMode); 5787944SGiacomo.Gabrielli@arm.com FpCondCodes = fpscr & FpCondCodesMask; 5797944SGiacomo.Gabrielli@arm.com ''' 5807944SGiacomo.Gabrielli@arm.com vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 5817597Sminkyu.jeong@arm.com { "code": vmlsSCode, 5827597Sminkyu.jeong@arm.com "predicate_test": predicateTest }, []) 5837597Sminkyu.jeong@arm.com header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 5842329SN/A decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 5852329SN/A exec_output += PredOpExecute.subst(vmlsSIop); 5862367SN/A 5872367SN/A vmlsDCode = vfpEnabledCheckCode + ''' 5887848SAli.Saidi@ARM.com FPSCR fpscr = Fpscr | FpCondCodes; 5897848SAli.Saidi@ARM.com double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5907600Sminkyu.jeong@arm.com dbl(FpOp2P0.uw, FpOp2P1.uw), 5917600Sminkyu.jeong@arm.com fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5927600Sminkyu.jeong@arm.com double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5934032Sktlim@umich.edu -mid, fpAddD, fpscr.fz, 5943731Sktlim@umich.edu fpscr.dn, fpscr.rMode); 5952367SN/A FpCondCodes = fpscr & FpCondCodesMask; 5962367SN/A FpDestP0.uw = dblLow(dest); 5972292SN/A FpDestP1.uw = dblHi(dest); 5982292SN/A ''' 5994032Sktlim@umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 6009046SAli.Saidi@ARM.com { "code": vmlsDCode, 6014032Sktlim@umich.edu "predicate_test": predicateTest }, []) 6024032Sktlim@umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 6034032Sktlim@umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 6048199SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(vmlsDIop); 6058199SAli.Saidi@ARM.com 6062292SN/A vnmlaSCode = vfpEnabledCheckCode + ''' 6072292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 6082292SN/A float mid = binaryOp(fpscr, FpOp1, FpOp2, 6092292SN/A fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6102292SN/A FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 6112292SN/A fpscr.fz, fpscr.dn, fpscr.rMode); 6122292SN/A FpCondCodes = fpscr & FpCondCodesMask; 6132292SN/A ''' 6142292SN/A vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 6152292SN/A { "code": vnmlaSCode, 6162292SN/A "predicate_test": predicateTest }, []) 6172292SN/A header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 6182292SN/A decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 6192292SN/A exec_output += PredOpExecute.subst(vnmlaSIop); 6202292SN/A 6217720Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 6227720Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6232292SN/A double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6244032Sktlim@umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6254032Sktlim@umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6262292SN/A double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6272292SN/A -mid, fpAddD, fpscr.fz, 6282292SN/A fpscr.dn, fpscr.rMode); 6292292SN/A FpCondCodes = fpscr & FpCondCodesMask; 6302292SN/A FpDestP0.uw = dblLow(dest); 6312292SN/A FpDestP1.uw = dblHi(dest); 6327944SGiacomo.Gabrielli@arm.com ''' 6337944SGiacomo.Gabrielli@arm.com vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 6347944SGiacomo.Gabrielli@arm.com { "code": vnmlaDCode, 6357944SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest }, []) 6367848SAli.Saidi@ARM.com header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 6377848SAli.Saidi@ARM.com decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 6387848SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(vnmlaDIop); 6392329SN/A 6407782Sminkyu.jeong@arm.com vnmlsSCode = vfpEnabledCheckCode + ''' 6417720Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6422292SN/A float mid = binaryOp(fpscr, FpOp1, FpOp2, 6432292SN/A fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6447782Sminkyu.jeong@arm.com FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 6457782Sminkyu.jeong@arm.com fpscr.fz, fpscr.dn, fpscr.rMode); 6467782Sminkyu.jeong@arm.com FpCondCodes = fpscr & FpCondCodesMask; 6477782Sminkyu.jeong@arm.com ''' 6482292SN/A vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 6492292SN/A { "code": vnmlsSCode, 6502292SN/A "predicate_test": predicateTest }, []) 6512292SN/A header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 6522336SN/A decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 6532336SN/A exec_output += PredOpExecute.subst(vnmlsSIop); 6542336SN/A 6552329SN/A vnmlsDCode = vfpEnabledCheckCode + ''' 6562292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 6572329SN/A double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6582292SN/A dbl(FpOp2P0.uw, FpOp2P1.uw), 6592292SN/A fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6608199SAli.Saidi@ARM.com double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6612292SN/A mid, fpAddD, fpscr.fz, 6622292SN/A fpscr.dn, fpscr.rMode); 6632292SN/A FpCondCodes = fpscr & FpCondCodesMask; 6642292SN/A FpDestP0.uw = dblLow(dest); 6652292SN/A FpDestP1.uw = dblHi(dest); 6662292SN/A ''' 6672292SN/A vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 6682292SN/A { "code": vnmlsDCode, 6692292SN/A "predicate_test": predicateTest }, []) 6707720Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 6717720Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 6722292SN/A exec_output += PredOpExecute.subst(vnmlsDIop); 6732292SN/A 6742292SN/A vnmulSCode = vfpEnabledCheckCode + ''' 6752292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 6762292SN/A FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 6772292SN/A fpscr.fz, fpscr.dn, fpscr.rMode); 6782292SN/A FpCondCodes = fpscr & FpCondCodesMask; 6792292SN/A ''' 6802292SN/A vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 6812292SN/A { "code": vnmulSCode, 6822292SN/A "predicate_test": predicateTest }, []) 6832292SN/A header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 6842292SN/A decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 6852292SN/A exec_output += PredOpExecute.subst(vnmulSIop); 6862292SN/A 6872292SN/A vnmulDCode = vfpEnabledCheckCode + ''' 6882292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 6892292SN/A double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6902292SN/A dbl(FpOp2P0.uw, FpOp2P1.uw), 6912292SN/A fpMulD, fpscr.fz, fpscr.dn, 6922292SN/A fpscr.rMode); 6932292SN/A FpCondCodes = fpscr & FpCondCodesMask; 6942292SN/A FpDestP0.uw = dblLow(dest); 6952292SN/A FpDestP1.uw = dblHi(dest); 6962292SN/A ''' 6972292SN/A vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 6982292SN/A { "code": vnmulDCode, 6992292SN/A "predicate_test": predicateTest }, []) 7002292SN/A header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 7012329SN/A decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 7022329SN/A exec_output += PredOpExecute.subst(vnmulDIop); 7032292SN/A}}; 7042292SN/A 7052292SN/Alet {{ 7062292SN/A 7072292SN/A header_output = "" 7087720Sgblack@eecs.umich.edu decoder_output = "" 7097720Sgblack@eecs.umich.edu exec_output = "" 7102292SN/A 7112292SN/A vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 7122292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 7132292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 7142292SN/A __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 7152292SN/A FpDest = FpOp1.uw; 7162292SN/A __asm__ __volatile__("" :: "m" (FpDest)); 7172292SN/A finishVfp(fpscr, state, fpscr.fz); 7182292SN/A FpCondCodes = fpscr & FpCondCodesMask; 7192292SN/A ''' 7202292SN/A vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 7212292SN/A { "code": vcvtUIntFpSCode, 7222292SN/A "predicate_test": predicateTest }, []) 7236974Stjones1@inf.ed.ac.uk header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 7246974Stjones1@inf.ed.ac.uk decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 7256974Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 7266974Stjones1@inf.ed.ac.uk 7276974Stjones1@inf.ed.ac.uk vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 7286974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 7296974Stjones1@inf.ed.ac.uk VfpSavedState state = prepFpState(fpscr.rMode); 7306974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 7316974Stjones1@inf.ed.ac.uk double cDest = (uint64_t)FpOp1P0.uw; 7326974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" :: "m" (cDest)); 7336974Stjones1@inf.ed.ac.uk finishVfp(fpscr, state, fpscr.fz); 7346974Stjones1@inf.ed.ac.uk FpCondCodes = fpscr & FpCondCodesMask; 7356974Stjones1@inf.ed.ac.uk FpDestP0.uw = dblLow(cDest); 7366974Stjones1@inf.ed.ac.uk FpDestP1.uw = dblHi(cDest); 7376974Stjones1@inf.ed.ac.uk ''' 7386974Stjones1@inf.ed.ac.uk vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 7392292SN/A { "code": vcvtUIntFpDCode, 7402292SN/A "predicate_test": predicateTest }, []) 7416974Stjones1@inf.ed.ac.uk header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 7426974Stjones1@inf.ed.ac.uk decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 7436974Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 7446974Stjones1@inf.ed.ac.uk 7456974Stjones1@inf.ed.ac.uk vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 7466974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 7472292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 7482292SN/A __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 7492292SN/A FpDest = FpOp1.sw; 7502292SN/A __asm__ __volatile__("" :: "m" (FpDest)); 7518727Snilay@cs.wisc.edu finishVfp(fpscr, state, fpscr.fz); 7522292SN/A FpCondCodes = fpscr & FpCondCodesMask; 7532292SN/A ''' 7542907Sktlim@umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 7552678Sktlim@umich.edu { "code": vcvtSIntFpSCode, 7562678Sktlim@umich.edu "predicate_test": predicateTest }, []) 7572678Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 7582678Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 7592678Sktlim@umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 7602329SN/A 7612329SN/A vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 7622292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 7632292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 7642292SN/A __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 7652292SN/A double cDest = FpOp1P0.sw; 7662292SN/A __asm__ __volatile__("" :: "m" (cDest)); 7672292SN/A finishVfp(fpscr, state, fpscr.fz); 7682292SN/A FpCondCodes = fpscr & FpCondCodesMask; 7692678Sktlim@umich.edu FpDestP0.uw = dblLow(cDest); 7702292SN/A FpDestP1.uw = dblHi(cDest); 7712292SN/A ''' 7722292SN/A vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 7732292SN/A { "code": vcvtSIntFpDCode, 7742292SN/A "predicate_test": predicateTest }, []) 7752292SN/A header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 7762292SN/A decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 7772292SN/A exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 7782292SN/A 7792292SN/A vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 7802292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 7816974Stjones1@inf.ed.ac.uk VfpSavedState state = prepFpState(fpscr.rMode); 7826974Stjones1@inf.ed.ac.uk vfpFlushToZero(fpscr, FpOp1); 7836974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7846974Stjones1@inf.ed.ac.uk FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 7856974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" :: "m" (FpDest.uw)); 7862669Sktlim@umich.edu finishVfp(fpscr, state, fpscr.fz); 7872669Sktlim@umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7882669Sktlim@umich.edu ''' 7898481Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 7908481Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 7918481Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7922292SN/A header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 7932292SN/A decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 7942669Sktlim@umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 7952669Sktlim@umich.edu 7963772Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 7974326Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7982669Sktlim@umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 7994878Sstever@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8004878Sstever@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8016102Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8026974Stjones1@inf.ed.ac.uk uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 8036974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" :: "m" (result)); 8042292SN/A finishVfp(fpscr, state, fpscr.fz); 8052678Sktlim@umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8062678Sktlim@umich.edu FpDestP0.uw = result; 8072678Sktlim@umich.edu ''' 8082678Sktlim@umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 8096974Stjones1@inf.ed.ac.uk { "code": vcvtFpUIntDRCode, 8106974Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 8116974Stjones1@inf.ed.ac.uk header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 8126974Stjones1@inf.ed.ac.uk decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 8138949Sandreas.hansson@arm.com exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 8146974Stjones1@inf.ed.ac.uk 8156974Stjones1@inf.ed.ac.uk vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 8166974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 8176974Stjones1@inf.ed.ac.uk VfpSavedState state = prepFpState(fpscr.rMode); 8188949Sandreas.hansson@arm.com vfpFlushToZero(fpscr, FpOp1); 8198949Sandreas.hansson@arm.com __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8206974Stjones1@inf.ed.ac.uk FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 8216974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" :: "m" (FpDest.sw)); 8226974Stjones1@inf.ed.ac.uk finishVfp(fpscr, state, fpscr.fz); 8236974Stjones1@inf.ed.ac.uk FpCondCodes = fpscr & FpCondCodesMask; 8246974Stjones1@inf.ed.ac.uk ''' 8256974Stjones1@inf.ed.ac.uk vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 8266974Stjones1@inf.ed.ac.uk { "code": vcvtFpSIntSRCode, 8276974Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 8286974Stjones1@inf.ed.ac.uk header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 8296974Stjones1@inf.ed.ac.uk decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 8306974Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 8316974Stjones1@inf.ed.ac.uk 8326974Stjones1@inf.ed.ac.uk vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 8336974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 8342678Sktlim@umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8357720Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8362292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 8377720Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8383797Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 8393221Sktlim@umich.edu __asm__ __volatile__("" :: "m" (result)); 8402292SN/A finishVfp(fpscr, state, fpscr.fz); 8412693Sktlim@umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8424350Sgblack@eecs.umich.edu FpDestP0.uw = result; 8436974Stjones1@inf.ed.ac.uk ''' 8443326Sktlim@umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 8453326Sktlim@umich.edu { "code": vcvtFpSIntDRCode, 8463326Sktlim@umich.edu "predicate_test": predicateTest }, []) 8479046SAli.Saidi@ARM.com header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 8483326Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 8499046SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 8503326Sktlim@umich.edu 8513326Sktlim@umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 8523326Sktlim@umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8533326Sktlim@umich.edu vfpFlushToZero(fpscr, FpOp1); 8543326Sktlim@umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8553326Sktlim@umich.edu fesetround(FeRoundZero); 8563326Sktlim@umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8577823Ssteve.reinhardt@amd.com FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 8588887Sgeoffrey.blake@arm.com __asm__ __volatile__("" :: "m" (FpDest.uw)); 8598887Sgeoffrey.blake@arm.com finishVfp(fpscr, state, fpscr.fz); 8608887Sgeoffrey.blake@arm.com FpCondCodes = fpscr & FpCondCodesMask; 8618887Sgeoffrey.blake@arm.com ''' 8628887Sgeoffrey.blake@arm.com vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 8638887Sgeoffrey.blake@arm.com { "code": vcvtFpUIntSCode, 8643326Sktlim@umich.edu "predicate_test": predicateTest }, []) 8653326Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 8663326Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 8672693Sktlim@umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 8682693Sktlim@umich.edu 8692693Sktlim@umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 8702693Sktlim@umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8712693Sktlim@umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8722693Sktlim@umich.edu vfpFlushToZero(fpscr, cOp1); 8738481Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8748481Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8758481Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8768481Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 8778481Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8788481Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8798481Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8808481Sgblack@eecs.umich.edu FpDestP0.uw = result; 8818481Sgblack@eecs.umich.edu ''' 8828481Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 8838481Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 8848481Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8858481Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 8868481Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 8878481Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 8888481Sgblack@eecs.umich.edu 8898481Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 8908481Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8918481Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8928481Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8938481Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8944032Sktlim@umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8953221Sktlim@umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 8963221Sktlim@umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 8976974Stjones1@inf.ed.ac.uk finishVfp(fpscr, state, fpscr.fz); 8986974Stjones1@inf.ed.ac.uk FpCondCodes = fpscr & FpCondCodesMask; 8998481Sgblack@eecs.umich.edu ''' 9006974Stjones1@inf.ed.ac.uk vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 9016974Stjones1@inf.ed.ac.uk { "code": vcvtFpSIntSCode, 9026974Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 9032669Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 9046974Stjones1@inf.ed.ac.uk decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 9056974Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 9068481Sgblack@eecs.umich.edu 9076974Stjones1@inf.ed.ac.uk vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 9086974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 9096974Stjones1@inf.ed.ac.uk double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9106974Stjones1@inf.ed.ac.uk vfpFlushToZero(fpscr, cOp1); 9116974Stjones1@inf.ed.ac.uk VfpSavedState state = prepFpState(fpscr.rMode); 9126974Stjones1@inf.ed.ac.uk fesetround(FeRoundZero); 9136974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9146974Stjones1@inf.ed.ac.uk int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 9156974Stjones1@inf.ed.ac.uk __asm__ __volatile__("" :: "m" (result)); 9166974Stjones1@inf.ed.ac.uk finishVfp(fpscr, state, fpscr.fz); 9176974Stjones1@inf.ed.ac.uk FpCondCodes = fpscr & FpCondCodesMask; 9186974Stjones1@inf.ed.ac.uk FpDestP0.uw = result; 9196974Stjones1@inf.ed.ac.uk ''' 9206974Stjones1@inf.ed.ac.uk vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 9216974Stjones1@inf.ed.ac.uk { "code": vcvtFpSIntDCode, 9226974Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 9236974Stjones1@inf.ed.ac.uk header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 9246974Stjones1@inf.ed.ac.uk decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 9256974Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 9266974Stjones1@inf.ed.ac.uk 9276974Stjones1@inf.ed.ac.uk vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 9286974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 9296974Stjones1@inf.ed.ac.uk vfpFlushToZero(fpscr, FpOp1); 9306974Stjones1@inf.ed.ac.uk VfpSavedState state = prepFpState(fpscr.rMode); 9312292SN/A __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9322292SN/A double cDest = fixFpSFpDDest(Fpscr, FpOp1); 9332292SN/A __asm__ __volatile__("" :: "m" (cDest)); 9342292SN/A finishVfp(fpscr, state, fpscr.fz); 9352292SN/A FpCondCodes = fpscr & FpCondCodesMask; 9362292SN/A FpDestP0.uw = dblLow(cDest); 9372292SN/A FpDestP1.uw = dblHi(cDest); 9382292SN/A ''' 9392292SN/A vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 9402292SN/A { "code": vcvtFpSFpDCode, 9412292SN/A "predicate_test": predicateTest }, []) 9422292SN/A header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 9432292SN/A decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 9442292SN/A exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 9452292SN/A 9462292SN/A vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 9472292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 9482292SN/A double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9492292SN/A vfpFlushToZero(fpscr, cOp1); 9502292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 9512292SN/A __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9522292SN/A FpDest = fixFpDFpSDest(Fpscr, cOp1); 9532292SN/A __asm__ __volatile__("" :: "m" (FpDest)); 9542292SN/A finishVfp(fpscr, state, fpscr.fz); 9552292SN/A FpCondCodes = fpscr & FpCondCodesMask; 9562292SN/A ''' 9572292SN/A vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 9582292SN/A { "code": vcvtFpDFpSCode, 9592329SN/A "predicate_test": predicateTest }, []) 9602292SN/A header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 9612292SN/A decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 9622292SN/A exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 9632292SN/A 9642292SN/A vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 9657720Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9662292SN/A vfpFlushToZero(fpscr, FpOp1); 9677720Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9682292SN/A __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9692292SN/A FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9702292SN/A bits(fpToBits(FpOp1), 31, 16)); 9712292SN/A __asm__ __volatile__("" :: "m" (FpDest)); 9722292SN/A finishVfp(fpscr, state, fpscr.fz); 9732292SN/A FpCondCodes = fpscr & FpCondCodesMask; 9742292SN/A ''' 9752292SN/A vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 9762329SN/A { "code": vcvtFpHTFpSCode, 9772731Sktlim@umich.edu "predicate_test": predicateTest }, []) 9782292SN/A header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 9792292SN/A decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 9802292SN/A exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 9812292SN/A 9822292SN/A vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 9832292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 9842292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 9852727Sktlim@umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9862292SN/A FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9872292SN/A bits(fpToBits(FpOp1), 15, 0)); 9882292SN/A __asm__ __volatile__("" :: "m" (FpDest)); 9892292SN/A finishVfp(fpscr, state, fpscr.fz); 9902292SN/A FpCondCodes = fpscr & FpCondCodesMask; 9912292SN/A ''' 9922292SN/A vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 9932292SN/A { "code": vcvtFpHBFpSCode, 9942292SN/A "predicate_test": predicateTest }, []) 9952292SN/A header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 9964032Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 9974032Sktlim@umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 9984032Sktlim@umich.edu 9994032Sktlim@umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 10002292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 10012292SN/A vfpFlushToZero(fpscr, FpOp1); 10022292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 10032292SN/A __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10042292SN/A : "m" (FpOp1), "m" (FpDest.uw)); 10052329SN/A FpDest.uw = insertBits(FpDest.uw, 31, 16,, 10062292SN/A vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10072292SN/A fpscr.rMode, fpscr.ahp, FpOp1)); 10082292SN/A __asm__ __volatile__("" :: "m" (FpDest.uw)); 10092292SN/A finishVfp(fpscr, state, fpscr.fz); 10107720Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10112292SN/A ''' 10127720Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 10132292SN/A { "code": vcvtFpHTFpSCode, 10142292SN/A "predicate_test": predicateTest }, []) 10152329SN/A header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 10162329SN/A decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 10172292SN/A exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 10182292SN/A 10192292SN/A vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 10202292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 10212292SN/A vfpFlushToZero(fpscr, FpOp1); 10222292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 10232292SN/A __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10242329SN/A : "m" (FpOp1), "m" (FpDest.uw)); 10252731Sktlim@umich.edu FpDest.uw = insertBits(FpDest.uw, 15, 0, 10262292SN/A vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10272292SN/A fpscr.rMode, fpscr.ahp, FpOp1)); 10282292SN/A __asm__ __volatile__("" :: "m" (FpDest.uw)); 10294032Sktlim@umich.edu finishVfp(fpscr, state, fpscr.fz); 10304032Sktlim@umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10314032Sktlim@umich.edu ''' 10324032Sktlim@umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 10336974Stjones1@inf.ed.ac.uk { "code": vcvtFpSFpHBCode, 10346974Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 10356974Stjones1@inf.ed.ac.uk header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 10366974Stjones1@inf.ed.ac.uk decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 10376974Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 10386974Stjones1@inf.ed.ac.uk 10396974Stjones1@inf.ed.ac.uk vcmpSCode = vfpEnabledCheckCode + ''' 10404032Sktlim@umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10412292SN/A vfpFlushToZero(fpscr, FpDest, FpOp1); 10422292SN/A if (FpDest == FpOp1) { 10432292SN/A fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10442292SN/A } else if (FpDest < FpOp1) { 10452292SN/A fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10462292SN/A } else if (FpDest > FpOp1) { 10472292SN/A fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10482727Sktlim@umich.edu } else { 10492292SN/A const uint32_t qnan = 0x7fc00000; 10502292SN/A const bool nan1 = std::isnan(FpDest); 10512292SN/A const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 10522292SN/A const bool nan2 = std::isnan(FpOp1); 10532292SN/A const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 10543349Sbinkertn@umich.edu if (signal1 || signal2) 10552693Sktlim@umich.edu fpscr.ioc = 1; 10562693Sktlim@umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10572693Sktlim@umich.edu } 10582693Sktlim@umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10592693Sktlim@umich.edu ''' 10602693Sktlim@umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 10612693Sktlim@umich.edu { "code": vcmpSCode, 10622693Sktlim@umich.edu "predicate_test": predicateTest }, []) 10632693Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 10642693Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 10652693Sktlim@umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 10662693Sktlim@umich.edu 10672693Sktlim@umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 10682693Sktlim@umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 10692693Sktlim@umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 10702693Sktlim@umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10718887Sgeoffrey.blake@arm.com vfpFlushToZero(fpscr, cDest, cOp1); 10722693Sktlim@umich.edu if (cDest == cOp1) { 10732732Sktlim@umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10742693Sktlim@umich.edu } else if (cDest < cOp1) { 10752693Sktlim@umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10762693Sktlim@umich.edu } else if (cDest > cOp1) { 10778727Snilay@cs.wisc.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10788727Snilay@cs.wisc.edu } else { 10798727Snilay@cs.wisc.edu const uint64_t qnan = ULL(0x7ff8000000000000); 10808727Snilay@cs.wisc.edu const bool nan1 = std::isnan(cDest); 10812693Sktlim@umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 10822693Sktlim@umich.edu const bool nan2 = std::isnan(cOp1); 10832693Sktlim@umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 10842693Sktlim@umich.edu if (signal1 || signal2) 10852693Sktlim@umich.edu fpscr.ioc = 1; 10862678Sktlim@umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10872678Sktlim@umich.edu } 10882678Sktlim@umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10892678Sktlim@umich.edu ''' 10902678Sktlim@umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 10912678Sktlim@umich.edu { "code": vcmpDCode, 10922927Sktlim@umich.edu "predicate_test": predicateTest }, []) 10932678Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 10942727Sktlim@umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 10952678Sktlim@umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 10962678Sktlim@umich.edu 10972678Sktlim@umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 10982678Sktlim@umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10992678Sktlim@umich.edu vfpFlushToZero(fpscr, FpDest); 11002678Sktlim@umich.edu // This only handles imm == 0 for now. 11012678Sktlim@umich.edu assert(imm == 0); 11022678Sktlim@umich.edu if (FpDest == imm) { 11032678Sktlim@umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11042678Sktlim@umich.edu } else if (FpDest < imm) { 11052678Sktlim@umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11062678Sktlim@umich.edu } else if (FpDest > imm) { 11072678Sktlim@umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11082678Sktlim@umich.edu } else { 11097598Sminkyu.jeong@arm.com const uint32_t qnan = 0x7fc00000; 11107598Sminkyu.jeong@arm.com const bool nan = std::isnan(FpDest); 11117598Sminkyu.jeong@arm.com const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 11122678Sktlim@umich.edu if (signal) 11132678Sktlim@umich.edu fpscr.ioc = 1; 11142678Sktlim@umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11152678Sktlim@umich.edu } 11162292SN/A FpCondCodes = fpscr & FpCondCodesMask; 11172292SN/A ''' 11182292SN/A vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 11192292SN/A { "code": vcmpZeroSCode, 11202292SN/A "predicate_test": predicateTest }, []) 11212292SN/A header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 11222292SN/A decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 11232292SN/A exec_output += PredOpExecute.subst(vcmpZeroSIop); 11243126Sktlim@umich.edu 11252292SN/A vcmpZeroDCode = vfpEnabledCheckCode + ''' 11262292SN/A // This only handles imm == 0 for now. 11272292SN/A assert(imm == 0); 11282292SN/A double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11292292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 11302292SN/A vfpFlushToZero(fpscr, cDest); 11312292SN/A if (cDest == imm) { 11322292SN/A fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11332292SN/A } else if (cDest < imm) { 11342292SN/A fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11352292SN/A } else if (cDest > imm) { 11362292SN/A fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11372292SN/A } else { 11382329SN/A const uint64_t qnan = ULL(0x7ff8000000000000); 11392329SN/A const bool nan = std::isnan(cDest); 11402329SN/A const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 11412292SN/A if (signal) 11429527SMatt.Horsnell@arm.com fpscr.ioc = 1; 11439527SMatt.Horsnell@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11449527SMatt.Horsnell@arm.com } 11459527SMatt.Horsnell@arm.com FpCondCodes = fpscr & FpCondCodesMask; 11469527SMatt.Horsnell@arm.com ''' 11479527SMatt.Horsnell@arm.com vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 11489527SMatt.Horsnell@arm.com { "code": vcmpZeroDCode, 11492292SN/A "predicate_test": predicateTest }, []) 11502292SN/A header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 11512292SN/A decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 11522292SN/A exec_output += PredOpExecute.subst(vcmpZeroDIop); 11532292SN/A 11542292SN/A vcmpeSCode = vfpEnabledCheckCode + ''' 11552292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 11562292SN/A vfpFlushToZero(fpscr, FpDest, FpOp1); 11572292SN/A if (FpDest == FpOp1) { 11582316SN/A fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11592316SN/A } else if (FpDest < FpOp1) { 11602329SN/A fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11618727Snilay@cs.wisc.edu } else if (FpDest > FpOp1) { 11628727Snilay@cs.wisc.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11638727Snilay@cs.wisc.edu } else { 11648727Snilay@cs.wisc.edu fpscr.ioc = 1; 11652329SN/A fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11662329SN/A } 11672329SN/A FpCondCodes = fpscr & FpCondCodesMask; 11682316SN/A ''' 11692732Sktlim@umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 11702316SN/A { "code": vcmpeSCode, 11712292SN/A "predicate_test": predicateTest }, []) 11722292SN/A header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 11732292SN/A decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 11746974Stjones1@inf.ed.ac.uk exec_output += PredOpExecute.subst(vcmpeSIop); 11756974Stjones1@inf.ed.ac.uk 11766974Stjones1@inf.ed.ac.uk vcmpeDCode = vfpEnabledCheckCode + ''' 11778975Sandreas.hansson@arm.com double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 11786974Stjones1@inf.ed.ac.uk double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11796974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 11806974Stjones1@inf.ed.ac.uk vfpFlushToZero(fpscr, cDest, cOp1); 11816974Stjones1@inf.ed.ac.uk if (cDest == cOp1) { 11826974Stjones1@inf.ed.ac.uk fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11836974Stjones1@inf.ed.ac.uk } else if (cDest < cOp1) { 11846974Stjones1@inf.ed.ac.uk fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11856974Stjones1@inf.ed.ac.uk } else if (cDest > cOp1) { 11866974Stjones1@inf.ed.ac.uk fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11876974Stjones1@inf.ed.ac.uk } else { 11886974Stjones1@inf.ed.ac.uk fpscr.ioc = 1; 11896974Stjones1@inf.ed.ac.uk fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11902693Sktlim@umich.edu } 11912693Sktlim@umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11922693Sktlim@umich.edu ''' 11932698Sktlim@umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 11944985Sktlim@umich.edu { "code": vcmpeDCode, 11952698Sktlim@umich.edu "predicate_test": predicateTest }, []) 11962693Sktlim@umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 11978587Snilay@cs.wisc.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 11988587Snilay@cs.wisc.edu exec_output += PredOpExecute.subst(vcmpeDIop); 11998587Snilay@cs.wisc.edu 12008975Sandreas.hansson@arm.com vcmpeZeroSCode = vfpEnabledCheckCode + ''' 12016974Stjones1@inf.ed.ac.uk FPSCR fpscr = Fpscr | FpCondCodes; 12028133SAli.Saidi@ARM.com vfpFlushToZero(fpscr, FpDest); 12038133SAli.Saidi@ARM.com if (FpDest == imm) { 12048133SAli.Saidi@ARM.com fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12056974Stjones1@inf.ed.ac.uk } else if (FpDest < imm) { 12066974Stjones1@inf.ed.ac.uk fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12072699Sktlim@umich.edu } else if (FpDest > imm) { 12082693Sktlim@umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12096221Snate@binkert.org } else { 12106974Stjones1@inf.ed.ac.uk fpscr.ioc = 1; 12116974Stjones1@inf.ed.ac.uk fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12126974Stjones1@inf.ed.ac.uk } 12136974Stjones1@inf.ed.ac.uk FpCondCodes = fpscr & FpCondCodesMask; 12146974Stjones1@inf.ed.ac.uk ''' 12156974Stjones1@inf.ed.ac.uk vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 12166974Stjones1@inf.ed.ac.uk { "code": vcmpeZeroSCode, 12176974Stjones1@inf.ed.ac.uk "predicate_test": predicateTest }, []) 12182693Sktlim@umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 12192693Sktlim@umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 12202727Sktlim@umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 12212907Sktlim@umich.edu 12222693Sktlim@umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 12232693Sktlim@umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 12242693Sktlim@umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12252693Sktlim@umich.edu vfpFlushToZero(fpscr, cDest); 12262693Sktlim@umich.edu if (cDest == imm) { 12272693Sktlim@umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12282693Sktlim@umich.edu } else if (cDest < imm) { 12292693Sktlim@umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12302693Sktlim@umich.edu } else if (cDest > imm) { 12312693Sktlim@umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12322292SN/A } else { 12339440SAndreas.Sandberg@ARM.com fpscr.ioc = 1; 12342292SN/A fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12352292SN/A } 12362292SN/A FpCondCodes = fpscr & FpCondCodesMask; 12372292SN/A ''' 12382292SN/A vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 12392292SN/A { "code": vcmpeZeroDCode, 12402292SN/A "predicate_test": predicateTest }, []) 12419440SAndreas.Sandberg@ARM.com header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 12422292SN/A decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 12432292SN/A exec_output += PredOpExecute.subst(vcmpeZeroDIop); 12442292SN/A}}; 12452292SN/A 12462292SN/Alet {{ 12472292SN/A 12482292SN/A header_output = "" 12499440SAndreas.Sandberg@ARM.com decoder_output = "" 12502292SN/A exec_output = "" 12512292SN/A 12522292SN/A vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 12532292SN/A FPSCR fpscr = Fpscr | FpCondCodes; 12542292SN/A vfpFlushToZero(fpscr, FpOp1); 12552292SN/A VfpSavedState state = prepFpState(fpscr.rMode); 12562292SN/A __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12579440SAndreas.Sandberg@ARM.com FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 12582292SN/A __asm__ __volatile__("" :: "m" (FpDest.sw)); 12592292SN/A finishVfp(fpscr, state, fpscr.fz); 12602292SN/A FpCondCodes = fpscr & FpCondCodesMask; 12612292SN/A ''' 12622329SN/A vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 12632329SN/A { "code": vcvtFpSFixedSCode, 12642329SN/A "predicate_test": predicateTest }, []) 12659440SAndreas.Sandberg@ARM.com header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 12662329SN/A decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 12672329SN/A exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 12682329SN/A 12692329SN/A vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 12702329SN/A FPSCR fpscr = Fpscr | FpCondCodes; 12712329SN/A double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12722329SN/A vfpFlushToZero(fpscr, cOp1); 12732329SN/A VfpSavedState state = prepFpState(fpscr.rMode); 12749440SAndreas.Sandberg@ARM.com __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 12759440SAndreas.Sandberg@ARM.com uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 12762329SN/A __asm__ __volatile__("" :: "m" (mid)); 12772329SN/A finishVfp(fpscr, state, fpscr.fz); 12782329SN/A FpCondCodes = fpscr & FpCondCodesMask; 12799440SAndreas.Sandberg@ARM.com FpDestP0.uw = mid; 12802329SN/A FpDestP1.uw = mid >> 32; 12812329SN/A ''' 12822329SN/A vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 12832329SN/A { "code": vcvtFpSFixedDCode, 12842329SN/A "predicate_test": predicateTest }, []) 12852329SN/A header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 12862329SN/A decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 12879440SAndreas.Sandberg@ARM.com exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 12889440SAndreas.Sandberg@ARM.com 12892329SN/A vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 12902329SN/A FPSCR fpscr = Fpscr | FpCondCodes; 12912329SN/A vfpFlushToZero(fpscr, FpOp1); 12922329SN/A VfpSavedState state = prepFpState(fpscr.rMode); 12932329SN/A __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12942329SN/A FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 12959944Smatt.horsnell@ARM.com __asm__ __volatile__("" :: "m" (FpDest.uw)); 12969944Smatt.horsnell@ARM.com finishVfp(fpscr, state, fpscr.fz); 1297 FpCondCodes = fpscr & FpCondCodesMask; 1298 ''' 1299 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1300 { "code": vcvtFpUFixedSCode, 1301 "predicate_test": predicateTest }, []) 1302 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1303 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1304 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1305 1306 vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 1307 FPSCR fpscr = Fpscr | FpCondCodes; 1308 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1309 vfpFlushToZero(fpscr, cOp1); 1310 VfpSavedState state = prepFpState(fpscr.rMode); 1311 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1312 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 1313 __asm__ __volatile__("" :: "m" (mid)); 1314 finishVfp(fpscr, state, fpscr.fz); 1315 FpCondCodes = fpscr & FpCondCodesMask; 1316 FpDestP0.uw = mid; 1317 FpDestP1.uw = mid >> 32; 1318 ''' 1319 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1320 { "code": vcvtFpUFixedDCode, 1321 "predicate_test": predicateTest }, []) 1322 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1323 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1324 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1325 1326 vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 1327 FPSCR fpscr = Fpscr | FpCondCodes; 1328 VfpSavedState state = prepFpState(fpscr.rMode); 1329 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 1330 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 1331 __asm__ __volatile__("" :: "m" (FpDest)); 1332 finishVfp(fpscr, state, fpscr.fz); 1333 FpCondCodes = fpscr & FpCondCodesMask; 1334 ''' 1335 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1336 { "code": vcvtSFixedFpSCode, 1337 "predicate_test": predicateTest }, []) 1338 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1339 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1340 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1341 1342 vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 1343 FPSCR fpscr = Fpscr | FpCondCodes; 1344 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1345 VfpSavedState state = prepFpState(fpscr.rMode); 1346 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1347 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1348 __asm__ __volatile__("" :: "m" (cDest)); 1349 finishVfp(fpscr, state, fpscr.fz); 1350 FpCondCodes = fpscr & FpCondCodesMask; 1351 FpDestP0.uw = dblLow(cDest); 1352 FpDestP1.uw = dblHi(cDest); 1353 ''' 1354 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1355 { "code": vcvtSFixedFpDCode, 1356 "predicate_test": predicateTest }, []) 1357 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1358 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1359 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1360 1361 vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 1362 FPSCR fpscr = Fpscr | FpCondCodes; 1363 VfpSavedState state = prepFpState(fpscr.rMode); 1364 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 1365 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 1366 __asm__ __volatile__("" :: "m" (FpDest)); 1367 finishVfp(fpscr, state, fpscr.fz); 1368 FpCondCodes = fpscr & FpCondCodesMask; 1369 ''' 1370 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1371 { "code": vcvtUFixedFpSCode, 1372 "predicate_test": predicateTest }, []) 1373 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1374 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1375 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1376 1377 vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 1378 FPSCR fpscr = Fpscr | FpCondCodes; 1379 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1380 VfpSavedState state = prepFpState(fpscr.rMode); 1381 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1382 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1383 __asm__ __volatile__("" :: "m" (cDest)); 1384 finishVfp(fpscr, state, fpscr.fz); 1385 FpCondCodes = fpscr & FpCondCodesMask; 1386 FpDestP0.uw = dblLow(cDest); 1387 FpDestP1.uw = dblHi(cDest); 1388 ''' 1389 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1390 { "code": vcvtUFixedFpDCode, 1391 "predicate_test": predicateTest }, []) 1392 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1393 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1394 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1395 1396 vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 1397 FPSCR fpscr = Fpscr | FpCondCodes; 1398 vfpFlushToZero(fpscr, FpOp1); 1399 VfpSavedState state = prepFpState(fpscr.rMode); 1400 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1401 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1402 __asm__ __volatile__("" :: "m" (FpDest.sh)); 1403 finishVfp(fpscr, state, fpscr.fz); 1404 FpCondCodes = fpscr & FpCondCodesMask; 1405 ''' 1406 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1407 "FpRegRegImmOp", 1408 { "code": vcvtFpSHFixedSCode, 1409 "predicate_test": predicateTest }, []) 1410 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1411 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1412 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1413 1414 vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 1415 FPSCR fpscr = Fpscr | FpCondCodes; 1416 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1417 vfpFlushToZero(fpscr, cOp1); 1418 VfpSavedState state = prepFpState(fpscr.rMode); 1419 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1420 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 1421 __asm__ __volatile__("" :: "m" (result)); 1422 finishVfp(fpscr, state, fpscr.fz); 1423 FpCondCodes = fpscr & FpCondCodesMask; 1424 FpDestP0.uw = result; 1425 FpDestP1.uw = result >> 32; 1426 ''' 1427 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1428 "FpRegRegImmOp", 1429 { "code": vcvtFpSHFixedDCode, 1430 "predicate_test": predicateTest }, []) 1431 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1432 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1433 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1434 1435 vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 1436 FPSCR fpscr = Fpscr | FpCondCodes; 1437 vfpFlushToZero(fpscr, FpOp1); 1438 VfpSavedState state = prepFpState(fpscr.rMode); 1439 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1440 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1441 __asm__ __volatile__("" :: "m" (FpDest.uh)); 1442 finishVfp(fpscr, state, fpscr.fz); 1443 FpCondCodes = fpscr & FpCondCodesMask; 1444 ''' 1445 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1446 "FpRegRegImmOp", 1447 { "code": vcvtFpUHFixedSCode, 1448 "predicate_test": predicateTest }, []) 1449 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1450 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1451 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1452 1453 vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 1454 FPSCR fpscr = Fpscr | FpCondCodes; 1455 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1456 vfpFlushToZero(fpscr, cOp1); 1457 VfpSavedState state = prepFpState(fpscr.rMode); 1458 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1459 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 1460 __asm__ __volatile__("" :: "m" (mid)); 1461 finishVfp(fpscr, state, fpscr.fz); 1462 FpCondCodes = fpscr & FpCondCodesMask; 1463 FpDestP0.uw = mid; 1464 FpDestP1.uw = mid >> 32; 1465 ''' 1466 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1467 "FpRegRegImmOp", 1468 { "code": vcvtFpUHFixedDCode, 1469 "predicate_test": predicateTest }, []) 1470 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1471 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1472 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1473 1474 vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 1475 FPSCR fpscr = Fpscr | FpCondCodes; 1476 VfpSavedState state = prepFpState(fpscr.rMode); 1477 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 1478 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 1479 __asm__ __volatile__("" :: "m" (FpDest)); 1480 finishVfp(fpscr, state, fpscr.fz); 1481 FpCondCodes = fpscr & FpCondCodesMask; 1482 ''' 1483 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1484 "FpRegRegImmOp", 1485 { "code": vcvtSHFixedFpSCode, 1486 "predicate_test": predicateTest }, []) 1487 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1488 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1489 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1490 1491 vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 1492 FPSCR fpscr = Fpscr | FpCondCodes; 1493 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1494 VfpSavedState state = prepFpState(fpscr.rMode); 1495 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1496 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1497 __asm__ __volatile__("" :: "m" (cDest)); 1498 finishVfp(fpscr, state, fpscr.fz); 1499 FpCondCodes = fpscr & FpCondCodesMask; 1500 FpDestP0.uw = dblLow(cDest); 1501 FpDestP1.uw = dblHi(cDest); 1502 ''' 1503 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1504 "FpRegRegImmOp", 1505 { "code": vcvtSHFixedFpDCode, 1506 "predicate_test": predicateTest }, []) 1507 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1508 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1509 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1510 1511 vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 1512 FPSCR fpscr = Fpscr | FpCondCodes; 1513 VfpSavedState state = prepFpState(fpscr.rMode); 1514 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 1515 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 1516 __asm__ __volatile__("" :: "m" (FpDest)); 1517 finishVfp(fpscr, state, fpscr.fz); 1518 FpCondCodes = fpscr & FpCondCodesMask; 1519 ''' 1520 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1521 "FpRegRegImmOp", 1522 { "code": vcvtUHFixedFpSCode, 1523 "predicate_test": predicateTest }, []) 1524 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1525 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1526 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1527 1528 vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 1529 FPSCR fpscr = Fpscr | FpCondCodes; 1530 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1531 VfpSavedState state = prepFpState(fpscr.rMode); 1532 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1533 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1534 __asm__ __volatile__("" :: "m" (cDest)); 1535 finishVfp(fpscr, state, fpscr.fz); 1536 FpCondCodes = fpscr & FpCondCodesMask; 1537 FpDestP0.uw = dblLow(cDest); 1538 FpDestP1.uw = dblHi(cDest); 1539 ''' 1540 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1541 "FpRegRegImmOp", 1542 { "code": vcvtUHFixedFpDCode, 1543 "predicate_test": predicateTest }, []) 1544 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1545 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1546 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1547}}; 1548