fp.isa revision 7643
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947396Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1957640Sgblack@eecs.umich.edu { "code": vmsrrsEnabledCheckCode + \ 1967640Sgblack@eecs.umich.edu "MiscDest = Op1;", 1977322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1987396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrIop); 1997396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 2007322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2017324Sgblack@eecs.umich.edu 2027643Sgblack@eecs.umich.edu vmsrFpscrCode = vmsrrsEnabledCheckCode + ''' 2037643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2047643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2057643Sgblack@eecs.umich.edu ''' 2067643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2077643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2087643Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2097643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2107643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2117643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2127643Sgblack@eecs.umich.edu 2137396Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2147640Sgblack@eecs.umich.edu { "code": vmsrrsEnabledCheckCode + \ 2157640Sgblack@eecs.umich.edu "Dest = MiscOp1;", 2167324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2177396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2187396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2197324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2207333Sgblack@eecs.umich.edu 2217643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2227643Sgblack@eecs.umich.edu { "code": vmsrrsEnabledCheckCode + \ 2237643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2247643Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2257643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2267643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2277643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2287643Sgblack@eecs.umich.edu 2297643Sgblack@eecs.umich.edu vmrsApsrCode = vmsrrsEnabledCheckCode + ''' 2307643Sgblack@eecs.umich.edu Dest = (MiscOp1 & imm) | (Dest & ~imm); 2317643Sgblack@eecs.umich.edu ''' 2327396Sgblack@eecs.umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 2337392Sgblack@eecs.umich.edu { "code": vmrsApsrCode, 2347392Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2357396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 2367396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 2377392Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrIop); 2387392Sgblack@eecs.umich.edu 2397643Sgblack@eecs.umich.edu vmrsApsrFpscrCode = vmsrrsEnabledCheckCode + ''' 2407643Sgblack@eecs.umich.edu assert((imm & ~FpCondCodesMask) == 0); 2417643Sgblack@eecs.umich.edu Dest = (FpCondCodes & imm) | (Dest & ~imm); 2427643Sgblack@eecs.umich.edu ''' 2437643Sgblack@eecs.umich.edu vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", 2447643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2457643Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2467643Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); 2477643Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); 2487643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2497643Sgblack@eecs.umich.edu 2507640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2517333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2527333Sgblack@eecs.umich.edu ''' 2537396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2547333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2557333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2567396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2577396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2587333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2597333Sgblack@eecs.umich.edu 2607640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2617333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2627333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2637333Sgblack@eecs.umich.edu ''' 2647396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2657333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2667333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2677396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2687396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2697333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2707333Sgblack@eecs.umich.edu 2717640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 2727333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2737333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2747333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2757333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2767333Sgblack@eecs.umich.edu ''' 2777396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2787333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2797333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2807396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2817396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2827333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2837333Sgblack@eecs.umich.edu 2847640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 2857333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2867333Sgblack@eecs.umich.edu ''' 2877396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 2887333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2897333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2907396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 2917396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 2927333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2937333Sgblack@eecs.umich.edu 2947640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 2957333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2967333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2977333Sgblack@eecs.umich.edu ''' 2987396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 2997333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3007333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3017396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3027396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3037333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3047333Sgblack@eecs.umich.edu 3057640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3067333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 3077333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 3087333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 3097333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 3107333Sgblack@eecs.umich.edu ''' 3117396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3127333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3137333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3147396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3157396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3167333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3177333Sgblack@eecs.umich.edu 3187640Sgblack@eecs.umich.edu vmovCoreRegBCode = vfpEnabledCheckCode + ''' 3197639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub); 3207333Sgblack@eecs.umich.edu ''' 3217396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3227333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3237333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3247396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3257396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3267333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3277333Sgblack@eecs.umich.edu 3287640Sgblack@eecs.umich.edu vmovCoreRegHCode = vfpEnabledCheckCode + ''' 3297639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh); 3307333Sgblack@eecs.umich.edu ''' 3317396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3327333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3337333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3347396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3357396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3367333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3377333Sgblack@eecs.umich.edu 3387640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3397333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 3407333Sgblack@eecs.umich.edu ''' 3417396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3427333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3437333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3447396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3457396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3467333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3477333Sgblack@eecs.umich.edu 3487640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3497639Sgblack@eecs.umich.edu assert(imm < 4); 3507639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8); 3517333Sgblack@eecs.umich.edu ''' 3527396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3537333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3547333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3557396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3567396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3577333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3587333Sgblack@eecs.umich.edu 3597640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3607639Sgblack@eecs.umich.edu assert(imm < 2); 3617639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16); 3627333Sgblack@eecs.umich.edu ''' 3637396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3647333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3657333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3667396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3677396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3687333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3697333Sgblack@eecs.umich.edu 3707640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 3717639Sgblack@eecs.umich.edu assert(imm < 4); 3727639Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8)); 3737333Sgblack@eecs.umich.edu ''' 3747396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3757333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3767333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3777396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3787396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3797333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3807333Sgblack@eecs.umich.edu 3817640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 3827639Sgblack@eecs.umich.edu assert(imm < 2); 3837639Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16)); 3847333Sgblack@eecs.umich.edu ''' 3857396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 3867333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3877333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3887396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3897396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3907333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3917333Sgblack@eecs.umich.edu 3927640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 3937333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3947333Sgblack@eecs.umich.edu ''' 3957396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 3967333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3977333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3987396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 3997396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4007333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4017333Sgblack@eecs.umich.edu 4027640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4037333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 4047333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 4057333Sgblack@eecs.umich.edu ''' 4067396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4077333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4087333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4097396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4107396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4117333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4127333Sgblack@eecs.umich.edu 4137640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4147333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 4157333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 4167333Sgblack@eecs.umich.edu ''' 4177396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4187333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4197333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4207396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4217396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4227333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4237381Sgblack@eecs.umich.edu}}; 4247381Sgblack@eecs.umich.edu 4257381Sgblack@eecs.umich.edulet {{ 4267381Sgblack@eecs.umich.edu 4277381Sgblack@eecs.umich.edu header_output = "" 4287381Sgblack@eecs.umich.edu decoder_output = "" 4297381Sgblack@eecs.umich.edu exec_output = "" 4307364Sgblack@eecs.umich.edu 4317640Sgblack@eecs.umich.edu singleCode = vfpEnabledCheckCode + ''' 4327643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 4337396Sgblack@eecs.umich.edu FpDest = %(op)s; 4347643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 4357364Sgblack@eecs.umich.edu ''' 4367396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4377639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4387396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4397640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4407643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 4417396Sgblack@eecs.umich.edu double dest = %(op)s; 4427643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 4437396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 4447396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 4457396Sgblack@eecs.umich.edu ''' 4467396Sgblack@eecs.umich.edu doubleBinOp = ''' 4477396Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 4487396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 4497639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 4507396Sgblack@eecs.umich.edu ''' 4517396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 4527396Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, 4537396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 4547396Sgblack@eecs.umich.edu ''' 4557364Sgblack@eecs.umich.edu 4567396Sgblack@eecs.umich.edu def buildBinFpOp(name, Name, base, singleOp, doubleOp): 4577396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4587365Sgblack@eecs.umich.edu 4597396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4607396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4617396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4627396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4637396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4647396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4657396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4667396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4677365Sgblack@eecs.umich.edu 4687396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4697396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4707366Sgblack@eecs.umich.edu 4717396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4727396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4737396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4747396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4757366Sgblack@eecs.umich.edu 4767396Sgblack@eecs.umich.edu buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "fpAddS", "fpAddD") 4777396Sgblack@eecs.umich.edu buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "fpSubS", "fpSubD") 4787396Sgblack@eecs.umich.edu buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "fpDivS", "fpDivD") 4797396Sgblack@eecs.umich.edu buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "fpMulS", "fpMulD") 4807367Sgblack@eecs.umich.edu 4817396Sgblack@eecs.umich.edu def buildUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4827396Sgblack@eecs.umich.edu if doubleOp is None: 4837396Sgblack@eecs.umich.edu doubleOp = singleOp 4847396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4857367Sgblack@eecs.umich.edu 4867396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 4877396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4887396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4897396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4907396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 4917396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4927396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4937396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4947368Sgblack@eecs.umich.edu 4957396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4967396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4977368Sgblack@eecs.umich.edu 4987396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4997396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5007396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5017396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5027369Sgblack@eecs.umich.edu 5037396Sgblack@eecs.umich.edu buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "sqrtf", "sqrt") 5047369Sgblack@eecs.umich.edu 5057396Sgblack@eecs.umich.edu def buildSimpleUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 5067396Sgblack@eecs.umich.edu if doubleOp is None: 5077396Sgblack@eecs.umich.edu doubleOp = singleOp 5087396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5097369Sgblack@eecs.umich.edu 5107396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5117396Sgblack@eecs.umich.edu { "code": singleCode % { "op": singleOp }, 5127396Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5137396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5147396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 5157396Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5167369Sgblack@eecs.umich.edu 5177396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5187396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5197396Sgblack@eecs.umich.edu 5207396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5217396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5227396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5237396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5247396Sgblack@eecs.umich.edu 5257396Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", 5267396Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") 5277396Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", 5287396Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") 5297381Sgblack@eecs.umich.edu}}; 5307381Sgblack@eecs.umich.edu 5317381Sgblack@eecs.umich.edulet {{ 5327381Sgblack@eecs.umich.edu 5337381Sgblack@eecs.umich.edu header_output = "" 5347381Sgblack@eecs.umich.edu decoder_output = "" 5357381Sgblack@eecs.umich.edu exec_output = "" 5367370Sgblack@eecs.umich.edu 5377640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 5387643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5397396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5407639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5417639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 5427639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5437643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 5447370Sgblack@eecs.umich.edu ''' 5457396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5467370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5477370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5487396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5497396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5507370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5517370Sgblack@eecs.umich.edu 5527640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 5537643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5547396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5557396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5567639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5577396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5587639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 5597639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5607643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 5617396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5627396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5637370Sgblack@eecs.umich.edu ''' 5647396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 5657370Sgblack@eecs.umich.edu { "code": vmlaDCode, 5667370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5677396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 5687396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 5697370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 5707370Sgblack@eecs.umich.edu 5717640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 5727643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5737396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5747639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5757639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 5767639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5777643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 5787370Sgblack@eecs.umich.edu ''' 5797396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 5807370Sgblack@eecs.umich.edu { "code": vmlsSCode, 5817370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5827396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 5837396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 5847370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 5857370Sgblack@eecs.umich.edu 5867640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 5877643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 5887396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5897396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5907639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5917396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5927639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 5937639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5947643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 5957396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5967396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5977370Sgblack@eecs.umich.edu ''' 5987396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 5997370Sgblack@eecs.umich.edu { "code": vmlsDCode, 6007370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6017396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 6027396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 6037370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 6047371Sgblack@eecs.umich.edu 6057640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 6067643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6077396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6087639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6097639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 6107639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6117643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6127371Sgblack@eecs.umich.edu ''' 6137396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 6147371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 6157371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6167396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 6177396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 6187371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 6197371Sgblack@eecs.umich.edu 6207640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 6217643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6227396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6237396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6247639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6257396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6267639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 6277639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6287643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6297396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6307396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6317371Sgblack@eecs.umich.edu ''' 6327396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 6337371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6347371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6357396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 6367396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 6377371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6387371Sgblack@eecs.umich.edu 6397640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 6407643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6417396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6427639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6437639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 6447639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6457643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6467371Sgblack@eecs.umich.edu ''' 6477396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 6487371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 6497371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6507396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 6517396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 6527371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 6537371Sgblack@eecs.umich.edu 6547640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 6557643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6567396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6577396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6587639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6597396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6607639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 6617639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6627643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6637396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6647396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6657371Sgblack@eecs.umich.edu ''' 6667396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 6677371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 6687371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6697396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 6707396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 6717371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 6727371Sgblack@eecs.umich.edu 6737640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 6747643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6757639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 6767639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6777643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6787371Sgblack@eecs.umich.edu ''' 6797396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 6807371Sgblack@eecs.umich.edu { "code": vnmulSCode, 6817371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6827396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 6837396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 6847371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 6857371Sgblack@eecs.umich.edu 6867640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 6877643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 6887396Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6897396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6907639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 6917639Sgblack@eecs.umich.edu fpscr.rMode); 6927643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 6937396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6947396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6957371Sgblack@eecs.umich.edu ''' 6967396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 6977371Sgblack@eecs.umich.edu { "code": vnmulDCode, 6987371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6997396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 7007396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 7017371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 7027381Sgblack@eecs.umich.edu}}; 7037381Sgblack@eecs.umich.edu 7047381Sgblack@eecs.umich.edulet {{ 7057381Sgblack@eecs.umich.edu 7067381Sgblack@eecs.umich.edu header_output = "" 7077381Sgblack@eecs.umich.edu decoder_output = "" 7087381Sgblack@eecs.umich.edu exec_output = "" 7097373Sgblack@eecs.umich.edu 7107640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 7117643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7127397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7137381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 7147373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 7157381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7167639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7177643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7187373Sgblack@eecs.umich.edu ''' 7197396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 7207373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 7217373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7227396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 7237396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 7247373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 7257373Sgblack@eecs.umich.edu 7267640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 7277643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7287397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7297381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 7307397Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0.uw; 7317397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7327639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7337643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7347397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7357397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7367373Sgblack@eecs.umich.edu ''' 7377396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 7387373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 7397373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7407396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 7417396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 7427373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 7437373Sgblack@eecs.umich.edu 7447640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 7457643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7467397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7477381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 7487373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 7497381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7507639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7517643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7527373Sgblack@eecs.umich.edu ''' 7537396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 7547373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 7557373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7567396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 7577396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 7587373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 7597373Sgblack@eecs.umich.edu 7607640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 7617643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7627397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7637381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 7647397Sgblack@eecs.umich.edu double cDest = FpOp1P0.sw; 7657397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7667639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7677643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7687397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7697397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7707373Sgblack@eecs.umich.edu ''' 7717396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 7727373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 7737373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7747396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 7757396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 7767373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 7777373Sgblack@eecs.umich.edu 7787640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 7797643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7807397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7817397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 7827381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7837388Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 7847381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 7857639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7867643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 7877380Sgblack@eecs.umich.edu ''' 7887396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 7897380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 7907380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7917396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 7927396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 7937380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 7947380Sgblack@eecs.umich.edu 7957640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 7967643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 7977397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 7987397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 7997397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8007397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8017397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 8027381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8037639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8047643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8057380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8067380Sgblack@eecs.umich.edu ''' 8077396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 8087380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 8097380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8107396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 8117396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 8127380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 8137380Sgblack@eecs.umich.edu 8147640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 8157643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8167397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8177397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8187381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8197388Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 8207381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 8217639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8227643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8237380Sgblack@eecs.umich.edu ''' 8247396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 8257380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 8267380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8277396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 8287396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 8297380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 8307380Sgblack@eecs.umich.edu 8317640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 8327643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8337397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8347397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8357397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8367397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8377397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 8387381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8397639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8407643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8417380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8427380Sgblack@eecs.umich.edu ''' 8437396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 8447380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 8457380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8467396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 8477396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 8487380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 8497380Sgblack@eecs.umich.edu 8507640Sgblack@eecs.umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 8517643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8527397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8537397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8547380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8557381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8567387Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 8577381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 8587639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8597643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8607373Sgblack@eecs.umich.edu ''' 8617396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 8627373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 8637373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8647396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 8657396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 8667373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 8677373Sgblack@eecs.umich.edu 8687640Sgblack@eecs.umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 8697643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8707397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8717397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8727397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8737380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8747397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8757397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 8767381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8777639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8787643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8797373Sgblack@eecs.umich.edu FpDestP0.uw = result; 8807373Sgblack@eecs.umich.edu ''' 8817396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 8827373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 8837373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8847396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 8857396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 8867373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 8877373Sgblack@eecs.umich.edu 8887640Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 8897643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 8907397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8917397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8927380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8937381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8947387Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 8957381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 8967639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8977643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 8987373Sgblack@eecs.umich.edu ''' 8997396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 9007373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 9017373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9027396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 9037396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 9047373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 9057373Sgblack@eecs.umich.edu 9067640Sgblack@eecs.umich.edu vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 9077643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9087397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9097397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9107397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9117380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9127397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9137397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 9147381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9167643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9177373Sgblack@eecs.umich.edu FpDestP0.uw = result; 9187373Sgblack@eecs.umich.edu ''' 9197396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 9207373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 9217373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9227396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 9237396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 9247373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 9257374Sgblack@eecs.umich.edu 9267640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 9277643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9287397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9297397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9307381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9317397Sgblack@eecs.umich.edu double cDest = fixFpSFpDDest(Fpscr, FpOp1); 9327397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9337639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9347643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9357397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 9367397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 9377374Sgblack@eecs.umich.edu ''' 9387396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 9397374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 9407374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9417396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 9427396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 9437374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 9447374Sgblack@eecs.umich.edu 9457640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 9467643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9477397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9487397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9497397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9507397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9517397Sgblack@eecs.umich.edu FpDest = fixFpDFpSDest(Fpscr, cOp1); 9527381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9537639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9547643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9557374Sgblack@eecs.umich.edu ''' 9567396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 9577374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 9587374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9597396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 9607396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 9617374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 9627377Sgblack@eecs.umich.edu 9637640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 9647643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9657398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9667398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9677398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9687639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9697639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 9707398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9717639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9727643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9737398Sgblack@eecs.umich.edu ''' 9747398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 9757398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 9767398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9777398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 9787398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 9797398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 9807398Sgblack@eecs.umich.edu 9817640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 9827643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 9837398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9847398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9857639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9867639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 9877398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9887639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9897643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 9907398Sgblack@eecs.umich.edu ''' 9917398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 9927398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 9937398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9947398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 9957398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 9967398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 9977398Sgblack@eecs.umich.edu 9987640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 9997643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10007398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10017398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10027639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10037639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 10047639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 31, 16,, 10057639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10067639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 10077639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10087639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10097643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10107398Sgblack@eecs.umich.edu ''' 10117398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 10127398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 10137398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10147398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 10157398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 10167398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 10177398Sgblack@eecs.umich.edu 10187640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 10197643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10207398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10217398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10227639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 10237639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 10247639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 15, 0, 10257639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 10267639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 10277639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10287639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10297643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10307398Sgblack@eecs.umich.edu ''' 10317398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 10327398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 10337398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10347398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 10357398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 10367398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 10377398Sgblack@eecs.umich.edu 10387640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 10397643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10407397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 10417377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 10427377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10437377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 10447377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10457377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 10467377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10477377Sgblack@eecs.umich.edu } else { 10487389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 10497389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 10507396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 10517389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 10527396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 10537389Sgblack@eecs.umich.edu if (signal1 || signal2) 10547389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10557377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10567377Sgblack@eecs.umich.edu } 10577643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10587377Sgblack@eecs.umich.edu ''' 10597396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 10607377Sgblack@eecs.umich.edu { "code": vcmpSCode, 10617377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10627396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 10637396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 10647377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 10657377Sgblack@eecs.umich.edu 10667640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 10677397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 10687397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 10697643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10707397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 10717397Sgblack@eecs.umich.edu if (cDest == cOp1) { 10727377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10737397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 10747377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10757397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 10767377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10777377Sgblack@eecs.umich.edu } else { 10787389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 10797397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 10807397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 10817397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 10827397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 10837389Sgblack@eecs.umich.edu if (signal1 || signal2) 10847389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10857377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10867377Sgblack@eecs.umich.edu } 10877643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 10887377Sgblack@eecs.umich.edu ''' 10897396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 10907377Sgblack@eecs.umich.edu { "code": vcmpDCode, 10917377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10927396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 10937396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 10947377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 10957377Sgblack@eecs.umich.edu 10967640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 10977643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 10987397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 10997389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11007389Sgblack@eecs.umich.edu assert(imm == 0); 11017377Sgblack@eecs.umich.edu if (FpDest == imm) { 11027377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11037377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11047377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11057377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11067377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11077377Sgblack@eecs.umich.edu } else { 11087389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11097389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 11107396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 11117389Sgblack@eecs.umich.edu if (signal) 11127389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11137377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11147377Sgblack@eecs.umich.edu } 11157643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11167377Sgblack@eecs.umich.edu ''' 11177396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 11187377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 11197377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11207396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 11217396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 11227377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 11237377Sgblack@eecs.umich.edu 11247640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 11257389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11267389Sgblack@eecs.umich.edu assert(imm == 0); 11277397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11287643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 11297397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 11307397Sgblack@eecs.umich.edu if (cDest == imm) { 11317377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11327397Sgblack@eecs.umich.edu } else if (cDest < imm) { 11337377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11347397Sgblack@eecs.umich.edu } else if (cDest > imm) { 11357377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11367377Sgblack@eecs.umich.edu } else { 11377389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 11387397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 11397397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 11407389Sgblack@eecs.umich.edu if (signal) 11417389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11427377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11437377Sgblack@eecs.umich.edu } 11447643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11457377Sgblack@eecs.umich.edu ''' 11467396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 11477377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 11487377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11497396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 11507396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 11517377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 11527389Sgblack@eecs.umich.edu 11537640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 11547643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 11557397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 11567389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11577389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11587389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11597389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11607389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11617389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11627389Sgblack@eecs.umich.edu } else { 11637389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11647389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11657389Sgblack@eecs.umich.edu } 11667643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11677389Sgblack@eecs.umich.edu ''' 11687396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 11697389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 11707389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11717396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 11727396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 11737389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 11747389Sgblack@eecs.umich.edu 11757640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 11767397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 11777397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11787643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 11797397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 11807397Sgblack@eecs.umich.edu if (cDest == cOp1) { 11817389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11827397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 11837389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11847397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 11857389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11867389Sgblack@eecs.umich.edu } else { 11877389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11887389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11897389Sgblack@eecs.umich.edu } 11907643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 11917389Sgblack@eecs.umich.edu ''' 11927396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 11937389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 11947389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11957396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 11967396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 11977389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 11987389Sgblack@eecs.umich.edu 11997640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 12007643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12017397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 12027389Sgblack@eecs.umich.edu if (FpDest == imm) { 12037389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12047389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12057389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12067389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12077389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12087389Sgblack@eecs.umich.edu } else { 12097389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12107389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12117389Sgblack@eecs.umich.edu } 12127643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12137389Sgblack@eecs.umich.edu ''' 12147396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 12157389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 12167389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12177396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 12187396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 12197389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 12207389Sgblack@eecs.umich.edu 12217640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 12227397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 12237643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12247397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 12257397Sgblack@eecs.umich.edu if (cDest == imm) { 12267389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12277397Sgblack@eecs.umich.edu } else if (cDest < imm) { 12287389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12297397Sgblack@eecs.umich.edu } else if (cDest > imm) { 12307389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12317389Sgblack@eecs.umich.edu } else { 12327389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12337389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12347389Sgblack@eecs.umich.edu } 12357643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12367389Sgblack@eecs.umich.edu ''' 12377396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 12387389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 12397389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12407396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 12417396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 12427389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 12437322Sgblack@eecs.umich.edu}}; 12447379Sgblack@eecs.umich.edu 12457379Sgblack@eecs.umich.edulet {{ 12467379Sgblack@eecs.umich.edu 12477379Sgblack@eecs.umich.edu header_output = "" 12487379Sgblack@eecs.umich.edu decoder_output = "" 12497379Sgblack@eecs.umich.edu exec_output = "" 12507379Sgblack@eecs.umich.edu 12517640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 12527643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12537397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12547397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12557381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12567379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 12577381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 12587639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12597643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12607379Sgblack@eecs.umich.edu ''' 12617396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 12627379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 12637379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12647396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 12657396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 12667379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 12677379Sgblack@eecs.umich.edu 12687640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 12697643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12707397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12717397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 12727397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12737397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 12747397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 12757381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 12767639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12777643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12787379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12797379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12807379Sgblack@eecs.umich.edu ''' 12817396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 12827379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 12837379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12847396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 12857396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 12867379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 12877379Sgblack@eecs.umich.edu 12887640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 12897643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 12907397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12917397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12927381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12937379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 12947381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 12957639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12967643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12977379Sgblack@eecs.umich.edu ''' 12987396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 12997379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 13007379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13017396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 13027396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 13037379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 13047379Sgblack@eecs.umich.edu 13057640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 13067643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13077397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 13087397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13097397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13107397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13117397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 13127381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13137639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13147643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13157379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13167379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13177379Sgblack@eecs.umich.edu ''' 13187396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 13197379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 13207379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13217396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 13227396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 13237379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 13247379Sgblack@eecs.umich.edu 13257640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 13267643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13277397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13287381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 13297639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 13307381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 13317639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13327643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13337379Sgblack@eecs.umich.edu ''' 13347396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 13357379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 13367379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13377396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 13387396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 13397379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 13407379Sgblack@eecs.umich.edu 13417640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 13427643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13437379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13447397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13457381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 13467639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 13477397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 13487639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13497643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13507397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 13517397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 13527379Sgblack@eecs.umich.edu ''' 13537396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 13547379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 13557379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13567396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 13577396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 13587379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 13597379Sgblack@eecs.umich.edu 13607640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 13617643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13627397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13637381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 13647639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 13657381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 13667639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13677643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13687379Sgblack@eecs.umich.edu ''' 13697396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 13707379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 13717379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13727396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 13737396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 13747379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 13757379Sgblack@eecs.umich.edu 13767640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 13777643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13787379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13797397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13807381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 13817639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 13827397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 13837639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13847643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13857397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 13867397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 13877379Sgblack@eecs.umich.edu ''' 13887396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 13897379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 13907379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13917396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 13927396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 13937379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 13947379Sgblack@eecs.umich.edu 13957640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 13967643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 13977397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13987397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13997381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14007379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 14017381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 14027639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14037643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14047379Sgblack@eecs.umich.edu ''' 14057379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 14067396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14077379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 14087379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14097396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 14107396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 14117379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 14127379Sgblack@eecs.umich.edu 14137640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 14147643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14157397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 14167397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14177397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14187397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 14197397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 14207381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 14217639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14227643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14237379Sgblack@eecs.umich.edu FpDestP0.uw = result; 14247379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 14257379Sgblack@eecs.umich.edu ''' 14267379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 14277396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14287379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 14297379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14307396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 14317396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 14327379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 14337379Sgblack@eecs.umich.edu 14347640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 14357643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14367397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14377397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14387381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14397379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 14407381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 14417639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14427643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14437379Sgblack@eecs.umich.edu ''' 14447379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 14457396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14467379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 14477379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14487396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 14497396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 14507379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 14517379Sgblack@eecs.umich.edu 14527640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 14537643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14547397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 14557397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14567397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14577397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 14587397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 14597381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 14607639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14617643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14627379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 14637379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 14647379Sgblack@eecs.umich.edu ''' 14657379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 14667396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14677379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 14687379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14697396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 14707396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 14717379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 14727379Sgblack@eecs.umich.edu 14737640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 14747643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14757397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14767381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 14777639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 14787381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14797639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14807643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14817379Sgblack@eecs.umich.edu ''' 14827379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 14837396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14847379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 14857379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14867396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 14877396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 14887379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 14897379Sgblack@eecs.umich.edu 14907640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 14917643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 14927379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14937397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14947381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14957639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 14967397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14977639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14987643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14997397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 15007397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 15017379Sgblack@eecs.umich.edu ''' 15027379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 15037396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15047379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 15057379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15067396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 15077396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 15087379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 15097379Sgblack@eecs.umich.edu 15107640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 15117643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 15127397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15137381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 15147639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 15157381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15167639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15177643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 15187379Sgblack@eecs.umich.edu ''' 15197379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 15207396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15217379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 15227379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15237396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 15247396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 15257379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 15267379Sgblack@eecs.umich.edu 15277640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 15287643Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr | FpCondCodes; 15297379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15317381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15327639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 15337397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15347639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15357643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 15367397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 15377397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 15387379Sgblack@eecs.umich.edu ''' 15397379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 15407396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15417379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 15427379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15437396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 15447396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 15457379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 15467379Sgblack@eecs.umich.edu}}; 1547