fp.isa revision 7640
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947396Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1957640Sgblack@eecs.umich.edu { "code": vmsrrsEnabledCheckCode + \ 1967640Sgblack@eecs.umich.edu "MiscDest = Op1;", 1977322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1987396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrIop); 1997396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 2007322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2017324Sgblack@eecs.umich.edu 2027396Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2037640Sgblack@eecs.umich.edu { "code": vmsrrsEnabledCheckCode + \ 2047640Sgblack@eecs.umich.edu "Dest = MiscOp1;", 2057324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2067396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2077396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2087324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2097333Sgblack@eecs.umich.edu 2107392Sgblack@eecs.umich.edu vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);" 2117396Sgblack@eecs.umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 2127392Sgblack@eecs.umich.edu { "code": vmrsApsrCode, 2137392Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2147396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 2157396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 2167392Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrIop); 2177392Sgblack@eecs.umich.edu 2187640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2197333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2207333Sgblack@eecs.umich.edu ''' 2217396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2227333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2237333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2247396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2257396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2267333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2277333Sgblack@eecs.umich.edu 2287640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2297333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2307333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2317333Sgblack@eecs.umich.edu ''' 2327396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2337333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2347333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2357396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2367396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2377333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2387333Sgblack@eecs.umich.edu 2397640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 2407333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2417333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2427333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2437333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2447333Sgblack@eecs.umich.edu ''' 2457396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2467333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2477333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2487396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2497396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2507333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2517333Sgblack@eecs.umich.edu 2527640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 2537333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2547333Sgblack@eecs.umich.edu ''' 2557396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 2567333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2577333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2587396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 2597396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 2607333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2617333Sgblack@eecs.umich.edu 2627640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 2637333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2647333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2657333Sgblack@eecs.umich.edu ''' 2667396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 2677333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2687333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2697396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 2707396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 2717333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2727333Sgblack@eecs.umich.edu 2737640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 2747333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2757333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2767333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2777333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2787333Sgblack@eecs.umich.edu ''' 2797396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 2807333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2817333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2827396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 2837396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 2847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2857333Sgblack@eecs.umich.edu 2867640Sgblack@eecs.umich.edu vmovCoreRegBCode = vfpEnabledCheckCode + ''' 2877639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub); 2887333Sgblack@eecs.umich.edu ''' 2897396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 2907333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2917333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2927396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2937396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2947333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2957333Sgblack@eecs.umich.edu 2967640Sgblack@eecs.umich.edu vmovCoreRegHCode = vfpEnabledCheckCode + ''' 2977639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh); 2987333Sgblack@eecs.umich.edu ''' 2997396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3007333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3017333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3027396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3037396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3057333Sgblack@eecs.umich.edu 3067640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3077333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 3087333Sgblack@eecs.umich.edu ''' 3097396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3107333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3117333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3127396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3137396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3147333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3157333Sgblack@eecs.umich.edu 3167640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3177639Sgblack@eecs.umich.edu assert(imm < 4); 3187639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8); 3197333Sgblack@eecs.umich.edu ''' 3207396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3217333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3227333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3237396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3247396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3257333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3267333Sgblack@eecs.umich.edu 3277640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3287639Sgblack@eecs.umich.edu assert(imm < 2); 3297639Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16); 3307333Sgblack@eecs.umich.edu ''' 3317396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3327333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3337333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3347396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3357396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3367333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3377333Sgblack@eecs.umich.edu 3387640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 3397639Sgblack@eecs.umich.edu assert(imm < 4); 3407639Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8)); 3417333Sgblack@eecs.umich.edu ''' 3427396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3437333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3447333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3457396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3467396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3477333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3487333Sgblack@eecs.umich.edu 3497640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 3507639Sgblack@eecs.umich.edu assert(imm < 2); 3517639Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16)); 3527333Sgblack@eecs.umich.edu ''' 3537396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 3547333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3557333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3567396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3577396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3587333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3597333Sgblack@eecs.umich.edu 3607640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 3617333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3627333Sgblack@eecs.umich.edu ''' 3637396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 3647333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3657333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3667396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 3677396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 3687333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 3697333Sgblack@eecs.umich.edu 3707640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 3717333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3727333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3737333Sgblack@eecs.umich.edu ''' 3747396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 3757333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3767333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3777396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3787396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3797333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3807333Sgblack@eecs.umich.edu 3817640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 3827333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3837333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3847333Sgblack@eecs.umich.edu ''' 3857396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 3867333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3877333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3887396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3897396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3907333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3917381Sgblack@eecs.umich.edu}}; 3927381Sgblack@eecs.umich.edu 3937381Sgblack@eecs.umich.edulet {{ 3947381Sgblack@eecs.umich.edu 3957381Sgblack@eecs.umich.edu header_output = "" 3967381Sgblack@eecs.umich.edu decoder_output = "" 3977381Sgblack@eecs.umich.edu exec_output = "" 3987364Sgblack@eecs.umich.edu 3997640Sgblack@eecs.umich.edu singleCode = vfpEnabledCheckCode + ''' 4007396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 4017396Sgblack@eecs.umich.edu FpDest = %(op)s; 4027396Sgblack@eecs.umich.edu Fpscr = fpscr; 4037364Sgblack@eecs.umich.edu ''' 4047396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4057639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4067396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4077640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4087396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 4097396Sgblack@eecs.umich.edu double dest = %(op)s; 4107396Sgblack@eecs.umich.edu Fpscr = fpscr; 4117396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 4127396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 4137396Sgblack@eecs.umich.edu ''' 4147396Sgblack@eecs.umich.edu doubleBinOp = ''' 4157396Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 4167396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 4177639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 4187396Sgblack@eecs.umich.edu ''' 4197396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 4207396Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, 4217396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 4227396Sgblack@eecs.umich.edu ''' 4237364Sgblack@eecs.umich.edu 4247396Sgblack@eecs.umich.edu def buildBinFpOp(name, Name, base, singleOp, doubleOp): 4257396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4267365Sgblack@eecs.umich.edu 4277396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4287396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4297396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4307396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4317396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4327396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4337396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4347396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4357365Sgblack@eecs.umich.edu 4367396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4377396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4387366Sgblack@eecs.umich.edu 4397396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4407396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4417396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4427396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4437366Sgblack@eecs.umich.edu 4447396Sgblack@eecs.umich.edu buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "fpAddS", "fpAddD") 4457396Sgblack@eecs.umich.edu buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "fpSubS", "fpSubD") 4467396Sgblack@eecs.umich.edu buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "fpDivS", "fpDivD") 4477396Sgblack@eecs.umich.edu buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "fpMulS", "fpMulD") 4487367Sgblack@eecs.umich.edu 4497396Sgblack@eecs.umich.edu def buildUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4507396Sgblack@eecs.umich.edu if doubleOp is None: 4517396Sgblack@eecs.umich.edu doubleOp = singleOp 4527396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4537367Sgblack@eecs.umich.edu 4547396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 4557396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4567396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4577396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4587396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 4597396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4607396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4617396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4627368Sgblack@eecs.umich.edu 4637396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4647396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4657368Sgblack@eecs.umich.edu 4667396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4677396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4687396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4697396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4707369Sgblack@eecs.umich.edu 4717396Sgblack@eecs.umich.edu buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "sqrtf", "sqrt") 4727369Sgblack@eecs.umich.edu 4737396Sgblack@eecs.umich.edu def buildSimpleUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4747396Sgblack@eecs.umich.edu if doubleOp is None: 4757396Sgblack@eecs.umich.edu doubleOp = singleOp 4767396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4777369Sgblack@eecs.umich.edu 4787396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4797396Sgblack@eecs.umich.edu { "code": singleCode % { "op": singleOp }, 4807396Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4817396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4827396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 4837396Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4847369Sgblack@eecs.umich.edu 4857396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4867396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4877396Sgblack@eecs.umich.edu 4887396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4897396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4907396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4917396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4927396Sgblack@eecs.umich.edu 4937396Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", 4947396Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") 4957396Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", 4967396Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") 4977381Sgblack@eecs.umich.edu}}; 4987381Sgblack@eecs.umich.edu 4997381Sgblack@eecs.umich.edulet {{ 5007381Sgblack@eecs.umich.edu 5017381Sgblack@eecs.umich.edu header_output = "" 5027381Sgblack@eecs.umich.edu decoder_output = "" 5037381Sgblack@eecs.umich.edu exec_output = "" 5047370Sgblack@eecs.umich.edu 5057640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 5067396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5077396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5087639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5097639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 5107639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5117396Sgblack@eecs.umich.edu Fpscr = fpscr; 5127370Sgblack@eecs.umich.edu ''' 5137396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5147370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5157370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5167396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5177396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5187370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5197370Sgblack@eecs.umich.edu 5207640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 5217396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5227396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5237396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5247639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5257396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5267639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 5277639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5287396Sgblack@eecs.umich.edu Fpscr = fpscr; 5297396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5307396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5317370Sgblack@eecs.umich.edu ''' 5327396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 5337370Sgblack@eecs.umich.edu { "code": vmlaDCode, 5347370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5357396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 5367396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 5377370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 5387370Sgblack@eecs.umich.edu 5397640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 5407396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5417396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5427639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5437639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 5447639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5457396Sgblack@eecs.umich.edu Fpscr = fpscr; 5467370Sgblack@eecs.umich.edu ''' 5477396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 5487370Sgblack@eecs.umich.edu { "code": vmlsSCode, 5497370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5507396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 5517396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 5527370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 5537370Sgblack@eecs.umich.edu 5547640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 5557396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5567396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5577396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5587639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5597396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5607639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 5617639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5627396Sgblack@eecs.umich.edu Fpscr = fpscr; 5637396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5647396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5657370Sgblack@eecs.umich.edu ''' 5667396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 5677370Sgblack@eecs.umich.edu { "code": vmlsDCode, 5687370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5697396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 5707396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 5717370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 5727371Sgblack@eecs.umich.edu 5737640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 5747396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5757396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5767639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5777639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 5787639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5797396Sgblack@eecs.umich.edu Fpscr = fpscr; 5807371Sgblack@eecs.umich.edu ''' 5817396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 5827371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 5837371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5847396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 5857396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 5867371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 5877371Sgblack@eecs.umich.edu 5887640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 5897396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5907396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5917396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5927639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5937396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 5947639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 5957639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5967396Sgblack@eecs.umich.edu Fpscr = fpscr; 5977396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5987396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5997371Sgblack@eecs.umich.edu ''' 6007396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 6017371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6027371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6037396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 6047396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 6057371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6067371Sgblack@eecs.umich.edu 6077640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 6087396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6097396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6107639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6117639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 6127639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6137396Sgblack@eecs.umich.edu Fpscr = fpscr; 6147371Sgblack@eecs.umich.edu ''' 6157396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 6167371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 6177371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6187396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 6197396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 6207371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 6217371Sgblack@eecs.umich.edu 6227640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 6237396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6247396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6257396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6267639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6277396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6287639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 6297639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6307396Sgblack@eecs.umich.edu Fpscr = fpscr; 6317396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6327396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6337371Sgblack@eecs.umich.edu ''' 6347396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 6357371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 6367371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6377396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 6387396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 6397371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 6407371Sgblack@eecs.umich.edu 6417640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 6427396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6437639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 6447639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6457396Sgblack@eecs.umich.edu Fpscr = fpscr; 6467371Sgblack@eecs.umich.edu ''' 6477396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 6487371Sgblack@eecs.umich.edu { "code": vnmulSCode, 6497371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6507396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 6517396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 6527371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 6537371Sgblack@eecs.umich.edu 6547640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 6557396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6567396Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6577396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6587639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 6597639Sgblack@eecs.umich.edu fpscr.rMode); 6607396Sgblack@eecs.umich.edu Fpscr = fpscr; 6617396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6627396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6637371Sgblack@eecs.umich.edu ''' 6647396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 6657371Sgblack@eecs.umich.edu { "code": vnmulDCode, 6667371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6677396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 6687396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 6697371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 6707381Sgblack@eecs.umich.edu}}; 6717381Sgblack@eecs.umich.edu 6727381Sgblack@eecs.umich.edulet {{ 6737381Sgblack@eecs.umich.edu 6747381Sgblack@eecs.umich.edu header_output = "" 6757381Sgblack@eecs.umich.edu decoder_output = "" 6767381Sgblack@eecs.umich.edu exec_output = "" 6777373Sgblack@eecs.umich.edu 6787640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 6797397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6807397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 6817381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 6827373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 6837381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6847639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 6857397Sgblack@eecs.umich.edu Fpscr = fpscr; 6867373Sgblack@eecs.umich.edu ''' 6877396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 6887373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 6897373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6907396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 6917396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 6927373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 6937373Sgblack@eecs.umich.edu 6947640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 6957397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6967397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 6977381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 6987397Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0.uw; 6997397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7007639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7017397Sgblack@eecs.umich.edu Fpscr = fpscr; 7027397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7037397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7047373Sgblack@eecs.umich.edu ''' 7057396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 7067373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 7077373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7087396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 7097396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 7107373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 7117373Sgblack@eecs.umich.edu 7127640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 7137397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7147397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7157381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 7167373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 7177381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7187639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7197397Sgblack@eecs.umich.edu Fpscr = fpscr; 7207373Sgblack@eecs.umich.edu ''' 7217396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 7227373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 7237373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7247396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 7257396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 7267373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 7277373Sgblack@eecs.umich.edu 7287640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 7297397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7317381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 7327397Sgblack@eecs.umich.edu double cDest = FpOp1P0.sw; 7337397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7347639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7357397Sgblack@eecs.umich.edu Fpscr = fpscr; 7367397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7377397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7387373Sgblack@eecs.umich.edu ''' 7397396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 7407373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 7417373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7427396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 7437396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 7447373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 7457373Sgblack@eecs.umich.edu 7467640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 7477397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7487397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7497397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 7507381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7517388Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 7527381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 7537639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7547397Sgblack@eecs.umich.edu Fpscr = fpscr; 7557380Sgblack@eecs.umich.edu ''' 7567396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 7577380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 7587380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7597396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 7607396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 7617380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 7627380Sgblack@eecs.umich.edu 7637640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 7647397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7657397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 7667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 7677397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7687397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 7697397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 7707381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 7717639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7727397Sgblack@eecs.umich.edu Fpscr = fpscr; 7737380Sgblack@eecs.umich.edu FpDestP0.uw = result; 7747380Sgblack@eecs.umich.edu ''' 7757396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 7767380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 7777380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7787396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 7797396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 7807380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 7817380Sgblack@eecs.umich.edu 7827640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 7837397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7847397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7857397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 7867381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7877388Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 7887381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 7897639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7907397Sgblack@eecs.umich.edu Fpscr = fpscr; 7917380Sgblack@eecs.umich.edu ''' 7927396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 7937380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 7947380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7957396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 7967396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 7977380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 7987380Sgblack@eecs.umich.edu 7997640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 8007397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8017397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8027397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8037397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8047397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8057397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 8067381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8077639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8087397Sgblack@eecs.umich.edu Fpscr = fpscr; 8097380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8107380Sgblack@eecs.umich.edu ''' 8117396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 8127380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 8137380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8147396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 8157396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 8167380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 8177380Sgblack@eecs.umich.edu 8187640Sgblack@eecs.umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 8197397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8207397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8217397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8227380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8237381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8247387Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 8257381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 8267639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8277397Sgblack@eecs.umich.edu Fpscr = fpscr; 8287373Sgblack@eecs.umich.edu ''' 8297396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 8307373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 8317373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8327396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 8337396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 8347373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 8357373Sgblack@eecs.umich.edu 8367640Sgblack@eecs.umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 8377397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8387397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8397397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8407397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8417380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8427397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8437397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 8447381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8457639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8467397Sgblack@eecs.umich.edu Fpscr = fpscr; 8477373Sgblack@eecs.umich.edu FpDestP0.uw = result; 8487373Sgblack@eecs.umich.edu ''' 8497396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 8507373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 8517373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8527396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 8537396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 8547373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 8557373Sgblack@eecs.umich.edu 8567640Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 8577397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8587397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8597397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8607380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8617381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8627387Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 8637381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 8647639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8657397Sgblack@eecs.umich.edu Fpscr = fpscr; 8667373Sgblack@eecs.umich.edu ''' 8677396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 8687373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 8697373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8707396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 8717396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 8727373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 8737373Sgblack@eecs.umich.edu 8747640Sgblack@eecs.umich.edu vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 8757397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8767397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8777397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8787397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8797380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8807397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8817397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 8827381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8837639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8847397Sgblack@eecs.umich.edu Fpscr = fpscr; 8857373Sgblack@eecs.umich.edu FpDestP0.uw = result; 8867373Sgblack@eecs.umich.edu ''' 8877396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 8887373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 8897373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8907396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 8917396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 8927373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 8937374Sgblack@eecs.umich.edu 8947640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 8957397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8967397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8977397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8997397Sgblack@eecs.umich.edu double cDest = fixFpSFpDDest(Fpscr, FpOp1); 9007397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9017639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9027397Sgblack@eecs.umich.edu Fpscr = fpscr; 9037397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 9047397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 9057374Sgblack@eecs.umich.edu ''' 9067396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 9077374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 9087374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9097396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 9107396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 9117374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 9127374Sgblack@eecs.umich.edu 9137640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 9147397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9157397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9167397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9177397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9187397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9197397Sgblack@eecs.umich.edu FpDest = fixFpDFpSDest(Fpscr, cOp1); 9207381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9217639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9227397Sgblack@eecs.umich.edu Fpscr = fpscr; 9237374Sgblack@eecs.umich.edu ''' 9247396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 9257374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 9267374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9277396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 9287396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 9297374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 9307377Sgblack@eecs.umich.edu 9317640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 9327398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9337398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9347398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9357398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9367639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9377639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 9387398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9397639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9407398Sgblack@eecs.umich.edu Fpscr = fpscr; 9417398Sgblack@eecs.umich.edu ''' 9427398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 9437398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 9447398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9457398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 9467398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 9477398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 9487398Sgblack@eecs.umich.edu 9497640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 9507398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9517398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9527398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9537639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9547639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 9557398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9567639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9577398Sgblack@eecs.umich.edu Fpscr = fpscr; 9587398Sgblack@eecs.umich.edu ''' 9597398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 9607398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 9617398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9627398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 9637398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 9647398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 9657398Sgblack@eecs.umich.edu 9667640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 9677398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9687398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9697398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9707639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 9717639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 9727639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 31, 16,, 9737639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 9747639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 9757639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 9767639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9777398Sgblack@eecs.umich.edu Fpscr = fpscr; 9787398Sgblack@eecs.umich.edu ''' 9797398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 9807398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 9817398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9827398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 9837398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 9847398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 9857398Sgblack@eecs.umich.edu 9867640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 9877398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9887398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9897398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9907639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 9917639Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 9927639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, 15, 0, 9937639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 9947639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 9957639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 9967639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9977398Sgblack@eecs.umich.edu Fpscr = fpscr; 9987398Sgblack@eecs.umich.edu ''' 9997398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 10007398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 10017398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10027398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 10037398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 10047398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 10057398Sgblack@eecs.umich.edu 10067640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 10077377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10087397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 10097377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 10107377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10117377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 10127377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10137377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 10147377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10157377Sgblack@eecs.umich.edu } else { 10167389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 10177389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 10187396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 10197389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 10207396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 10217389Sgblack@eecs.umich.edu if (signal1 || signal2) 10227389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10237377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10247377Sgblack@eecs.umich.edu } 10257377Sgblack@eecs.umich.edu Fpscr = fpscr; 10267377Sgblack@eecs.umich.edu ''' 10277396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 10287377Sgblack@eecs.umich.edu { "code": vcmpSCode, 10297377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10307396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 10317396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 10327377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 10337377Sgblack@eecs.umich.edu 10347640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 10357397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 10367397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 10377377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10387397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 10397397Sgblack@eecs.umich.edu if (cDest == cOp1) { 10407377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10417397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 10427377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10437397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 10447377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10457377Sgblack@eecs.umich.edu } else { 10467389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 10477397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 10487397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 10497397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 10507397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 10517389Sgblack@eecs.umich.edu if (signal1 || signal2) 10527389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10537377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10547377Sgblack@eecs.umich.edu } 10557377Sgblack@eecs.umich.edu Fpscr = fpscr; 10567377Sgblack@eecs.umich.edu ''' 10577396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 10587377Sgblack@eecs.umich.edu { "code": vcmpDCode, 10597377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10607396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 10617396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 10627377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 10637377Sgblack@eecs.umich.edu 10647640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 10657377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 10677389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 10687389Sgblack@eecs.umich.edu assert(imm == 0); 10697377Sgblack@eecs.umich.edu if (FpDest == imm) { 10707377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10717377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 10727377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10737377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 10747377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10757377Sgblack@eecs.umich.edu } else { 10767389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 10777389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 10787396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 10797389Sgblack@eecs.umich.edu if (signal) 10807389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10817377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10827377Sgblack@eecs.umich.edu } 10837377Sgblack@eecs.umich.edu Fpscr = fpscr; 10847377Sgblack@eecs.umich.edu ''' 10857396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 10867377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 10877377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10887396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 10897396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 10907377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 10917377Sgblack@eecs.umich.edu 10927640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 10937389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 10947389Sgblack@eecs.umich.edu assert(imm == 0); 10957397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 10967377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10977397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 10987397Sgblack@eecs.umich.edu if (cDest == imm) { 10997377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11007397Sgblack@eecs.umich.edu } else if (cDest < imm) { 11017377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11027397Sgblack@eecs.umich.edu } else if (cDest > imm) { 11037377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11047377Sgblack@eecs.umich.edu } else { 11057389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 11067397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 11077397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 11087389Sgblack@eecs.umich.edu if (signal) 11097389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11107377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11117377Sgblack@eecs.umich.edu } 11127377Sgblack@eecs.umich.edu Fpscr = fpscr; 11137377Sgblack@eecs.umich.edu ''' 11147396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 11157377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 11167377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11177396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 11187396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 11197377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 11207389Sgblack@eecs.umich.edu 11217640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 11227389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11237397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 11247389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11257389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11267389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11277389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11287389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11297389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11307389Sgblack@eecs.umich.edu } else { 11317389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11327389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11337389Sgblack@eecs.umich.edu } 11347389Sgblack@eecs.umich.edu Fpscr = fpscr; 11357389Sgblack@eecs.umich.edu ''' 11367396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 11377389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 11387389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11397396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 11407396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 11417389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 11427389Sgblack@eecs.umich.edu 11437640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 11447397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 11457397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11467389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11477397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 11487397Sgblack@eecs.umich.edu if (cDest == cOp1) { 11497389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11507397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 11517389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11527397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 11537389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11547389Sgblack@eecs.umich.edu } else { 11557389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11567389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11577389Sgblack@eecs.umich.edu } 11587389Sgblack@eecs.umich.edu Fpscr = fpscr; 11597389Sgblack@eecs.umich.edu ''' 11607396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 11617389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 11627389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11637396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 11647396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 11657389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 11667389Sgblack@eecs.umich.edu 11677640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 11687389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11697397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 11707389Sgblack@eecs.umich.edu if (FpDest == imm) { 11717389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11727389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11737389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11747389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11757389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11767389Sgblack@eecs.umich.edu } else { 11777389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11787389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11797389Sgblack@eecs.umich.edu } 11807389Sgblack@eecs.umich.edu Fpscr = fpscr; 11817389Sgblack@eecs.umich.edu ''' 11827396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 11837389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 11847389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11857396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 11867396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 11877389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 11887389Sgblack@eecs.umich.edu 11897640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 11907397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11917389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11927397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 11937397Sgblack@eecs.umich.edu if (cDest == imm) { 11947389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11957397Sgblack@eecs.umich.edu } else if (cDest < imm) { 11967389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11977397Sgblack@eecs.umich.edu } else if (cDest > imm) { 11987389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11997389Sgblack@eecs.umich.edu } else { 12007389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12017389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12027389Sgblack@eecs.umich.edu } 12037389Sgblack@eecs.umich.edu Fpscr = fpscr; 12047389Sgblack@eecs.umich.edu ''' 12057396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 12067389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 12077389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12087396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 12097396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 12107389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 12117322Sgblack@eecs.umich.edu}}; 12127379Sgblack@eecs.umich.edu 12137379Sgblack@eecs.umich.edulet {{ 12147379Sgblack@eecs.umich.edu 12157379Sgblack@eecs.umich.edu header_output = "" 12167379Sgblack@eecs.umich.edu decoder_output = "" 12177379Sgblack@eecs.umich.edu exec_output = "" 12187379Sgblack@eecs.umich.edu 12197640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 12207397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12217397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12227397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12237381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12247379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 12257381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 12267639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12277397Sgblack@eecs.umich.edu Fpscr = fpscr; 12287379Sgblack@eecs.umich.edu ''' 12297396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 12307379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 12317379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12327396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 12337396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 12347379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 12357379Sgblack@eecs.umich.edu 12367640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 12377397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12387397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12397397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 12407397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12417397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 12427397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 12437381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 12447639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12457397Sgblack@eecs.umich.edu Fpscr = fpscr; 12467379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12477379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12487379Sgblack@eecs.umich.edu ''' 12497396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 12507379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 12517379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12527396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 12537396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 12547379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 12557379Sgblack@eecs.umich.edu 12567640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 12577397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12587397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12597397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12607381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12617379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 12627381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 12637639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12647397Sgblack@eecs.umich.edu Fpscr = fpscr; 12657379Sgblack@eecs.umich.edu ''' 12667396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 12677379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 12687379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12697396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 12707396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 12717379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 12727379Sgblack@eecs.umich.edu 12737640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 12747397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12757397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12767397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 12777397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12787397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 12797397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 12807381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 12817639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 12827397Sgblack@eecs.umich.edu Fpscr = fpscr; 12837379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12847379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12857379Sgblack@eecs.umich.edu ''' 12867396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 12877379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 12887379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12897396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 12907396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 12917379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 12927379Sgblack@eecs.umich.edu 12937640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 12947397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12957397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12967381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 12977639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 12987381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 12997639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13007397Sgblack@eecs.umich.edu Fpscr = fpscr; 13017379Sgblack@eecs.umich.edu ''' 13027396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 13037379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 13047379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13057396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 13067396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 13077379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 13087379Sgblack@eecs.umich.edu 13097640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 13107397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13117379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13127397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13137381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 13147639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 13157397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 13167639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13177397Sgblack@eecs.umich.edu Fpscr = fpscr; 13187397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 13197397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 13207379Sgblack@eecs.umich.edu ''' 13217396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 13227379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 13237379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13247396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 13257396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 13267379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 13277379Sgblack@eecs.umich.edu 13287640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 13297397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13317381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 13327639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 13337381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 13347639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13357397Sgblack@eecs.umich.edu Fpscr = fpscr; 13367379Sgblack@eecs.umich.edu ''' 13377396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 13387379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 13397379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13407396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 13417396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 13427379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 13437379Sgblack@eecs.umich.edu 13447640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 13457397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13467379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13477397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13487381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 13497639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 13507397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 13517639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13527397Sgblack@eecs.umich.edu Fpscr = fpscr; 13537397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 13547397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 13557379Sgblack@eecs.umich.edu ''' 13567396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 13577379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 13587379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13597396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 13607396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 13617379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 13627379Sgblack@eecs.umich.edu 13637640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 13647397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13657397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13667397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13677381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13687379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 13697381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 13707639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13717397Sgblack@eecs.umich.edu Fpscr = fpscr; 13727379Sgblack@eecs.umich.edu ''' 13737379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 13747396Sgblack@eecs.umich.edu "FpRegRegImmOp", 13757379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 13767379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13777396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 13787396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 13797379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 13807379Sgblack@eecs.umich.edu 13817640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 13827397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13837397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 13847397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13857397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13867397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13877397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 13887381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 13897639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 13907397Sgblack@eecs.umich.edu Fpscr = fpscr; 13917379Sgblack@eecs.umich.edu FpDestP0.uw = result; 13927379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 13937379Sgblack@eecs.umich.edu ''' 13947379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 13957396Sgblack@eecs.umich.edu "FpRegRegImmOp", 13967379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 13977379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13987396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 13997396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 14007379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 14017379Sgblack@eecs.umich.edu 14027640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 14037397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14047397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14057397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14067381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14077379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 14087381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 14097639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14107397Sgblack@eecs.umich.edu Fpscr = fpscr; 14117379Sgblack@eecs.umich.edu ''' 14127379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 14137396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14147379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 14157379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14167396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 14177396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 14187379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 14197379Sgblack@eecs.umich.edu 14207640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 14217397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14227397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 14237397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14247397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14257397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 14267397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 14277381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 14287639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14297397Sgblack@eecs.umich.edu Fpscr = fpscr; 14307379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 14317379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 14327379Sgblack@eecs.umich.edu ''' 14337379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 14347396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14357379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 14367379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14377396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 14387396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 14397379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 14407379Sgblack@eecs.umich.edu 14417640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 14427397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14437397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14447381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 14457639Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 14467381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14477639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14487397Sgblack@eecs.umich.edu Fpscr = fpscr; 14497379Sgblack@eecs.umich.edu ''' 14507379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 14517396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14527379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 14537379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14547396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 14557396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 14567379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 14577379Sgblack@eecs.umich.edu 14587640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 14597397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14607379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14617397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14627381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14637639Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 14647397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14657639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14667397Sgblack@eecs.umich.edu Fpscr = fpscr; 14677397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 14687397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 14697379Sgblack@eecs.umich.edu ''' 14707379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 14717396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14727379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 14737379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14747396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 14757396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 14767379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 14777379Sgblack@eecs.umich.edu 14787640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 14797397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14807397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14817381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 14827639Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 14837381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14847639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14857397Sgblack@eecs.umich.edu Fpscr = fpscr; 14867379Sgblack@eecs.umich.edu ''' 14877379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 14887396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14897379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 14907379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14917396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 14927396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 14937379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 14947379Sgblack@eecs.umich.edu 14957640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 14967397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14977379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14987397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14997381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15007639Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 15017397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15027639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15037397Sgblack@eecs.umich.edu Fpscr = fpscr; 15047397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 15057397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 15067379Sgblack@eecs.umich.edu ''' 15077379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 15087396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15097379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 15107379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15117396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 15127396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 15137379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 15147379Sgblack@eecs.umich.edu}}; 1515