fp.isa revision 7639
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 312110SRekai.GonzalezAlberquilla@arm.com// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247119Sgblack@eecs.umich.edu// this software without specific prior written permission. 257119Sgblack@eecs.umich.edu// 267119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119Sgblack@eecs.umich.edu// 387119Sgblack@eecs.umich.edu// Authors: Gabe Black 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.eduoutput header {{ 417119Sgblack@eecs.umich.edu 427119Sgblack@eecs.umich.edutemplate <class Micro> 437119Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447646Sgene.wu@arm.com{ 4510196SCurtis.Dunham@arm.com public: 467646Sgene.wu@arm.com VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477646Sgene.wu@arm.com IntRegIndex _op1, bool _wide) : 487646Sgene.wu@arm.com VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497646Sgene.wu@arm.com { 507646Sgene.wu@arm.com numMicroops = machInst.fpscrLen + 1; 517646Sgene.wu@arm.com assert(numMicroops > 1); 527646Sgene.wu@arm.com microOps = new StaticInstPtr[numMicroops]; 537646Sgene.wu@arm.com for (unsigned i = 0; i < numMicroops; i++) { 5410196SCurtis.Dunham@arm.com VfpMicroMode mode = VfpMicroop; 557646Sgene.wu@arm.com if (i == 0) 567646Sgene.wu@arm.com mode = VfpFirstMicroop; 577646Sgene.wu@arm.com else if (i == numMicroops - 1) 587646Sgene.wu@arm.com mode = VfpLastMicroop; 597646Sgene.wu@arm.com microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607646Sgene.wu@arm.com nextIdxs(_dest, _op1); 617646Sgene.wu@arm.com } 627646Sgene.wu@arm.com } 637646Sgene.wu@arm.com 6410196SCurtis.Dunham@arm.com %(BasicExecPanic)s 657646Sgene.wu@arm.com}; 667646Sgene.wu@arm.com 677646Sgene.wu@arm.comtemplate <class VfpOp> 687646Sgene.wu@arm.comstatic StaticInstPtr 697646Sgene.wu@arm.comdecodeVfpRegRegOp(ExtMachInst machInst, 707646Sgene.wu@arm.com IntRegIndex dest, IntRegIndex op1, bool wide) 717646Sgene.wu@arm.com{ 727646Sgene.wu@arm.com if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737205Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 7410196SCurtis.Dunham@arm.com } else { 757205Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767205Sgblack@eecs.umich.edu } 777205Sgblack@eecs.umich.edu} 787205Sgblack@eecs.umich.edu 797205Sgblack@eecs.umich.edutemplate <class Micro> 807205Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817205Sgblack@eecs.umich.edu{ 827205Sgblack@eecs.umich.edu public: 837205Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847205Sgblack@eecs.umich.edu bool _wide) : 857205Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867205Sgblack@eecs.umich.edu { 877205Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887205Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897205Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 908442Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 918442Sgblack@eecs.umich.edu if (i == 0) 927205Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937205Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947205Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957205Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967205Sgblack@eecs.umich.edu nextIdxs(_dest); 977205Sgblack@eecs.umich.edu } 987205Sgblack@eecs.umich.edu } 997205Sgblack@eecs.umich.edu 1007205Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017597Sminkyu.jeong@arm.com}; 1027597Sminkyu.jeong@arm.com 1037205Sgblack@eecs.umich.edutemplate <class VfpOp> 1047205Sgblack@eecs.umich.edustatic StaticInstPtr 1057205Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067205Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077205Sgblack@eecs.umich.edu{ 1087205Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097205Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 11010196SCurtis.Dunham@arm.com } else { 1117205Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127205Sgblack@eecs.umich.edu } 1137205Sgblack@eecs.umich.edu} 1147205Sgblack@eecs.umich.edu 1157205Sgblack@eecs.umich.edutemplate <class Micro> 1167205Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177205Sgblack@eecs.umich.edu{ 1187205Sgblack@eecs.umich.edu public: 1197205Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207205Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217205Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227205Sgblack@eecs.umich.edu { 1237205Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247205Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257205Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1268442Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1278442Sgblack@eecs.umich.edu if (i == 0) 1287205Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297597Sminkyu.jeong@arm.com else if (i == numMicroops - 1) 1307597Sminkyu.jeong@arm.com mode = VfpLastMicroop; 1317205Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327205Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337205Sgblack@eecs.umich.edu } 1347205Sgblack@eecs.umich.edu } 1357205Sgblack@eecs.umich.edu 1367205Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377205Sgblack@eecs.umich.edu}; 1387205Sgblack@eecs.umich.edu 13910196SCurtis.Dunham@arm.comtemplate <class VfpOp> 1407205Sgblack@eecs.umich.edustatic StaticInstPtr 1417205Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427205Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437205Sgblack@eecs.umich.edu{ 1447205Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457205Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467205Sgblack@eecs.umich.edu } else { 1477205Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487205Sgblack@eecs.umich.edu } 1497205Sgblack@eecs.umich.edu} 1508442Sgblack@eecs.umich.edu 1518442Sgblack@eecs.umich.edutemplate <class Micro> 1527205Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537205Sgblack@eecs.umich.edu{ 1547205Sgblack@eecs.umich.edu public: 1557205Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567205Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577205Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587205Sgblack@eecs.umich.edu { 1597205Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607205Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617205Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627205Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637205Sgblack@eecs.umich.edu if (i == 0) 1647119Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 16510196SCurtis.Dunham@arm.com else if (i == numMicroops - 1) 1667119Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677119Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687119Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697119Sgblack@eecs.umich.edu } 1707119Sgblack@eecs.umich.edu } 1717119Sgblack@eecs.umich.edu 1727119Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737119Sgblack@eecs.umich.edu}; 1747119Sgblack@eecs.umich.edu 1757119Sgblack@eecs.umich.edutemplate <class VfpOp> 1767119Sgblack@eecs.umich.edustatic StaticInstPtr 1777119Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1788442Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797119Sgblack@eecs.umich.edu{ 1807119Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817119Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827119Sgblack@eecs.umich.edu } else { 1837119Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847119Sgblack@eecs.umich.edu } 1857597Sminkyu.jeong@arm.com} 1867597Sminkyu.jeong@arm.com}}; 1877119Sgblack@eecs.umich.edu 1887119Sgblack@eecs.umich.edulet {{ 1897119Sgblack@eecs.umich.edu 1907119Sgblack@eecs.umich.edu header_output = "" 1917119Sgblack@eecs.umich.edu decoder_output = "" 1927119Sgblack@eecs.umich.edu exec_output = "" 1937639Sgblack@eecs.umich.edu 1947639Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1957639Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 19610196SCurtis.Dunham@arm.com "predicate_test": predicateTest }, []) 1977639Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrIop); 1987639Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 1997639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2007639Sgblack@eecs.umich.edu 2017639Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2027639Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 2037639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047639Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2057639Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2067639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2077639Sgblack@eecs.umich.edu 2087639Sgblack@eecs.umich.edu vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);" 2097639Sgblack@eecs.umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 2107639Sgblack@eecs.umich.edu { "code": vmrsApsrCode, 2117639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2128444Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 2137639Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 2147639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrIop); 2157639Sgblack@eecs.umich.edu 2167639Sgblack@eecs.umich.edu vmovImmSCode = ''' 2177639Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2187639Sgblack@eecs.umich.edu ''' 2198072SGiacomo.Gabrielli@arm.com vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2208072SGiacomo.Gabrielli@arm.com { "code": vmovImmSCode, 2217639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2227639Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2237639Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2247639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2257639Sgblack@eecs.umich.edu 2267639Sgblack@eecs.umich.edu vmovImmDCode = ''' 2277120Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 22810196SCurtis.Dunham@arm.com FpDestP1.uw = bits(imm, 63, 32); 2297120Sgblack@eecs.umich.edu ''' 2307120Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2317120Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2327120Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2337120Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2347120Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2357120Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2367120Sgblack@eecs.umich.edu 2377120Sgblack@eecs.umich.edu vmovImmQCode = ''' 2387120Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2397120Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2407120Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2417120Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2427120Sgblack@eecs.umich.edu ''' 2437120Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2447120Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2458442Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2468442Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2477120Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2487120Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2497120Sgblack@eecs.umich.edu 2507120Sgblack@eecs.umich.edu vmovRegSCode = ''' 2517120Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2527597Sminkyu.jeong@arm.com ''' 2537597Sminkyu.jeong@arm.com vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 2547120Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2557120Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2567120Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 2577120Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 2587120Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2597120Sgblack@eecs.umich.edu 2607639Sgblack@eecs.umich.edu vmovRegDCode = ''' 2617639Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2627639Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 26310196SCurtis.Dunham@arm.com ''' 2647639Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 2657639Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2667639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2677639Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 2687639Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 2697639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2707639Sgblack@eecs.umich.edu 2717639Sgblack@eecs.umich.edu vmovRegQCode = ''' 2727639Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2737639Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2747639Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2757639Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2767639Sgblack@eecs.umich.edu ''' 2777639Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 2787639Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2797639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2807639Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 2817639Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 2827639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2838444Sgblack@eecs.umich.edu 2848444Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 2857639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub); 2867639Sgblack@eecs.umich.edu ''' 2877639Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 2887639Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2897639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2908072SGiacomo.Gabrielli@arm.com header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2918072SGiacomo.Gabrielli@arm.com decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2927639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2937639Sgblack@eecs.umich.edu 2947639Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 2957639Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh); 2967639Sgblack@eecs.umich.edu ''' 2977639Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 2987303Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 29910196SCurtis.Dunham@arm.com "predicate_test": predicateTest }, []) 3007303Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3017303Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3027303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3037303Sgblack@eecs.umich.edu 3047303Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 3057303Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 3067303Sgblack@eecs.umich.edu ''' 3077303Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3087303Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3097303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3107303Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3117303Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3127303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3137303Sgblack@eecs.umich.edu 3147303Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 3157303Sgblack@eecs.umich.edu assert(imm < 4); 3167303Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8); 3177303Sgblack@eecs.umich.edu ''' 3188442Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3198442Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3207303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3217303Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3227303Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3237303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3247303Sgblack@eecs.umich.edu 3257303Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 3267303Sgblack@eecs.umich.edu assert(imm < 2); 3277303Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16); 3287303Sgblack@eecs.umich.edu ''' 3297597Sminkyu.jeong@arm.com vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3307597Sminkyu.jeong@arm.com { "code": vmovRegCoreUHCode, 3317303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3327303Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3337303Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3347303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3357303Sgblack@eecs.umich.edu 3367303Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 3377303Sgblack@eecs.umich.edu assert(imm < 4); 33810196SCurtis.Dunham@arm.com Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8)); 3397303Sgblack@eecs.umich.edu ''' 3407303Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3417303Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3427303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3437303Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3447303Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3457303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3467303Sgblack@eecs.umich.edu 3477303Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 3487303Sgblack@eecs.umich.edu assert(imm < 2); 3497303Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16)); 3507303Sgblack@eecs.umich.edu ''' 3517303Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 3527303Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3537303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3547303Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3558442Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3568442Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3577303Sgblack@eecs.umich.edu 3587597Sminkyu.jeong@arm.com vmovRegCoreWCode = ''' 3597597Sminkyu.jeong@arm.com Dest = FpOp1.uw; 3607303Sgblack@eecs.umich.edu ''' 3617408Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 3627303Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3637303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3647303Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 3657303Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 3667120Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 36710196SCurtis.Dunham@arm.com 3687120Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 3697120Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3707120Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3717120Sgblack@eecs.umich.edu ''' 3727120Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 3737120Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3747120Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3757120Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3767120Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3777120Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3787120Sgblack@eecs.umich.edu 3797120Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 3807120Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3817120Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3827120Sgblack@eecs.umich.edu ''' 3837120Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 3848442Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3858442Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3867120Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3877597Sminkyu.jeong@arm.com decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3887597Sminkyu.jeong@arm.com exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3897120Sgblack@eecs.umich.edu}}; 3907120Sgblack@eecs.umich.edu 3917120Sgblack@eecs.umich.edulet {{ 3927120Sgblack@eecs.umich.edu 3937120Sgblack@eecs.umich.edu header_output = "" 3947120Sgblack@eecs.umich.edu decoder_output = "" 3957639Sgblack@eecs.umich.edu exec_output = "" 3967639Sgblack@eecs.umich.edu 3977639Sgblack@eecs.umich.edu singleCode = ''' 39810196SCurtis.Dunham@arm.com FPSCR fpscr = Fpscr; 3997639Sgblack@eecs.umich.edu FpDest = %(op)s; 4007639Sgblack@eecs.umich.edu Fpscr = fpscr; 4017639Sgblack@eecs.umich.edu ''' 4027639Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4037639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4047639Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4057639Sgblack@eecs.umich.edu doubleCode = ''' 4067639Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 4077639Sgblack@eecs.umich.edu double dest = %(op)s; 4087639Sgblack@eecs.umich.edu Fpscr = fpscr; 4097639Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 4107639Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 4117639Sgblack@eecs.umich.edu ''' 4127639Sgblack@eecs.umich.edu doubleBinOp = ''' 4137639Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 4147639Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 4157639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 4168444Sgblack@eecs.umich.edu ''' 4178444Sgblack@eecs.umich.edu doubleUnaryOp = ''' 4187639Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, 4198072SGiacomo.Gabrielli@arm.com fpscr.fz, fpscr.rMode) 4208072SGiacomo.Gabrielli@arm.com ''' 4217639Sgblack@eecs.umich.edu 4227639Sgblack@eecs.umich.edu def buildBinFpOp(name, Name, base, singleOp, doubleOp): 4237639Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4247639Sgblack@eecs.umich.edu 4257639Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4267639Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4277119Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 42810196SCurtis.Dunham@arm.com { "code": code, "predicate_test": predicateTest }, []) 4297119Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4307119Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4317119Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4327119Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4337119Sgblack@eecs.umich.edu 4347119Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4357119Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4367119Sgblack@eecs.umich.edu 4377119Sgblack@eecs.umich.edu for iop in sIop, dIop: 4387119Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4397119Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4407119Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 44111303Ssteve.reinhardt@amd.com 44211303Ssteve.reinhardt@amd.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "fpAddS", "fpAddD") 4437119Sgblack@eecs.umich.edu buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "fpSubS", "fpSubD") 4447597Sminkyu.jeong@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "fpDivS", "fpDivD") 4457597Sminkyu.jeong@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "fpMulS", "fpMulD") 4467119Sgblack@eecs.umich.edu 4477119Sgblack@eecs.umich.edu def buildUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4487119Sgblack@eecs.umich.edu if doubleOp is None: 4497119Sgblack@eecs.umich.edu doubleOp = singleOp 4507119Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4517119Sgblack@eecs.umich.edu 4527639Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 4537639Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4547639Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 45510196SCurtis.Dunham@arm.com { "code": code, "predicate_test": predicateTest }, []) 4567639Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 4577639Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4587639Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4597639Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4608207SAli.Saidi@ARM.com 4618207SAli.Saidi@ARM.com declareTempl = eval(base + "Declare"); 4627639Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4637639Sgblack@eecs.umich.edu 4647639Sgblack@eecs.umich.edu for iop in sIop, dIop: 4657639Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4667639Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4677639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 46811303Ssteve.reinhardt@amd.com 4697639Sgblack@eecs.umich.edu buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "sqrtf", "sqrt") 4708072SGiacomo.Gabrielli@arm.com 4718072SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4727639Sgblack@eecs.umich.edu if doubleOp is None: 4737639Sgblack@eecs.umich.edu doubleOp = singleOp 4747639Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4757639Sgblack@eecs.umich.edu 4767639Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4777639Sgblack@eecs.umich.edu { "code": singleCode % { "op": singleOp }, 4787119Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4797119Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 48010196SCurtis.Dunham@arm.com { "code": doubleCode % { "op": doubleOp }, 4817119Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4827119Sgblack@eecs.umich.edu 4837119Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4847119Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4857119Sgblack@eecs.umich.edu 4867119Sgblack@eecs.umich.edu for iop in sIop, dIop: 4877119Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4887119Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4897119Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4907119Sgblack@eecs.umich.edu 4918442Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", 4927119Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") 4937119Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", 4947119Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") 4957119Sgblack@eecs.umich.edu}}; 4967119Sgblack@eecs.umich.edu 4977119Sgblack@eecs.umich.edulet {{ 4987119Sgblack@eecs.umich.edu 4997119Sgblack@eecs.umich.edu header_output = "" 5007119Sgblack@eecs.umich.edu decoder_output = "" 5017119Sgblack@eecs.umich.edu exec_output = "" 5027119Sgblack@eecs.umich.edu 5037119Sgblack@eecs.umich.edu vmlaSCode = ''' 5047119Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5057119Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5067639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5077639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 5087639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 50910196SCurtis.Dunham@arm.com Fpscr = fpscr; 5107639Sgblack@eecs.umich.edu ''' 5117639Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5127639Sgblack@eecs.umich.edu { "code": vmlaSCode, 5137639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5147639Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5157639Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5167639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5177639Sgblack@eecs.umich.edu 5187639Sgblack@eecs.umich.edu vmlaDCode = ''' 5197639Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5207639Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5217639Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5227639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5237639Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5247639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 5257639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5267639Sgblack@eecs.umich.edu Fpscr = fpscr; 5277639Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5287639Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5297639Sgblack@eecs.umich.edu ''' 5307639Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 5317639Sgblack@eecs.umich.edu { "code": vmlaDCode, 5327639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5337639Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 5347639Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 5357639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 5367120Sgblack@eecs.umich.edu 5377120Sgblack@eecs.umich.edu vmlsSCode = ''' 53810196SCurtis.Dunham@arm.com FPSCR fpscr = Fpscr; 5397120Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5407120Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5417712Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 5427120Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5437120Sgblack@eecs.umich.edu Fpscr = fpscr; 5447120Sgblack@eecs.umich.edu ''' 5457639Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 5467639Sgblack@eecs.umich.edu { "code": vmlsSCode, 5477639Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 54810196SCurtis.Dunham@arm.com header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 5497639Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 5507639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 5517712Sgblack@eecs.umich.edu 5527639Sgblack@eecs.umich.edu vmlsDCode = ''' 5537639Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5547639Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5557303Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5567303Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 55710196SCurtis.Dunham@arm.com double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5587303Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 5597303Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5607303Sgblack@eecs.umich.edu Fpscr = fpscr; 5617303Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5627303Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5637303Sgblack@eecs.umich.edu ''' 5647303Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 5657303Sgblack@eecs.umich.edu { "code": vmlsDCode, 5667303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5677303Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 5687303Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 5697303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 5707303Sgblack@eecs.umich.edu 5717303Sgblack@eecs.umich.edu vnmlaSCode = ''' 5727303Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5737303Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5747303Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 5757303Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 5767303Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 5777303Sgblack@eecs.umich.edu Fpscr = fpscr; 5787303Sgblack@eecs.umich.edu ''' 5797291Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 5807291Sgblack@eecs.umich.edu { "code": vnmlaSCode, 5817291Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5827291Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 5837291Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 5847291Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 5857291Sgblack@eecs.umich.edu 5867291Sgblack@eecs.umich.edu vnmlaDCode = ''' 5877291Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5887291Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5897291Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5907291Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 5917291Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 5927291Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 5937291Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 5947291Sgblack@eecs.umich.edu Fpscr = fpscr; 5957291Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5967291Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5977291Sgblack@eecs.umich.edu ''' 5987291Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 5997312Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6007312Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6017312Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 6027312Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 6037312Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6047312Sgblack@eecs.umich.edu 6057312Sgblack@eecs.umich.edu vnmlsSCode = ''' 6067312Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6077312Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6087312Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6097312Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 6107312Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6117312Sgblack@eecs.umich.edu Fpscr = fpscr; 6127312Sgblack@eecs.umich.edu ''' 6137312Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 6147312Sgblack@eecs.umich.edu { "code": vnmlsSCode, 6157312Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6167312Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 6177312Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 6187312Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 6197205Sgblack@eecs.umich.edu 6207205Sgblack@eecs.umich.edu vnmlsDCode = ''' 6217205Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6227205Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6237205Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6247205Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6257205Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6267205Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 6277205Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6287205Sgblack@eecs.umich.edu Fpscr = fpscr; 6297205Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6307205Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6317205Sgblack@eecs.umich.edu ''' 6327205Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 6337205Sgblack@eecs.umich.edu { "code": vnmlsDCode, 6347205Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6357205Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 6367205Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 6377205Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 6387205Sgblack@eecs.umich.edu 6397279Sgblack@eecs.umich.edu vnmulSCode = ''' 6407279Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6417279Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 6427279Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6437279Sgblack@eecs.umich.edu Fpscr = fpscr; 6447279Sgblack@eecs.umich.edu ''' 6457279Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 6467279Sgblack@eecs.umich.edu { "code": vnmulSCode, 6477279Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6487279Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 6497279Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 6507279Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 6517279Sgblack@eecs.umich.edu 6527279Sgblack@eecs.umich.edu vnmulDCode = ''' 6537279Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6547279Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6557279Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6567279Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 6577279Sgblack@eecs.umich.edu fpscr.rMode); 6587279Sgblack@eecs.umich.edu Fpscr = fpscr; 6597279Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6607303Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6617303Sgblack@eecs.umich.edu ''' 6627303Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 6637303Sgblack@eecs.umich.edu { "code": vnmulDCode, 6647303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6657303Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 6667303Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 6677303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 6687303Sgblack@eecs.umich.edu}}; 6697303Sgblack@eecs.umich.edu 6707303Sgblack@eecs.umich.edulet {{ 6717303Sgblack@eecs.umich.edu 6727303Sgblack@eecs.umich.edu header_output = "" 6737303Sgblack@eecs.umich.edu decoder_output = "" 6747303Sgblack@eecs.umich.edu exec_output = "" 6757303Sgblack@eecs.umich.edu 6767303Sgblack@eecs.umich.edu vcvtUIntFpSCode = ''' 6777303Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6787303Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 6797303Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 6807303Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 6817119Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6827119Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 6837119Sgblack@eecs.umich.edu Fpscr = fpscr; 6847119Sgblack@eecs.umich.edu ''' 6857119Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 6867119Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 6877119Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6887119Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 6897119Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 6907119Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 6917119Sgblack@eecs.umich.edu 6927119Sgblack@eecs.umich.edu vcvtUIntFpDCode = ''' 6937119Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6947119Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 6957119Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 6967119Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0.uw; 6977119Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 69810037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 69910037SARM gem5 Developers Fpscr = fpscr; 70010037SARM gem5 Developers FpDestP0.uw = dblLow(cDest); 70110037SARM gem5 Developers FpDestP1.uw = dblHi(cDest); 70210037SARM gem5 Developers ''' 7037119Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 7047119Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 7057119Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7067303Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 7077303Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 7087303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 7097303Sgblack@eecs.umich.edu 7107303Sgblack@eecs.umich.edu vcvtSIntFpSCode = ''' 7117303Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7127303Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7137303Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 7147303Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 7157303Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7167303Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7177303Sgblack@eecs.umich.edu Fpscr = fpscr; 7187303Sgblack@eecs.umich.edu ''' 7197303Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 7207303Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 7217303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7227303Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 7237303Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 7247303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 7257303Sgblack@eecs.umich.edu 7267303Sgblack@eecs.umich.edu vcvtSIntFpDCode = ''' 7277646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 7287279Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7297279Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 7307279Sgblack@eecs.umich.edu double cDest = FpOp1P0.sw; 7317279Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7327279Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7337279Sgblack@eecs.umich.edu Fpscr = fpscr; 7347279Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7357279Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7367279Sgblack@eecs.umich.edu ''' 7377279Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 7387279Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 7397279Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7407279Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 7417279Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 7427279Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 7437279Sgblack@eecs.umich.edu 7447279Sgblack@eecs.umich.edu vcvtFpUIntSRCode = ''' 7457279Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7467279Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7477279Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 7487279Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7497279Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 7507646Sgene.wu@arm.com __asm__ __volatile__("" :: "m" (FpDest.uw)); 7517119Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 7527119Sgblack@eecs.umich.edu Fpscr = fpscr; 7537119Sgblack@eecs.umich.edu ''' 7547119Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 7557119Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 7567119Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7577119Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 7587119Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 7597119Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 7607119Sgblack@eecs.umich.edu 7617119Sgblack@eecs.umich.edu vcvtFpUIntDRCode = ''' 7627119Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7637119Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 7647119Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 7657119Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7667119Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 7677119Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 7687119Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 76910037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 77010037SARM gem5 Developers Fpscr = fpscr; 77110037SARM gem5 Developers FpDestP0.uw = result; 77210037SARM gem5 Developers ''' 77310037SARM gem5 Developers vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 7747119Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 7757119Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7767119Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 7777646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 7787646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 7797646Sgene.wu@arm.com 7807646Sgene.wu@arm.com vcvtFpSIntSRCode = ''' 7817646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 7827646Sgene.wu@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 7837646Sgene.wu@arm.com vfpFlushToZero(fpscr, FpOp1); 7847646Sgene.wu@arm.com __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7857646Sgene.wu@arm.com FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 7867646Sgene.wu@arm.com __asm__ __volatile__("" :: "m" (FpDest.sw)); 7877646Sgene.wu@arm.com finishVfp(fpscr, state, fpscr.fz); 7887646Sgene.wu@arm.com Fpscr = fpscr; 7897646Sgene.wu@arm.com ''' 7907646Sgene.wu@arm.com vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 7917646Sgene.wu@arm.com { "code": vcvtFpSIntSRCode, 7927646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 7937646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 7947646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 7957646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 7967646Sgene.wu@arm.com 7977646Sgene.wu@arm.com vcvtFpSIntDRCode = ''' 7987646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 7997646Sgene.wu@arm.com double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8007646Sgene.wu@arm.com vfpFlushToZero(fpscr, cOp1); 8017646Sgene.wu@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 8027646Sgene.wu@arm.com __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8037646Sgene.wu@arm.com int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 8047646Sgene.wu@arm.com __asm__ __volatile__("" :: "m" (result)); 8057646Sgene.wu@arm.com finishVfp(fpscr, state, fpscr.fz); 8067646Sgene.wu@arm.com Fpscr = fpscr; 8077646Sgene.wu@arm.com FpDestP0.uw = result; 8087646Sgene.wu@arm.com ''' 8097646Sgene.wu@arm.com vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 8107646Sgene.wu@arm.com { "code": vcvtFpSIntDRCode, 8117646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 8127646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 8137646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 8147646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 8157646Sgene.wu@arm.com 8167646Sgene.wu@arm.com vcvtFpUIntSCode = ''' 8177646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 8187646Sgene.wu@arm.com vfpFlushToZero(fpscr, FpOp1); 81910037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 82010037SARM gem5 Developers fesetround(FeRoundZero); 82110037SARM gem5 Developers __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 82210037SARM gem5 Developers FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 82310037SARM gem5 Developers __asm__ __volatile__("" :: "m" (FpDest.uw)); 8247646Sgene.wu@arm.com finishVfp(fpscr, state, fpscr.fz); 8257646Sgene.wu@arm.com Fpscr = fpscr; 8267646Sgene.wu@arm.com ''' 8277646Sgene.wu@arm.com vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 8287646Sgene.wu@arm.com { "code": vcvtFpUIntSCode, 8297646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 8307646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 8317646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 8327646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 8337646Sgene.wu@arm.com 8347646Sgene.wu@arm.com vcvtFpUIntDCode = ''' 8357646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 8367646Sgene.wu@arm.com double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8377646Sgene.wu@arm.com vfpFlushToZero(fpscr, cOp1); 8387646Sgene.wu@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 8397646Sgene.wu@arm.com fesetround(FeRoundZero); 8407646Sgene.wu@arm.com __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8417646Sgene.wu@arm.com uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 8427646Sgene.wu@arm.com __asm__ __volatile__("" :: "m" (result)); 8437646Sgene.wu@arm.com finishVfp(fpscr, state, fpscr.fz); 84410037SARM gem5 Developers Fpscr = fpscr; 84510037SARM gem5 Developers FpDestP0.uw = result; 84610037SARM gem5 Developers ''' 84710037SARM gem5 Developers vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 84810037SARM gem5 Developers { "code": vcvtFpUIntDCode, 8497646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 8507646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 8517646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 8527119Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 8537119Sgblack@eecs.umich.edu 8547119Sgblack@eecs.umich.edu vcvtFpSIntSCode = ''' 8557119Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8567119Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8577119Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8587119Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8597119Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8607291Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 86110184SCurtis.Dunham@arm.com __asm__ __volatile__("" :: "m" (FpDest.sw)); 8628140SMatt.Horsnell@arm.com finishVfp(fpscr, state, fpscr.fz); 8638140SMatt.Horsnell@arm.com Fpscr = fpscr; 8648140SMatt.Horsnell@arm.com ''' 8657291Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 8667291Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 8677848SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 8687848SAli.Saidi@ARM.com header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 8697848SAli.Saidi@ARM.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 8707848SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 8717848SAli.Saidi@ARM.com 8727646Sgene.wu@arm.com vcvtFpSIntDCode = ''' 8738140SMatt.Horsnell@arm.com FPSCR fpscr = Fpscr; 8748140SMatt.Horsnell@arm.com double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8758140SMatt.Horsnell@arm.com vfpFlushToZero(fpscr, cOp1); 8768140SMatt.Horsnell@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 8778140SMatt.Horsnell@arm.com fesetround(FeRoundZero); 8788140SMatt.Horsnell@arm.com __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8798140SMatt.Horsnell@arm.com int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 8808140SMatt.Horsnell@arm.com __asm__ __volatile__("" :: "m" (result)); 8818140SMatt.Horsnell@arm.com finishVfp(fpscr, state, fpscr.fz); 8828140SMatt.Horsnell@arm.com Fpscr = fpscr; 8838140SMatt.Horsnell@arm.com FpDestP0.uw = result; 88410666SAli.Saidi@ARM.com ''' 8858140SMatt.Horsnell@arm.com vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 8867646Sgene.wu@arm.com { "code": vcvtFpSIntDCode, 8877291Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8887291Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 8897291Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 8907312Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 89110184SCurtis.Dunham@arm.com 8927312Sgblack@eecs.umich.edu vcvtFpSFpDCode = ''' 8937312Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8947312Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8957312Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8967312Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8977848SAli.Saidi@ARM.com double cDest = fixFpSFpDDest(Fpscr, FpOp1); 8987848SAli.Saidi@ARM.com __asm__ __volatile__("" :: "m" (cDest)); 8997848SAli.Saidi@ARM.com finishVfp(fpscr, state, fpscr.fz); 9007848SAli.Saidi@ARM.com Fpscr = fpscr; 9017848SAli.Saidi@ARM.com FpDestP0.uw = dblLow(cDest); 9027646Sgene.wu@arm.com FpDestP1.uw = dblHi(cDest); 9037646Sgene.wu@arm.com ''' 9047646Sgene.wu@arm.com vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 9057646Sgene.wu@arm.com { "code": vcvtFpSFpDCode, 9067724SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 90710666SAli.Saidi@ARM.com header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 9087646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 9097646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 9107646Sgene.wu@arm.com 9117312Sgblack@eecs.umich.edu vcvtFpDFpSCode = ''' 9127312Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9137312Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9147205Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 91510184SCurtis.Dunham@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 9167205Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9177205Sgblack@eecs.umich.edu FpDest = fixFpDFpSDest(Fpscr, cOp1); 9187205Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9197205Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9207205Sgblack@eecs.umich.edu Fpscr = fpscr; 9217848SAli.Saidi@ARM.com ''' 9227848SAli.Saidi@ARM.com vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 9237848SAli.Saidi@ARM.com { "code": vcvtFpDFpSCode, 9247848SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 9257848SAli.Saidi@ARM.com header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 9267205Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 9277205Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 9287205Sgblack@eecs.umich.edu 9297279Sgblack@eecs.umich.edu vcvtFpHTFpSCode = ''' 93010184SCurtis.Dunham@arm.com FPSCR fpscr = Fpscr; 9317279Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9327279Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9337279Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9347279Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9357279Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 9367279Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9377279Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9387848SAli.Saidi@ARM.com Fpscr = fpscr; 9397848SAli.Saidi@ARM.com ''' 9407848SAli.Saidi@ARM.com vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 9417848SAli.Saidi@ARM.com { "code": vcvtFpHTFpSCode, 9427848SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 9437646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 9447646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 9457646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 9467646Sgene.wu@arm.com 94710666SAli.Saidi@ARM.com vcvtFpHBFpSCode = ''' 9487724SAli.Saidi@ARM.com FPSCR fpscr = Fpscr; 9497646Sgene.wu@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 9507646Sgene.wu@arm.com __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9517646Sgene.wu@arm.com FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 9527279Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 9537279Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9547279Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9557303Sgblack@eecs.umich.edu Fpscr = fpscr; 95610184SCurtis.Dunham@arm.com ''' 9577303Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 9587303Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 9597303Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9607303Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 9617303Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 9627303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 9637303Sgblack@eecs.umich.edu 9647303Sgblack@eecs.umich.edu vcvtFpSFpHTCode = ''' 9657848SAli.Saidi@ARM.com FPSCR fpscr = Fpscr; 9667848SAli.Saidi@ARM.com vfpFlushToZero(fpscr, FpOp1); 9677848SAli.Saidi@ARM.com VfpSavedState state = prepFpState(fpscr.rMode); 9687848SAli.Saidi@ARM.com __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 9697848SAli.Saidi@ARM.com : "m" (FpOp1), "m" (FpDest.uw)); 9707646Sgene.wu@arm.com FpDest.uw = insertBits(FpDest.uw, 31, 16,, 9717646Sgene.wu@arm.com vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 9727646Sgene.wu@arm.com fpscr.rMode, fpscr.ahp, FpOp1)); 9737646Sgene.wu@arm.com __asm__ __volatile__("" :: "m" (FpDest.uw)); 9747646Sgene.wu@arm.com finishVfp(fpscr, state, fpscr.fz); 9757724SAli.Saidi@ARM.com Fpscr = fpscr; 97610666SAli.Saidi@ARM.com ''' 9777646Sgene.wu@arm.com vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 9787646Sgene.wu@arm.com { "code": vcvtFpHTFpSCode, 9797646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 9807303Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 9817303Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 9827303Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 9837119Sgblack@eecs.umich.edu 98410184SCurtis.Dunham@arm.com vcvtFpSFpHBCode = ''' 9857119Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9867119Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9877119Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9887119Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) 9897119Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest.uw)); 9907848SAli.Saidi@ARM.com FpDest.uw = insertBits(FpDest.uw, 15, 0, 9917848SAli.Saidi@ARM.com vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 9927848SAli.Saidi@ARM.com fpscr.rMode, fpscr.ahp, FpOp1)); 9937848SAli.Saidi@ARM.com __asm__ __volatile__("" :: "m" (FpDest.uw)); 9947848SAli.Saidi@ARM.com finishVfp(fpscr, state, fpscr.fz); 9957646Sgene.wu@arm.com Fpscr = fpscr; 9967646Sgene.wu@arm.com ''' 9977646Sgene.wu@arm.com vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 9987646Sgene.wu@arm.com { "code": vcvtFpSFpHBCode, 9997724SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 100010666SAli.Saidi@ARM.com header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 10017646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 10027646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 10037646Sgene.wu@arm.com 10047119Sgblack@eecs.umich.edu vcmpSCode = ''' 10057119Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10067119Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 10077303Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 100810184SCurtis.Dunham@arm.com fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10097303Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 10107303Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10117303Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 10127303Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10137303Sgblack@eecs.umich.edu } else { 10147303Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 10157303Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 10167848SAli.Saidi@ARM.com const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 10177848SAli.Saidi@ARM.com const bool nan2 = std::isnan(FpOp1); 10187848SAli.Saidi@ARM.com const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 10197848SAli.Saidi@ARM.com if (signal1 || signal2) 10207848SAli.Saidi@ARM.com fpscr.ioc = 1; 10217646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10227646Sgene.wu@arm.com } 10237646Sgene.wu@arm.com Fpscr = fpscr; 10247646Sgene.wu@arm.com ''' 10257646Sgene.wu@arm.com vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 10267724SAli.Saidi@ARM.com { "code": vcmpSCode, 102710666SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 10287646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcmpSIop); 10297646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 10307646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcmpSIop); 10317303Sgblack@eecs.umich.edu 10327303Sgblack@eecs.umich.edu vcmpDCode = ''' 10337303Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 10347646Sgene.wu@arm.com double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 103510184SCurtis.Dunham@arm.com FPSCR fpscr = Fpscr; 10367279Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 10377279Sgblack@eecs.umich.edu if (cDest == cOp1) { 10387279Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10397279Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 10407279Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10417279Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 10427279Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10437279Sgblack@eecs.umich.edu } else { 10447279Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 10457848SAli.Saidi@ARM.com const bool nan1 = std::isnan(cDest); 10467848SAli.Saidi@ARM.com const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 10477848SAli.Saidi@ARM.com const bool nan2 = std::isnan(cOp1); 10487848SAli.Saidi@ARM.com const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 10497848SAli.Saidi@ARM.com if (signal1 || signal2) 10507646Sgene.wu@arm.com fpscr.ioc = 1; 10517646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10527646Sgene.wu@arm.com } 10537646Sgene.wu@arm.com Fpscr = fpscr; 10547646Sgene.wu@arm.com ''' 10557724SAli.Saidi@ARM.com vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 105610666SAli.Saidi@ARM.com { "code": vcmpDCode, 10577646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 10587646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcmpDIop); 10597646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 10607279Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 10617279Sgblack@eecs.umich.edu 10627279Sgblack@eecs.umich.edu vcmpZeroSCode = ''' 10637646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 106410184SCurtis.Dunham@arm.com vfpFlushToZero(fpscr, FpDest); 10657119Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 10667119Sgblack@eecs.umich.edu assert(imm == 0); 10677119Sgblack@eecs.umich.edu if (FpDest == imm) { 10687119Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10697119Sgblack@eecs.umich.edu } else if (FpDest < imm) { 10707119Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10717119Sgblack@eecs.umich.edu } else if (FpDest > imm) { 10727119Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10737848SAli.Saidi@ARM.com } else { 10747848SAli.Saidi@ARM.com const uint32_t qnan = 0x7fc00000; 10757848SAli.Saidi@ARM.com const bool nan = std::isnan(FpDest); 10767848SAli.Saidi@ARM.com const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 10777848SAli.Saidi@ARM.com if (signal) 10787646Sgene.wu@arm.com fpscr.ioc = 1; 10797646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10807646Sgene.wu@arm.com } 10817646Sgene.wu@arm.com Fpscr = fpscr; 10827646Sgene.wu@arm.com ''' 10837724SAli.Saidi@ARM.com vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 108410666SAli.Saidi@ARM.com { "code": vcmpZeroSCode, 10857646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 10867646Sgene.wu@arm.com header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 10877646Sgene.wu@arm.com decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 10887119Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 10897119Sgblack@eecs.umich.edu 10907646Sgene.wu@arm.com vcmpZeroDCode = ''' 10917646Sgene.wu@arm.com // This only handles imm == 0 for now. 109210184SCurtis.Dunham@arm.com assert(imm == 0); 10937646Sgene.wu@arm.com double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 10947646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 10957646Sgene.wu@arm.com vfpFlushToZero(fpscr, cDest); 10967646Sgene.wu@arm.com if (cDest == imm) { 10977646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10987646Sgene.wu@arm.com } else if (cDest < imm) { 10997646Sgene.wu@arm.com fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11007646Sgene.wu@arm.com } else if (cDest > imm) { 11017646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11027848SAli.Saidi@ARM.com } else { 11037848SAli.Saidi@ARM.com const uint64_t qnan = ULL(0x7ff8000000000000); 11047848SAli.Saidi@ARM.com const bool nan = std::isnan(cDest); 11057848SAli.Saidi@ARM.com const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 11067848SAli.Saidi@ARM.com if (signal) 11077646Sgene.wu@arm.com fpscr.ioc = 1; 11087646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11097646Sgene.wu@arm.com } 11107646Sgene.wu@arm.com Fpscr = fpscr; 11117646Sgene.wu@arm.com ''' 11127646Sgene.wu@arm.com vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 11137724SAli.Saidi@ARM.com { "code": vcmpZeroDCode, 111410666SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 11157646Sgene.wu@arm.com header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 11167646Sgene.wu@arm.com decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 11177724SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(vcmpZeroDIop); 11187646Sgene.wu@arm.com 11197646Sgene.wu@arm.com vcmpeSCode = ''' 11207646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 11217646Sgene.wu@arm.com vfpFlushToZero(fpscr, FpDest, FpOp1); 11227646Sgene.wu@arm.com if (FpDest == FpOp1) { 11237646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11247724SAli.Saidi@ARM.com } else if (FpDest < FpOp1) { 112510666SAli.Saidi@ARM.com fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11267646Sgene.wu@arm.com } else if (FpDest > FpOp1) { 11277646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11287646Sgene.wu@arm.com } else { 11297646Sgene.wu@arm.com fpscr.ioc = 1; 11307646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11317646Sgene.wu@arm.com } 11327646Sgene.wu@arm.com Fpscr = fpscr; 11337646Sgene.wu@arm.com ''' 113410184SCurtis.Dunham@arm.com vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 11357646Sgene.wu@arm.com { "code": vcmpeSCode, 11367646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 11377646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 11387646Sgene.wu@arm.com decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 11397646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcmpeSIop); 11407646Sgene.wu@arm.com 11417646Sgene.wu@arm.com vcmpeDCode = ''' 11427646Sgene.wu@arm.com double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 11438607Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11447848SAli.Saidi@ARM.com FPSCR fpscr = Fpscr; 11458203SAli.Saidi@ARM.com vfpFlushToZero(fpscr, cDest, cOp1); 11467848SAli.Saidi@ARM.com if (cDest == cOp1) { 11477848SAli.Saidi@ARM.com fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11487848SAli.Saidi@ARM.com } else if (cDest < cOp1) { 11497848SAli.Saidi@ARM.com fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11507646Sgene.wu@arm.com } else if (cDest > cOp1) { 11517646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11527646Sgene.wu@arm.com } else { 115312110SRekai.GonzalezAlberquilla@arm.com fpscr.ioc = 1; 11547646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11557646Sgene.wu@arm.com } 11567646Sgene.wu@arm.com Fpscr = fpscr; 11577724SAli.Saidi@ARM.com ''' 115810666SAli.Saidi@ARM.com vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 11597646Sgene.wu@arm.com { "code": vcmpeDCode, 11607724SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 11617646Sgene.wu@arm.com header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 11628203SAli.Saidi@ARM.com decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 11638203SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(vcmpeDIop); 11648203SAli.Saidi@ARM.com 11658203SAli.Saidi@ARM.com vcmpeZeroSCode = ''' 11668203SAli.Saidi@ARM.com FPSCR fpscr = Fpscr; 11678203SAli.Saidi@ARM.com vfpFlushToZero(fpscr, FpDest); 11687646Sgene.wu@arm.com if (FpDest == imm) { 11697646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11707646Sgene.wu@arm.com } else if (FpDest < imm) { 11717646Sgene.wu@arm.com fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11727724SAli.Saidi@ARM.com } else if (FpDest > imm) { 117310666SAli.Saidi@ARM.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11747646Sgene.wu@arm.com } else { 11757646Sgene.wu@arm.com fpscr.ioc = 1; 11767724SAli.Saidi@ARM.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11777646Sgene.wu@arm.com } 11787646Sgene.wu@arm.com Fpscr = fpscr; 11797646Sgene.wu@arm.com ''' 11807646Sgene.wu@arm.com vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 11817646Sgene.wu@arm.com { "code": vcmpeZeroSCode, 11827646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 11837724SAli.Saidi@ARM.com header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 118410666SAli.Saidi@ARM.com decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 11857646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcmpeZeroSIop); 11867646Sgene.wu@arm.com 11877646Sgene.wu@arm.com vcmpeZeroDCode = ''' 11887646Sgene.wu@arm.com double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11899250SAli.Saidi@ARM.com FPSCR fpscr = Fpscr; 119012110SRekai.GonzalezAlberquilla@arm.com vfpFlushToZero(fpscr, cDest); 11919250SAli.Saidi@ARM.com if (cDest == imm) { 11929250SAli.Saidi@ARM.com fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11939250SAli.Saidi@ARM.com } else if (cDest < imm) { 11949250SAli.Saidi@ARM.com fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11959250SAli.Saidi@ARM.com } else if (cDest > imm) { 11969250SAli.Saidi@ARM.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11979250SAli.Saidi@ARM.com } else { 11987646Sgene.wu@arm.com fpscr.ioc = 1; 11997646Sgene.wu@arm.com fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12007646Sgene.wu@arm.com } 12017646Sgene.wu@arm.com Fpscr = fpscr; 12027646Sgene.wu@arm.com ''' 120310184SCurtis.Dunham@arm.com vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 12047646Sgene.wu@arm.com { "code": vcmpeZeroDCode, 12057646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 12067646Sgene.wu@arm.com header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 12077646Sgene.wu@arm.com decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 12087646Sgene.wu@arm.com exec_output += PredOpExecute.subst(vcmpeZeroDIop); 12098607Sgblack@eecs.umich.edu}}; 12107848SAli.Saidi@ARM.com 12118203SAli.Saidi@ARM.comlet {{ 12127848SAli.Saidi@ARM.com 12137848SAli.Saidi@ARM.com header_output = "" 12147848SAli.Saidi@ARM.com decoder_output = "" 12157848SAli.Saidi@ARM.com exec_output = "" 12167646Sgene.wu@arm.com 12177646Sgene.wu@arm.com vcvtFpSFixedSCode = ''' 12187646Sgene.wu@arm.com FPSCR fpscr = Fpscr; 121912110SRekai.GonzalezAlberquilla@arm.com vfpFlushToZero(fpscr, FpOp1); 12207646Sgene.wu@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 12217646Sgene.wu@arm.com __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12227724SAli.Saidi@ARM.com FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 122310666SAli.Saidi@ARM.com __asm__ __volatile__("" :: "m" (FpDest.sw)); 12247646Sgene.wu@arm.com finishVfp(fpscr, state, fpscr.fz); 12257724SAli.Saidi@ARM.com Fpscr = fpscr; 12267646Sgene.wu@arm.com ''' 12278203SAli.Saidi@ARM.com vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 12288203SAli.Saidi@ARM.com { "code": vcvtFpSFixedSCode, 122910199SAndrew.Bardsley@arm.com "predicate_test": predicateTest }, []) 123010199SAndrew.Bardsley@arm.com header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 123110199SAndrew.Bardsley@arm.com decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 123210199SAndrew.Bardsley@arm.com exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 123310199SAndrew.Bardsley@arm.com 12348203SAli.Saidi@ARM.com vcvtFpSFixedDCode = ''' 123510199SAndrew.Bardsley@arm.com FPSCR fpscr = Fpscr; 123610199SAndrew.Bardsley@arm.com double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12378203SAli.Saidi@ARM.com vfpFlushToZero(fpscr, cOp1); 123810199SAndrew.Bardsley@arm.com VfpSavedState state = prepFpState(fpscr.rMode); 123910199SAndrew.Bardsley@arm.com __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 124010199SAndrew.Bardsley@arm.com uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 12418203SAli.Saidi@ARM.com __asm__ __volatile__("" :: "m" (mid)); 124210199SAndrew.Bardsley@arm.com finishVfp(fpscr, state, fpscr.fz); 124310199SAndrew.Bardsley@arm.com Fpscr = fpscr; 12447646Sgene.wu@arm.com FpDestP0.uw = mid; 12457646Sgene.wu@arm.com FpDestP1.uw = mid >> 32; 12467646Sgene.wu@arm.com ''' 12477724SAli.Saidi@ARM.com vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 124810666SAli.Saidi@ARM.com { "code": vcvtFpSFixedDCode, 12497646Sgene.wu@arm.com "predicate_test": predicateTest }, []) 12507646Sgene.wu@arm.com header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 12517646Sgene.wu@arm.com decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 12529250SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 125312110SRekai.GonzalezAlberquilla@arm.com 12549250SAli.Saidi@ARM.com vcvtFpUFixedSCode = ''' 12559250SAli.Saidi@ARM.com FPSCR fpscr = Fpscr; 12569250SAli.Saidi@ARM.com vfpFlushToZero(fpscr, FpOp1); 12579250SAli.Saidi@ARM.com VfpSavedState state = prepFpState(fpscr.rMode); 12589250SAli.Saidi@ARM.com __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12599250SAli.Saidi@ARM.com FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 12609250SAli.Saidi@ARM.com __asm__ __volatile__("" :: "m" (FpDest.uw)); 12617646Sgene.wu@arm.com finishVfp(fpscr, state, fpscr.fz); 12627646Sgene.wu@arm.com Fpscr = fpscr; 12637646Sgene.wu@arm.com ''' 12647646Sgene.wu@arm.com vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 1265 { "code": vcvtFpUFixedSCode, 1266 "predicate_test": predicateTest }, []) 1267 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1268 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1269 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1270 1271 vcvtFpUFixedDCode = ''' 1272 FPSCR fpscr = Fpscr; 1273 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1274 vfpFlushToZero(fpscr, cOp1); 1275 VfpSavedState state = prepFpState(fpscr.rMode); 1276 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1277 uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 1278 __asm__ __volatile__("" :: "m" (mid)); 1279 finishVfp(fpscr, state, fpscr.fz); 1280 Fpscr = fpscr; 1281 FpDestP0.uw = mid; 1282 FpDestP1.uw = mid >> 32; 1283 ''' 1284 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 1285 { "code": vcvtFpUFixedDCode, 1286 "predicate_test": predicateTest }, []) 1287 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1288 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1289 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1290 1291 vcvtSFixedFpSCode = ''' 1292 FPSCR fpscr = Fpscr; 1293 VfpSavedState state = prepFpState(fpscr.rMode); 1294 __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 1295 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); 1296 __asm__ __volatile__("" :: "m" (FpDest)); 1297 finishVfp(fpscr, state, fpscr.fz); 1298 Fpscr = fpscr; 1299 ''' 1300 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 1301 { "code": vcvtSFixedFpSCode, 1302 "predicate_test": predicateTest }, []) 1303 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1304 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1305 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1306 1307 vcvtSFixedFpDCode = ''' 1308 FPSCR fpscr = Fpscr; 1309 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1310 VfpSavedState state = prepFpState(fpscr.rMode); 1311 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1312 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1313 __asm__ __volatile__("" :: "m" (cDest)); 1314 finishVfp(fpscr, state, fpscr.fz); 1315 Fpscr = fpscr; 1316 FpDestP0.uw = dblLow(cDest); 1317 FpDestP1.uw = dblHi(cDest); 1318 ''' 1319 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 1320 { "code": vcvtSFixedFpDCode, 1321 "predicate_test": predicateTest }, []) 1322 header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1323 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1324 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1325 1326 vcvtUFixedFpSCode = ''' 1327 FPSCR fpscr = Fpscr; 1328 VfpSavedState state = prepFpState(fpscr.rMode); 1329 __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 1330 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); 1331 __asm__ __volatile__("" :: "m" (FpDest)); 1332 finishVfp(fpscr, state, fpscr.fz); 1333 Fpscr = fpscr; 1334 ''' 1335 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 1336 { "code": vcvtUFixedFpSCode, 1337 "predicate_test": predicateTest }, []) 1338 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1339 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1340 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1341 1342 vcvtUFixedFpDCode = ''' 1343 FPSCR fpscr = Fpscr; 1344 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1345 VfpSavedState state = prepFpState(fpscr.rMode); 1346 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1347 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); 1348 __asm__ __volatile__("" :: "m" (cDest)); 1349 finishVfp(fpscr, state, fpscr.fz); 1350 Fpscr = fpscr; 1351 FpDestP0.uw = dblLow(cDest); 1352 FpDestP1.uw = dblHi(cDest); 1353 ''' 1354 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 1355 { "code": vcvtUFixedFpDCode, 1356 "predicate_test": predicateTest }, []) 1357 header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1358 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1359 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1360 1361 vcvtFpSHFixedSCode = ''' 1362 FPSCR fpscr = Fpscr; 1363 vfpFlushToZero(fpscr, FpOp1); 1364 VfpSavedState state = prepFpState(fpscr.rMode); 1365 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1366 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1367 __asm__ __volatile__("" :: "m" (FpDest.sh)); 1368 finishVfp(fpscr, state, fpscr.fz); 1369 Fpscr = fpscr; 1370 ''' 1371 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1372 "FpRegRegImmOp", 1373 { "code": vcvtFpSHFixedSCode, 1374 "predicate_test": predicateTest }, []) 1375 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1376 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1377 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1378 1379 vcvtFpSHFixedDCode = ''' 1380 FPSCR fpscr = Fpscr; 1381 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1382 vfpFlushToZero(fpscr, cOp1); 1383 VfpSavedState state = prepFpState(fpscr.rMode); 1384 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1385 uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 1386 __asm__ __volatile__("" :: "m" (result)); 1387 finishVfp(fpscr, state, fpscr.fz); 1388 Fpscr = fpscr; 1389 FpDestP0.uw = result; 1390 FpDestP1.uw = result >> 32; 1391 ''' 1392 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1393 "FpRegRegImmOp", 1394 { "code": vcvtFpSHFixedDCode, 1395 "predicate_test": predicateTest }, []) 1396 header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1397 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1398 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1399 1400 vcvtFpUHFixedSCode = ''' 1401 FPSCR fpscr = Fpscr; 1402 vfpFlushToZero(fpscr, FpOp1); 1403 VfpSavedState state = prepFpState(fpscr.rMode); 1404 __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 1405 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1406 __asm__ __volatile__("" :: "m" (FpDest.uh)); 1407 finishVfp(fpscr, state, fpscr.fz); 1408 Fpscr = fpscr; 1409 ''' 1410 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1411 "FpRegRegImmOp", 1412 { "code": vcvtFpUHFixedSCode, 1413 "predicate_test": predicateTest }, []) 1414 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1415 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1416 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1417 1418 vcvtFpUHFixedDCode = ''' 1419 FPSCR fpscr = Fpscr; 1420 double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 1421 vfpFlushToZero(fpscr, cOp1); 1422 VfpSavedState state = prepFpState(fpscr.rMode); 1423 __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 1424 uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 1425 __asm__ __volatile__("" :: "m" (mid)); 1426 finishVfp(fpscr, state, fpscr.fz); 1427 Fpscr = fpscr; 1428 FpDestP0.uw = mid; 1429 FpDestP1.uw = mid >> 32; 1430 ''' 1431 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1432 "FpRegRegImmOp", 1433 { "code": vcvtFpUHFixedDCode, 1434 "predicate_test": predicateTest }, []) 1435 header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1436 decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1437 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1438 1439 vcvtSHFixedFpSCode = ''' 1440 FPSCR fpscr = Fpscr; 1441 VfpSavedState state = prepFpState(fpscr.rMode); 1442 __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 1443 FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); 1444 __asm__ __volatile__("" :: "m" (FpDest)); 1445 finishVfp(fpscr, state, fpscr.fz); 1446 Fpscr = fpscr; 1447 ''' 1448 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1449 "FpRegRegImmOp", 1450 { "code": vcvtSHFixedFpSCode, 1451 "predicate_test": predicateTest }, []) 1452 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1453 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1454 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1455 1456 vcvtSHFixedFpDCode = ''' 1457 FPSCR fpscr = Fpscr; 1458 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1459 VfpSavedState state = prepFpState(fpscr.rMode); 1460 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1461 double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1462 __asm__ __volatile__("" :: "m" (cDest)); 1463 finishVfp(fpscr, state, fpscr.fz); 1464 Fpscr = fpscr; 1465 FpDestP0.uw = dblLow(cDest); 1466 FpDestP1.uw = dblHi(cDest); 1467 ''' 1468 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1469 "FpRegRegImmOp", 1470 { "code": vcvtSHFixedFpDCode, 1471 "predicate_test": predicateTest }, []) 1472 header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1473 decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1474 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1475 1476 vcvtUHFixedFpSCode = ''' 1477 FPSCR fpscr = Fpscr; 1478 VfpSavedState state = prepFpState(fpscr.rMode); 1479 __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 1480 FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); 1481 __asm__ __volatile__("" :: "m" (FpDest)); 1482 finishVfp(fpscr, state, fpscr.fz); 1483 Fpscr = fpscr; 1484 ''' 1485 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1486 "FpRegRegImmOp", 1487 { "code": vcvtUHFixedFpSCode, 1488 "predicate_test": predicateTest }, []) 1489 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1490 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1491 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1492 1493 vcvtUHFixedFpDCode = ''' 1494 FPSCR fpscr = Fpscr; 1495 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1496 VfpSavedState state = prepFpState(fpscr.rMode); 1497 __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 1498 double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); 1499 __asm__ __volatile__("" :: "m" (cDest)); 1500 finishVfp(fpscr, state, fpscr.fz); 1501 Fpscr = fpscr; 1502 FpDestP0.uw = dblLow(cDest); 1503 FpDestP1.uw = dblHi(cDest); 1504 ''' 1505 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1506 "FpRegRegImmOp", 1507 { "code": vcvtUHFixedFpDCode, 1508 "predicate_test": predicateTest }, []) 1509 header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1510 decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1511 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1512}}; 1513