fp.isa revision 7398
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947396Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", 1957322Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 1967322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1977396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrIop); 1987396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrIop); 1997322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2007324Sgblack@eecs.umich.edu 2017396Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", 2027324Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 2037324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsIop); 2057396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsIop); 2067324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2077333Sgblack@eecs.umich.edu 2087392Sgblack@eecs.umich.edu vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);" 2097396Sgblack@eecs.umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", 2107392Sgblack@eecs.umich.edu { "code": vmrsApsrCode, 2117392Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2127396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmrsApsrIop); 2137396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); 2147392Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrIop); 2157392Sgblack@eecs.umich.edu 2167333Sgblack@eecs.umich.edu vmovImmSCode = ''' 2177333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2187333Sgblack@eecs.umich.edu ''' 2197396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2207333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2217333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2227396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2237396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2247333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2257333Sgblack@eecs.umich.edu 2267333Sgblack@eecs.umich.edu vmovImmDCode = ''' 2277333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2287333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2297333Sgblack@eecs.umich.edu ''' 2307396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2317333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2327333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2337396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2347396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2357333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2367333Sgblack@eecs.umich.edu 2377333Sgblack@eecs.umich.edu vmovImmQCode = ''' 2387333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2397333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2407333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2417333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2427333Sgblack@eecs.umich.edu ''' 2437396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2447333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2457333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2467396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 2477396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 2487333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2497333Sgblack@eecs.umich.edu 2507333Sgblack@eecs.umich.edu vmovRegSCode = ''' 2517333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2527333Sgblack@eecs.umich.edu ''' 2537396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 2547333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2557333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2567396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 2577396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 2587333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2597333Sgblack@eecs.umich.edu 2607333Sgblack@eecs.umich.edu vmovRegDCode = ''' 2617333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2627333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2637333Sgblack@eecs.umich.edu ''' 2647396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 2657333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2667333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2677396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 2687396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 2697333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2707333Sgblack@eecs.umich.edu 2717333Sgblack@eecs.umich.edu vmovRegQCode = ''' 2727333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2737333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2747333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2757333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2767333Sgblack@eecs.umich.edu ''' 2777396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 2787333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2797333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 2817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 2827333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2837333Sgblack@eecs.umich.edu 2847333Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 2857333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 2867333Sgblack@eecs.umich.edu ''' 2877396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 2887333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2897333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2907396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2917396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2927333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2937333Sgblack@eecs.umich.edu 2947333Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 2957333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 2967333Sgblack@eecs.umich.edu ''' 2977396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 2987333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 2997333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3007396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3017396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3027333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3037333Sgblack@eecs.umich.edu 3047333Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 3057333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 3067333Sgblack@eecs.umich.edu ''' 3077396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3087333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3097333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3107396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3117396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3127333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3137333Sgblack@eecs.umich.edu 3147333Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 3157333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 3167333Sgblack@eecs.umich.edu ''' 3177396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3187333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3197333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3207396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3217396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3227333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3237333Sgblack@eecs.umich.edu 3247333Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 3257333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 3267333Sgblack@eecs.umich.edu ''' 3277396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3287333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3297333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3307396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3317396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3327333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3337333Sgblack@eecs.umich.edu 3347333Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 3357333Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 3367333Sgblack@eecs.umich.edu ''' 3377396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 3387333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3397333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3407396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3417396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3427333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3437333Sgblack@eecs.umich.edu 3447333Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 3457333Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 3467333Sgblack@eecs.umich.edu ''' 3477396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 3487333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3497333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3507396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3517396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3527333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3537333Sgblack@eecs.umich.edu 3547333Sgblack@eecs.umich.edu vmovRegCoreWCode = ''' 3557333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3567333Sgblack@eecs.umich.edu ''' 3577396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 3587333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3597333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3607396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 3617396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 3627333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 3637333Sgblack@eecs.umich.edu 3647333Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 3657333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3667333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3677333Sgblack@eecs.umich.edu ''' 3687396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 3697333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3707333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3717396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3727396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3737333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3747333Sgblack@eecs.umich.edu 3757333Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 3767333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3777333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3787333Sgblack@eecs.umich.edu ''' 3797396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 3807333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3817333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3827396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3837396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3857381Sgblack@eecs.umich.edu}}; 3867381Sgblack@eecs.umich.edu 3877381Sgblack@eecs.umich.edulet {{ 3887381Sgblack@eecs.umich.edu 3897381Sgblack@eecs.umich.edu header_output = "" 3907381Sgblack@eecs.umich.edu decoder_output = "" 3917381Sgblack@eecs.umich.edu exec_output = "" 3927364Sgblack@eecs.umich.edu 3937396Sgblack@eecs.umich.edu singleCode = ''' 3947396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 3957396Sgblack@eecs.umich.edu FpDest = %(op)s; 3967396Sgblack@eecs.umich.edu Fpscr = fpscr; 3977364Sgblack@eecs.umich.edu ''' 3987396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 3997396Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.rMode)" 4007396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4017396Sgblack@eecs.umich.edu doubleCode = ''' 4027396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 4037396Sgblack@eecs.umich.edu double dest = %(op)s; 4047396Sgblack@eecs.umich.edu Fpscr = fpscr; 4057396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 4067396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 4077396Sgblack@eecs.umich.edu ''' 4087396Sgblack@eecs.umich.edu doubleBinOp = ''' 4097396Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 4107396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 4117396Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.rMode); 4127396Sgblack@eecs.umich.edu ''' 4137396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 4147396Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, 4157396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 4167396Sgblack@eecs.umich.edu ''' 4177364Sgblack@eecs.umich.edu 4187396Sgblack@eecs.umich.edu def buildBinFpOp(name, Name, base, singleOp, doubleOp): 4197396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4207365Sgblack@eecs.umich.edu 4217396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 4227396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4237396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4247396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4257396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 4267396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4277396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4287396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4297365Sgblack@eecs.umich.edu 4307396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4317396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4327366Sgblack@eecs.umich.edu 4337396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4347396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4357396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4367396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4377366Sgblack@eecs.umich.edu 4387396Sgblack@eecs.umich.edu buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "fpAddS", "fpAddD") 4397396Sgblack@eecs.umich.edu buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "fpSubS", "fpSubD") 4407396Sgblack@eecs.umich.edu buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "fpDivS", "fpDivD") 4417396Sgblack@eecs.umich.edu buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "fpMulS", "fpMulD") 4427367Sgblack@eecs.umich.edu 4437396Sgblack@eecs.umich.edu def buildUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4447396Sgblack@eecs.umich.edu if doubleOp is None: 4457396Sgblack@eecs.umich.edu doubleOp = singleOp 4467396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4477367Sgblack@eecs.umich.edu 4487396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 4497396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 4507396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4517396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4527396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 4537396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 4547396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4557396Sgblack@eecs.umich.edu { "code": code, "predicate_test": predicateTest }, []) 4567368Sgblack@eecs.umich.edu 4577396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4587396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4597368Sgblack@eecs.umich.edu 4607396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4617396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4627396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4637396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4647369Sgblack@eecs.umich.edu 4657396Sgblack@eecs.umich.edu buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "sqrtf", "sqrt") 4667369Sgblack@eecs.umich.edu 4677396Sgblack@eecs.umich.edu def buildSimpleUnaryFpOp(name, Name, base, singleOp, doubleOp = None): 4687396Sgblack@eecs.umich.edu if doubleOp is None: 4697396Sgblack@eecs.umich.edu doubleOp = singleOp 4707396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 4717369Sgblack@eecs.umich.edu 4727396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 4737396Sgblack@eecs.umich.edu { "code": singleCode % { "op": singleOp }, 4747396Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4757396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 4767396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 4777396Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4787369Sgblack@eecs.umich.edu 4797396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 4807396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 4817396Sgblack@eecs.umich.edu 4827396Sgblack@eecs.umich.edu for iop in sIop, dIop: 4837396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 4847396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 4857396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 4867396Sgblack@eecs.umich.edu 4877396Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", 4887396Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") 4897396Sgblack@eecs.umich.edu buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", 4907396Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") 4917381Sgblack@eecs.umich.edu}}; 4927381Sgblack@eecs.umich.edu 4937381Sgblack@eecs.umich.edulet {{ 4947381Sgblack@eecs.umich.edu 4957381Sgblack@eecs.umich.edu header_output = "" 4967381Sgblack@eecs.umich.edu decoder_output = "" 4977381Sgblack@eecs.umich.edu exec_output = "" 4987370Sgblack@eecs.umich.edu 4997370Sgblack@eecs.umich.edu vmlaSCode = ''' 5007396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5017396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5027396Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.rMode); 5037396Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, fpscr.fz, fpscr.rMode); 5047396Sgblack@eecs.umich.edu Fpscr = fpscr; 5057370Sgblack@eecs.umich.edu ''' 5067396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 5077370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5087370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5097396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 5107396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 5117370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5127370Sgblack@eecs.umich.edu 5137370Sgblack@eecs.umich.edu vmlaDCode = ''' 5147396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5157396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5167396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5177396Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.rMode); 5187396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5197396Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, fpscr.rMode); 5207396Sgblack@eecs.umich.edu Fpscr = fpscr; 5217396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5227396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5237370Sgblack@eecs.umich.edu ''' 5247396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 5257370Sgblack@eecs.umich.edu { "code": vmlaDCode, 5267370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5277396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 5287396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 5297370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 5307370Sgblack@eecs.umich.edu 5317370Sgblack@eecs.umich.edu vmlsSCode = ''' 5327396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5337396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5347396Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.rMode); 5357396Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, fpscr.fz, fpscr.rMode); 5367396Sgblack@eecs.umich.edu Fpscr = fpscr; 5377370Sgblack@eecs.umich.edu ''' 5387396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 5397370Sgblack@eecs.umich.edu { "code": vmlsSCode, 5407370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5417396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 5427396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 5437370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 5447370Sgblack@eecs.umich.edu 5457370Sgblack@eecs.umich.edu vmlsDCode = ''' 5467396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5477396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5487396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5497396Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.rMode); 5507396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), 5517396Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, fpscr.rMode); 5527396Sgblack@eecs.umich.edu Fpscr = fpscr; 5537396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5547396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5557370Sgblack@eecs.umich.edu ''' 5567396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 5577370Sgblack@eecs.umich.edu { "code": vmlsDCode, 5587370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5597396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 5607396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 5617370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 5627371Sgblack@eecs.umich.edu 5637371Sgblack@eecs.umich.edu vnmlaSCode = ''' 5647396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5657396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5667396Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.rMode); 5677396Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, fpscr.fz, fpscr.rMode); 5687396Sgblack@eecs.umich.edu Fpscr = fpscr; 5697371Sgblack@eecs.umich.edu ''' 5707396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 5717371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 5727371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5737396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 5747396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 5757371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 5767371Sgblack@eecs.umich.edu 5777371Sgblack@eecs.umich.edu vnmlaDCode = ''' 5787396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5797396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 5807396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 5817396Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.rMode); 5827396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 5837396Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, fpscr.rMode); 5847396Sgblack@eecs.umich.edu Fpscr = fpscr; 5857396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 5867396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 5877371Sgblack@eecs.umich.edu ''' 5887396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 5897371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 5907371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5917396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 5927396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 5937371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 5947371Sgblack@eecs.umich.edu 5957371Sgblack@eecs.umich.edu vnmlsSCode = ''' 5967396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 5977396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 5987396Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.rMode); 5997396Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, fpscr.fz, fpscr.rMode); 6007396Sgblack@eecs.umich.edu Fpscr = fpscr; 6017371Sgblack@eecs.umich.edu ''' 6027396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 6037371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 6047371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6057396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 6067396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 6077371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 6087371Sgblack@eecs.umich.edu 6097371Sgblack@eecs.umich.edu vnmlsDCode = ''' 6107396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6117396Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6127396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6137396Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.rMode); 6147396Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), 6157396Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, fpscr.rMode); 6167396Sgblack@eecs.umich.edu Fpscr = fpscr; 6177396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6187396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6197371Sgblack@eecs.umich.edu ''' 6207396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 6217371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 6227371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6237396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 6247396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 6257371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 6267371Sgblack@eecs.umich.edu 6277371Sgblack@eecs.umich.edu vnmulSCode = ''' 6287396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6297396Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, fpscr.fz, fpscr.rMode); 6307396Sgblack@eecs.umich.edu Fpscr = fpscr; 6317371Sgblack@eecs.umich.edu ''' 6327396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 6337371Sgblack@eecs.umich.edu { "code": vnmulSCode, 6347371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6357396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 6367396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 6377371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 6387371Sgblack@eecs.umich.edu 6397371Sgblack@eecs.umich.edu vnmulDCode = ''' 6407396Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6417396Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), 6427396Sgblack@eecs.umich.edu dbl(FpOp2P0.uw, FpOp2P1.uw), 6437396Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.rMode); 6447396Sgblack@eecs.umich.edu Fpscr = fpscr; 6457396Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(dest); 6467396Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(dest); 6477371Sgblack@eecs.umich.edu ''' 6487396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 6497371Sgblack@eecs.umich.edu { "code": vnmulDCode, 6507371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6517396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 6527396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 6537371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 6547381Sgblack@eecs.umich.edu}}; 6557381Sgblack@eecs.umich.edu 6567381Sgblack@eecs.umich.edulet {{ 6577381Sgblack@eecs.umich.edu 6587381Sgblack@eecs.umich.edu header_output = "" 6597381Sgblack@eecs.umich.edu decoder_output = "" 6607381Sgblack@eecs.umich.edu exec_output = "" 6617373Sgblack@eecs.umich.edu 6627373Sgblack@eecs.umich.edu vcvtUIntFpSCode = ''' 6637397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6647397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 6657381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 6667373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 6677381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6687397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 6697397Sgblack@eecs.umich.edu Fpscr = fpscr; 6707373Sgblack@eecs.umich.edu ''' 6717396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 6727373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 6737373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6747396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 6757396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 6767373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 6777373Sgblack@eecs.umich.edu 6787373Sgblack@eecs.umich.edu vcvtUIntFpDCode = ''' 6797397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6807397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 6817381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 6827397Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0.uw; 6837397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 6847397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 6857397Sgblack@eecs.umich.edu Fpscr = fpscr; 6867397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 6877397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 6887373Sgblack@eecs.umich.edu ''' 6897396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 6907373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 6917373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6927396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 6937396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 6947373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 6957373Sgblack@eecs.umich.edu 6967373Sgblack@eecs.umich.edu vcvtSIntFpSCode = ''' 6977397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 6987397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 6997381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 7007373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 7017381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7027397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 7037397Sgblack@eecs.umich.edu Fpscr = fpscr; 7047373Sgblack@eecs.umich.edu ''' 7057396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 7067373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 7077373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7087396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 7097396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 7107373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 7117373Sgblack@eecs.umich.edu 7127373Sgblack@eecs.umich.edu vcvtSIntFpDCode = ''' 7137397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7147397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7157381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 7167397Sgblack@eecs.umich.edu double cDest = FpOp1P0.sw; 7177397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 7187397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 7197397Sgblack@eecs.umich.edu Fpscr = fpscr; 7207397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 7217397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 7227373Sgblack@eecs.umich.edu ''' 7237396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 7247373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 7257373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7267396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 7277396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 7287373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 7297373Sgblack@eecs.umich.edu 7307380Sgblack@eecs.umich.edu vcvtFpUIntSRCode = ''' 7317397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7327397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7337397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 7347381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7357388Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 7367381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 7377397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 7387397Sgblack@eecs.umich.edu Fpscr = fpscr; 7397380Sgblack@eecs.umich.edu ''' 7407396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 7417380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 7427380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7437396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 7447396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 7457380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 7467380Sgblack@eecs.umich.edu 7477380Sgblack@eecs.umich.edu vcvtFpUIntDRCode = ''' 7487397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7497397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 7507397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 7517397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7527397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 7537397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); 7547381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 7557397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 7567397Sgblack@eecs.umich.edu Fpscr = fpscr; 7577380Sgblack@eecs.umich.edu FpDestP0.uw = result; 7587380Sgblack@eecs.umich.edu ''' 7597396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 7607380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 7617380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7627396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 7637396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 7647380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 7657380Sgblack@eecs.umich.edu 7667380Sgblack@eecs.umich.edu vcvtFpSIntSRCode = ''' 7677397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7687397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7697397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 7707381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7717388Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 7727381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 7737397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 7747397Sgblack@eecs.umich.edu Fpscr = fpscr; 7757380Sgblack@eecs.umich.edu ''' 7767396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 7777380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 7787380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7797396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 7807396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 7817380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 7827380Sgblack@eecs.umich.edu 7837380Sgblack@eecs.umich.edu vcvtFpSIntDRCode = ''' 7847397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 7857397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 7867397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 7877397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 7887397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 7897397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); 7907381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 7917397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 7927397Sgblack@eecs.umich.edu Fpscr = fpscr; 7937380Sgblack@eecs.umich.edu FpDestP0.uw = result; 7947380Sgblack@eecs.umich.edu ''' 7957396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 7967380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 7977380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7987396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 7997396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 8007380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 8017380Sgblack@eecs.umich.edu 8027373Sgblack@eecs.umich.edu vcvtFpUIntSCode = ''' 8037397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8047397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8057397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8067380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8077381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8087387Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 8097381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 8107397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 8117397Sgblack@eecs.umich.edu Fpscr = fpscr; 8127373Sgblack@eecs.umich.edu ''' 8137396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 8147373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 8157373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8167396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 8177396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 8187373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 8197373Sgblack@eecs.umich.edu 8207373Sgblack@eecs.umich.edu vcvtFpUIntDCode = ''' 8217397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8227397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8237397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8247397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8257380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8267397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8277397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); 8287381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8297397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 8307397Sgblack@eecs.umich.edu Fpscr = fpscr; 8317373Sgblack@eecs.umich.edu FpDestP0.uw = result; 8327373Sgblack@eecs.umich.edu ''' 8337396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 8347373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 8357373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8367396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 8377396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 8387373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 8397373Sgblack@eecs.umich.edu 8407373Sgblack@eecs.umich.edu vcvtFpSIntSCode = ''' 8417397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8427397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8437397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8447380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8457381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8467387Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 8477381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 8487397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 8497397Sgblack@eecs.umich.edu Fpscr = fpscr; 8507373Sgblack@eecs.umich.edu ''' 8517396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 8527373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 8537373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8547396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 8557396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 8567373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 8577373Sgblack@eecs.umich.edu 8587373Sgblack@eecs.umich.edu vcvtFpSIntDCode = ''' 8597397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8607397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 8617397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 8627397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8637380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8647397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 8657397Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1, true, false, 0); 8667381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 8677397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 8687397Sgblack@eecs.umich.edu Fpscr = fpscr; 8697373Sgblack@eecs.umich.edu FpDestP0.uw = result; 8707373Sgblack@eecs.umich.edu ''' 8717396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 8727373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 8737373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8747396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 8757396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 8767373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 8777374Sgblack@eecs.umich.edu 8787374Sgblack@eecs.umich.edu vcvtFpSFpDCode = ''' 8797397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8807397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 8817397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8827381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8837397Sgblack@eecs.umich.edu double cDest = fixFpSFpDDest(Fpscr, FpOp1); 8847397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8857397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 8867397Sgblack@eecs.umich.edu Fpscr = fpscr; 8877397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 8887397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 8897374Sgblack@eecs.umich.edu ''' 8907396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 8917374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 8927374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8937396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 8947396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 8957374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 8967374Sgblack@eecs.umich.edu 8977374Sgblack@eecs.umich.edu vcvtFpDFpSCode = ''' 8987397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8997397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 9007397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9017397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9027397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 9037397Sgblack@eecs.umich.edu FpDest = fixFpDFpSDest(Fpscr, cOp1); 9047381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9057397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 9067397Sgblack@eecs.umich.edu Fpscr = fpscr; 9077374Sgblack@eecs.umich.edu ''' 9087396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 9097374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 9107374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9117396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 9127396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 9137374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 9147377Sgblack@eecs.umich.edu 9157398Sgblack@eecs.umich.edu vcvtFpHTFpSCode = ''' 9167398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9177398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9187398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9197398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9207398Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, FpOp1, true); 9217398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9227398Sgblack@eecs.umich.edu finishVfp(fpscr, state); 9237398Sgblack@eecs.umich.edu Fpscr = fpscr; 9247398Sgblack@eecs.umich.edu ''' 9257398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 9267398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 9277398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9287398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 9297398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 9307398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 9317398Sgblack@eecs.umich.edu 9327398Sgblack@eecs.umich.edu vcvtFpHBFpSCode = ''' 9337398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9347398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9357398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9367398Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, FpOp1, false); 9377398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9387398Sgblack@eecs.umich.edu finishVfp(fpscr, state); 9397398Sgblack@eecs.umich.edu Fpscr = fpscr; 9407398Sgblack@eecs.umich.edu ''' 9417398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 9427398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 9437398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9447398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 9457398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 9467398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 9477398Sgblack@eecs.umich.edu 9487398Sgblack@eecs.umich.edu vcvtFpSFpHTCode = ''' 9497398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9507398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9517398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9527398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest) 9537398Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest)); 9547398Sgblack@eecs.umich.edu FpDest = vcvtFpSFpH(fpscr, FpOp1, FpDest, true); 9557398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9567398Sgblack@eecs.umich.edu finishVfp(fpscr, state); 9577398Sgblack@eecs.umich.edu Fpscr = fpscr; 9587398Sgblack@eecs.umich.edu ''' 9597398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 9607398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 9617398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9627398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 9637398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 9647398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 9657398Sgblack@eecs.umich.edu 9667398Sgblack@eecs.umich.edu vcvtFpSFpHBCode = ''' 9677398Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9687398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9697398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9707398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest) 9717398Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest)); 9727398Sgblack@eecs.umich.edu FpDest = vcvtFpSFpH(fpscr, FpOp1, FpDest, false); 9737398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9747398Sgblack@eecs.umich.edu finishVfp(fpscr, state); 9757398Sgblack@eecs.umich.edu Fpscr = fpscr; 9767398Sgblack@eecs.umich.edu ''' 9777398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 9787398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 9797398Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9807398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 9817398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 9827398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 9837398Sgblack@eecs.umich.edu 9847377Sgblack@eecs.umich.edu vcmpSCode = ''' 9857377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9867397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 9877377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 9887377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 9897377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 9907377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 9917377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 9927377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 9937377Sgblack@eecs.umich.edu } else { 9947389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 9957389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 9967396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 9977389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 9987396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 9997389Sgblack@eecs.umich.edu if (signal1 || signal2) 10007389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10017377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10027377Sgblack@eecs.umich.edu } 10037377Sgblack@eecs.umich.edu Fpscr = fpscr; 10047377Sgblack@eecs.umich.edu ''' 10057396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 10067377Sgblack@eecs.umich.edu { "code": vcmpSCode, 10077377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10087396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 10097396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 10107377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 10117377Sgblack@eecs.umich.edu 10127377Sgblack@eecs.umich.edu vcmpDCode = ''' 10137397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 10147397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 10157377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10167397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 10177397Sgblack@eecs.umich.edu if (cDest == cOp1) { 10187377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10197397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 10207377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10217397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 10227377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10237377Sgblack@eecs.umich.edu } else { 10247389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 10257397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 10267397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 10277397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 10287397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 10297389Sgblack@eecs.umich.edu if (signal1 || signal2) 10307389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10317377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10327377Sgblack@eecs.umich.edu } 10337377Sgblack@eecs.umich.edu Fpscr = fpscr; 10347377Sgblack@eecs.umich.edu ''' 10357396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 10367377Sgblack@eecs.umich.edu { "code": vcmpDCode, 10377377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10387396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 10397396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 10407377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 10417377Sgblack@eecs.umich.edu 10427377Sgblack@eecs.umich.edu vcmpZeroSCode = ''' 10437377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10447397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 10457389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 10467389Sgblack@eecs.umich.edu assert(imm == 0); 10477377Sgblack@eecs.umich.edu if (FpDest == imm) { 10487377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10497377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 10507377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10517377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 10527377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10537377Sgblack@eecs.umich.edu } else { 10547389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 10557389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 10567396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 10577389Sgblack@eecs.umich.edu if (signal) 10587389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10597377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10607377Sgblack@eecs.umich.edu } 10617377Sgblack@eecs.umich.edu Fpscr = fpscr; 10627377Sgblack@eecs.umich.edu ''' 10637396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 10647377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 10657377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10667396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 10677396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 10687377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 10697377Sgblack@eecs.umich.edu 10707377Sgblack@eecs.umich.edu vcmpZeroDCode = ''' 10717389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 10727389Sgblack@eecs.umich.edu assert(imm == 0); 10737397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 10747377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10757397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 10767397Sgblack@eecs.umich.edu if (cDest == imm) { 10777377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10787397Sgblack@eecs.umich.edu } else if (cDest < imm) { 10797377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10807397Sgblack@eecs.umich.edu } else if (cDest > imm) { 10817377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10827377Sgblack@eecs.umich.edu } else { 10837389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 10847397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 10857397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 10867389Sgblack@eecs.umich.edu if (signal) 10877389Sgblack@eecs.umich.edu fpscr.ioc = 1; 10887377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10897377Sgblack@eecs.umich.edu } 10907377Sgblack@eecs.umich.edu Fpscr = fpscr; 10917377Sgblack@eecs.umich.edu ''' 10927396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 10937377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 10947377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10957396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 10967396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 10977377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 10987389Sgblack@eecs.umich.edu 10997389Sgblack@eecs.umich.edu vcmpeSCode = ''' 11007389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11017397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 11027389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11037389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11047389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11057389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11067389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11077389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11087389Sgblack@eecs.umich.edu } else { 11097389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11107389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11117389Sgblack@eecs.umich.edu } 11127389Sgblack@eecs.umich.edu Fpscr = fpscr; 11137389Sgblack@eecs.umich.edu ''' 11147396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 11157389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 11167389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11177396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 11187396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 11197389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 11207389Sgblack@eecs.umich.edu 11217389Sgblack@eecs.umich.edu vcmpeDCode = ''' 11227397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 11237397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11247389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11257397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 11267397Sgblack@eecs.umich.edu if (cDest == cOp1) { 11277389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11287397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 11297389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11307397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 11317389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11327389Sgblack@eecs.umich.edu } else { 11337389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11347389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11357389Sgblack@eecs.umich.edu } 11367389Sgblack@eecs.umich.edu Fpscr = fpscr; 11377389Sgblack@eecs.umich.edu ''' 11387396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 11397389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 11407389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11417396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 11427396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 11437389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 11447389Sgblack@eecs.umich.edu 11457389Sgblack@eecs.umich.edu vcmpeZeroSCode = ''' 11467389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11477397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 11487389Sgblack@eecs.umich.edu if (FpDest == imm) { 11497389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11507389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11517389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11527389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11537389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11547389Sgblack@eecs.umich.edu } else { 11557389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11567389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11577389Sgblack@eecs.umich.edu } 11587389Sgblack@eecs.umich.edu Fpscr = fpscr; 11597389Sgblack@eecs.umich.edu ''' 11607396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 11617389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 11627389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11637396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 11647396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 11657389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 11667389Sgblack@eecs.umich.edu 11677389Sgblack@eecs.umich.edu vcmpeZeroDCode = ''' 11687397Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0.uw, FpDestP1.uw); 11697389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11707397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 11717397Sgblack@eecs.umich.edu if (cDest == imm) { 11727389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11737397Sgblack@eecs.umich.edu } else if (cDest < imm) { 11747389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11757397Sgblack@eecs.umich.edu } else if (cDest > imm) { 11767389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11777389Sgblack@eecs.umich.edu } else { 11787389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11797389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11807389Sgblack@eecs.umich.edu } 11817389Sgblack@eecs.umich.edu Fpscr = fpscr; 11827389Sgblack@eecs.umich.edu ''' 11837396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 11847389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 11857389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11867396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 11877396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 11887389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 11897322Sgblack@eecs.umich.edu}}; 11907379Sgblack@eecs.umich.edu 11917379Sgblack@eecs.umich.edulet {{ 11927379Sgblack@eecs.umich.edu 11937379Sgblack@eecs.umich.edu header_output = "" 11947379Sgblack@eecs.umich.edu decoder_output = "" 11957379Sgblack@eecs.umich.edu exec_output = "" 11967379Sgblack@eecs.umich.edu 11977379Sgblack@eecs.umich.edu vcvtFpSFixedSCode = ''' 11987397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11997397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12007397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12017381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12027379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 12037381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 12047397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 12057397Sgblack@eecs.umich.edu Fpscr = fpscr; 12067379Sgblack@eecs.umich.edu ''' 12077396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 12087379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 12097379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12107396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 12117396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 12127379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 12137379Sgblack@eecs.umich.edu 12147379Sgblack@eecs.umich.edu vcvtFpSFixedDCode = ''' 12157397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12167397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12177397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 12187397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12197397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 12207397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); 12217381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 12227397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 12237397Sgblack@eecs.umich.edu Fpscr = fpscr; 12247379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12257379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12267379Sgblack@eecs.umich.edu ''' 12277396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 12287379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 12297379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12307396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 12317396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 12327379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 12337379Sgblack@eecs.umich.edu 12347379Sgblack@eecs.umich.edu vcvtFpUFixedSCode = ''' 12357397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12367397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 12377397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12387381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12397379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 12407381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 12417397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 12427397Sgblack@eecs.umich.edu Fpscr = fpscr; 12437379Sgblack@eecs.umich.edu ''' 12447396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 12457379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 12467379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12477396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 12487396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 12497379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 12507379Sgblack@eecs.umich.edu 12517379Sgblack@eecs.umich.edu vcvtFpUFixedDCode = ''' 12527397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12537397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 12547397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 12557397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12567397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 12577397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); 12587381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 12597397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 12607397Sgblack@eecs.umich.edu Fpscr = fpscr; 12617379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12627379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12637379Sgblack@eecs.umich.edu ''' 12647396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 12657379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 12667379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12677396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 12687396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 12697379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 12707379Sgblack@eecs.umich.edu 12717379Sgblack@eecs.umich.edu vcvtSFixedFpSCode = ''' 12727397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12737397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12747381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 12757386Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm); 12767381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 12777397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 12787397Sgblack@eecs.umich.edu Fpscr = fpscr; 12797379Sgblack@eecs.umich.edu ''' 12807396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 12817379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 12827379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12837396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 12847396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 12857379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 12867379Sgblack@eecs.umich.edu 12877379Sgblack@eecs.umich.edu vcvtSFixedFpDCode = ''' 12887397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12897379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12907397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 12917381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 12927397Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(Fpscr, mid, false, imm); 12937397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 12947397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 12957397Sgblack@eecs.umich.edu Fpscr = fpscr; 12967397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 12977397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 12987379Sgblack@eecs.umich.edu ''' 12997396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 13007379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 13017379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13027396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 13037396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 13047379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 13057379Sgblack@eecs.umich.edu 13067379Sgblack@eecs.umich.edu vcvtUFixedFpSCode = ''' 13077397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13087397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13097381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 13107386Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm); 13117381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 13127397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 13137397Sgblack@eecs.umich.edu Fpscr = fpscr; 13147379Sgblack@eecs.umich.edu ''' 13157396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 13167379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 13177379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13187396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 13197396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 13207379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 13217379Sgblack@eecs.umich.edu 13227379Sgblack@eecs.umich.edu vcvtUFixedFpDCode = ''' 13237397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13247379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13257397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13267381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 13277397Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(Fpscr, mid, false, imm); 13287397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 13297397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 13307397Sgblack@eecs.umich.edu Fpscr = fpscr; 13317397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 13327397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 13337379Sgblack@eecs.umich.edu ''' 13347396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 13357379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 13367379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13377396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 13387396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 13397379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 13407379Sgblack@eecs.umich.edu 13417379Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = ''' 13427397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13437397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13447397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13457381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13467379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 13477381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 13487397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 13497397Sgblack@eecs.umich.edu Fpscr = fpscr; 13507379Sgblack@eecs.umich.edu ''' 13517379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 13527396Sgblack@eecs.umich.edu "FpRegRegImmOp", 13537379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 13547379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13557396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 13567396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 13577379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 13587379Sgblack@eecs.umich.edu 13597379Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = ''' 13607397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13617397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 13627397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 13637397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13647397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 13657397Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); 13667381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 13677397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 13687397Sgblack@eecs.umich.edu Fpscr = fpscr; 13697379Sgblack@eecs.umich.edu FpDestP0.uw = result; 13707379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 13717379Sgblack@eecs.umich.edu ''' 13727379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 13737396Sgblack@eecs.umich.edu "FpRegRegImmOp", 13747379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 13757379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13767396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 13777396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 13787379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 13797379Sgblack@eecs.umich.edu 13807379Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = ''' 13817397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13827397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 13837397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 13847381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13857379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 13867381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 13877397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 13887397Sgblack@eecs.umich.edu Fpscr = fpscr; 13897379Sgblack@eecs.umich.edu ''' 13907379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 13917396Sgblack@eecs.umich.edu "FpRegRegImmOp", 13927379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 13937379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13947396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 13957396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 13967379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 13977379Sgblack@eecs.umich.edu 13987379Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = ''' 13997397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14007397Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); 14017397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14027397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14037397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 14047397Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); 14057381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 14067397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 14077397Sgblack@eecs.umich.edu Fpscr = fpscr; 14087379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 14097379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 14107379Sgblack@eecs.umich.edu ''' 14117379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 14127396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14137379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 14147379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14157396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 14167396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 14177379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 14187379Sgblack@eecs.umich.edu 14197379Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = ''' 14207397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14217397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14227381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 14237386Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm); 14247381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14257397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 14267397Sgblack@eecs.umich.edu Fpscr = fpscr; 14277379Sgblack@eecs.umich.edu ''' 14287379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 14297396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14307379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 14317379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14327396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 14337396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 14347379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 14357379Sgblack@eecs.umich.edu 14367379Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = ''' 14377397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14387379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14397397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14407381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14417397Sgblack@eecs.umich.edu double cDest = vfpSFixedToFpD(Fpscr, mid, true, imm); 14427397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14437397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 14447397Sgblack@eecs.umich.edu Fpscr = fpscr; 14457397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 14467397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 14477379Sgblack@eecs.umich.edu ''' 14487379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 14497396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14507379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 14517379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14527396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 14537396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 14547379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 14557379Sgblack@eecs.umich.edu 14567379Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = ''' 14577397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14587397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14597381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 14607386Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm); 14617381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14627397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 14637397Sgblack@eecs.umich.edu Fpscr = fpscr; 14647379Sgblack@eecs.umich.edu ''' 14657379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 14667396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14677379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 14687379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14697396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 14707396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 14717379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 14727379Sgblack@eecs.umich.edu 14737379Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = ''' 14747397Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 14757379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14767397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14777381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14787397Sgblack@eecs.umich.edu double cDest = vfpUFixedToFpD(Fpscr, mid, true, imm); 14797397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 14807397Sgblack@eecs.umich.edu finishVfp(fpscr, state); 14817397Sgblack@eecs.umich.edu Fpscr = fpscr; 14827397Sgblack@eecs.umich.edu FpDestP0.uw = dblLow(cDest); 14837397Sgblack@eecs.umich.edu FpDestP1.uw = dblHi(cDest); 14847379Sgblack@eecs.umich.edu ''' 14857379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 14867396Sgblack@eecs.umich.edu "FpRegRegImmOp", 14877379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 14887379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14897396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 14907396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 14917379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 14927379Sgblack@eecs.umich.edu}}; 1493