fp.isa revision 7392
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947375Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp", 1957322Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 1967322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1977375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmsrIop); 1987375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmsrIop); 1997322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2007324Sgblack@eecs.umich.edu 2017375Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp", 2027324Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 2037324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmrsIop); 2057375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmrsIop); 2067324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2077333Sgblack@eecs.umich.edu 2087392Sgblack@eecs.umich.edu vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);" 2097392Sgblack@eecs.umich.edu vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "VfpRegRegImmOp", 2107392Sgblack@eecs.umich.edu { "code": vmrsApsrCode, 2117392Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2127392Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmrsApsrIop); 2137392Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmrsApsrIop); 2147392Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrIop); 2157392Sgblack@eecs.umich.edu 2167333Sgblack@eecs.umich.edu vmovImmSCode = ''' 2177333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2187333Sgblack@eecs.umich.edu ''' 2197375Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp", 2207333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2217333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2227375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmSIop); 2237375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop); 2247333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2257333Sgblack@eecs.umich.edu 2267333Sgblack@eecs.umich.edu vmovImmDCode = ''' 2277333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2287333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2297333Sgblack@eecs.umich.edu ''' 2307375Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp", 2317333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2327333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2337375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmDIop); 2347375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop); 2357333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2367333Sgblack@eecs.umich.edu 2377333Sgblack@eecs.umich.edu vmovImmQCode = ''' 2387333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2397333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2407333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2417333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2427333Sgblack@eecs.umich.edu ''' 2437375Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp", 2447333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2457333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2467375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmQIop); 2477375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop); 2487333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2497333Sgblack@eecs.umich.edu 2507333Sgblack@eecs.umich.edu vmovRegSCode = ''' 2517333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2527333Sgblack@eecs.umich.edu ''' 2537375Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp", 2547333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2557333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2567375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegSIop); 2577375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop); 2587333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2597333Sgblack@eecs.umich.edu 2607333Sgblack@eecs.umich.edu vmovRegDCode = ''' 2617333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2627333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2637333Sgblack@eecs.umich.edu ''' 2647375Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp", 2657333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2667333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2677375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegDIop); 2687375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop); 2697333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2707333Sgblack@eecs.umich.edu 2717333Sgblack@eecs.umich.edu vmovRegQCode = ''' 2727333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2737333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2747333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2757333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2767333Sgblack@eecs.umich.edu ''' 2777375Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp", 2787333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2797333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2807375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegQIop); 2817375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegQIop); 2827333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2837333Sgblack@eecs.umich.edu 2847333Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 2857333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 2867333Sgblack@eecs.umich.edu ''' 2877375Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp", 2887333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2897333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2907375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2917375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2927333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2937333Sgblack@eecs.umich.edu 2947333Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 2957333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 2967333Sgblack@eecs.umich.edu ''' 2977375Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp", 2987333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 2997333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3007375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3017375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3027333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3037333Sgblack@eecs.umich.edu 3047333Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 3057333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 3067333Sgblack@eecs.umich.edu ''' 3077375Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp", 3087333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3097333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3107375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovCoreRegWIop); 3117375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovCoreRegWIop); 3127333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3137333Sgblack@eecs.umich.edu 3147333Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 3157333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 3167333Sgblack@eecs.umich.edu ''' 3177375Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp", 3187333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3197333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3207375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3217375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3227333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3237333Sgblack@eecs.umich.edu 3247333Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 3257333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 3267333Sgblack@eecs.umich.edu ''' 3277375Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp", 3287333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3297333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3307375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3317375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3327333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3337333Sgblack@eecs.umich.edu 3347333Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 3357333Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 3367333Sgblack@eecs.umich.edu ''' 3377375Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp", 3387333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3397333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3407375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3417375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3427333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3437333Sgblack@eecs.umich.edu 3447333Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 3457333Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 3467333Sgblack@eecs.umich.edu ''' 3477375Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp", 3487333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3497333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3507375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3517375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3527333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3537333Sgblack@eecs.umich.edu 3547333Sgblack@eecs.umich.edu vmovRegCoreWCode = ''' 3557333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3567333Sgblack@eecs.umich.edu ''' 3577375Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp", 3587333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3597333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3607375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegCoreWIop); 3617375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegCoreWIop); 3627333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 3637333Sgblack@eecs.umich.edu 3647333Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 3657333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3667333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3677333Sgblack@eecs.umich.edu ''' 3687375Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp", 3697333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3707333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3717375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3727375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3737333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3747333Sgblack@eecs.umich.edu 3757333Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 3767333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3777333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3787333Sgblack@eecs.umich.edu ''' 3797375Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp", 3807333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3817333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3827375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3837375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3857381Sgblack@eecs.umich.edu}}; 3867381Sgblack@eecs.umich.edu 3877381Sgblack@eecs.umich.edulet {{ 3887381Sgblack@eecs.umich.edu 3897381Sgblack@eecs.umich.edu header_output = "" 3907381Sgblack@eecs.umich.edu decoder_output = "" 3917381Sgblack@eecs.umich.edu exec_output = "" 3927364Sgblack@eecs.umich.edu 3937364Sgblack@eecs.umich.edu vmulSCode = ''' 3947382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 3957378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 3967381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 3977386Sgblack@eecs.umich.edu FpDest = fixMultDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 3987381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 3997378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4007364Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 4017364Sgblack@eecs.umich.edu FpDest = NAN; 4027364Sgblack@eecs.umich.edu } 4037364Sgblack@eecs.umich.edu ''' 4047375Sgblack@eecs.umich.edu vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 4057364Sgblack@eecs.umich.edu { "code": vmulSCode, 4067364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4077375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulSIop); 4087375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop); 4097364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulSIop); 4107364Sgblack@eecs.umich.edu 4117364Sgblack@eecs.umich.edu vmulDCode = ''' 4127364Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4137364Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4147364Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4157382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 4167378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4177381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 4187386Sgblack@eecs.umich.edu cDest.fp = fixMultDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 4197381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 4207378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4217364Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 4227364Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 4237364Sgblack@eecs.umich.edu cDest.fp = NAN; 4247364Sgblack@eecs.umich.edu } 4257364Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4267364Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4277364Sgblack@eecs.umich.edu ''' 4287375Sgblack@eecs.umich.edu vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp", 4297364Sgblack@eecs.umich.edu { "code": vmulDCode, 4307364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4317375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulDIop); 4327375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop); 4337364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulDIop); 4347365Sgblack@eecs.umich.edu 4357365Sgblack@eecs.umich.edu vnegSCode = ''' 4367365Sgblack@eecs.umich.edu FpDest = -FpOp1; 4377365Sgblack@eecs.umich.edu ''' 4387375Sgblack@eecs.umich.edu vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp", 4397365Sgblack@eecs.umich.edu { "code": vnegSCode, 4407365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4417375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegSIop); 4427375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegSIop); 4437365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegSIop); 4447365Sgblack@eecs.umich.edu 4457365Sgblack@eecs.umich.edu vnegDCode = ''' 4467365Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4477365Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4487365Sgblack@eecs.umich.edu cDest.fp = -cOp1.fp; 4497365Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4507365Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4517365Sgblack@eecs.umich.edu ''' 4527375Sgblack@eecs.umich.edu vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp", 4537365Sgblack@eecs.umich.edu { "code": vnegDCode, 4547365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4557375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegDIop); 4567375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegDIop); 4577365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegDIop); 4587366Sgblack@eecs.umich.edu 4597366Sgblack@eecs.umich.edu vabsSCode = ''' 4607366Sgblack@eecs.umich.edu FpDest = fabsf(FpOp1); 4617366Sgblack@eecs.umich.edu ''' 4627375Sgblack@eecs.umich.edu vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp", 4637366Sgblack@eecs.umich.edu { "code": vabsSCode, 4647366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4657375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsSIop); 4667375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsSIop); 4677366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsSIop); 4687366Sgblack@eecs.umich.edu 4697366Sgblack@eecs.umich.edu vabsDCode = ''' 4707366Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4717366Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4727366Sgblack@eecs.umich.edu cDest.fp = fabs(cOp1.fp); 4737366Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4747366Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4757366Sgblack@eecs.umich.edu ''' 4767375Sgblack@eecs.umich.edu vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp", 4777366Sgblack@eecs.umich.edu { "code": vabsDCode, 4787366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4797375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsDIop); 4807375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsDIop); 4817366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsDIop); 4827367Sgblack@eecs.umich.edu 4837367Sgblack@eecs.umich.edu vaddSCode = ''' 4847382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 4857378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4867381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 4877385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpOp1 + FpOp2, FpOp1, FpOp2); 4887381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 4897378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4907367Sgblack@eecs.umich.edu ''' 4917375Sgblack@eecs.umich.edu vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp", 4927367Sgblack@eecs.umich.edu { "code": vaddSCode, 4937367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4947375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddSIop); 4957375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop); 4967367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddSIop); 4977367Sgblack@eecs.umich.edu 4987367Sgblack@eecs.umich.edu vaddDCode = ''' 4997367Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5007367Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5017367Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5027385Sgblack@eecs.umich.edu DPRINTFN("cOp1.bits = %#x, cOp1.fp = %f.\\n", cOp1.bits, cOp1.fp); 5037385Sgblack@eecs.umich.edu DPRINTFN("cOp2.bits = %#x, cOp2.fp = %f.\\n", cOp2.bits, cOp2.fp); 5047382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 5057378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5067381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 5077385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cOp1.fp + cOp2.fp, cOp1.fp, cOp2.fp); 5087385Sgblack@eecs.umich.edu DPRINTFN("cDest.bits = %#x, cDest.fp = %f.\\n", cDest.bits, cDest.fp); 5097381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5107378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5117367Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5127367Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5137367Sgblack@eecs.umich.edu ''' 5147375Sgblack@eecs.umich.edu vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp", 5157367Sgblack@eecs.umich.edu { "code": vaddDCode, 5167367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5177375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddDIop); 5187375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop); 5197367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddDIop); 5207368Sgblack@eecs.umich.edu 5217368Sgblack@eecs.umich.edu vsubSCode = ''' 5227382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 5237378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5247381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5257385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpOp1 - FpOp2, FpOp1, FpOp2); 5267381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5277378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state) 5287368Sgblack@eecs.umich.edu ''' 5297375Sgblack@eecs.umich.edu vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp", 5307368Sgblack@eecs.umich.edu { "code": vsubSCode, 5317368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5327375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubSIop); 5337375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop); 5347368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubSIop); 5357368Sgblack@eecs.umich.edu 5367368Sgblack@eecs.umich.edu vsubDCode = ''' 5377368Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5387368Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5397368Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5407382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 5417378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5427381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 5437385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cOp1.fp - cOp2.fp, cOp1.fp, cOp2.fp); 5447381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5457378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5467368Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5477368Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5487368Sgblack@eecs.umich.edu ''' 5497375Sgblack@eecs.umich.edu vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp", 5507368Sgblack@eecs.umich.edu { "code": vsubDCode, 5517368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5527375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubDIop); 5537375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop); 5547368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubDIop); 5557369Sgblack@eecs.umich.edu 5567369Sgblack@eecs.umich.edu vdivSCode = ''' 5577382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 5587378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5597381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5607385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpOp1 / FpOp2, FpOp1, FpOp2); 5617381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5627378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5637369Sgblack@eecs.umich.edu ''' 5647375Sgblack@eecs.umich.edu vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp", 5657369Sgblack@eecs.umich.edu { "code": vdivSCode, 5667369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5677375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivSIop); 5687375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop); 5697369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivSIop); 5707369Sgblack@eecs.umich.edu 5717369Sgblack@eecs.umich.edu vdivDCode = ''' 5727369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5737369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5747369Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5757382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 5767378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5777381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); 5787385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cOp1.fp / cOp2.fp, cOp1.fp, cOp2.fp); 5797381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5807378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5817369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5827369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5837369Sgblack@eecs.umich.edu ''' 5847375Sgblack@eecs.umich.edu vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp", 5857369Sgblack@eecs.umich.edu { "code": vdivDCode, 5867369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5877375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivDIop); 5887375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop); 5897369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivDIop); 5907369Sgblack@eecs.umich.edu 5917369Sgblack@eecs.umich.edu vsqrtSCode = ''' 5927382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 5937378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5947381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5957369Sgblack@eecs.umich.edu FpDest = sqrtf(FpOp1); 5967381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5977378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5987369Sgblack@eecs.umich.edu if (FpOp1 < 0) { 5997369Sgblack@eecs.umich.edu FpDest = NAN; 6007369Sgblack@eecs.umich.edu } 6017369Sgblack@eecs.umich.edu ''' 6027375Sgblack@eecs.umich.edu vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp", 6037369Sgblack@eecs.umich.edu { "code": vsqrtSCode, 6047369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6057375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtSIop); 6067375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop); 6077369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtSIop); 6087369Sgblack@eecs.umich.edu 6097369Sgblack@eecs.umich.edu vsqrtDCode = ''' 6107369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 6117369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6127382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 6137378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6147381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); 6157369Sgblack@eecs.umich.edu cDest.fp = sqrt(cOp1.fp); 6167381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 6177378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6187369Sgblack@eecs.umich.edu if (cOp1.fp < 0) { 6197369Sgblack@eecs.umich.edu cDest.fp = NAN; 6207369Sgblack@eecs.umich.edu } 6217369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6227369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6237369Sgblack@eecs.umich.edu ''' 6247375Sgblack@eecs.umich.edu vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp", 6257369Sgblack@eecs.umich.edu { "code": vsqrtDCode, 6267369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6277375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtDIop); 6287375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop); 6297369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtDIop); 6307381Sgblack@eecs.umich.edu}}; 6317381Sgblack@eecs.umich.edu 6327381Sgblack@eecs.umich.edulet {{ 6337381Sgblack@eecs.umich.edu 6347381Sgblack@eecs.umich.edu header_output = "" 6357381Sgblack@eecs.umich.edu decoder_output = "" 6367381Sgblack@eecs.umich.edu exec_output = "" 6377370Sgblack@eecs.umich.edu 6387370Sgblack@eecs.umich.edu vmlaSCode = ''' 6397382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 6407378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6417381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 6427385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 6437370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6447370Sgblack@eecs.umich.edu mid = NAN; 6457370Sgblack@eecs.umich.edu } 6467382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 6477385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpDest + mid, FpDest, mid); 6487381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6497378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6507370Sgblack@eecs.umich.edu ''' 6517375Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp", 6527370Sgblack@eecs.umich.edu { "code": vmlaSCode, 6537370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6547375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop); 6557375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop); 6567370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 6577370Sgblack@eecs.umich.edu 6587370Sgblack@eecs.umich.edu vmlaDCode = ''' 6597370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6607370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6617370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6627370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6637382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 6647378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6657381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 6667385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 6677370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6687370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6697370Sgblack@eecs.umich.edu mid = NAN; 6707370Sgblack@eecs.umich.edu } 6717382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 6727385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cDest.fp + mid, cDest.fp, mid); 6737381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 6747378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6757370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6767370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6777370Sgblack@eecs.umich.edu ''' 6787375Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp", 6797370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6807370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6817375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop); 6827375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop); 6837370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6847370Sgblack@eecs.umich.edu 6857370Sgblack@eecs.umich.edu vmlsSCode = ''' 6867382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 6877378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6887381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 6897385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 6907370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6917370Sgblack@eecs.umich.edu mid = NAN; 6927370Sgblack@eecs.umich.edu } 6937382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 6947386Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpDest - mid, FpDest, -mid); 6957381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6967378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6977370Sgblack@eecs.umich.edu ''' 6987375Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 6997370Sgblack@eecs.umich.edu { "code": vmlsSCode, 7007370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7017375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 7027375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); 7037370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 7047370Sgblack@eecs.umich.edu 7057370Sgblack@eecs.umich.edu vmlsDCode = ''' 7067370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7077370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7087370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7097370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7107382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7117378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7127381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7137385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 7147370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7157370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7167370Sgblack@eecs.umich.edu mid = NAN; 7177370Sgblack@eecs.umich.edu } 7187386Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cDest.fp - mid, cDest.fp, -mid); 7197382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 7207381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 7217378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7227370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7237370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7247370Sgblack@eecs.umich.edu ''' 7257375Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 7267370Sgblack@eecs.umich.edu { "code": vmlsDCode, 7277370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7287375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop); 7297375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop); 7307370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 7317371Sgblack@eecs.umich.edu 7327371Sgblack@eecs.umich.edu vnmlaSCode = ''' 7337382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 7347378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7357381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7367385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 7377371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7387371Sgblack@eecs.umich.edu mid = NAN; 7397371Sgblack@eecs.umich.edu } 7407382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 7417386Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, -FpDest - mid, -FpDest, -mid); 7427381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7437378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7447371Sgblack@eecs.umich.edu ''' 7457375Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 7467371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 7477371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7487375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 7497375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); 7507371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 7517371Sgblack@eecs.umich.edu 7527371Sgblack@eecs.umich.edu vnmlaDCode = ''' 7537371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7547371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7557371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7567371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7577382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7587378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7597381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7607385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 7617371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7627371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7637371Sgblack@eecs.umich.edu mid = NAN; 7647371Sgblack@eecs.umich.edu } 7657382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 7667386Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, -cDest.fp - mid, -cDest.fp, -mid); 7677381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 7687378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7697371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7707371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7717371Sgblack@eecs.umich.edu ''' 7727375Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 7737371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 7747371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7757375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop); 7767375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop); 7777371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 7787371Sgblack@eecs.umich.edu 7797371Sgblack@eecs.umich.edu vnmlsSCode = ''' 7807382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 7817378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7827381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7837385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 7847371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7857371Sgblack@eecs.umich.edu mid = NAN; 7867371Sgblack@eecs.umich.edu } 7877382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 7887386Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, -FpDest + mid, -FpDest, mid); 7897381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7907378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7917371Sgblack@eecs.umich.edu ''' 7927375Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 7937371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 7947371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7957375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 7967375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); 7977371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7987371Sgblack@eecs.umich.edu 7997371Sgblack@eecs.umich.edu vnmlsDCode = ''' 8007371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 8017371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8027371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 8037371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 8047382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 8057378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8067381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 8077385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 8087371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 8097371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 8107371Sgblack@eecs.umich.edu mid = NAN; 8117371Sgblack@eecs.umich.edu } 8127382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 8137386Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, -cDest.fp + mid, -cDest.fp, mid); 8147381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8157378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8167371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8177371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8187371Sgblack@eecs.umich.edu ''' 8197375Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 8207371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 8217371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8227375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop); 8237375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop); 8247371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 8257371Sgblack@eecs.umich.edu 8267371Sgblack@eecs.umich.edu vnmulSCode = ''' 8277382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 8287378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8297381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8307385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 8317371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 8327371Sgblack@eecs.umich.edu mid = NAN; 8337371Sgblack@eecs.umich.edu } 8347371Sgblack@eecs.umich.edu FpDest = -mid; 8357381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8367378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8377371Sgblack@eecs.umich.edu ''' 8387375Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp", 8397371Sgblack@eecs.umich.edu { "code": vnmulSCode, 8407371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8417375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop); 8427375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop); 8437371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 8447371Sgblack@eecs.umich.edu 8457371Sgblack@eecs.umich.edu vnmulDCode = ''' 8467371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 8477371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8487371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 8497371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 8507382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 8517378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8527381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 8537385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 8547371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 8557371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 8567371Sgblack@eecs.umich.edu mid = NAN; 8577371Sgblack@eecs.umich.edu } 8587371Sgblack@eecs.umich.edu cDest.fp = -mid; 8597381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8607378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8617371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8627371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8637371Sgblack@eecs.umich.edu ''' 8647375Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp", 8657371Sgblack@eecs.umich.edu { "code": vnmulDCode, 8667371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8677375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop); 8687375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop); 8697371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 8707381Sgblack@eecs.umich.edu}}; 8717381Sgblack@eecs.umich.edu 8727381Sgblack@eecs.umich.edulet {{ 8737381Sgblack@eecs.umich.edu 8747381Sgblack@eecs.umich.edu header_output = "" 8757381Sgblack@eecs.umich.edu decoder_output = "" 8767381Sgblack@eecs.umich.edu exec_output = "" 8777373Sgblack@eecs.umich.edu 8787373Sgblack@eecs.umich.edu vcvtUIntFpSCode = ''' 8797378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8807381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 8817373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 8827381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8837378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8847373Sgblack@eecs.umich.edu ''' 8857375Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp", 8867373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 8877373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8887375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop); 8897375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop); 8907373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 8917373Sgblack@eecs.umich.edu 8927373Sgblack@eecs.umich.edu vcvtUIntFpDCode = ''' 8937373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 8947378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8957381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 8967373Sgblack@eecs.umich.edu cDest.fp = (uint64_t)FpOp1P0.uw; 8977381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8987378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8997373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 9007373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 9017373Sgblack@eecs.umich.edu ''' 9027375Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp", 9037373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 9047373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9057375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop); 9067375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop); 9077373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 9087373Sgblack@eecs.umich.edu 9097373Sgblack@eecs.umich.edu vcvtSIntFpSCode = ''' 9107378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9117381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 9127373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 9137381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9147378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9157373Sgblack@eecs.umich.edu ''' 9167375Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp", 9177373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 9187373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9197375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop); 9207375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop); 9217373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 9227373Sgblack@eecs.umich.edu 9237373Sgblack@eecs.umich.edu vcvtSIntFpDCode = ''' 9247373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 9257378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9267381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 9277373Sgblack@eecs.umich.edu cDest.fp = FpOp1P0.sw; 9287381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 9297378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9307373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 9317373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 9327373Sgblack@eecs.umich.edu ''' 9337375Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp", 9347373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 9357373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9367375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop); 9377375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop); 9387373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 9397373Sgblack@eecs.umich.edu 9407380Sgblack@eecs.umich.edu vcvtFpUIntSRCode = ''' 9417382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 9427380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9437381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9447388Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 9457381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 9467380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9477380Sgblack@eecs.umich.edu ''' 9487380Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp", 9497380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 9507380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9517380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 9527380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 9537380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 9547380Sgblack@eecs.umich.edu 9557380Sgblack@eecs.umich.edu vcvtFpUIntDRCode = ''' 9567380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9577380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9587382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 9597380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9607381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 9617388Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0, false); 9627381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9637380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9647380Sgblack@eecs.umich.edu FpDestP0.uw = result; 9657380Sgblack@eecs.umich.edu ''' 9667380Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp", 9677380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 9687380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9697380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 9707380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 9717380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 9727380Sgblack@eecs.umich.edu 9737380Sgblack@eecs.umich.edu vcvtFpSIntSRCode = ''' 9747382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 9757380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9767381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9777388Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 9787381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 9797380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9807380Sgblack@eecs.umich.edu ''' 9817380Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp", 9827380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 9837380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9847380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 9857380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 9867380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 9877380Sgblack@eecs.umich.edu 9887380Sgblack@eecs.umich.edu vcvtFpSIntDRCode = ''' 9897380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9907380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9917382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 9927380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9937381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 9947388Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0, false); 9957381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9967380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9977380Sgblack@eecs.umich.edu FpDestP0.uw = result; 9987380Sgblack@eecs.umich.edu ''' 9997380Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp", 10007380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 10017380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10027380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 10037380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 10047380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 10057380Sgblack@eecs.umich.edu 10067373Sgblack@eecs.umich.edu vcvtFpUIntSCode = ''' 10077382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10087378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10097380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10107381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10117387Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 10127381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10137378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10147373Sgblack@eecs.umich.edu ''' 10157375Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp", 10167373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 10177373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10187375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop); 10197375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop); 10207373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 10217373Sgblack@eecs.umich.edu 10227373Sgblack@eecs.umich.edu vcvtFpUIntDCode = ''' 10237373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10247373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10257382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10267378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10277380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10287381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10297387Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0); 10307381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10317378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10327373Sgblack@eecs.umich.edu FpDestP0.uw = result; 10337373Sgblack@eecs.umich.edu ''' 10347375Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp", 10357373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 10367373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10377375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop); 10387375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop); 10397373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 10407373Sgblack@eecs.umich.edu 10417373Sgblack@eecs.umich.edu vcvtFpSIntSCode = ''' 10427382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10437378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10447380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10457381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10467387Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 10477381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 10487378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10497373Sgblack@eecs.umich.edu ''' 10507375Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp", 10517373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 10527373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10537375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop); 10547375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop); 10557373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 10567373Sgblack@eecs.umich.edu 10577373Sgblack@eecs.umich.edu vcvtFpSIntDCode = ''' 10587373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10597373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10607382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10617378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10627380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10637381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10647387Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0); 10657381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10667378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10677373Sgblack@eecs.umich.edu FpDestP0.uw = result; 10687373Sgblack@eecs.umich.edu ''' 10697375Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp", 10707373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 10717373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10727375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop); 10737375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop); 10747373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 10757374Sgblack@eecs.umich.edu 10767374Sgblack@eecs.umich.edu vcvtFpSFpDCode = ''' 10777374Sgblack@eecs.umich.edu IntDoubleUnion cDest; 10787382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10797378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10807381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10817374Sgblack@eecs.umich.edu cDest.fp = FpOp1; 10827381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 10837378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10847374Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 10857374Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 10867374Sgblack@eecs.umich.edu ''' 10877375Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp", 10887374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 10897374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10907375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop); 10917375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop); 10927374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 10937374Sgblack@eecs.umich.edu 10947374Sgblack@eecs.umich.edu vcvtFpDFpSCode = ''' 10957374Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10967374Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10977382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10987378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10997381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 11007386Sgblack@eecs.umich.edu FpDest = fixFpDFpSDest(Fpscr, cOp1.fp); 11017381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11027378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11037374Sgblack@eecs.umich.edu ''' 11047375Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 11057374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 11067374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11077375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 11087375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 11097374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 11107377Sgblack@eecs.umich.edu 11117377Sgblack@eecs.umich.edu vcmpSCode = ''' 11127389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, FpOp1); 11137377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11147377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11157377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11167377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11177377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11187377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11197377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11207377Sgblack@eecs.umich.edu } else { 11217389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11227389Sgblack@eecs.umich.edu union 11237389Sgblack@eecs.umich.edu { 11247389Sgblack@eecs.umich.edu float fp; 11257389Sgblack@eecs.umich.edu uint32_t bits; 11267389Sgblack@eecs.umich.edu } cvtr; 11277389Sgblack@eecs.umich.edu cvtr.fp = FpDest; 11287389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 11297389Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((cvtr.bits & qnan) != qnan); 11307389Sgblack@eecs.umich.edu cvtr.fp = FpOp1; 11317389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 11327389Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((cvtr.bits & qnan) != qnan); 11337389Sgblack@eecs.umich.edu if (signal1 || signal2) 11347389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11357377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11367377Sgblack@eecs.umich.edu } 11377377Sgblack@eecs.umich.edu Fpscr = fpscr; 11387377Sgblack@eecs.umich.edu ''' 11397377Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 11407377Sgblack@eecs.umich.edu { "code": vcmpSCode, 11417377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11427377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpSIop); 11437377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop); 11447377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 11457377Sgblack@eecs.umich.edu 11467377Sgblack@eecs.umich.edu vcmpDCode = ''' 11477377Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 11487377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 11497377Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 11507382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); 11517377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11527377Sgblack@eecs.umich.edu if (cDest.fp == cOp1.fp) { 11537377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11547377Sgblack@eecs.umich.edu } else if (cDest.fp < cOp1.fp) { 11557377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11567377Sgblack@eecs.umich.edu } else if (cDest.fp > cOp1.fp) { 11577377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11587377Sgblack@eecs.umich.edu } else { 11597389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 11607389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest.fp); 11617389Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((cDest.bits & qnan) != qnan); 11627389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1.fp); 11637389Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan); 11647389Sgblack@eecs.umich.edu if (signal1 || signal2) 11657389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11667377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11677377Sgblack@eecs.umich.edu } 11687377Sgblack@eecs.umich.edu Fpscr = fpscr; 11697377Sgblack@eecs.umich.edu ''' 11707377Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 11717377Sgblack@eecs.umich.edu { "code": vcmpDCode, 11727377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11737377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 11747377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 11757377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 11767377Sgblack@eecs.umich.edu 11777377Sgblack@eecs.umich.edu vcmpZeroSCode = ''' 11787389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest); 11797377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11807389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11817389Sgblack@eecs.umich.edu assert(imm == 0); 11827377Sgblack@eecs.umich.edu if (FpDest == imm) { 11837377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11847377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11857377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11867377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11877377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11887377Sgblack@eecs.umich.edu } else { 11897389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11907389Sgblack@eecs.umich.edu union 11917389Sgblack@eecs.umich.edu { 11927389Sgblack@eecs.umich.edu float fp; 11937389Sgblack@eecs.umich.edu uint32_t bits; 11947389Sgblack@eecs.umich.edu } cvtr; 11957389Sgblack@eecs.umich.edu cvtr.fp = FpDest; 11967389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 11977389Sgblack@eecs.umich.edu const bool signal = nan && ((cvtr.bits & qnan) != qnan); 11987389Sgblack@eecs.umich.edu if (signal) 11997389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12007377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12017377Sgblack@eecs.umich.edu } 12027377Sgblack@eecs.umich.edu Fpscr = fpscr; 12037377Sgblack@eecs.umich.edu ''' 12047377Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 12057377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 12067377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12077377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 12087377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 12097377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 12107377Sgblack@eecs.umich.edu 12117377Sgblack@eecs.umich.edu vcmpZeroDCode = ''' 12127377Sgblack@eecs.umich.edu IntDoubleUnion cDest; 12137389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12147389Sgblack@eecs.umich.edu assert(imm == 0); 12157377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 12167382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp); 12177377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12187377Sgblack@eecs.umich.edu if (cDest.fp == imm) { 12197377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12207377Sgblack@eecs.umich.edu } else if (cDest.fp < imm) { 12217377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12227377Sgblack@eecs.umich.edu } else if (cDest.fp > imm) { 12237377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12247377Sgblack@eecs.umich.edu } else { 12257389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12267389Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest.fp); 12277389Sgblack@eecs.umich.edu const bool signal = nan && ((cDest.bits & qnan) != qnan); 12287389Sgblack@eecs.umich.edu if (signal) 12297389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12307377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12317377Sgblack@eecs.umich.edu } 12327377Sgblack@eecs.umich.edu Fpscr = fpscr; 12337377Sgblack@eecs.umich.edu ''' 12347377Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 12357377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 12367377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12377377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 12387377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 12397377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 12407389Sgblack@eecs.umich.edu 12417389Sgblack@eecs.umich.edu vcmpeSCode = ''' 12427389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, FpOp1); 12437389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12447389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12457389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12467389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12477389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12487389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12497389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12507389Sgblack@eecs.umich.edu } else { 12517389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12527389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12537389Sgblack@eecs.umich.edu } 12547389Sgblack@eecs.umich.edu Fpscr = fpscr; 12557389Sgblack@eecs.umich.edu ''' 12567389Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "VfpRegRegOp", 12577389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 12587389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12597389Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpeSIop); 12607389Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpeSIop); 12617389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 12627389Sgblack@eecs.umich.edu 12637389Sgblack@eecs.umich.edu vcmpeDCode = ''' 12647389Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 12657389Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 12667389Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12677389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); 12687389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12697389Sgblack@eecs.umich.edu if (cDest.fp == cOp1.fp) { 12707389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12717389Sgblack@eecs.umich.edu } else if (cDest.fp < cOp1.fp) { 12727389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12737389Sgblack@eecs.umich.edu } else if (cDest.fp > cOp1.fp) { 12747389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12757389Sgblack@eecs.umich.edu } else { 12767389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12777389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12787389Sgblack@eecs.umich.edu } 12797389Sgblack@eecs.umich.edu Fpscr = fpscr; 12807389Sgblack@eecs.umich.edu ''' 12817389Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "VfpRegRegOp", 12827389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 12837389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12847389Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpeDIop); 12857389Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpeDIop); 12867389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 12877389Sgblack@eecs.umich.edu 12887389Sgblack@eecs.umich.edu vcmpeZeroSCode = ''' 12897389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest); 12907389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12917389Sgblack@eecs.umich.edu if (FpDest == imm) { 12927389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12937389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12947389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12957389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12967389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12977389Sgblack@eecs.umich.edu } else { 12987389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12997389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13007389Sgblack@eecs.umich.edu } 13017389Sgblack@eecs.umich.edu Fpscr = fpscr; 13027389Sgblack@eecs.umich.edu ''' 13037389Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "VfpRegImmOp", 13047389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 13057389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13067389Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpeZeroSIop); 13077389Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroSIop); 13087389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 13097389Sgblack@eecs.umich.edu 13107389Sgblack@eecs.umich.edu vcmpeZeroDCode = ''' 13117389Sgblack@eecs.umich.edu IntDoubleUnion cDest; 13127389Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 13137389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp); 13147389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13157389Sgblack@eecs.umich.edu if (cDest.fp == imm) { 13167389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13177389Sgblack@eecs.umich.edu } else if (cDest.fp < imm) { 13187389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13197389Sgblack@eecs.umich.edu } else if (cDest.fp > imm) { 13207389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13217389Sgblack@eecs.umich.edu } else { 13227389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13237389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13247389Sgblack@eecs.umich.edu } 13257389Sgblack@eecs.umich.edu Fpscr = fpscr; 13267389Sgblack@eecs.umich.edu ''' 13277389Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "VfpRegImmOp", 13287389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 13297389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13307389Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpeZeroDIop); 13317389Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroDIop); 13327389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 13337322Sgblack@eecs.umich.edu}}; 13347379Sgblack@eecs.umich.edu 13357379Sgblack@eecs.umich.edulet {{ 13367379Sgblack@eecs.umich.edu 13377379Sgblack@eecs.umich.edu header_output = "" 13387379Sgblack@eecs.umich.edu decoder_output = "" 13397379Sgblack@eecs.umich.edu exec_output = "" 13407379Sgblack@eecs.umich.edu 13417379Sgblack@eecs.umich.edu vcvtFpSFixedSCode = ''' 13427382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 13437379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13447381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13457379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 13467381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 13477379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13487379Sgblack@eecs.umich.edu ''' 13497379Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp", 13507379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 13517379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13527379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 13537379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 13547379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 13557379Sgblack@eecs.umich.edu 13567379Sgblack@eecs.umich.edu vcvtFpSFixedDCode = ''' 13577379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 13587379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13597382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 13607379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13617381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 13627379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); 13637381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13647379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13657379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13667379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13677379Sgblack@eecs.umich.edu ''' 13687379Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp", 13697379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 13707379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13717379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 13727379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 13737379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 13747379Sgblack@eecs.umich.edu 13757379Sgblack@eecs.umich.edu vcvtFpUFixedSCode = ''' 13767382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 13777379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13787381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13797379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 13807381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 13817379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13827379Sgblack@eecs.umich.edu ''' 13837379Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp", 13847379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 13857379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13867379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 13877379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 13887379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 13897379Sgblack@eecs.umich.edu 13907379Sgblack@eecs.umich.edu vcvtFpUFixedDCode = ''' 13917379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 13927379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13937382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 13947379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13957381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 13967379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); 13977381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13987379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13997379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 14007379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 14017379Sgblack@eecs.umich.edu ''' 14027379Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp", 14037379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 14047379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14057379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 14067379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 14077379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 14087379Sgblack@eecs.umich.edu 14097379Sgblack@eecs.umich.edu vcvtSFixedFpSCode = ''' 14107379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14117381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 14127386Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm); 14137381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14147379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14157379Sgblack@eecs.umich.edu ''' 14167379Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 14177379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 14187379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14197379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 14207379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 14217379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 14227379Sgblack@eecs.umich.edu 14237379Sgblack@eecs.umich.edu vcvtSFixedFpDCode = ''' 14247379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 14257379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14267379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14277381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14287386Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm); 14297381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 14307379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14317379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 14327379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 14337379Sgblack@eecs.umich.edu ''' 14347379Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 14357379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 14367379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14377379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 14387379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 14397379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 14407379Sgblack@eecs.umich.edu 14417379Sgblack@eecs.umich.edu vcvtUFixedFpSCode = ''' 14427379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14437381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 14447386Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm); 14457381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14467379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14477379Sgblack@eecs.umich.edu ''' 14487379Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 14497379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 14507379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14517379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 14527379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 14537379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 14547379Sgblack@eecs.umich.edu 14557379Sgblack@eecs.umich.edu vcvtUFixedFpDCode = ''' 14567379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 14577379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14587379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14597381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14607386Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm); 14617381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 14627379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14637379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 14647379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 14657379Sgblack@eecs.umich.edu ''' 14667379Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 14677379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 14687379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14697379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 14707379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 14717379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 14727379Sgblack@eecs.umich.edu 14737379Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = ''' 14747382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 14757379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14767381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14777379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 14787381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 14797379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14807379Sgblack@eecs.umich.edu ''' 14817379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 14827379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 14837379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 14847379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14857379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 14867379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 14877379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 14887379Sgblack@eecs.umich.edu 14897379Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = ''' 14907379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 14917379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14927382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 14937379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14947381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 14957379Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); 14967381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 14977379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14987379Sgblack@eecs.umich.edu FpDestP0.uw = result; 14997379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 15007379Sgblack@eecs.umich.edu ''' 15017379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 15027379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15037379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 15047379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15057379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 15067379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 15077379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 15087379Sgblack@eecs.umich.edu 15097379Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = ''' 15107382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 15117379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15127381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 15137379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 15147381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 15157379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15167379Sgblack@eecs.umich.edu ''' 15177379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 15187379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15197379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 15207379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15217379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 15227379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 15237379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 15247379Sgblack@eecs.umich.edu 15257379Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = ''' 15267379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 15277379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15287382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 15297379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15307381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 15317379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); 15327381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15337379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15347379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 15357379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 15367379Sgblack@eecs.umich.edu ''' 15377379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 15387379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15397379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 15407379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15417379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 15427379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 15437379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 15447379Sgblack@eecs.umich.edu 15457379Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = ''' 15467379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15477381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 15487386Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm); 15497381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15507379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15517379Sgblack@eecs.umich.edu ''' 15527379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 15537379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15547379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 15557379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15567379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 15577379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 15587379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 15597379Sgblack@eecs.umich.edu 15607379Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = ''' 15617379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 15627379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15637379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15647381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15657386Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm); 15667381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 15677379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15687379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 15697379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 15707379Sgblack@eecs.umich.edu ''' 15717379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 15727379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15737379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 15747379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15757379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 15767379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 15777379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 15787379Sgblack@eecs.umich.edu 15797379Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = ''' 15807379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15817381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 15827386Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm); 15837381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15847379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15857379Sgblack@eecs.umich.edu ''' 15867379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 15877379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15887379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 15897379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15907379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 15917379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 15927379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 15937379Sgblack@eecs.umich.edu 15947379Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = ''' 15957379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 15967379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15977379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15997386Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm); 16007381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 16017379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 16027379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 16037379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 16047379Sgblack@eecs.umich.edu ''' 16057379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 16067379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 16077379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 16087379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 16097379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 16107379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 16117379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 16127379Sgblack@eecs.umich.edu}}; 1613