fp.isa revision 7389
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947375Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp", 1957322Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 1967322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1977375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmsrIop); 1987375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmsrIop); 1997322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2007324Sgblack@eecs.umich.edu 2017375Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp", 2027324Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 2037324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmrsIop); 2057375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmrsIop); 2067324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2077333Sgblack@eecs.umich.edu 2087333Sgblack@eecs.umich.edu vmovImmSCode = ''' 2097333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2107333Sgblack@eecs.umich.edu ''' 2117375Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp", 2127333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2137333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2147375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmSIop); 2157375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop); 2167333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2177333Sgblack@eecs.umich.edu 2187333Sgblack@eecs.umich.edu vmovImmDCode = ''' 2197333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2207333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2217333Sgblack@eecs.umich.edu ''' 2227375Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp", 2237333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2247333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2257375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmDIop); 2267375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop); 2277333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2287333Sgblack@eecs.umich.edu 2297333Sgblack@eecs.umich.edu vmovImmQCode = ''' 2307333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2317333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2327333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2337333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2347333Sgblack@eecs.umich.edu ''' 2357375Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp", 2367333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2377333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2387375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmQIop); 2397375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop); 2407333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2417333Sgblack@eecs.umich.edu 2427333Sgblack@eecs.umich.edu vmovRegSCode = ''' 2437333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2447333Sgblack@eecs.umich.edu ''' 2457375Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp", 2467333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2477333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2487375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegSIop); 2497375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop); 2507333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2517333Sgblack@eecs.umich.edu 2527333Sgblack@eecs.umich.edu vmovRegDCode = ''' 2537333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2547333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2557333Sgblack@eecs.umich.edu ''' 2567375Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp", 2577333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2587333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2597375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegDIop); 2607375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop); 2617333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2627333Sgblack@eecs.umich.edu 2637333Sgblack@eecs.umich.edu vmovRegQCode = ''' 2647333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2657333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2667333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2677333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2687333Sgblack@eecs.umich.edu ''' 2697375Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp", 2707333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2717333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2727375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegQIop); 2737375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegQIop); 2747333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2757333Sgblack@eecs.umich.edu 2767333Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 2777333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 2787333Sgblack@eecs.umich.edu ''' 2797375Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp", 2807333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2817333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2827375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2837375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2857333Sgblack@eecs.umich.edu 2867333Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 2877333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 2887333Sgblack@eecs.umich.edu ''' 2897375Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp", 2907333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 2917333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2927375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 2937375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 2947333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 2957333Sgblack@eecs.umich.edu 2967333Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 2977333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 2987333Sgblack@eecs.umich.edu ''' 2997375Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp", 3007333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3017333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3027375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovCoreRegWIop); 3037375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovCoreRegWIop); 3047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3057333Sgblack@eecs.umich.edu 3067333Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 3077333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 3087333Sgblack@eecs.umich.edu ''' 3097375Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp", 3107333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3117333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3127375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3137375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3147333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3157333Sgblack@eecs.umich.edu 3167333Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 3177333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 3187333Sgblack@eecs.umich.edu ''' 3197375Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp", 3207333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3217333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3227375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3237375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3247333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3257333Sgblack@eecs.umich.edu 3267333Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 3277333Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 3287333Sgblack@eecs.umich.edu ''' 3297375Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp", 3307333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3317333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3327375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3337375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3347333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3357333Sgblack@eecs.umich.edu 3367333Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 3377333Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 3387333Sgblack@eecs.umich.edu ''' 3397375Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp", 3407333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3417333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3427375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3437375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3447333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3457333Sgblack@eecs.umich.edu 3467333Sgblack@eecs.umich.edu vmovRegCoreWCode = ''' 3477333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3487333Sgblack@eecs.umich.edu ''' 3497375Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp", 3507333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3517333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3527375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegCoreWIop); 3537375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegCoreWIop); 3547333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 3557333Sgblack@eecs.umich.edu 3567333Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 3577333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3587333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3597333Sgblack@eecs.umich.edu ''' 3607375Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp", 3617333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3627333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3637375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3647375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3657333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3667333Sgblack@eecs.umich.edu 3677333Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 3687333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3697333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3707333Sgblack@eecs.umich.edu ''' 3717375Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp", 3727333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3737333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3747375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3757375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3767333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3777381Sgblack@eecs.umich.edu}}; 3787381Sgblack@eecs.umich.edu 3797381Sgblack@eecs.umich.edulet {{ 3807381Sgblack@eecs.umich.edu 3817381Sgblack@eecs.umich.edu header_output = "" 3827381Sgblack@eecs.umich.edu decoder_output = "" 3837381Sgblack@eecs.umich.edu exec_output = "" 3847364Sgblack@eecs.umich.edu 3857364Sgblack@eecs.umich.edu vmulSCode = ''' 3867382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 3877378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 3887381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 3897386Sgblack@eecs.umich.edu FpDest = fixMultDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 3907381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 3917378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 3927364Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 3937364Sgblack@eecs.umich.edu FpDest = NAN; 3947364Sgblack@eecs.umich.edu } 3957364Sgblack@eecs.umich.edu ''' 3967375Sgblack@eecs.umich.edu vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 3977364Sgblack@eecs.umich.edu { "code": vmulSCode, 3987364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3997375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulSIop); 4007375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop); 4017364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulSIop); 4027364Sgblack@eecs.umich.edu 4037364Sgblack@eecs.umich.edu vmulDCode = ''' 4047364Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4057364Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4067364Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4077382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 4087378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4097381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 4107386Sgblack@eecs.umich.edu cDest.fp = fixMultDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 4117381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 4127378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4137364Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 4147364Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 4157364Sgblack@eecs.umich.edu cDest.fp = NAN; 4167364Sgblack@eecs.umich.edu } 4177364Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4187364Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4197364Sgblack@eecs.umich.edu ''' 4207375Sgblack@eecs.umich.edu vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp", 4217364Sgblack@eecs.umich.edu { "code": vmulDCode, 4227364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4237375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulDIop); 4247375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop); 4257364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulDIop); 4267365Sgblack@eecs.umich.edu 4277365Sgblack@eecs.umich.edu vnegSCode = ''' 4287365Sgblack@eecs.umich.edu FpDest = -FpOp1; 4297365Sgblack@eecs.umich.edu ''' 4307375Sgblack@eecs.umich.edu vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp", 4317365Sgblack@eecs.umich.edu { "code": vnegSCode, 4327365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4337375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegSIop); 4347375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegSIop); 4357365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegSIop); 4367365Sgblack@eecs.umich.edu 4377365Sgblack@eecs.umich.edu vnegDCode = ''' 4387365Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4397365Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4407365Sgblack@eecs.umich.edu cDest.fp = -cOp1.fp; 4417365Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4427365Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4437365Sgblack@eecs.umich.edu ''' 4447375Sgblack@eecs.umich.edu vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp", 4457365Sgblack@eecs.umich.edu { "code": vnegDCode, 4467365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4477375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegDIop); 4487375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegDIop); 4497365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegDIop); 4507366Sgblack@eecs.umich.edu 4517366Sgblack@eecs.umich.edu vabsSCode = ''' 4527366Sgblack@eecs.umich.edu FpDest = fabsf(FpOp1); 4537366Sgblack@eecs.umich.edu ''' 4547375Sgblack@eecs.umich.edu vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp", 4557366Sgblack@eecs.umich.edu { "code": vabsSCode, 4567366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4577375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsSIop); 4587375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsSIop); 4597366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsSIop); 4607366Sgblack@eecs.umich.edu 4617366Sgblack@eecs.umich.edu vabsDCode = ''' 4627366Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4637366Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4647366Sgblack@eecs.umich.edu cDest.fp = fabs(cOp1.fp); 4657366Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4667366Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4677366Sgblack@eecs.umich.edu ''' 4687375Sgblack@eecs.umich.edu vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp", 4697366Sgblack@eecs.umich.edu { "code": vabsDCode, 4707366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4717375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsDIop); 4727375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsDIop); 4737366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsDIop); 4747367Sgblack@eecs.umich.edu 4757367Sgblack@eecs.umich.edu vaddSCode = ''' 4767382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 4777378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4787381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 4797385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpOp1 + FpOp2, FpOp1, FpOp2); 4807381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 4817378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4827367Sgblack@eecs.umich.edu ''' 4837375Sgblack@eecs.umich.edu vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp", 4847367Sgblack@eecs.umich.edu { "code": vaddSCode, 4857367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4867375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddSIop); 4877375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop); 4887367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddSIop); 4897367Sgblack@eecs.umich.edu 4907367Sgblack@eecs.umich.edu vaddDCode = ''' 4917367Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4927367Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4937367Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4947385Sgblack@eecs.umich.edu DPRINTFN("cOp1.bits = %#x, cOp1.fp = %f.\\n", cOp1.bits, cOp1.fp); 4957385Sgblack@eecs.umich.edu DPRINTFN("cOp2.bits = %#x, cOp2.fp = %f.\\n", cOp2.bits, cOp2.fp); 4967382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 4977378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 4997385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cOp1.fp + cOp2.fp, cOp1.fp, cOp2.fp); 5007385Sgblack@eecs.umich.edu DPRINTFN("cDest.bits = %#x, cDest.fp = %f.\\n", cDest.bits, cDest.fp); 5017381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5027378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5037367Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5047367Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5057367Sgblack@eecs.umich.edu ''' 5067375Sgblack@eecs.umich.edu vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp", 5077367Sgblack@eecs.umich.edu { "code": vaddDCode, 5087367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5097375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddDIop); 5107375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop); 5117367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddDIop); 5127368Sgblack@eecs.umich.edu 5137368Sgblack@eecs.umich.edu vsubSCode = ''' 5147382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 5157378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5167381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5177385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpOp1 - FpOp2, FpOp1, FpOp2); 5187381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5197378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state) 5207368Sgblack@eecs.umich.edu ''' 5217375Sgblack@eecs.umich.edu vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp", 5227368Sgblack@eecs.umich.edu { "code": vsubSCode, 5237368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5247375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubSIop); 5257375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop); 5267368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubSIop); 5277368Sgblack@eecs.umich.edu 5287368Sgblack@eecs.umich.edu vsubDCode = ''' 5297368Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5307368Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5317368Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5327382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 5337378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5347381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 5357385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cOp1.fp - cOp2.fp, cOp1.fp, cOp2.fp); 5367381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5377378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5387368Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5397368Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5407368Sgblack@eecs.umich.edu ''' 5417375Sgblack@eecs.umich.edu vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp", 5427368Sgblack@eecs.umich.edu { "code": vsubDCode, 5437368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5447375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubDIop); 5457375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop); 5467368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubDIop); 5477369Sgblack@eecs.umich.edu 5487369Sgblack@eecs.umich.edu vdivSCode = ''' 5497382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 5507378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5517381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5527385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpOp1 / FpOp2, FpOp1, FpOp2); 5537381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5547378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5557369Sgblack@eecs.umich.edu ''' 5567375Sgblack@eecs.umich.edu vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp", 5577369Sgblack@eecs.umich.edu { "code": vdivSCode, 5587369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5597375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivSIop); 5607375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop); 5617369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivSIop); 5627369Sgblack@eecs.umich.edu 5637369Sgblack@eecs.umich.edu vdivDCode = ''' 5647369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5657369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5667369Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5677382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 5687378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5697381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); 5707385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cOp1.fp / cOp2.fp, cOp1.fp, cOp2.fp); 5717381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5727378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5737369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5747369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5757369Sgblack@eecs.umich.edu ''' 5767375Sgblack@eecs.umich.edu vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp", 5777369Sgblack@eecs.umich.edu { "code": vdivDCode, 5787369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5797375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivDIop); 5807375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop); 5817369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivDIop); 5827369Sgblack@eecs.umich.edu 5837369Sgblack@eecs.umich.edu vsqrtSCode = ''' 5847382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 5857378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5867381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5877369Sgblack@eecs.umich.edu FpDest = sqrtf(FpOp1); 5887381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5897378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5907369Sgblack@eecs.umich.edu if (FpOp1 < 0) { 5917369Sgblack@eecs.umich.edu FpDest = NAN; 5927369Sgblack@eecs.umich.edu } 5937369Sgblack@eecs.umich.edu ''' 5947375Sgblack@eecs.umich.edu vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp", 5957369Sgblack@eecs.umich.edu { "code": vsqrtSCode, 5967369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5977375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtSIop); 5987375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop); 5997369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtSIop); 6007369Sgblack@eecs.umich.edu 6017369Sgblack@eecs.umich.edu vsqrtDCode = ''' 6027369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 6037369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6047382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 6057378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6067381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); 6077369Sgblack@eecs.umich.edu cDest.fp = sqrt(cOp1.fp); 6087381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 6097378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6107369Sgblack@eecs.umich.edu if (cOp1.fp < 0) { 6117369Sgblack@eecs.umich.edu cDest.fp = NAN; 6127369Sgblack@eecs.umich.edu } 6137369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6147369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6157369Sgblack@eecs.umich.edu ''' 6167375Sgblack@eecs.umich.edu vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp", 6177369Sgblack@eecs.umich.edu { "code": vsqrtDCode, 6187369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6197375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtDIop); 6207375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop); 6217369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtDIop); 6227381Sgblack@eecs.umich.edu}}; 6237381Sgblack@eecs.umich.edu 6247381Sgblack@eecs.umich.edulet {{ 6257381Sgblack@eecs.umich.edu 6267381Sgblack@eecs.umich.edu header_output = "" 6277381Sgblack@eecs.umich.edu decoder_output = "" 6287381Sgblack@eecs.umich.edu exec_output = "" 6297370Sgblack@eecs.umich.edu 6307370Sgblack@eecs.umich.edu vmlaSCode = ''' 6317382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 6327378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6337381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 6347385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 6357370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6367370Sgblack@eecs.umich.edu mid = NAN; 6377370Sgblack@eecs.umich.edu } 6387382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 6397385Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpDest + mid, FpDest, mid); 6407381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6417378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6427370Sgblack@eecs.umich.edu ''' 6437375Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp", 6447370Sgblack@eecs.umich.edu { "code": vmlaSCode, 6457370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6467375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop); 6477375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop); 6487370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 6497370Sgblack@eecs.umich.edu 6507370Sgblack@eecs.umich.edu vmlaDCode = ''' 6517370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6527370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6537370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6547370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6557382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 6567378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6577381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 6587385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 6597370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6607370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6617370Sgblack@eecs.umich.edu mid = NAN; 6627370Sgblack@eecs.umich.edu } 6637382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 6647385Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cDest.fp + mid, cDest.fp, mid); 6657381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 6667378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6677370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6687370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6697370Sgblack@eecs.umich.edu ''' 6707375Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp", 6717370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6727370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6737375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop); 6747375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop); 6757370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6767370Sgblack@eecs.umich.edu 6777370Sgblack@eecs.umich.edu vmlsSCode = ''' 6787382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 6797378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6807381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 6817385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 6827370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6837370Sgblack@eecs.umich.edu mid = NAN; 6847370Sgblack@eecs.umich.edu } 6857382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 6867386Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, FpDest - mid, FpDest, -mid); 6877381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6887378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6897370Sgblack@eecs.umich.edu ''' 6907375Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 6917370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6927370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6937375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 6947375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); 6957370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 6967370Sgblack@eecs.umich.edu 6977370Sgblack@eecs.umich.edu vmlsDCode = ''' 6987370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6997370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7007370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7017370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7027382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7037378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7047381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7057385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 7067370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7077370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7087370Sgblack@eecs.umich.edu mid = NAN; 7097370Sgblack@eecs.umich.edu } 7107386Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, cDest.fp - mid, cDest.fp, -mid); 7117382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 7127381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 7137378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7147370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7157370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7167370Sgblack@eecs.umich.edu ''' 7177375Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 7187370Sgblack@eecs.umich.edu { "code": vmlsDCode, 7197370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7207375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop); 7217375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop); 7227370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 7237371Sgblack@eecs.umich.edu 7247371Sgblack@eecs.umich.edu vnmlaSCode = ''' 7257382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 7267378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7277381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7287385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 7297371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7307371Sgblack@eecs.umich.edu mid = NAN; 7317371Sgblack@eecs.umich.edu } 7327382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 7337386Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, -FpDest - mid, -FpDest, -mid); 7347381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7357378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7367371Sgblack@eecs.umich.edu ''' 7377375Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 7387371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 7397371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7407375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 7417375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); 7427371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 7437371Sgblack@eecs.umich.edu 7447371Sgblack@eecs.umich.edu vnmlaDCode = ''' 7457371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7467371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7477371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7487371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7497382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7507378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7517381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7527385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 7537371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7547371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7557371Sgblack@eecs.umich.edu mid = NAN; 7567371Sgblack@eecs.umich.edu } 7577382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 7587386Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, -cDest.fp - mid, -cDest.fp, -mid); 7597381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 7607378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7617371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7627371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7637371Sgblack@eecs.umich.edu ''' 7647375Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 7657371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 7667371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7677375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop); 7687375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop); 7697371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 7707371Sgblack@eecs.umich.edu 7717371Sgblack@eecs.umich.edu vnmlsSCode = ''' 7727382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 7737378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7747381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7757385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 7767371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7777371Sgblack@eecs.umich.edu mid = NAN; 7787371Sgblack@eecs.umich.edu } 7797382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 7807386Sgblack@eecs.umich.edu FpDest = fixDest(Fpscr, -FpDest + mid, -FpDest, mid); 7817381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7827378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7837371Sgblack@eecs.umich.edu ''' 7847375Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 7857371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 7867371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7877375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 7887375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); 7897371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7907371Sgblack@eecs.umich.edu 7917371Sgblack@eecs.umich.edu vnmlsDCode = ''' 7927371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7937371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7947371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7957371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7967382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7977378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7997385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 8007371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 8017371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 8027371Sgblack@eecs.umich.edu mid = NAN; 8037371Sgblack@eecs.umich.edu } 8047382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 8057386Sgblack@eecs.umich.edu cDest.fp = fixDest(Fpscr, -cDest.fp + mid, -cDest.fp, mid); 8067381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8077378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8087371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8097371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8107371Sgblack@eecs.umich.edu ''' 8117375Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 8127371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 8137371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8147375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop); 8157375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop); 8167371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 8177371Sgblack@eecs.umich.edu 8187371Sgblack@eecs.umich.edu vnmulSCode = ''' 8197382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 8207378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8217381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8227385Sgblack@eecs.umich.edu float mid = fixDest(Fpscr, FpOp1 * FpOp2, FpOp1, FpOp2); 8237371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 8247371Sgblack@eecs.umich.edu mid = NAN; 8257371Sgblack@eecs.umich.edu } 8267371Sgblack@eecs.umich.edu FpDest = -mid; 8277381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8287378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8297371Sgblack@eecs.umich.edu ''' 8307375Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp", 8317371Sgblack@eecs.umich.edu { "code": vnmulSCode, 8327371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8337375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop); 8347375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop); 8357371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 8367371Sgblack@eecs.umich.edu 8377371Sgblack@eecs.umich.edu vnmulDCode = ''' 8387371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 8397371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8407371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 8417371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 8427382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 8437378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8447381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 8457385Sgblack@eecs.umich.edu double mid = fixDest(Fpscr, cOp1.fp * cOp2.fp, cOp1.fp, cOp2.fp); 8467371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 8477371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 8487371Sgblack@eecs.umich.edu mid = NAN; 8497371Sgblack@eecs.umich.edu } 8507371Sgblack@eecs.umich.edu cDest.fp = -mid; 8517381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8527378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8537371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8547371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8557371Sgblack@eecs.umich.edu ''' 8567375Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp", 8577371Sgblack@eecs.umich.edu { "code": vnmulDCode, 8587371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8597375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop); 8607375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop); 8617371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 8627381Sgblack@eecs.umich.edu}}; 8637381Sgblack@eecs.umich.edu 8647381Sgblack@eecs.umich.edulet {{ 8657381Sgblack@eecs.umich.edu 8667381Sgblack@eecs.umich.edu header_output = "" 8677381Sgblack@eecs.umich.edu decoder_output = "" 8687381Sgblack@eecs.umich.edu exec_output = "" 8697373Sgblack@eecs.umich.edu 8707373Sgblack@eecs.umich.edu vcvtUIntFpSCode = ''' 8717378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8727381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 8737373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 8747381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8757378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8767373Sgblack@eecs.umich.edu ''' 8777375Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp", 8787373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 8797373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8807375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop); 8817375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop); 8827373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 8837373Sgblack@eecs.umich.edu 8847373Sgblack@eecs.umich.edu vcvtUIntFpDCode = ''' 8857373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 8867378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8877381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 8887373Sgblack@eecs.umich.edu cDest.fp = (uint64_t)FpOp1P0.uw; 8897381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8907378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8917373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8927373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8937373Sgblack@eecs.umich.edu ''' 8947375Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp", 8957373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 8967373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8977375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop); 8987375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop); 8997373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 9007373Sgblack@eecs.umich.edu 9017373Sgblack@eecs.umich.edu vcvtSIntFpSCode = ''' 9027378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9037381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 9047373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 9057381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9067378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9077373Sgblack@eecs.umich.edu ''' 9087375Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp", 9097373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 9107373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9117375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop); 9127375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop); 9137373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 9147373Sgblack@eecs.umich.edu 9157373Sgblack@eecs.umich.edu vcvtSIntFpDCode = ''' 9167373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 9177378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9187381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 9197373Sgblack@eecs.umich.edu cDest.fp = FpOp1P0.sw; 9207381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 9217378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9227373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 9237373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 9247373Sgblack@eecs.umich.edu ''' 9257375Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp", 9267373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 9277373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9287375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop); 9297375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop); 9307373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 9317373Sgblack@eecs.umich.edu 9327380Sgblack@eecs.umich.edu vcvtFpUIntSRCode = ''' 9337382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 9347380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9357381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9367388Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); 9377381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 9387380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9397380Sgblack@eecs.umich.edu ''' 9407380Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp", 9417380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 9427380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9437380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 9447380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 9457380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 9467380Sgblack@eecs.umich.edu 9477380Sgblack@eecs.umich.edu vcvtFpUIntDRCode = ''' 9487380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9497380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9507382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 9517380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9527381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 9537388Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0, false); 9547381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9557380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9567380Sgblack@eecs.umich.edu FpDestP0.uw = result; 9577380Sgblack@eecs.umich.edu ''' 9587380Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp", 9597380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 9607380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9617380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 9627380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 9637380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 9647380Sgblack@eecs.umich.edu 9657380Sgblack@eecs.umich.edu vcvtFpSIntSRCode = ''' 9667382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 9677380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9687381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9697388Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); 9707381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 9717380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9727380Sgblack@eecs.umich.edu ''' 9737380Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp", 9747380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 9757380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9767380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 9777380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 9787380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 9797380Sgblack@eecs.umich.edu 9807380Sgblack@eecs.umich.edu vcvtFpSIntDRCode = ''' 9817380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9827380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9837382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 9847380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9857381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 9867388Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0, false); 9877381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9887380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9897380Sgblack@eecs.umich.edu FpDestP0.uw = result; 9907380Sgblack@eecs.umich.edu ''' 9917380Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp", 9927380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 9937380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9947380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 9957380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 9967380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 9977380Sgblack@eecs.umich.edu 9987373Sgblack@eecs.umich.edu vcvtFpUIntSCode = ''' 9997382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10007378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10017380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10027381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10037387Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); 10047381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10057378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10067373Sgblack@eecs.umich.edu ''' 10077375Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp", 10087373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 10097373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10107375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop); 10117375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop); 10127373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 10137373Sgblack@eecs.umich.edu 10147373Sgblack@eecs.umich.edu vcvtFpUIntDCode = ''' 10157373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10167373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10177382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10187378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10197380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10207381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10217387Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, false, false, 0); 10227381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10237378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10247373Sgblack@eecs.umich.edu FpDestP0.uw = result; 10257373Sgblack@eecs.umich.edu ''' 10267375Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp", 10277373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 10287373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10297375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop); 10307375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop); 10317373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 10327373Sgblack@eecs.umich.edu 10337373Sgblack@eecs.umich.edu vcvtFpSIntSCode = ''' 10347382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10357378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10367380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10377381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10387387Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); 10397381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 10407378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10417373Sgblack@eecs.umich.edu ''' 10427375Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp", 10437373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 10447373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10457375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop); 10467375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop); 10477373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 10487373Sgblack@eecs.umich.edu 10497373Sgblack@eecs.umich.edu vcvtFpSIntDCode = ''' 10507373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10517373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10527382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10537378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10547380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10557381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10567387Sgblack@eecs.umich.edu int64_t result = vfpFpDToFixed(cOp1.fp, true, false, 0); 10577381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10587378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10597373Sgblack@eecs.umich.edu FpDestP0.uw = result; 10607373Sgblack@eecs.umich.edu ''' 10617375Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp", 10627373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 10637373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10647375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop); 10657375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop); 10667373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 10677374Sgblack@eecs.umich.edu 10687374Sgblack@eecs.umich.edu vcvtFpSFpDCode = ''' 10697374Sgblack@eecs.umich.edu IntDoubleUnion cDest; 10707382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10717378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10727381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10737374Sgblack@eecs.umich.edu cDest.fp = FpOp1; 10747381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 10757378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10767374Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 10777374Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 10787374Sgblack@eecs.umich.edu ''' 10797375Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp", 10807374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 10817374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10827375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop); 10837375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop); 10847374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 10857374Sgblack@eecs.umich.edu 10867374Sgblack@eecs.umich.edu vcvtFpDFpSCode = ''' 10877374Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10887374Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10897382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10907378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10917381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10927386Sgblack@eecs.umich.edu FpDest = fixFpDFpSDest(Fpscr, cOp1.fp); 10937381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10947378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10957374Sgblack@eecs.umich.edu ''' 10967375Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 10977374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 10987374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10997375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 11007375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 11017374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 11027377Sgblack@eecs.umich.edu 11037377Sgblack@eecs.umich.edu vcmpSCode = ''' 11047389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, FpOp1); 11057377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11067377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11077377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11087377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11097377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11107377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11117377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11127377Sgblack@eecs.umich.edu } else { 11137389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11147389Sgblack@eecs.umich.edu union 11157389Sgblack@eecs.umich.edu { 11167389Sgblack@eecs.umich.edu float fp; 11177389Sgblack@eecs.umich.edu uint32_t bits; 11187389Sgblack@eecs.umich.edu } cvtr; 11197389Sgblack@eecs.umich.edu cvtr.fp = FpDest; 11207389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 11217389Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((cvtr.bits & qnan) != qnan); 11227389Sgblack@eecs.umich.edu cvtr.fp = FpOp1; 11237389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 11247389Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((cvtr.bits & qnan) != qnan); 11257389Sgblack@eecs.umich.edu if (signal1 || signal2) 11267389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11277377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11287377Sgblack@eecs.umich.edu } 11297377Sgblack@eecs.umich.edu Fpscr = fpscr; 11307377Sgblack@eecs.umich.edu ''' 11317377Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 11327377Sgblack@eecs.umich.edu { "code": vcmpSCode, 11337377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11347377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpSIop); 11357377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop); 11367377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 11377377Sgblack@eecs.umich.edu 11387377Sgblack@eecs.umich.edu vcmpDCode = ''' 11397377Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 11407377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 11417377Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 11427382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); 11437377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11447377Sgblack@eecs.umich.edu if (cDest.fp == cOp1.fp) { 11457377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11467377Sgblack@eecs.umich.edu } else if (cDest.fp < cOp1.fp) { 11477377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11487377Sgblack@eecs.umich.edu } else if (cDest.fp > cOp1.fp) { 11497377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11507377Sgblack@eecs.umich.edu } else { 11517389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 11527389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest.fp); 11537389Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((cDest.bits & qnan) != qnan); 11547389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1.fp); 11557389Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((cOp1.bits & qnan) != qnan); 11567389Sgblack@eecs.umich.edu if (signal1 || signal2) 11577389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11587377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11597377Sgblack@eecs.umich.edu } 11607377Sgblack@eecs.umich.edu Fpscr = fpscr; 11617377Sgblack@eecs.umich.edu ''' 11627377Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 11637377Sgblack@eecs.umich.edu { "code": vcmpDCode, 11647377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11657377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 11667377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 11677377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 11687377Sgblack@eecs.umich.edu 11697377Sgblack@eecs.umich.edu vcmpZeroSCode = ''' 11707389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest); 11717377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11727389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 11737389Sgblack@eecs.umich.edu assert(imm == 0); 11747377Sgblack@eecs.umich.edu if (FpDest == imm) { 11757377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11767377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11777377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11787377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11797377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11807377Sgblack@eecs.umich.edu } else { 11817389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11827389Sgblack@eecs.umich.edu union 11837389Sgblack@eecs.umich.edu { 11847389Sgblack@eecs.umich.edu float fp; 11857389Sgblack@eecs.umich.edu uint32_t bits; 11867389Sgblack@eecs.umich.edu } cvtr; 11877389Sgblack@eecs.umich.edu cvtr.fp = FpDest; 11887389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 11897389Sgblack@eecs.umich.edu const bool signal = nan && ((cvtr.bits & qnan) != qnan); 11907389Sgblack@eecs.umich.edu if (signal) 11917389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11927377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11937377Sgblack@eecs.umich.edu } 11947377Sgblack@eecs.umich.edu Fpscr = fpscr; 11957377Sgblack@eecs.umich.edu ''' 11967377Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 11977377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 11987377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11997377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 12007377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 12017377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 12027377Sgblack@eecs.umich.edu 12037377Sgblack@eecs.umich.edu vcmpZeroDCode = ''' 12047377Sgblack@eecs.umich.edu IntDoubleUnion cDest; 12057389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12067389Sgblack@eecs.umich.edu assert(imm == 0); 12077377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 12087382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp); 12097377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12107377Sgblack@eecs.umich.edu if (cDest.fp == imm) { 12117377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12127377Sgblack@eecs.umich.edu } else if (cDest.fp < imm) { 12137377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12147377Sgblack@eecs.umich.edu } else if (cDest.fp > imm) { 12157377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12167377Sgblack@eecs.umich.edu } else { 12177389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12187389Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest.fp); 12197389Sgblack@eecs.umich.edu const bool signal = nan && ((cDest.bits & qnan) != qnan); 12207389Sgblack@eecs.umich.edu if (signal) 12217389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12227377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12237377Sgblack@eecs.umich.edu } 12247377Sgblack@eecs.umich.edu Fpscr = fpscr; 12257377Sgblack@eecs.umich.edu ''' 12267377Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 12277377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 12287377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12297377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 12307377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 12317377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 12327389Sgblack@eecs.umich.edu 12337389Sgblack@eecs.umich.edu vcmpeSCode = ''' 12347389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, FpOp1); 12357389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12367389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12377389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12387389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12397389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12407389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12417389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12427389Sgblack@eecs.umich.edu } else { 12437389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12447389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12457389Sgblack@eecs.umich.edu } 12467389Sgblack@eecs.umich.edu Fpscr = fpscr; 12477389Sgblack@eecs.umich.edu ''' 12487389Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "VfpRegRegOp", 12497389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 12507389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12517389Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpeSIop); 12527389Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpeSIop); 12537389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 12547389Sgblack@eecs.umich.edu 12557389Sgblack@eecs.umich.edu vcmpeDCode = ''' 12567389Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 12577389Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 12587389Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12597389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); 12607389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12617389Sgblack@eecs.umich.edu if (cDest.fp == cOp1.fp) { 12627389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12637389Sgblack@eecs.umich.edu } else if (cDest.fp < cOp1.fp) { 12647389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12657389Sgblack@eecs.umich.edu } else if (cDest.fp > cOp1.fp) { 12667389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12677389Sgblack@eecs.umich.edu } else { 12687389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12697389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12707389Sgblack@eecs.umich.edu } 12717389Sgblack@eecs.umich.edu Fpscr = fpscr; 12727389Sgblack@eecs.umich.edu ''' 12737389Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "VfpRegRegOp", 12747389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 12757389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12767389Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpeDIop); 12777389Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpeDIop); 12787389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 12797389Sgblack@eecs.umich.edu 12807389Sgblack@eecs.umich.edu vcmpeZeroSCode = ''' 12817389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest); 12827389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 12837389Sgblack@eecs.umich.edu if (FpDest == imm) { 12847389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12857389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12867389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12877389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12887389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12897389Sgblack@eecs.umich.edu } else { 12907389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12917389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12927389Sgblack@eecs.umich.edu } 12937389Sgblack@eecs.umich.edu Fpscr = fpscr; 12947389Sgblack@eecs.umich.edu ''' 12957389Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "VfpRegImmOp", 12967389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 12977389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12987389Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpeZeroSIop); 12997389Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroSIop); 13007389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 13017389Sgblack@eecs.umich.edu 13027389Sgblack@eecs.umich.edu vcmpeZeroDCode = ''' 13037389Sgblack@eecs.umich.edu IntDoubleUnion cDest; 13047389Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 13057389Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp); 13067389Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 13077389Sgblack@eecs.umich.edu if (cDest.fp == imm) { 13087389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13097389Sgblack@eecs.umich.edu } else if (cDest.fp < imm) { 13107389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13117389Sgblack@eecs.umich.edu } else if (cDest.fp > imm) { 13127389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13137389Sgblack@eecs.umich.edu } else { 13147389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13157389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13167389Sgblack@eecs.umich.edu } 13177389Sgblack@eecs.umich.edu Fpscr = fpscr; 13187389Sgblack@eecs.umich.edu ''' 13197389Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "VfpRegImmOp", 13207389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 13217389Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13227389Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpeZeroDIop); 13237389Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpeZeroDIop); 13247389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 13257322Sgblack@eecs.umich.edu}}; 13267379Sgblack@eecs.umich.edu 13277379Sgblack@eecs.umich.edulet {{ 13287379Sgblack@eecs.umich.edu 13297379Sgblack@eecs.umich.edu header_output = "" 13307379Sgblack@eecs.umich.edu decoder_output = "" 13317379Sgblack@eecs.umich.edu exec_output = "" 13327379Sgblack@eecs.umich.edu 13337379Sgblack@eecs.umich.edu vcvtFpSFixedSCode = ''' 13347382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 13357379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13367381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13377379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 13387381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 13397379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13407379Sgblack@eecs.umich.edu ''' 13417379Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp", 13427379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 13437379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13447379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 13457379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 13467379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 13477379Sgblack@eecs.umich.edu 13487379Sgblack@eecs.umich.edu vcvtFpSFixedDCode = ''' 13497379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 13507379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13517382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 13527379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13537381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 13547379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); 13557381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13567379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13577379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13587379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13597379Sgblack@eecs.umich.edu ''' 13607379Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp", 13617379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 13627379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13637379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 13647379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 13657379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 13667379Sgblack@eecs.umich.edu 13677379Sgblack@eecs.umich.edu vcvtFpUFixedSCode = ''' 13687382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 13697379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13707381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13717379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 13727381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 13737379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13747379Sgblack@eecs.umich.edu ''' 13757379Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp", 13767379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 13777379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13787379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 13797379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 13807379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 13817379Sgblack@eecs.umich.edu 13827379Sgblack@eecs.umich.edu vcvtFpUFixedDCode = ''' 13837379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 13847379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13857382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 13867379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13877381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 13887379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); 13897381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13907379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13917379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13927379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13937379Sgblack@eecs.umich.edu ''' 13947379Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp", 13957379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 13967379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13977379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 13987379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 13997379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 14007379Sgblack@eecs.umich.edu 14017379Sgblack@eecs.umich.edu vcvtSFixedFpSCode = ''' 14027379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14037381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 14047386Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sw, false, imm); 14057381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14067379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14077379Sgblack@eecs.umich.edu ''' 14087379Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 14097379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 14107379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14117379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 14127379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 14137379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 14147379Sgblack@eecs.umich.edu 14157379Sgblack@eecs.umich.edu vcvtSFixedFpDCode = ''' 14167379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 14177379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14187379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14197381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14207386Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(Fpscr, mid, false, imm); 14217381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 14227379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14237379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 14247379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 14257379Sgblack@eecs.umich.edu ''' 14267379Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 14277379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 14287379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14297379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 14307379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 14317379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 14327379Sgblack@eecs.umich.edu 14337379Sgblack@eecs.umich.edu vcvtUFixedFpSCode = ''' 14347379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14357381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 14367386Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uw, false, imm); 14377381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14387379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14397379Sgblack@eecs.umich.edu ''' 14407379Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 14417379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 14427379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14437379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 14447379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 14457379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 14467379Sgblack@eecs.umich.edu 14477379Sgblack@eecs.umich.edu vcvtUFixedFpDCode = ''' 14487379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 14497379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14507379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14517381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14527386Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(Fpscr, mid, false, imm); 14537381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 14547379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14557379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 14567379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 14577379Sgblack@eecs.umich.edu ''' 14587379Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 14597379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 14607379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14617379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 14627379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 14637379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 14647379Sgblack@eecs.umich.edu 14657379Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = ''' 14667382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 14677379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14687381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 14697379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 14707381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 14717379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14727379Sgblack@eecs.umich.edu ''' 14737379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 14747379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 14757379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 14767379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14777379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 14787379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 14797379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 14807379Sgblack@eecs.umich.edu 14817379Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = ''' 14827379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 14837379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14847382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 14857379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14867381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 14877379Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); 14887381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 14897379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14907379Sgblack@eecs.umich.edu FpDestP0.uw = result; 14917379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 14927379Sgblack@eecs.umich.edu ''' 14937379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 14947379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 14957379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 14967379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14977379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 14987379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 14997379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 15007379Sgblack@eecs.umich.edu 15017379Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = ''' 15027382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 15037379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15047381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 15057379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 15067381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 15077379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15087379Sgblack@eecs.umich.edu ''' 15097379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 15107379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15117379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 15127379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15137379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 15147379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 15157379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 15167379Sgblack@eecs.umich.edu 15177379Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = ''' 15187379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 15197379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15207382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 15217379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15227381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 15237379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); 15247381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15257379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15267379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 15277379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 15287379Sgblack@eecs.umich.edu ''' 15297379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 15307379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15317379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 15327379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15337379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 15347379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 15357379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 15367379Sgblack@eecs.umich.edu 15377379Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = ''' 15387379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15397381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 15407386Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(Fpscr, FpOp1.sh, true, imm); 15417381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15427379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15437379Sgblack@eecs.umich.edu ''' 15447379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 15457379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15467379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 15477379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15487379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 15497379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 15507379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 15517379Sgblack@eecs.umich.edu 15527379Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = ''' 15537379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 15547379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15557379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15567381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15577386Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(Fpscr, mid, true, imm); 15587381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 15597379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15607379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 15617379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 15627379Sgblack@eecs.umich.edu ''' 15637379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 15647379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15657379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 15667379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15677379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 15687379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 15697379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 15707379Sgblack@eecs.umich.edu 15717379Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = ''' 15727379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15737381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 15747386Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(Fpscr, FpOp1.uh, true, imm); 15757381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15767379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15777379Sgblack@eecs.umich.edu ''' 15787379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 15797379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15807379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 15817379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 15827379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 15837379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 15847379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 15857379Sgblack@eecs.umich.edu 15867379Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = ''' 15877379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 15887379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 15897379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 15907381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 15917386Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(Fpscr, mid, true, imm); 15927381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 15937379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 15947379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 15957379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 15967379Sgblack@eecs.umich.edu ''' 15977379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 15987379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 15997379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 16007379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 16017379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 16027379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 16037379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 16047379Sgblack@eecs.umich.edu}}; 1605