fp.isa revision 7382
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947375Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp", 1957322Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 1967322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1977375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmsrIop); 1987375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmsrIop); 1997322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2007324Sgblack@eecs.umich.edu 2017375Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp", 2027324Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 2037324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmrsIop); 2057375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmrsIop); 2067324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2077333Sgblack@eecs.umich.edu 2087333Sgblack@eecs.umich.edu vmovImmSCode = ''' 2097333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2107333Sgblack@eecs.umich.edu ''' 2117375Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp", 2127333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2137333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2147375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmSIop); 2157375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop); 2167333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2177333Sgblack@eecs.umich.edu 2187333Sgblack@eecs.umich.edu vmovImmDCode = ''' 2197333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2207333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2217333Sgblack@eecs.umich.edu ''' 2227375Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp", 2237333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2247333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2257375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmDIop); 2267375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop); 2277333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2287333Sgblack@eecs.umich.edu 2297333Sgblack@eecs.umich.edu vmovImmQCode = ''' 2307333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2317333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2327333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2337333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2347333Sgblack@eecs.umich.edu ''' 2357375Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp", 2367333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2377333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2387375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmQIop); 2397375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop); 2407333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2417333Sgblack@eecs.umich.edu 2427333Sgblack@eecs.umich.edu vmovRegSCode = ''' 2437333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2447333Sgblack@eecs.umich.edu ''' 2457375Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp", 2467333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2477333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2487375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegSIop); 2497375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop); 2507333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2517333Sgblack@eecs.umich.edu 2527333Sgblack@eecs.umich.edu vmovRegDCode = ''' 2537333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2547333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2557333Sgblack@eecs.umich.edu ''' 2567375Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp", 2577333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2587333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2597375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegDIop); 2607375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop); 2617333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2627333Sgblack@eecs.umich.edu 2637333Sgblack@eecs.umich.edu vmovRegQCode = ''' 2647333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2657333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2667333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2677333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2687333Sgblack@eecs.umich.edu ''' 2697375Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp", 2707333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2717333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2727375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegQIop); 2737375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegQIop); 2747333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2757333Sgblack@eecs.umich.edu 2767333Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 2777333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 2787333Sgblack@eecs.umich.edu ''' 2797375Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp", 2807333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2817333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2827375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2837375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2857333Sgblack@eecs.umich.edu 2867333Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 2877333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 2887333Sgblack@eecs.umich.edu ''' 2897375Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp", 2907333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 2917333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2927375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 2937375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 2947333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 2957333Sgblack@eecs.umich.edu 2967333Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 2977333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 2987333Sgblack@eecs.umich.edu ''' 2997375Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp", 3007333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3017333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3027375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovCoreRegWIop); 3037375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovCoreRegWIop); 3047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3057333Sgblack@eecs.umich.edu 3067333Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 3077333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 3087333Sgblack@eecs.umich.edu ''' 3097375Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp", 3107333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3117333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3127375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3137375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3147333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3157333Sgblack@eecs.umich.edu 3167333Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 3177333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 3187333Sgblack@eecs.umich.edu ''' 3197375Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp", 3207333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3217333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3227375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3237375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3247333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3257333Sgblack@eecs.umich.edu 3267333Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 3277333Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 3287333Sgblack@eecs.umich.edu ''' 3297375Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp", 3307333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3317333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3327375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3337375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3347333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3357333Sgblack@eecs.umich.edu 3367333Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 3377333Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 3387333Sgblack@eecs.umich.edu ''' 3397375Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp", 3407333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3417333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3427375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3437375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3447333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3457333Sgblack@eecs.umich.edu 3467333Sgblack@eecs.umich.edu vmovRegCoreWCode = ''' 3477333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3487333Sgblack@eecs.umich.edu ''' 3497375Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp", 3507333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3517333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3527375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegCoreWIop); 3537375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegCoreWIop); 3547333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 3557333Sgblack@eecs.umich.edu 3567333Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 3577333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3587333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3597333Sgblack@eecs.umich.edu ''' 3607375Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp", 3617333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3627333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3637375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3647375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3657333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3667333Sgblack@eecs.umich.edu 3677333Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 3687333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3697333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3707333Sgblack@eecs.umich.edu ''' 3717375Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp", 3727333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3737333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3747375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3757375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3767333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3777381Sgblack@eecs.umich.edu}}; 3787381Sgblack@eecs.umich.edu 3797381Sgblack@eecs.umich.edulet {{ 3807381Sgblack@eecs.umich.edu 3817381Sgblack@eecs.umich.edu header_output = "" 3827381Sgblack@eecs.umich.edu decoder_output = "" 3837381Sgblack@eecs.umich.edu exec_output = "" 3847364Sgblack@eecs.umich.edu 3857364Sgblack@eecs.umich.edu vmulSCode = ''' 3867382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 3877378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 3887381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 3897364Sgblack@eecs.umich.edu FpDest = FpOp1 * FpOp2; 3907381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 3917378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 3927364Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 3937364Sgblack@eecs.umich.edu FpDest = NAN; 3947364Sgblack@eecs.umich.edu } 3957364Sgblack@eecs.umich.edu ''' 3967375Sgblack@eecs.umich.edu vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 3977364Sgblack@eecs.umich.edu { "code": vmulSCode, 3987364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3997375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulSIop); 4007375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop); 4017364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulSIop); 4027364Sgblack@eecs.umich.edu 4037364Sgblack@eecs.umich.edu vmulDCode = ''' 4047364Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4057364Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4067364Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4077382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 4087378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4097381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 4107364Sgblack@eecs.umich.edu cDest.fp = cOp1.fp * cOp2.fp; 4117381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 4127378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4137364Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 4147364Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 4157364Sgblack@eecs.umich.edu cDest.fp = NAN; 4167364Sgblack@eecs.umich.edu } 4177364Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4187364Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4197364Sgblack@eecs.umich.edu ''' 4207375Sgblack@eecs.umich.edu vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp", 4217364Sgblack@eecs.umich.edu { "code": vmulDCode, 4227364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4237375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulDIop); 4247375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop); 4257364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulDIop); 4267365Sgblack@eecs.umich.edu 4277365Sgblack@eecs.umich.edu vnegSCode = ''' 4287365Sgblack@eecs.umich.edu FpDest = -FpOp1; 4297365Sgblack@eecs.umich.edu ''' 4307375Sgblack@eecs.umich.edu vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp", 4317365Sgblack@eecs.umich.edu { "code": vnegSCode, 4327365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4337375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegSIop); 4347375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegSIop); 4357365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegSIop); 4367365Sgblack@eecs.umich.edu 4377365Sgblack@eecs.umich.edu vnegDCode = ''' 4387365Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4397365Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4407365Sgblack@eecs.umich.edu cDest.fp = -cOp1.fp; 4417365Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4427365Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4437365Sgblack@eecs.umich.edu ''' 4447375Sgblack@eecs.umich.edu vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp", 4457365Sgblack@eecs.umich.edu { "code": vnegDCode, 4467365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4477375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegDIop); 4487375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegDIop); 4497365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegDIop); 4507366Sgblack@eecs.umich.edu 4517366Sgblack@eecs.umich.edu vabsSCode = ''' 4527366Sgblack@eecs.umich.edu FpDest = fabsf(FpOp1); 4537366Sgblack@eecs.umich.edu ''' 4547375Sgblack@eecs.umich.edu vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp", 4557366Sgblack@eecs.umich.edu { "code": vabsSCode, 4567366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4577375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsSIop); 4587375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsSIop); 4597366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsSIop); 4607366Sgblack@eecs.umich.edu 4617366Sgblack@eecs.umich.edu vabsDCode = ''' 4627366Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4637366Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4647366Sgblack@eecs.umich.edu cDest.fp = fabs(cOp1.fp); 4657366Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4667366Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4677366Sgblack@eecs.umich.edu ''' 4687375Sgblack@eecs.umich.edu vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp", 4697366Sgblack@eecs.umich.edu { "code": vabsDCode, 4707366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4717375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsDIop); 4727375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsDIop); 4737366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsDIop); 4747367Sgblack@eecs.umich.edu 4757367Sgblack@eecs.umich.edu vaddSCode = ''' 4767382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 4777378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4787381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 4797367Sgblack@eecs.umich.edu FpDest = FpOp1 + FpOp2; 4807381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 4817378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4827367Sgblack@eecs.umich.edu ''' 4837375Sgblack@eecs.umich.edu vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp", 4847367Sgblack@eecs.umich.edu { "code": vaddSCode, 4857367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4867375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddSIop); 4877375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop); 4887367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddSIop); 4897367Sgblack@eecs.umich.edu 4907367Sgblack@eecs.umich.edu vaddDCode = ''' 4917367Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4927367Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4937367Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4947382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 4957378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4967381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 4977367Sgblack@eecs.umich.edu cDest.fp = cOp1.fp + cOp2.fp; 4987381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 4997378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5007367Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5017367Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5027367Sgblack@eecs.umich.edu ''' 5037375Sgblack@eecs.umich.edu vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp", 5047367Sgblack@eecs.umich.edu { "code": vaddDCode, 5057367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5067375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddDIop); 5077375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop); 5087367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddDIop); 5097368Sgblack@eecs.umich.edu 5107368Sgblack@eecs.umich.edu vsubSCode = ''' 5117382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 5127378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5137381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5147368Sgblack@eecs.umich.edu FpDest = FpOp1 - FpOp2; 5157381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5167378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state) 5177368Sgblack@eecs.umich.edu ''' 5187375Sgblack@eecs.umich.edu vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp", 5197368Sgblack@eecs.umich.edu { "code": vsubSCode, 5207368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5217375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubSIop); 5227375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop); 5237368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubSIop); 5247368Sgblack@eecs.umich.edu 5257368Sgblack@eecs.umich.edu vsubDCode = ''' 5267368Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5277368Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5287368Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5297382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 5307378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5317381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 5327368Sgblack@eecs.umich.edu cDest.fp = cOp1.fp - cOp2.fp; 5337381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5347378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5357368Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5367368Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5377368Sgblack@eecs.umich.edu ''' 5387375Sgblack@eecs.umich.edu vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp", 5397368Sgblack@eecs.umich.edu { "code": vsubDCode, 5407368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5417375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubDIop); 5427375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop); 5437368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubDIop); 5447369Sgblack@eecs.umich.edu 5457369Sgblack@eecs.umich.edu vdivSCode = ''' 5467382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 5477378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5487381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5497369Sgblack@eecs.umich.edu FpDest = FpOp1 / FpOp2; 5507381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5517378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5527369Sgblack@eecs.umich.edu ''' 5537375Sgblack@eecs.umich.edu vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp", 5547369Sgblack@eecs.umich.edu { "code": vdivSCode, 5557369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5567375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivSIop); 5577375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop); 5587369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivSIop); 5597369Sgblack@eecs.umich.edu 5607369Sgblack@eecs.umich.edu vdivDCode = ''' 5617369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5627369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5637369Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5647382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 5657378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5667381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); 5677369Sgblack@eecs.umich.edu cDest.fp = cOp1.fp / cOp2.fp; 5687381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 5697378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5707369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5717369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5727369Sgblack@eecs.umich.edu ''' 5737375Sgblack@eecs.umich.edu vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp", 5747369Sgblack@eecs.umich.edu { "code": vdivDCode, 5757369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5767375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivDIop); 5777375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop); 5787369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivDIop); 5797369Sgblack@eecs.umich.edu 5807369Sgblack@eecs.umich.edu vsqrtSCode = ''' 5817382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 5827378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5837381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 5847369Sgblack@eecs.umich.edu FpDest = sqrtf(FpOp1); 5857381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 5867378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5877369Sgblack@eecs.umich.edu if (FpOp1 < 0) { 5887369Sgblack@eecs.umich.edu FpDest = NAN; 5897369Sgblack@eecs.umich.edu } 5907369Sgblack@eecs.umich.edu ''' 5917375Sgblack@eecs.umich.edu vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp", 5927369Sgblack@eecs.umich.edu { "code": vsqrtSCode, 5937369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5947375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtSIop); 5957375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop); 5967369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtSIop); 5977369Sgblack@eecs.umich.edu 5987369Sgblack@eecs.umich.edu vsqrtDCode = ''' 5997369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 6007369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6017382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 6027378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6037381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cDest.fp)); 6047369Sgblack@eecs.umich.edu cDest.fp = sqrt(cOp1.fp); 6057381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 6067378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6077369Sgblack@eecs.umich.edu if (cOp1.fp < 0) { 6087369Sgblack@eecs.umich.edu cDest.fp = NAN; 6097369Sgblack@eecs.umich.edu } 6107369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6117369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6127369Sgblack@eecs.umich.edu ''' 6137375Sgblack@eecs.umich.edu vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp", 6147369Sgblack@eecs.umich.edu { "code": vsqrtDCode, 6157369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6167375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtDIop); 6177375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop); 6187369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtDIop); 6197381Sgblack@eecs.umich.edu}}; 6207381Sgblack@eecs.umich.edu 6217381Sgblack@eecs.umich.edulet {{ 6227381Sgblack@eecs.umich.edu 6237381Sgblack@eecs.umich.edu header_output = "" 6247381Sgblack@eecs.umich.edu decoder_output = "" 6257381Sgblack@eecs.umich.edu exec_output = "" 6267370Sgblack@eecs.umich.edu 6277370Sgblack@eecs.umich.edu vmlaSCode = ''' 6287382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 6297378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6307381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 6317370Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 6327370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6337370Sgblack@eecs.umich.edu mid = NAN; 6347370Sgblack@eecs.umich.edu } 6357382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 6367370Sgblack@eecs.umich.edu FpDest = FpDest + mid; 6377381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6387378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6397370Sgblack@eecs.umich.edu ''' 6407375Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp", 6417370Sgblack@eecs.umich.edu { "code": vmlaSCode, 6427370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6437375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop); 6447375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop); 6457370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 6467370Sgblack@eecs.umich.edu 6477370Sgblack@eecs.umich.edu vmlaDCode = ''' 6487370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6497370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6507370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6517370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6527382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 6537378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6547381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 6557370Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 6567370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6577370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6587370Sgblack@eecs.umich.edu mid = NAN; 6597370Sgblack@eecs.umich.edu } 6607382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 6617370Sgblack@eecs.umich.edu cDest.fp = cDest.fp + mid; 6627381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 6637378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6647370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6657370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6667370Sgblack@eecs.umich.edu ''' 6677375Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp", 6687370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6697370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6707375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop); 6717375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop); 6727370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6737370Sgblack@eecs.umich.edu 6747370Sgblack@eecs.umich.edu vmlsSCode = ''' 6757382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 6767378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6777381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 6787370Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 6797370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6807370Sgblack@eecs.umich.edu mid = NAN; 6817370Sgblack@eecs.umich.edu } 6827382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 6837370Sgblack@eecs.umich.edu FpDest = FpDest - mid; 6847381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 6857378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6867370Sgblack@eecs.umich.edu ''' 6877375Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 6887370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6897370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6907375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 6917375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); 6927370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 6937370Sgblack@eecs.umich.edu 6947370Sgblack@eecs.umich.edu vmlsDCode = ''' 6957370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6967370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6977370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6987370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6997382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7007378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7017381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7027370Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 7037370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7047370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7057370Sgblack@eecs.umich.edu mid = NAN; 7067370Sgblack@eecs.umich.edu } 7077370Sgblack@eecs.umich.edu cDest.fp = cDest.fp - mid; 7087382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 7097381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 7107378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7117370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7127370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7137370Sgblack@eecs.umich.edu ''' 7147375Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 7157370Sgblack@eecs.umich.edu { "code": vmlsDCode, 7167370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7177375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop); 7187375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop); 7197370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 7207371Sgblack@eecs.umich.edu 7217371Sgblack@eecs.umich.edu vnmlaSCode = ''' 7227382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 7237378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7247381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7257371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 7267371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7277371Sgblack@eecs.umich.edu mid = NAN; 7287371Sgblack@eecs.umich.edu } 7297382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 7307371Sgblack@eecs.umich.edu FpDest = -FpDest - mid; 7317381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7327378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7337371Sgblack@eecs.umich.edu ''' 7347375Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 7357371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 7367371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7377375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 7387375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); 7397371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 7407371Sgblack@eecs.umich.edu 7417371Sgblack@eecs.umich.edu vnmlaDCode = ''' 7427371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7437371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7447371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7457371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7467382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7477378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7487381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7497371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 7507371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7517371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7527371Sgblack@eecs.umich.edu mid = NAN; 7537371Sgblack@eecs.umich.edu } 7547382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 7557371Sgblack@eecs.umich.edu cDest.fp = -cDest.fp - mid; 7567381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 7577378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7587371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7597371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7607371Sgblack@eecs.umich.edu ''' 7617375Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 7627371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 7637371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7647375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop); 7657375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop); 7667371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 7677371Sgblack@eecs.umich.edu 7687371Sgblack@eecs.umich.edu vnmlsSCode = ''' 7697382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 7707378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7717381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 7727371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 7737371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7747371Sgblack@eecs.umich.edu mid = NAN; 7757371Sgblack@eecs.umich.edu } 7767382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, mid); 7777371Sgblack@eecs.umich.edu FpDest = -FpDest + mid; 7787381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 7797378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7807371Sgblack@eecs.umich.edu ''' 7817375Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 7827371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 7837371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7847375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 7857375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); 7867371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7877371Sgblack@eecs.umich.edu 7887371Sgblack@eecs.umich.edu vnmlsDCode = ''' 7897371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7907371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7917371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7927371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7937382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 7947378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7957381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 7967371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 7977371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7987371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7997371Sgblack@eecs.umich.edu mid = NAN; 8007371Sgblack@eecs.umich.edu } 8017382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, mid); 8027371Sgblack@eecs.umich.edu cDest.fp = -cDest.fp + mid; 8037381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8047378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8057371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8067371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8077371Sgblack@eecs.umich.edu ''' 8087375Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 8097371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 8107371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8117375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop); 8127375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop); 8137371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 8147371Sgblack@eecs.umich.edu 8157371Sgblack@eecs.umich.edu vnmulSCode = ''' 8167382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1, FpOp2); 8177378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8187381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 8197371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 8207371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 8217371Sgblack@eecs.umich.edu mid = NAN; 8227371Sgblack@eecs.umich.edu } 8237371Sgblack@eecs.umich.edu FpDest = -mid; 8247381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8257378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8267371Sgblack@eecs.umich.edu ''' 8277375Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp", 8287371Sgblack@eecs.umich.edu { "code": vnmulSCode, 8297371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8307375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop); 8317375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop); 8327371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 8337371Sgblack@eecs.umich.edu 8347371Sgblack@eecs.umich.edu vnmulDCode = ''' 8357371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 8367371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8377371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 8387371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 8397382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp, cOp2.fp); 8407378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8417381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 8427371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 8437371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 8447371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 8457371Sgblack@eecs.umich.edu mid = NAN; 8467371Sgblack@eecs.umich.edu } 8477371Sgblack@eecs.umich.edu cDest.fp = -mid; 8487381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8497378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8507371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8517371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8527371Sgblack@eecs.umich.edu ''' 8537375Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp", 8547371Sgblack@eecs.umich.edu { "code": vnmulDCode, 8557371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8567375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop); 8577375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop); 8587371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 8597381Sgblack@eecs.umich.edu}}; 8607381Sgblack@eecs.umich.edu 8617381Sgblack@eecs.umich.edulet {{ 8627381Sgblack@eecs.umich.edu 8637381Sgblack@eecs.umich.edu header_output = "" 8647381Sgblack@eecs.umich.edu decoder_output = "" 8657381Sgblack@eecs.umich.edu exec_output = "" 8667373Sgblack@eecs.umich.edu 8677373Sgblack@eecs.umich.edu vcvtUIntFpSCode = ''' 8687378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8697381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 8707373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 8717381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8727378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8737373Sgblack@eecs.umich.edu ''' 8747375Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp", 8757373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 8767373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8777375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop); 8787375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop); 8797373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 8807373Sgblack@eecs.umich.edu 8817373Sgblack@eecs.umich.edu vcvtUIntFpDCode = ''' 8827373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 8837378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8847381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); 8857373Sgblack@eecs.umich.edu cDest.fp = (uint64_t)FpOp1P0.uw; 8867381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 8877378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8887373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8897373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8907373Sgblack@eecs.umich.edu ''' 8917375Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp", 8927373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 8937373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8947375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop); 8957375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop); 8967373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 8977373Sgblack@eecs.umich.edu 8987373Sgblack@eecs.umich.edu vcvtSIntFpSCode = ''' 8997378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9007381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 9017373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 9027381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 9037378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9047373Sgblack@eecs.umich.edu ''' 9057375Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp", 9067373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 9077373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9087375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop); 9097375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop); 9107373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 9117373Sgblack@eecs.umich.edu 9127373Sgblack@eecs.umich.edu vcvtSIntFpDCode = ''' 9137373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 9147378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9157381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); 9167373Sgblack@eecs.umich.edu cDest.fp = FpOp1P0.sw; 9177381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 9187378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9197373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 9207373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 9217373Sgblack@eecs.umich.edu ''' 9227375Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp", 9237373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 9247373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9257375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop); 9267375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop); 9277373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 9287373Sgblack@eecs.umich.edu 9297380Sgblack@eecs.umich.edu vcvtFpUIntSRCode = ''' 9307382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 9317380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9327381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9337380Sgblack@eecs.umich.edu FpDest.uw = FpOp1; 9347381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 9357380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9367380Sgblack@eecs.umich.edu ''' 9377380Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp", 9387380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 9397380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9407380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 9417380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 9427380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 9437380Sgblack@eecs.umich.edu 9447380Sgblack@eecs.umich.edu vcvtFpUIntDRCode = ''' 9457380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9467380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9477382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 9487380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9497381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 9507380Sgblack@eecs.umich.edu uint64_t result = cOp1.fp; 9517381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9527380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9537380Sgblack@eecs.umich.edu FpDestP0.uw = result; 9547380Sgblack@eecs.umich.edu ''' 9557380Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp", 9567380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 9577380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9587380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 9597380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 9607380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 9617380Sgblack@eecs.umich.edu 9627380Sgblack@eecs.umich.edu vcvtFpSIntSRCode = ''' 9637382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 9647380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9657381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 9667380Sgblack@eecs.umich.edu FpDest.sw = FpOp1; 9677381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 9687380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9697380Sgblack@eecs.umich.edu ''' 9707380Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp", 9717380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 9727380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9737380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 9747380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 9757380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 9767380Sgblack@eecs.umich.edu 9777380Sgblack@eecs.umich.edu vcvtFpSIntDRCode = ''' 9787380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9797380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9807382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 9817380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9827381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 9837380Sgblack@eecs.umich.edu int64_t result = cOp1.fp; 9847381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9857380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9867380Sgblack@eecs.umich.edu FpDestP0.uw = result; 9877380Sgblack@eecs.umich.edu ''' 9887380Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp", 9897380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 9907380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9917380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 9927380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 9937380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 9947380Sgblack@eecs.umich.edu 9957373Sgblack@eecs.umich.edu vcvtFpUIntSCode = ''' 9967382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 9977378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9987380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9997381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10007373Sgblack@eecs.umich.edu FpDest.uw = FpOp1; 10017381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 10027378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10037373Sgblack@eecs.umich.edu ''' 10047375Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp", 10057373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 10067373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10077375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop); 10087375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop); 10097373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 10107373Sgblack@eecs.umich.edu 10117373Sgblack@eecs.umich.edu vcvtFpUIntDCode = ''' 10127373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10137373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10147382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10157378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10167380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10177381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10187373Sgblack@eecs.umich.edu uint64_t result = cOp1.fp; 10197381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10207378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10217373Sgblack@eecs.umich.edu FpDestP0.uw = result; 10227373Sgblack@eecs.umich.edu ''' 10237375Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp", 10247373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 10257373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10267375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop); 10277375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop); 10287373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 10297373Sgblack@eecs.umich.edu 10307373Sgblack@eecs.umich.edu vcvtFpSIntSCode = ''' 10317382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10327378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10337380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10347381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10357373Sgblack@eecs.umich.edu FpDest.sw = FpOp1; 10367381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 10377378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10387373Sgblack@eecs.umich.edu ''' 10397375Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp", 10407373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 10417373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10427375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop); 10437375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop); 10447373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 10457373Sgblack@eecs.umich.edu 10467373Sgblack@eecs.umich.edu vcvtFpSIntDCode = ''' 10477373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10487373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10497382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10507378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10517380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10527381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10537373Sgblack@eecs.umich.edu int64_t result = cOp1.fp; 10547381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10557378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10567373Sgblack@eecs.umich.edu FpDestP0.uw = result; 10577373Sgblack@eecs.umich.edu ''' 10587375Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp", 10597373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 10607373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10617375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop); 10627375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop); 10637373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 10647374Sgblack@eecs.umich.edu 10657374Sgblack@eecs.umich.edu vcvtFpSFpDCode = ''' 10667374Sgblack@eecs.umich.edu IntDoubleUnion cDest; 10677382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 10687378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10697381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10707374Sgblack@eecs.umich.edu cDest.fp = FpOp1; 10717381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 10727378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10737374Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 10747374Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 10757374Sgblack@eecs.umich.edu ''' 10767375Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp", 10777374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 10787374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10797375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop); 10807375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop); 10817374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 10827374Sgblack@eecs.umich.edu 10837374Sgblack@eecs.umich.edu vcvtFpDFpSCode = ''' 10847374Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10857374Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10867382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 10877378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10887381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 10897374Sgblack@eecs.umich.edu FpDest = cOp1.fp; 10907381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10917378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10927374Sgblack@eecs.umich.edu ''' 10937375Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 10947374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 10957374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10967375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 10977375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 10987374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 10997377Sgblack@eecs.umich.edu 11007377Sgblack@eecs.umich.edu vcmpSCode = ''' 11017377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11027382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest, FpOp1); 11037377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11047377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11057377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11067377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11077377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11087377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11097377Sgblack@eecs.umich.edu } else { 11107377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11117377Sgblack@eecs.umich.edu } 11127377Sgblack@eecs.umich.edu Fpscr = fpscr; 11137377Sgblack@eecs.umich.edu ''' 11147377Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 11157377Sgblack@eecs.umich.edu { "code": vcmpSCode, 11167377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11177377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpSIop); 11187377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop); 11197377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 11207377Sgblack@eecs.umich.edu 11217377Sgblack@eecs.umich.edu vcmpDCode = ''' 11227377Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 11237377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 11247377Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 11257382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp, cOp1.fp); 11267377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11277377Sgblack@eecs.umich.edu if (cDest.fp == cOp1.fp) { 11287377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11297377Sgblack@eecs.umich.edu } else if (cDest.fp < cOp1.fp) { 11307377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11317377Sgblack@eecs.umich.edu } else if (cDest.fp > cOp1.fp) { 11327377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11337377Sgblack@eecs.umich.edu } else { 11347377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11357377Sgblack@eecs.umich.edu } 11367377Sgblack@eecs.umich.edu Fpscr = fpscr; 11377377Sgblack@eecs.umich.edu ''' 11387377Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 11397377Sgblack@eecs.umich.edu { "code": vcmpDCode, 11407377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11417377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 11427377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 11437377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 11447377Sgblack@eecs.umich.edu 11457377Sgblack@eecs.umich.edu vcmpZeroSCode = ''' 11467377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11477382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpDest); 11487377Sgblack@eecs.umich.edu if (FpDest == imm) { 11497377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11507377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 11517377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11527377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 11537377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11547377Sgblack@eecs.umich.edu } else { 11557377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11567377Sgblack@eecs.umich.edu } 11577377Sgblack@eecs.umich.edu Fpscr = fpscr; 11587377Sgblack@eecs.umich.edu ''' 11597377Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 11607377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 11617377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11627377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 11637377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 11647377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 11657377Sgblack@eecs.umich.edu 11667377Sgblack@eecs.umich.edu vcmpZeroDCode = ''' 11677377Sgblack@eecs.umich.edu IntDoubleUnion cDest; 11687377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 11697382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cDest.fp); 11707377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 11717377Sgblack@eecs.umich.edu if (cDest.fp == imm) { 11727377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11737377Sgblack@eecs.umich.edu } else if (cDest.fp < imm) { 11747377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11757377Sgblack@eecs.umich.edu } else if (cDest.fp > imm) { 11767377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11777377Sgblack@eecs.umich.edu } else { 11787377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 11797377Sgblack@eecs.umich.edu } 11807377Sgblack@eecs.umich.edu Fpscr = fpscr; 11817377Sgblack@eecs.umich.edu ''' 11827377Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 11837377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 11847377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11857377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 11867377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 11877377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 11887322Sgblack@eecs.umich.edu}}; 11897379Sgblack@eecs.umich.edu 11907379Sgblack@eecs.umich.edulet {{ 11917379Sgblack@eecs.umich.edu 11927379Sgblack@eecs.umich.edu header_output = "" 11937379Sgblack@eecs.umich.edu decoder_output = "" 11947379Sgblack@eecs.umich.edu exec_output = "" 11957379Sgblack@eecs.umich.edu 11967379Sgblack@eecs.umich.edu vcvtFpSFixedSCode = ''' 11977382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 11987379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11997381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12007379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 12017381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sw)); 12027379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12037379Sgblack@eecs.umich.edu ''' 12047379Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp", 12057379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 12067379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12077379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 12087379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 12097379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 12107379Sgblack@eecs.umich.edu 12117379Sgblack@eecs.umich.edu vcvtFpSFixedDCode = ''' 12127379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 12137379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12147382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 12157379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12167381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 12177379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); 12187381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 12197379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12207379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12217379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12227379Sgblack@eecs.umich.edu ''' 12237379Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp", 12247379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 12257379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12267379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 12277379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 12287379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 12297379Sgblack@eecs.umich.edu 12307379Sgblack@eecs.umich.edu vcvtFpUFixedSCode = ''' 12317382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 12327379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12337381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 12347379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 12357381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uw)); 12367379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12377379Sgblack@eecs.umich.edu ''' 12387379Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp", 12397379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 12407379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12417379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 12427379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 12437379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 12447379Sgblack@eecs.umich.edu 12457379Sgblack@eecs.umich.edu vcvtFpUFixedDCode = ''' 12467379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 12477379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12487382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 12497379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12507381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 12517379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); 12527381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 12537379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12547379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12557379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12567379Sgblack@eecs.umich.edu ''' 12577379Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp", 12587379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 12597379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12607379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 12617379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 12627379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 12637379Sgblack@eecs.umich.edu 12647379Sgblack@eecs.umich.edu vcvtSFixedFpSCode = ''' 12657379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12667381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); 12677380Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm); 12687381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 12697379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12707379Sgblack@eecs.umich.edu ''' 12717379Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 12727379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 12737379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12747379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 12757379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 12767379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 12777379Sgblack@eecs.umich.edu 12787379Sgblack@eecs.umich.edu vcvtSFixedFpDCode = ''' 12797379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 12807379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12817379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12827381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 12837380Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(mid, false, imm); 12847381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 12857379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12867379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 12877379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 12887379Sgblack@eecs.umich.edu ''' 12897379Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 12907379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 12917379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12927379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 12937379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 12947379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 12957379Sgblack@eecs.umich.edu 12967379Sgblack@eecs.umich.edu vcvtUFixedFpSCode = ''' 12977379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12987381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); 12997379Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm); 13007381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 13017379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13027379Sgblack@eecs.umich.edu ''' 13037379Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 13047379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 13057379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13067379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 13077379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 13087379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 13097379Sgblack@eecs.umich.edu 13107379Sgblack@eecs.umich.edu vcvtUFixedFpDCode = ''' 13117379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 13127379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13137379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13147381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 13157379Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(mid, false, imm); 13167381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 13177379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13187379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 13197379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 13207379Sgblack@eecs.umich.edu ''' 13217379Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 13227379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 13237379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13247379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 13257379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 13267379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 13277379Sgblack@eecs.umich.edu 13287379Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = ''' 13297382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 13307379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13317381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13327379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 13337381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.sh)); 13347379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13357379Sgblack@eecs.umich.edu ''' 13367379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 13377379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 13387379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 13397379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13407379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 13417379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 13427379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 13437379Sgblack@eecs.umich.edu 13447379Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = ''' 13457379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 13467379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13477382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 13487379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13497381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 13507379Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); 13517381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 13527379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13537379Sgblack@eecs.umich.edu FpDestP0.uw = result; 13547379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 13557379Sgblack@eecs.umich.edu ''' 13567379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 13577379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 13587379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 13597379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13607379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 13617379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 13627379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 13637379Sgblack@eecs.umich.edu 13647379Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = ''' 13657382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, FpOp1); 13667379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13677381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 13687379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 13697381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest.uh)); 13707379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13717379Sgblack@eecs.umich.edu ''' 13727379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 13737379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 13747379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 13757379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13767379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 13777379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 13787379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 13797379Sgblack@eecs.umich.edu 13807379Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = ''' 13817379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 13827379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 13837382Sgblack@eecs.umich.edu vfpFlushToZero(Fpscr, cOp1.fp); 13847379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 13857381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1.fp) : "m" (cOp1.fp)); 13867379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); 13877381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 13887379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 13897379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 13907379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 13917379Sgblack@eecs.umich.edu ''' 13927379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 13937379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 13947379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 13957379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 13967379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 13977379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 13987379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 13997379Sgblack@eecs.umich.edu 14007379Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = ''' 14017379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14027381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); 14037379Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm); 14047381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14057379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14067379Sgblack@eecs.umich.edu ''' 14077379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 14087379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 14097379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 14107379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14117379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 14127379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 14137379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 14147379Sgblack@eecs.umich.edu 14157379Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = ''' 14167379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 14177379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14187379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14197381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14207379Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(mid, true, imm); 14217381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 14227379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14237379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 14247379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 14257379Sgblack@eecs.umich.edu ''' 14267379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 14277379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 14287379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 14297379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14307379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 14317379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 14327379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 14337379Sgblack@eecs.umich.edu 14347379Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = ''' 14357379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14367381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); 14377379Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm); 14387381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14397379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14407379Sgblack@eecs.umich.edu ''' 14417379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 14427379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 14437379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 14447379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14457379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 14467379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 14477379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 14487379Sgblack@eecs.umich.edu 14497379Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = ''' 14507379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 14517379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 14527379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 14537381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 14547379Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(mid, true, imm); 14557381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest.fp)); 14567379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 14577379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 14587379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 14597379Sgblack@eecs.umich.edu ''' 14607379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 14617379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 14627379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 14637379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 14647379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 14657379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 14667379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 14677379Sgblack@eecs.umich.edu}}; 1468