fp.isa revision 7380
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947375Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp", 1957322Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 1967322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1977375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmsrIop); 1987375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmsrIop); 1997322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2007324Sgblack@eecs.umich.edu 2017375Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp", 2027324Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 2037324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmrsIop); 2057375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmrsIop); 2067324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2077333Sgblack@eecs.umich.edu 2087333Sgblack@eecs.umich.edu vmovImmSCode = ''' 2097333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2107333Sgblack@eecs.umich.edu ''' 2117375Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp", 2127333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2137333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2147375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmSIop); 2157375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop); 2167333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2177333Sgblack@eecs.umich.edu 2187333Sgblack@eecs.umich.edu vmovImmDCode = ''' 2197333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2207333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2217333Sgblack@eecs.umich.edu ''' 2227375Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp", 2237333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2247333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2257375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmDIop); 2267375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop); 2277333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2287333Sgblack@eecs.umich.edu 2297333Sgblack@eecs.umich.edu vmovImmQCode = ''' 2307333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2317333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2327333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2337333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2347333Sgblack@eecs.umich.edu ''' 2357375Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp", 2367333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2377333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2387375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmQIop); 2397375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop); 2407333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2417333Sgblack@eecs.umich.edu 2427333Sgblack@eecs.umich.edu vmovRegSCode = ''' 2437333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2447333Sgblack@eecs.umich.edu ''' 2457375Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp", 2467333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2477333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2487375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegSIop); 2497375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop); 2507333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2517333Sgblack@eecs.umich.edu 2527333Sgblack@eecs.umich.edu vmovRegDCode = ''' 2537333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2547333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2557333Sgblack@eecs.umich.edu ''' 2567375Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp", 2577333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2587333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2597375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegDIop); 2607375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop); 2617333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2627333Sgblack@eecs.umich.edu 2637333Sgblack@eecs.umich.edu vmovRegQCode = ''' 2647333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2657333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2667333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2677333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2687333Sgblack@eecs.umich.edu ''' 2697375Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp", 2707333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2717333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2727375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegQIop); 2737375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegQIop); 2747333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2757333Sgblack@eecs.umich.edu 2767333Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 2777333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 2787333Sgblack@eecs.umich.edu ''' 2797375Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp", 2807333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2817333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2827375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2837375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2857333Sgblack@eecs.umich.edu 2867333Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 2877333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 2887333Sgblack@eecs.umich.edu ''' 2897375Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp", 2907333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 2917333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2927375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 2937375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 2947333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 2957333Sgblack@eecs.umich.edu 2967333Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 2977333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 2987333Sgblack@eecs.umich.edu ''' 2997375Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp", 3007333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3017333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3027375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovCoreRegWIop); 3037375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovCoreRegWIop); 3047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3057333Sgblack@eecs.umich.edu 3067333Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 3077333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 3087333Sgblack@eecs.umich.edu ''' 3097375Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp", 3107333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3117333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3127375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3137375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3147333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3157333Sgblack@eecs.umich.edu 3167333Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 3177333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 3187333Sgblack@eecs.umich.edu ''' 3197375Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp", 3207333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3217333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3227375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3237375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3247333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3257333Sgblack@eecs.umich.edu 3267333Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 3277333Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 3287333Sgblack@eecs.umich.edu ''' 3297375Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp", 3307333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3317333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3327375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3337375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3347333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3357333Sgblack@eecs.umich.edu 3367333Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 3377333Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 3387333Sgblack@eecs.umich.edu ''' 3397375Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp", 3407333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3417333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3427375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3437375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3447333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3457333Sgblack@eecs.umich.edu 3467333Sgblack@eecs.umich.edu vmovRegCoreWCode = ''' 3477333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3487333Sgblack@eecs.umich.edu ''' 3497375Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp", 3507333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3517333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3527375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegCoreWIop); 3537375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegCoreWIop); 3547333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 3557333Sgblack@eecs.umich.edu 3567333Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 3577333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3587333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3597333Sgblack@eecs.umich.edu ''' 3607375Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp", 3617333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3627333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3637375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3647375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3657333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3667333Sgblack@eecs.umich.edu 3677333Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 3687333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3697333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3707333Sgblack@eecs.umich.edu ''' 3717375Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp", 3727333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3737333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3747375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3757375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3767333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3777364Sgblack@eecs.umich.edu 3787364Sgblack@eecs.umich.edu vmulSCode = ''' 3797378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 3807364Sgblack@eecs.umich.edu FpDest = FpOp1 * FpOp2; 3817378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 3827364Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 3837364Sgblack@eecs.umich.edu FpDest = NAN; 3847364Sgblack@eecs.umich.edu } 3857364Sgblack@eecs.umich.edu ''' 3867375Sgblack@eecs.umich.edu vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 3877364Sgblack@eecs.umich.edu { "code": vmulSCode, 3887364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3897375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulSIop); 3907375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop); 3917364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulSIop); 3927364Sgblack@eecs.umich.edu 3937364Sgblack@eecs.umich.edu vmulDCode = ''' 3947364Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 3957364Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 3967364Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 3977378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 3987364Sgblack@eecs.umich.edu cDest.fp = cOp1.fp * cOp2.fp; 3997378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4007364Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 4017364Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 4027364Sgblack@eecs.umich.edu cDest.fp = NAN; 4037364Sgblack@eecs.umich.edu } 4047364Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4057364Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4067364Sgblack@eecs.umich.edu ''' 4077375Sgblack@eecs.umich.edu vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp", 4087364Sgblack@eecs.umich.edu { "code": vmulDCode, 4097364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4107375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulDIop); 4117375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop); 4127364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulDIop); 4137365Sgblack@eecs.umich.edu 4147365Sgblack@eecs.umich.edu vnegSCode = ''' 4157365Sgblack@eecs.umich.edu FpDest = -FpOp1; 4167365Sgblack@eecs.umich.edu ''' 4177375Sgblack@eecs.umich.edu vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp", 4187365Sgblack@eecs.umich.edu { "code": vnegSCode, 4197365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4207375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegSIop); 4217375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegSIop); 4227365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegSIop); 4237365Sgblack@eecs.umich.edu 4247365Sgblack@eecs.umich.edu vnegDCode = ''' 4257365Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4267365Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4277365Sgblack@eecs.umich.edu cDest.fp = -cOp1.fp; 4287365Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4297365Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4307365Sgblack@eecs.umich.edu ''' 4317375Sgblack@eecs.umich.edu vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp", 4327365Sgblack@eecs.umich.edu { "code": vnegDCode, 4337365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4347375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegDIop); 4357375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegDIop); 4367365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegDIop); 4377366Sgblack@eecs.umich.edu 4387366Sgblack@eecs.umich.edu vabsSCode = ''' 4397366Sgblack@eecs.umich.edu FpDest = fabsf(FpOp1); 4407366Sgblack@eecs.umich.edu ''' 4417375Sgblack@eecs.umich.edu vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp", 4427366Sgblack@eecs.umich.edu { "code": vabsSCode, 4437366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4447375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsSIop); 4457375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsSIop); 4467366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsSIop); 4477366Sgblack@eecs.umich.edu 4487366Sgblack@eecs.umich.edu vabsDCode = ''' 4497366Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4507366Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4517366Sgblack@eecs.umich.edu cDest.fp = fabs(cOp1.fp); 4527366Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4537366Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4547366Sgblack@eecs.umich.edu ''' 4557375Sgblack@eecs.umich.edu vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp", 4567366Sgblack@eecs.umich.edu { "code": vabsDCode, 4577366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4587375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsDIop); 4597375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsDIop); 4607366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsDIop); 4617367Sgblack@eecs.umich.edu 4627367Sgblack@eecs.umich.edu vaddSCode = ''' 4637378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4647367Sgblack@eecs.umich.edu FpDest = FpOp1 + FpOp2; 4657378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4667367Sgblack@eecs.umich.edu ''' 4677375Sgblack@eecs.umich.edu vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp", 4687367Sgblack@eecs.umich.edu { "code": vaddSCode, 4697367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4707375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddSIop); 4717375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop); 4727367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddSIop); 4737367Sgblack@eecs.umich.edu 4747367Sgblack@eecs.umich.edu vaddDCode = ''' 4757367Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4767367Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4777367Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4787378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4797367Sgblack@eecs.umich.edu cDest.fp = cOp1.fp + cOp2.fp; 4807378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 4817367Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4827367Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4837367Sgblack@eecs.umich.edu ''' 4847375Sgblack@eecs.umich.edu vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp", 4857367Sgblack@eecs.umich.edu { "code": vaddDCode, 4867367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4877375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddDIop); 4887375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop); 4897367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddDIop); 4907368Sgblack@eecs.umich.edu 4917368Sgblack@eecs.umich.edu vsubSCode = ''' 4927378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 4937368Sgblack@eecs.umich.edu FpDest = FpOp1 - FpOp2; 4947378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state) 4957368Sgblack@eecs.umich.edu ''' 4967375Sgblack@eecs.umich.edu vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp", 4977368Sgblack@eecs.umich.edu { "code": vsubSCode, 4987368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4997375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubSIop); 5007375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop); 5017368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubSIop); 5027368Sgblack@eecs.umich.edu 5037368Sgblack@eecs.umich.edu vsubDCode = ''' 5047368Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5057368Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5067368Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5077378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5087368Sgblack@eecs.umich.edu cDest.fp = cOp1.fp - cOp2.fp; 5097378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5107368Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5117368Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5127368Sgblack@eecs.umich.edu ''' 5137375Sgblack@eecs.umich.edu vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp", 5147368Sgblack@eecs.umich.edu { "code": vsubDCode, 5157368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5167375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubDIop); 5177375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop); 5187368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubDIop); 5197369Sgblack@eecs.umich.edu 5207369Sgblack@eecs.umich.edu vdivSCode = ''' 5217378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5227369Sgblack@eecs.umich.edu FpDest = FpOp1 / FpOp2; 5237378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5247369Sgblack@eecs.umich.edu ''' 5257375Sgblack@eecs.umich.edu vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp", 5267369Sgblack@eecs.umich.edu { "code": vdivSCode, 5277369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5287375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivSIop); 5297375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop); 5307369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivSIop); 5317369Sgblack@eecs.umich.edu 5327369Sgblack@eecs.umich.edu vdivDCode = ''' 5337369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5347369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5357369Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5367378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5377369Sgblack@eecs.umich.edu cDest.fp = cOp1.fp / cOp2.fp; 5387378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5397369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5407369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5417369Sgblack@eecs.umich.edu ''' 5427375Sgblack@eecs.umich.edu vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp", 5437369Sgblack@eecs.umich.edu { "code": vdivDCode, 5447369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5457375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivDIop); 5467375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop); 5477369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivDIop); 5487369Sgblack@eecs.umich.edu 5497369Sgblack@eecs.umich.edu vsqrtSCode = ''' 5507378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5517369Sgblack@eecs.umich.edu FpDest = sqrtf(FpOp1); 5527378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5537369Sgblack@eecs.umich.edu if (FpOp1 < 0) { 5547369Sgblack@eecs.umich.edu FpDest = NAN; 5557369Sgblack@eecs.umich.edu } 5567369Sgblack@eecs.umich.edu ''' 5577375Sgblack@eecs.umich.edu vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp", 5587369Sgblack@eecs.umich.edu { "code": vsqrtSCode, 5597369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5607375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtSIop); 5617375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop); 5627369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtSIop); 5637369Sgblack@eecs.umich.edu 5647369Sgblack@eecs.umich.edu vsqrtDCode = ''' 5657369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 5667369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5677378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5687369Sgblack@eecs.umich.edu cDest.fp = sqrt(cOp1.fp); 5697378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5707369Sgblack@eecs.umich.edu if (cOp1.fp < 0) { 5717369Sgblack@eecs.umich.edu cDest.fp = NAN; 5727369Sgblack@eecs.umich.edu } 5737369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5747369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5757369Sgblack@eecs.umich.edu ''' 5767375Sgblack@eecs.umich.edu vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp", 5777369Sgblack@eecs.umich.edu { "code": vsqrtDCode, 5787369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5797375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtDIop); 5807375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop); 5817369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtDIop); 5827370Sgblack@eecs.umich.edu 5837370Sgblack@eecs.umich.edu vmlaSCode = ''' 5847378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 5857370Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 5867370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 5877370Sgblack@eecs.umich.edu mid = NAN; 5887370Sgblack@eecs.umich.edu } 5897370Sgblack@eecs.umich.edu FpDest = FpDest + mid; 5907378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 5917370Sgblack@eecs.umich.edu ''' 5927375Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp", 5937370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5947370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5957375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop); 5967375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop); 5977370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5987370Sgblack@eecs.umich.edu 5997370Sgblack@eecs.umich.edu vmlaDCode = ''' 6007370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6017370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6027370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6037370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6047378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6057370Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 6067370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6077370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6087370Sgblack@eecs.umich.edu mid = NAN; 6097370Sgblack@eecs.umich.edu } 6107370Sgblack@eecs.umich.edu cDest.fp = cDest.fp + mid; 6117378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6127370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6137370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6147370Sgblack@eecs.umich.edu ''' 6157375Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp", 6167370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6177370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6187375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop); 6197375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop); 6207370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6217370Sgblack@eecs.umich.edu 6227370Sgblack@eecs.umich.edu vmlsSCode = ''' 6237378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6247370Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 6257370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6267370Sgblack@eecs.umich.edu mid = NAN; 6277370Sgblack@eecs.umich.edu } 6287370Sgblack@eecs.umich.edu FpDest = FpDest - mid; 6297378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6307370Sgblack@eecs.umich.edu ''' 6317375Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 6327370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6337370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6347375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 6357375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); 6367370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 6377370Sgblack@eecs.umich.edu 6387370Sgblack@eecs.umich.edu vmlsDCode = ''' 6397370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6407370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6417370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6427370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6437378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6447370Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 6457370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6467370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6477370Sgblack@eecs.umich.edu mid = NAN; 6487370Sgblack@eecs.umich.edu } 6497370Sgblack@eecs.umich.edu cDest.fp = cDest.fp - mid; 6507378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6517370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6527370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6537370Sgblack@eecs.umich.edu ''' 6547375Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 6557370Sgblack@eecs.umich.edu { "code": vmlsDCode, 6567370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6577375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop); 6587375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop); 6597370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 6607371Sgblack@eecs.umich.edu 6617371Sgblack@eecs.umich.edu vnmlaSCode = ''' 6627378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6637371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 6647371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6657371Sgblack@eecs.umich.edu mid = NAN; 6667371Sgblack@eecs.umich.edu } 6677371Sgblack@eecs.umich.edu FpDest = -FpDest - mid; 6687378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6697371Sgblack@eecs.umich.edu ''' 6707375Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 6717371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 6727371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6737375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 6747375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); 6757371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 6767371Sgblack@eecs.umich.edu 6777371Sgblack@eecs.umich.edu vnmlaDCode = ''' 6787371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6797371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6807371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6817371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6827378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 6837371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 6847371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6857371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6867371Sgblack@eecs.umich.edu mid = NAN; 6877371Sgblack@eecs.umich.edu } 6887371Sgblack@eecs.umich.edu cDest.fp = -cDest.fp - mid; 6897378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 6907371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6917371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6927371Sgblack@eecs.umich.edu ''' 6937375Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 6947371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6957371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6967375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop); 6977375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop); 6987371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6997371Sgblack@eecs.umich.edu 7007371Sgblack@eecs.umich.edu vnmlsSCode = ''' 7017378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7027371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 7037371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7047371Sgblack@eecs.umich.edu mid = NAN; 7057371Sgblack@eecs.umich.edu } 7067371Sgblack@eecs.umich.edu FpDest = -FpDest + mid; 7077378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7087371Sgblack@eecs.umich.edu ''' 7097375Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 7107371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 7117371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7127375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 7137375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); 7147371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7157371Sgblack@eecs.umich.edu 7167371Sgblack@eecs.umich.edu vnmlsDCode = ''' 7177371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7187371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7197371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7207371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7217378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7227371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 7237371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7247371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7257371Sgblack@eecs.umich.edu mid = NAN; 7267371Sgblack@eecs.umich.edu } 7277371Sgblack@eecs.umich.edu cDest.fp = -cDest.fp + mid; 7287378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7297371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7307371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7317371Sgblack@eecs.umich.edu ''' 7327375Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 7337371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 7347371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7357375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop); 7367375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop); 7377371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 7387371Sgblack@eecs.umich.edu 7397371Sgblack@eecs.umich.edu vnmulSCode = ''' 7407378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7417371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 7427371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7437371Sgblack@eecs.umich.edu mid = NAN; 7447371Sgblack@eecs.umich.edu } 7457371Sgblack@eecs.umich.edu FpDest = -mid; 7467378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7477371Sgblack@eecs.umich.edu ''' 7487375Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp", 7497371Sgblack@eecs.umich.edu { "code": vnmulSCode, 7507371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7517375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop); 7527375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop); 7537371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 7547371Sgblack@eecs.umich.edu 7557371Sgblack@eecs.umich.edu vnmulDCode = ''' 7567371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7577371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7587371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7597371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7607378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7617371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 7627371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7637371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7647371Sgblack@eecs.umich.edu mid = NAN; 7657371Sgblack@eecs.umich.edu } 7667371Sgblack@eecs.umich.edu cDest.fp = -mid; 7677378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7687371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7697371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7707371Sgblack@eecs.umich.edu ''' 7717375Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp", 7727371Sgblack@eecs.umich.edu { "code": vnmulDCode, 7737371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7747375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop); 7757375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop); 7767371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 7777373Sgblack@eecs.umich.edu 7787373Sgblack@eecs.umich.edu vcvtUIntFpSCode = ''' 7797378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7807373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 7817378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7827373Sgblack@eecs.umich.edu ''' 7837375Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp", 7847373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 7857373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7867375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop); 7877375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop); 7887373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 7897373Sgblack@eecs.umich.edu 7907373Sgblack@eecs.umich.edu vcvtUIntFpDCode = ''' 7917373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 7927378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 7937373Sgblack@eecs.umich.edu cDest.fp = (uint64_t)FpOp1P0.uw; 7947378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 7957373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7967373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7977373Sgblack@eecs.umich.edu ''' 7987375Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp", 7997373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 8007373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8017375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop); 8027375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop); 8037373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 8047373Sgblack@eecs.umich.edu 8057373Sgblack@eecs.umich.edu vcvtSIntFpSCode = ''' 8067378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8077373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 8087378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8097373Sgblack@eecs.umich.edu ''' 8107375Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp", 8117373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 8127373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8137375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop); 8147375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop); 8157373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 8167373Sgblack@eecs.umich.edu 8177373Sgblack@eecs.umich.edu vcvtSIntFpDCode = ''' 8187373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 8197378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8207373Sgblack@eecs.umich.edu cDest.fp = FpOp1P0.sw; 8217378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8227373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8237373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8247373Sgblack@eecs.umich.edu ''' 8257375Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp", 8267373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 8277373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8287375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop); 8297375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop); 8307373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 8317373Sgblack@eecs.umich.edu 8327380Sgblack@eecs.umich.edu vcvtFpUIntSRCode = ''' 8337380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8347380Sgblack@eecs.umich.edu FpDest.uw = FpOp1; 8357380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8367380Sgblack@eecs.umich.edu ''' 8377380Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp", 8387380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 8397380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8407380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 8417380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 8427380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 8437380Sgblack@eecs.umich.edu 8447380Sgblack@eecs.umich.edu vcvtFpUIntDRCode = ''' 8457380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 8467380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8477380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8487380Sgblack@eecs.umich.edu uint64_t result = cOp1.fp; 8497380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8507380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8517380Sgblack@eecs.umich.edu ''' 8527380Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp", 8537380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 8547380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8557380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 8567380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 8577380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 8587380Sgblack@eecs.umich.edu 8597380Sgblack@eecs.umich.edu vcvtFpSIntSRCode = ''' 8607380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8617380Sgblack@eecs.umich.edu FpDest.sw = FpOp1; 8627380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8637380Sgblack@eecs.umich.edu ''' 8647380Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp", 8657380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 8667380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8677380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 8687380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 8697380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 8707380Sgblack@eecs.umich.edu 8717380Sgblack@eecs.umich.edu vcvtFpSIntDRCode = ''' 8727380Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 8737380Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8747380Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8757380Sgblack@eecs.umich.edu int64_t result = cOp1.fp; 8767380Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8777380Sgblack@eecs.umich.edu FpDestP0.uw = result; 8787380Sgblack@eecs.umich.edu ''' 8797380Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp", 8807380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 8817380Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8827380Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 8837380Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 8847380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 8857380Sgblack@eecs.umich.edu 8867373Sgblack@eecs.umich.edu vcvtFpUIntSCode = ''' 8877378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 8887380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 8897373Sgblack@eecs.umich.edu FpDest.uw = FpOp1; 8907378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 8917373Sgblack@eecs.umich.edu ''' 8927375Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp", 8937373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 8947373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8957375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop); 8967375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop); 8977373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 8987373Sgblack@eecs.umich.edu 8997373Sgblack@eecs.umich.edu vcvtFpUIntDCode = ''' 9007373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9017373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9027378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9037380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9047373Sgblack@eecs.umich.edu uint64_t result = cOp1.fp; 9057378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9067373Sgblack@eecs.umich.edu FpDestP0.uw = result; 9077373Sgblack@eecs.umich.edu ''' 9087375Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp", 9097373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 9107373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9117375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop); 9127375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop); 9137373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 9147373Sgblack@eecs.umich.edu 9157373Sgblack@eecs.umich.edu vcvtFpSIntSCode = ''' 9167378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9177380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9187373Sgblack@eecs.umich.edu FpDest.sw = FpOp1; 9197378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9207373Sgblack@eecs.umich.edu ''' 9217375Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp", 9227373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 9237373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9247375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop); 9257375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop); 9267373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 9277373Sgblack@eecs.umich.edu 9287373Sgblack@eecs.umich.edu vcvtFpSIntDCode = ''' 9297373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9307373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9317378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9327380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9337373Sgblack@eecs.umich.edu int64_t result = cOp1.fp; 9347378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9357373Sgblack@eecs.umich.edu FpDestP0.uw = result; 9367373Sgblack@eecs.umich.edu ''' 9377375Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp", 9387373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 9397373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9407375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop); 9417375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop); 9427373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 9437374Sgblack@eecs.umich.edu 9447374Sgblack@eecs.umich.edu vcvtFpSFpDCode = ''' 9457374Sgblack@eecs.umich.edu IntDoubleUnion cDest; 9467378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9477374Sgblack@eecs.umich.edu cDest.fp = FpOp1; 9487378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9497374Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 9507374Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 9517374Sgblack@eecs.umich.edu ''' 9527375Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp", 9537374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 9547374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9557375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop); 9567375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop); 9577374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 9587374Sgblack@eecs.umich.edu 9597374Sgblack@eecs.umich.edu vcvtFpDFpSCode = ''' 9607374Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 9617374Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9627378Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 9637374Sgblack@eecs.umich.edu FpDest = cOp1.fp; 9647378Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 9657374Sgblack@eecs.umich.edu ''' 9667375Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 9677374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 9687374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9697375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 9707375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 9717374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 9727377Sgblack@eecs.umich.edu 9737377Sgblack@eecs.umich.edu vcmpSCode = ''' 9747377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9757377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 9767377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 9777377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 9787377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 9797377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 9807377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 9817377Sgblack@eecs.umich.edu } else { 9827377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 9837377Sgblack@eecs.umich.edu } 9847377Sgblack@eecs.umich.edu Fpscr = fpscr; 9857377Sgblack@eecs.umich.edu ''' 9867377Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 9877377Sgblack@eecs.umich.edu { "code": vcmpSCode, 9887377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9897377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpSIop); 9907377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop); 9917377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 9927377Sgblack@eecs.umich.edu 9937377Sgblack@eecs.umich.edu vcmpDCode = ''' 9947377Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 9957377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 9967377Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 9977377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9987377Sgblack@eecs.umich.edu if (cDest.fp == cOp1.fp) { 9997377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10007377Sgblack@eecs.umich.edu } else if (cDest.fp < cOp1.fp) { 10017377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10027377Sgblack@eecs.umich.edu } else if (cDest.fp > cOp1.fp) { 10037377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10047377Sgblack@eecs.umich.edu } else { 10057377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10067377Sgblack@eecs.umich.edu } 10077377Sgblack@eecs.umich.edu Fpscr = fpscr; 10087377Sgblack@eecs.umich.edu ''' 10097377Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 10107377Sgblack@eecs.umich.edu { "code": vcmpDCode, 10117377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10127377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 10137377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 10147377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 10157377Sgblack@eecs.umich.edu 10167377Sgblack@eecs.umich.edu vcmpZeroSCode = ''' 10177377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10187377Sgblack@eecs.umich.edu if (FpDest == imm) { 10197377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10207377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 10217377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10227377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 10237377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10247377Sgblack@eecs.umich.edu } else { 10257377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10267377Sgblack@eecs.umich.edu } 10277377Sgblack@eecs.umich.edu Fpscr = fpscr; 10287377Sgblack@eecs.umich.edu ''' 10297377Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 10307377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 10317377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10327377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 10337377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 10347377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 10357377Sgblack@eecs.umich.edu 10367377Sgblack@eecs.umich.edu vcmpZeroDCode = ''' 10377377Sgblack@eecs.umich.edu IntDoubleUnion cDest; 10387377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 10397377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 10407377Sgblack@eecs.umich.edu if (cDest.fp == imm) { 10417377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 10427377Sgblack@eecs.umich.edu } else if (cDest.fp < imm) { 10437377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 10447377Sgblack@eecs.umich.edu } else if (cDest.fp > imm) { 10457377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 10467377Sgblack@eecs.umich.edu } else { 10477377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 10487377Sgblack@eecs.umich.edu } 10497377Sgblack@eecs.umich.edu Fpscr = fpscr; 10507377Sgblack@eecs.umich.edu ''' 10517377Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 10527377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 10537377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10547377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 10557377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 10567377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 10577322Sgblack@eecs.umich.edu}}; 10587379Sgblack@eecs.umich.edu 10597379Sgblack@eecs.umich.edulet {{ 10607379Sgblack@eecs.umich.edu 10617379Sgblack@eecs.umich.edu header_output = "" 10627379Sgblack@eecs.umich.edu decoder_output = "" 10637379Sgblack@eecs.umich.edu exec_output = "" 10647379Sgblack@eecs.umich.edu 10657379Sgblack@eecs.umich.edu vcvtFpSFixedSCode = ''' 10667379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10677379Sgblack@eecs.umich.edu FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 10687379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10697379Sgblack@eecs.umich.edu ''' 10707379Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp", 10717379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 10727379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10737379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 10747379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 10757379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 10767379Sgblack@eecs.umich.edu 10777379Sgblack@eecs.umich.edu vcvtFpSFixedDCode = ''' 10787379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 10797379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 10807379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10817379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); 10827379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10837379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 10847379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 10857379Sgblack@eecs.umich.edu ''' 10867379Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp", 10877379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 10887379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 10897379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 10907379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 10917379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 10927379Sgblack@eecs.umich.edu 10937379Sgblack@eecs.umich.edu vcvtFpUFixedSCode = ''' 10947379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 10957379Sgblack@eecs.umich.edu FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 10967379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 10977379Sgblack@eecs.umich.edu ''' 10987379Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp", 10997379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 11007379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11017379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 11027379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 11037379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 11047379Sgblack@eecs.umich.edu 11057379Sgblack@eecs.umich.edu vcvtFpUFixedDCode = ''' 11067379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 11077379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 11087379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11097379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); 11107379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11117379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 11127379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 11137379Sgblack@eecs.umich.edu ''' 11147379Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp", 11157379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 11167379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11177379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 11187379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 11197379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 11207379Sgblack@eecs.umich.edu 11217379Sgblack@eecs.umich.edu vcvtSFixedFpSCode = ''' 11227379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11237380Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm); 11247379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11257379Sgblack@eecs.umich.edu ''' 11267379Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 11277379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 11287379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11297379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 11307379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 11317379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 11327379Sgblack@eecs.umich.edu 11337379Sgblack@eecs.umich.edu vcvtSFixedFpDCode = ''' 11347379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 11357379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 11367379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11377380Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(mid, false, imm); 11387379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11397379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 11407379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 11417379Sgblack@eecs.umich.edu ''' 11427379Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 11437379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 11447379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11457379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 11467379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 11477379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 11487379Sgblack@eecs.umich.edu 11497379Sgblack@eecs.umich.edu vcvtUFixedFpSCode = ''' 11507379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11517379Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm); 11527379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11537379Sgblack@eecs.umich.edu ''' 11547379Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 11557379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 11567379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11577379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 11587379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 11597379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 11607379Sgblack@eecs.umich.edu 11617379Sgblack@eecs.umich.edu vcvtUFixedFpDCode = ''' 11627379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 11637379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 11647379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11657379Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(mid, false, imm); 11667379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11677379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 11687379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 11697379Sgblack@eecs.umich.edu ''' 11707379Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 11717379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 11727379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11737379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 11747379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 11757379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 11767379Sgblack@eecs.umich.edu 11777379Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = ''' 11787379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11797379Sgblack@eecs.umich.edu FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 11807379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11817379Sgblack@eecs.umich.edu ''' 11827379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 11837379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 11847379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 11857379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 11867379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 11877379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 11887379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 11897379Sgblack@eecs.umich.edu 11907379Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = ''' 11917379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 11927379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 11937379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 11947379Sgblack@eecs.umich.edu uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); 11957379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 11967379Sgblack@eecs.umich.edu FpDestP0.uw = result; 11977379Sgblack@eecs.umich.edu FpDestP1.uw = result >> 32; 11987379Sgblack@eecs.umich.edu ''' 11997379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 12007379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 12017379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 12027379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12037379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 12047379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 12057379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 12067379Sgblack@eecs.umich.edu 12077379Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = ''' 12087379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12097379Sgblack@eecs.umich.edu FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 12107379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12117379Sgblack@eecs.umich.edu ''' 12127379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 12137379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 12147379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 12157379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12167379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 12177379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 12187379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 12197379Sgblack@eecs.umich.edu 12207379Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = ''' 12217379Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 12227379Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12237379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12247379Sgblack@eecs.umich.edu uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); 12257379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12267379Sgblack@eecs.umich.edu FpDestP0.uw = mid; 12277379Sgblack@eecs.umich.edu FpDestP1.uw = mid >> 32; 12287379Sgblack@eecs.umich.edu ''' 12297379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 12307379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 12317379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 12327379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12337379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 12347379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 12357379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 12367379Sgblack@eecs.umich.edu 12377379Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = ''' 12387379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12397379Sgblack@eecs.umich.edu FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm); 12407379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12417379Sgblack@eecs.umich.edu ''' 12427379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 12437379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 12447379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 12457379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12467379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 12477379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 12487379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 12497379Sgblack@eecs.umich.edu 12507379Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = ''' 12517379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 12527379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12537379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12547379Sgblack@eecs.umich.edu cDest.fp = vfpSFixedToFpD(mid, true, imm); 12557379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12567379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 12577379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 12587379Sgblack@eecs.umich.edu ''' 12597379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 12607379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 12617379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 12627379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12637379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 12647379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 12657379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 12667379Sgblack@eecs.umich.edu 12677379Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = ''' 12687379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12697379Sgblack@eecs.umich.edu FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm); 12707379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12717379Sgblack@eecs.umich.edu ''' 12727379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 12737379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 12747379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 12757379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12767379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 12777379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 12787379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 12797379Sgblack@eecs.umich.edu 12807379Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = ''' 12817379Sgblack@eecs.umich.edu IntDoubleUnion cDest; 12827379Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 12837379Sgblack@eecs.umich.edu VfpSavedState state = prepVfpFpscr(Fpscr); 12847379Sgblack@eecs.umich.edu cDest.fp = vfpUFixedToFpD(mid, true, imm); 12857379Sgblack@eecs.umich.edu Fpscr = setVfpFpscr(Fpscr, state); 12867379Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 12877379Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 12887379Sgblack@eecs.umich.edu ''' 12897379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 12907379Sgblack@eecs.umich.edu "VfpRegRegImmOp", 12917379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 12927379Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 12937379Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 12947379Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 12957379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 12967379Sgblack@eecs.umich.edu}}; 1297