fp.isa revision 7377
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 1947375Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp", 1957322Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 1967322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1977375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmsrIop); 1987375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmsrIop); 1997322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2007324Sgblack@eecs.umich.edu 2017375Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp", 2027324Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 2037324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmrsIop); 2057375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmrsIop); 2067324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2077333Sgblack@eecs.umich.edu 2087333Sgblack@eecs.umich.edu vmovImmSCode = ''' 2097333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 2107333Sgblack@eecs.umich.edu ''' 2117375Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp", 2127333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2137333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2147375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmSIop); 2157375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop); 2167333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2177333Sgblack@eecs.umich.edu 2187333Sgblack@eecs.umich.edu vmovImmDCode = ''' 2197333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2207333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2217333Sgblack@eecs.umich.edu ''' 2227375Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp", 2237333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2247333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2257375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmDIop); 2267375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop); 2277333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2287333Sgblack@eecs.umich.edu 2297333Sgblack@eecs.umich.edu vmovImmQCode = ''' 2307333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 2317333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 2327333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 2337333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 2347333Sgblack@eecs.umich.edu ''' 2357375Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp", 2367333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 2377333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2387375Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vmovImmQIop); 2397375Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop); 2407333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 2417333Sgblack@eecs.umich.edu 2427333Sgblack@eecs.umich.edu vmovRegSCode = ''' 2437333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 2447333Sgblack@eecs.umich.edu ''' 2457375Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp", 2467333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 2477333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2487375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegSIop); 2497375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop); 2507333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 2517333Sgblack@eecs.umich.edu 2527333Sgblack@eecs.umich.edu vmovRegDCode = ''' 2537333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2547333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2557333Sgblack@eecs.umich.edu ''' 2567375Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp", 2577333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 2587333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2597375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegDIop); 2607375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop); 2617333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 2627333Sgblack@eecs.umich.edu 2637333Sgblack@eecs.umich.edu vmovRegQCode = ''' 2647333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 2657333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 2667333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 2677333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 2687333Sgblack@eecs.umich.edu ''' 2697375Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp", 2707333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 2717333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2727375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegQIop); 2737375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegQIop); 2747333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 2757333Sgblack@eecs.umich.edu 2767333Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 2777333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 2787333Sgblack@eecs.umich.edu ''' 2797375Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp", 2807333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 2817333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2827375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 2837375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 2847333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 2857333Sgblack@eecs.umich.edu 2867333Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 2877333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 2887333Sgblack@eecs.umich.edu ''' 2897375Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp", 2907333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 2917333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2927375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 2937375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 2947333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 2957333Sgblack@eecs.umich.edu 2967333Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 2977333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 2987333Sgblack@eecs.umich.edu ''' 2997375Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp", 3007333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3017333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3027375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovCoreRegWIop); 3037375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovCoreRegWIop); 3047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3057333Sgblack@eecs.umich.edu 3067333Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 3077333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 3087333Sgblack@eecs.umich.edu ''' 3097375Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp", 3107333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3117333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3127375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3137375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3147333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3157333Sgblack@eecs.umich.edu 3167333Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 3177333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 3187333Sgblack@eecs.umich.edu ''' 3197375Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp", 3207333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3217333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3227375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3237375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3247333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3257333Sgblack@eecs.umich.edu 3267333Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 3277333Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 3287333Sgblack@eecs.umich.edu ''' 3297375Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp", 3307333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 3317333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3327375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 3337375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 3347333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 3357333Sgblack@eecs.umich.edu 3367333Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 3377333Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 3387333Sgblack@eecs.umich.edu ''' 3397375Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp", 3407333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 3417333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3427375Sgblack@eecs.umich.edu header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 3437375Sgblack@eecs.umich.edu decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 3447333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 3457333Sgblack@eecs.umich.edu 3467333Sgblack@eecs.umich.edu vmovRegCoreWCode = ''' 3477333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 3487333Sgblack@eecs.umich.edu ''' 3497375Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp", 3507333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 3517333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3527375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vmovRegCoreWIop); 3537375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vmovRegCoreWIop); 3547333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 3557333Sgblack@eecs.umich.edu 3567333Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 3577333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 3587333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 3597333Sgblack@eecs.umich.edu ''' 3607375Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp", 3617333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 3627333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3637375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 3647375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 3657333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 3667333Sgblack@eecs.umich.edu 3677333Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 3687333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 3697333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 3707333Sgblack@eecs.umich.edu ''' 3717375Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp", 3727333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 3737333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3747375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 3757375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 3767333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 3777364Sgblack@eecs.umich.edu 3787364Sgblack@eecs.umich.edu vmulSCode = ''' 3797364Sgblack@eecs.umich.edu FpDest = FpOp1 * FpOp2; 3807364Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 3817364Sgblack@eecs.umich.edu FpDest = NAN; 3827364Sgblack@eecs.umich.edu } 3837364Sgblack@eecs.umich.edu ''' 3847375Sgblack@eecs.umich.edu vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 3857364Sgblack@eecs.umich.edu { "code": vmulSCode, 3867364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3877375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulSIop); 3887375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop); 3897364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulSIop); 3907364Sgblack@eecs.umich.edu 3917364Sgblack@eecs.umich.edu vmulDCode = ''' 3927364Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 3937364Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 3947364Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 3957364Sgblack@eecs.umich.edu cDest.fp = cOp1.fp * cOp2.fp; 3967364Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 3977364Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 3987364Sgblack@eecs.umich.edu cDest.fp = NAN; 3997364Sgblack@eecs.umich.edu } 4007364Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4017364Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4027364Sgblack@eecs.umich.edu ''' 4037375Sgblack@eecs.umich.edu vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp", 4047364Sgblack@eecs.umich.edu { "code": vmulDCode, 4057364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4067375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmulDIop); 4077375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop); 4087364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulDIop); 4097365Sgblack@eecs.umich.edu 4107365Sgblack@eecs.umich.edu vnegSCode = ''' 4117365Sgblack@eecs.umich.edu FpDest = -FpOp1; 4127365Sgblack@eecs.umich.edu ''' 4137375Sgblack@eecs.umich.edu vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp", 4147365Sgblack@eecs.umich.edu { "code": vnegSCode, 4157365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4167375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegSIop); 4177375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegSIop); 4187365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegSIop); 4197365Sgblack@eecs.umich.edu 4207365Sgblack@eecs.umich.edu vnegDCode = ''' 4217365Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4227365Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4237365Sgblack@eecs.umich.edu cDest.fp = -cOp1.fp; 4247365Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4257365Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4267365Sgblack@eecs.umich.edu ''' 4277375Sgblack@eecs.umich.edu vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp", 4287365Sgblack@eecs.umich.edu { "code": vnegDCode, 4297365Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4307375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vnegDIop); 4317375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vnegDIop); 4327365Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnegDIop); 4337366Sgblack@eecs.umich.edu 4347366Sgblack@eecs.umich.edu vabsSCode = ''' 4357366Sgblack@eecs.umich.edu FpDest = fabsf(FpOp1); 4367366Sgblack@eecs.umich.edu ''' 4377375Sgblack@eecs.umich.edu vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp", 4387366Sgblack@eecs.umich.edu { "code": vabsSCode, 4397366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4407375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsSIop); 4417375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsSIop); 4427366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsSIop); 4437366Sgblack@eecs.umich.edu 4447366Sgblack@eecs.umich.edu vabsDCode = ''' 4457366Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 4467366Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4477366Sgblack@eecs.umich.edu cDest.fp = fabs(cOp1.fp); 4487366Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4497366Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4507366Sgblack@eecs.umich.edu ''' 4517375Sgblack@eecs.umich.edu vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp", 4527366Sgblack@eecs.umich.edu { "code": vabsDCode, 4537366Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4547375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vabsDIop); 4557375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vabsDIop); 4567366Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vabsDIop); 4577367Sgblack@eecs.umich.edu 4587367Sgblack@eecs.umich.edu vaddSCode = ''' 4597367Sgblack@eecs.umich.edu FpDest = FpOp1 + FpOp2; 4607367Sgblack@eecs.umich.edu ''' 4617375Sgblack@eecs.umich.edu vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp", 4627367Sgblack@eecs.umich.edu { "code": vaddSCode, 4637367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4647375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddSIop); 4657375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop); 4667367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddSIop); 4677367Sgblack@eecs.umich.edu 4687367Sgblack@eecs.umich.edu vaddDCode = ''' 4697367Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4707367Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4717367Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4727367Sgblack@eecs.umich.edu cDest.fp = cOp1.fp + cOp2.fp; 4737367Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4747367Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 4757367Sgblack@eecs.umich.edu ''' 4767375Sgblack@eecs.umich.edu vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp", 4777367Sgblack@eecs.umich.edu { "code": vaddDCode, 4787367Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4797375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vaddDIop); 4807375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop); 4817367Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vaddDIop); 4827368Sgblack@eecs.umich.edu 4837368Sgblack@eecs.umich.edu vsubSCode = ''' 4847368Sgblack@eecs.umich.edu FpDest = FpOp1 - FpOp2; 4857368Sgblack@eecs.umich.edu ''' 4867375Sgblack@eecs.umich.edu vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp", 4877368Sgblack@eecs.umich.edu { "code": vsubSCode, 4887368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4897375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubSIop); 4907375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop); 4917368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubSIop); 4927368Sgblack@eecs.umich.edu 4937368Sgblack@eecs.umich.edu vsubDCode = ''' 4947368Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 4957368Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 4967368Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 4977368Sgblack@eecs.umich.edu cDest.fp = cOp1.fp - cOp2.fp; 4987368Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 4997368Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5007368Sgblack@eecs.umich.edu ''' 5017375Sgblack@eecs.umich.edu vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp", 5027368Sgblack@eecs.umich.edu { "code": vsubDCode, 5037368Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5047375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vsubDIop); 5057375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop); 5067368Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsubDIop); 5077369Sgblack@eecs.umich.edu 5087369Sgblack@eecs.umich.edu vdivSCode = ''' 5097369Sgblack@eecs.umich.edu FpDest = FpOp1 / FpOp2; 5107369Sgblack@eecs.umich.edu ''' 5117375Sgblack@eecs.umich.edu vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp", 5127369Sgblack@eecs.umich.edu { "code": vdivSCode, 5137369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5147375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivSIop); 5157375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop); 5167369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivSIop); 5177369Sgblack@eecs.umich.edu 5187369Sgblack@eecs.umich.edu vdivDCode = ''' 5197369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5207369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5217369Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5227369Sgblack@eecs.umich.edu cDest.fp = cOp1.fp / cOp2.fp; 5237369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5247369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5257369Sgblack@eecs.umich.edu ''' 5267375Sgblack@eecs.umich.edu vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp", 5277369Sgblack@eecs.umich.edu { "code": vdivDCode, 5287369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5297375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vdivDIop); 5307375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop); 5317369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vdivDIop); 5327369Sgblack@eecs.umich.edu 5337369Sgblack@eecs.umich.edu vsqrtSCode = ''' 5347369Sgblack@eecs.umich.edu FpDest = sqrtf(FpOp1); 5357369Sgblack@eecs.umich.edu if (FpOp1 < 0) { 5367369Sgblack@eecs.umich.edu FpDest = NAN; 5377369Sgblack@eecs.umich.edu } 5387369Sgblack@eecs.umich.edu ''' 5397375Sgblack@eecs.umich.edu vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp", 5407369Sgblack@eecs.umich.edu { "code": vsqrtSCode, 5417369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5427375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtSIop); 5437375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop); 5447369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtSIop); 5457369Sgblack@eecs.umich.edu 5467369Sgblack@eecs.umich.edu vsqrtDCode = ''' 5477369Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 5487369Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5497369Sgblack@eecs.umich.edu cDest.fp = sqrt(cOp1.fp); 5507369Sgblack@eecs.umich.edu if (cOp1.fp < 0) { 5517369Sgblack@eecs.umich.edu cDest.fp = NAN; 5527369Sgblack@eecs.umich.edu } 5537369Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5547369Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5557369Sgblack@eecs.umich.edu ''' 5567375Sgblack@eecs.umich.edu vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp", 5577369Sgblack@eecs.umich.edu { "code": vsqrtDCode, 5587369Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5597375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vsqrtDIop); 5607375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop); 5617369Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vsqrtDIop); 5627370Sgblack@eecs.umich.edu 5637370Sgblack@eecs.umich.edu vmlaSCode = ''' 5647370Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 5657370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 5667370Sgblack@eecs.umich.edu mid = NAN; 5677370Sgblack@eecs.umich.edu } 5687370Sgblack@eecs.umich.edu FpDest = FpDest + mid; 5697370Sgblack@eecs.umich.edu ''' 5707375Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp", 5717370Sgblack@eecs.umich.edu { "code": vmlaSCode, 5727370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5737375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop); 5747375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop); 5757370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 5767370Sgblack@eecs.umich.edu 5777370Sgblack@eecs.umich.edu vmlaDCode = ''' 5787370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 5797370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 5807370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 5817370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 5827370Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 5837370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 5847370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 5857370Sgblack@eecs.umich.edu mid = NAN; 5867370Sgblack@eecs.umich.edu } 5877370Sgblack@eecs.umich.edu cDest.fp = cDest.fp + mid; 5887370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 5897370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 5907370Sgblack@eecs.umich.edu ''' 5917375Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp", 5927370Sgblack@eecs.umich.edu { "code": vmlaDCode, 5937370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 5947375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop); 5957375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop); 5967370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 5977370Sgblack@eecs.umich.edu 5987370Sgblack@eecs.umich.edu vmlsSCode = ''' 5997370Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 6007370Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6017370Sgblack@eecs.umich.edu mid = NAN; 6027370Sgblack@eecs.umich.edu } 6037370Sgblack@eecs.umich.edu FpDest = FpDest - mid; 6047370Sgblack@eecs.umich.edu ''' 6057375Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 6067370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6077370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6087375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 6097375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); 6107370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 6117370Sgblack@eecs.umich.edu 6127370Sgblack@eecs.umich.edu vmlsDCode = ''' 6137370Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6147370Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6157370Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6167370Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6177370Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 6187370Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6197370Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6207370Sgblack@eecs.umich.edu mid = NAN; 6217370Sgblack@eecs.umich.edu } 6227370Sgblack@eecs.umich.edu cDest.fp = cDest.fp - mid; 6237370Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6247370Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6257370Sgblack@eecs.umich.edu ''' 6267375Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 6277370Sgblack@eecs.umich.edu { "code": vmlsDCode, 6287370Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6297375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop); 6307375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop); 6317370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 6327371Sgblack@eecs.umich.edu 6337371Sgblack@eecs.umich.edu vnmlaSCode = ''' 6347371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 6357371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6367371Sgblack@eecs.umich.edu mid = NAN; 6377371Sgblack@eecs.umich.edu } 6387371Sgblack@eecs.umich.edu FpDest = -FpDest - mid; 6397371Sgblack@eecs.umich.edu ''' 6407375Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 6417371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 6427371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6437375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 6447375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); 6457371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 6467371Sgblack@eecs.umich.edu 6477371Sgblack@eecs.umich.edu vnmlaDCode = ''' 6487371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6497371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6507371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6517371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6527371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 6537371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6547371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6557371Sgblack@eecs.umich.edu mid = NAN; 6567371Sgblack@eecs.umich.edu } 6577371Sgblack@eecs.umich.edu cDest.fp = -cDest.fp - mid; 6587371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6597371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6607371Sgblack@eecs.umich.edu ''' 6617375Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 6627371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 6637371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6647375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop); 6657375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop); 6667371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 6677371Sgblack@eecs.umich.edu 6687371Sgblack@eecs.umich.edu vnmlsSCode = ''' 6697371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 6707371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 6717371Sgblack@eecs.umich.edu mid = NAN; 6727371Sgblack@eecs.umich.edu } 6737371Sgblack@eecs.umich.edu FpDest = -FpDest + mid; 6747371Sgblack@eecs.umich.edu ''' 6757375Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 6767371Sgblack@eecs.umich.edu { "code": vnmlsSCode, 6777371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6787375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 6797375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); 6807371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 6817371Sgblack@eecs.umich.edu 6827371Sgblack@eecs.umich.edu vnmlsDCode = ''' 6837371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 6847371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 6857371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 6867371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 6877371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 6887371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 6897371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 6907371Sgblack@eecs.umich.edu mid = NAN; 6917371Sgblack@eecs.umich.edu } 6927371Sgblack@eecs.umich.edu cDest.fp = -cDest.fp + mid; 6937371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 6947371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 6957371Sgblack@eecs.umich.edu ''' 6967375Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 6977371Sgblack@eecs.umich.edu { "code": vnmlsDCode, 6987371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6997375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop); 7007375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop); 7017371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 7027371Sgblack@eecs.umich.edu 7037371Sgblack@eecs.umich.edu vnmulSCode = ''' 7047371Sgblack@eecs.umich.edu float mid = FpOp1 * FpOp2; 7057371Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 7067371Sgblack@eecs.umich.edu mid = NAN; 7077371Sgblack@eecs.umich.edu } 7087371Sgblack@eecs.umich.edu FpDest = -mid; 7097371Sgblack@eecs.umich.edu ''' 7107375Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp", 7117371Sgblack@eecs.umich.edu { "code": vnmulSCode, 7127371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7137375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop); 7147375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop); 7157371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 7167371Sgblack@eecs.umich.edu 7177371Sgblack@eecs.umich.edu vnmulDCode = ''' 7187371Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 7197371Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7207371Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 7217371Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 7227371Sgblack@eecs.umich.edu double mid = cOp1.fp * cOp2.fp; 7237371Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 7247371Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 7257371Sgblack@eecs.umich.edu mid = NAN; 7267371Sgblack@eecs.umich.edu } 7277371Sgblack@eecs.umich.edu cDest.fp = -mid; 7287371Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7297371Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7307371Sgblack@eecs.umich.edu ''' 7317375Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp", 7327371Sgblack@eecs.umich.edu { "code": vnmulDCode, 7337371Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7347375Sgblack@eecs.umich.edu header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop); 7357375Sgblack@eecs.umich.edu decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop); 7367371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 7377373Sgblack@eecs.umich.edu 7387373Sgblack@eecs.umich.edu vcvtUIntFpSCode = ''' 7397373Sgblack@eecs.umich.edu FpDest = FpOp1.uw; 7407373Sgblack@eecs.umich.edu ''' 7417375Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp", 7427373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 7437373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7447375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop); 7457375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop); 7467373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 7477373Sgblack@eecs.umich.edu 7487373Sgblack@eecs.umich.edu vcvtUIntFpDCode = ''' 7497373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 7507373Sgblack@eecs.umich.edu cDest.fp = (uint64_t)FpOp1P0.uw; 7517373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7527373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7537373Sgblack@eecs.umich.edu ''' 7547375Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp", 7557373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 7567373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7577375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop); 7587375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop); 7597373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 7607373Sgblack@eecs.umich.edu 7617373Sgblack@eecs.umich.edu vcvtSIntFpSCode = ''' 7627373Sgblack@eecs.umich.edu FpDest = FpOp1.sw; 7637373Sgblack@eecs.umich.edu ''' 7647375Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp", 7657373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 7667373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7677375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop); 7687375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop); 7697373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 7707373Sgblack@eecs.umich.edu 7717373Sgblack@eecs.umich.edu vcvtSIntFpDCode = ''' 7727373Sgblack@eecs.umich.edu IntDoubleUnion cDest; 7737373Sgblack@eecs.umich.edu cDest.fp = FpOp1P0.sw; 7747373Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 7757373Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 7767373Sgblack@eecs.umich.edu ''' 7777375Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp", 7787373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 7797373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7807375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop); 7817375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop); 7827373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 7837373Sgblack@eecs.umich.edu 7847373Sgblack@eecs.umich.edu vcvtFpUIntSCode = ''' 7857373Sgblack@eecs.umich.edu FpDest.uw = FpOp1; 7867373Sgblack@eecs.umich.edu ''' 7877375Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp", 7887373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 7897373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7907375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop); 7917375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop); 7927373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 7937373Sgblack@eecs.umich.edu 7947373Sgblack@eecs.umich.edu vcvtFpUIntDCode = ''' 7957373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 7967373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 7977373Sgblack@eecs.umich.edu uint64_t result = cOp1.fp; 7987373Sgblack@eecs.umich.edu FpDestP0.uw = result; 7997373Sgblack@eecs.umich.edu ''' 8007375Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp", 8017373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 8027373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8037375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop); 8047375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop); 8057373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 8067373Sgblack@eecs.umich.edu 8077373Sgblack@eecs.umich.edu vcvtFpSIntSCode = ''' 8087373Sgblack@eecs.umich.edu FpDest.sw = FpOp1; 8097373Sgblack@eecs.umich.edu ''' 8107375Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp", 8117373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 8127373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8137375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop); 8147375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop); 8157373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 8167373Sgblack@eecs.umich.edu 8177373Sgblack@eecs.umich.edu vcvtFpSIntDCode = ''' 8187373Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 8197373Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8207373Sgblack@eecs.umich.edu int64_t result = cOp1.fp; 8217373Sgblack@eecs.umich.edu FpDestP0.uw = result; 8227373Sgblack@eecs.umich.edu ''' 8237375Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp", 8247373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 8257373Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8267375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop); 8277375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop); 8287373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 8297374Sgblack@eecs.umich.edu 8307374Sgblack@eecs.umich.edu vcvtFpSFpDCode = ''' 8317374Sgblack@eecs.umich.edu IntDoubleUnion cDest; 8327374Sgblack@eecs.umich.edu cDest.fp = FpOp1; 8337374Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 8347374Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 8357374Sgblack@eecs.umich.edu ''' 8367375Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp", 8377374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 8387374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8397375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop); 8407375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop); 8417374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 8427374Sgblack@eecs.umich.edu 8437374Sgblack@eecs.umich.edu vcvtFpDFpSCode = ''' 8447374Sgblack@eecs.umich.edu IntDoubleUnion cOp1; 8457374Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8467374Sgblack@eecs.umich.edu FpDest = cOp1.fp; 8477374Sgblack@eecs.umich.edu ''' 8487375Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 8497374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 8507374Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8517375Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 8527375Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 8537374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 8547377Sgblack@eecs.umich.edu 8557377Sgblack@eecs.umich.edu vcmpSCode = ''' 8567377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8577377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 8587377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 8597377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 8607377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 8617377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 8627377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 8637377Sgblack@eecs.umich.edu } else { 8647377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 8657377Sgblack@eecs.umich.edu } 8667377Sgblack@eecs.umich.edu Fpscr = fpscr; 8677377Sgblack@eecs.umich.edu ''' 8687377Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 8697377Sgblack@eecs.umich.edu { "code": vcmpSCode, 8707377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8717377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpSIop); 8727377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop); 8737377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 8747377Sgblack@eecs.umich.edu 8757377Sgblack@eecs.umich.edu vcmpDCode = ''' 8767377Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cDest; 8777377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 8787377Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 8797377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 8807377Sgblack@eecs.umich.edu if (cDest.fp == cOp1.fp) { 8817377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 8827377Sgblack@eecs.umich.edu } else if (cDest.fp < cOp1.fp) { 8837377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 8847377Sgblack@eecs.umich.edu } else if (cDest.fp > cOp1.fp) { 8857377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 8867377Sgblack@eecs.umich.edu } else { 8877377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 8887377Sgblack@eecs.umich.edu } 8897377Sgblack@eecs.umich.edu Fpscr = fpscr; 8907377Sgblack@eecs.umich.edu ''' 8917377Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 8927377Sgblack@eecs.umich.edu { "code": vcmpDCode, 8937377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 8947377Sgblack@eecs.umich.edu header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 8957377Sgblack@eecs.umich.edu decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 8967377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 8977377Sgblack@eecs.umich.edu 8987377Sgblack@eecs.umich.edu vcmpZeroSCode = ''' 8997377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9007377Sgblack@eecs.umich.edu if (FpDest == imm) { 9017377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 9027377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 9037377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 9047377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 9057377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 9067377Sgblack@eecs.umich.edu } else { 9077377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 9087377Sgblack@eecs.umich.edu } 9097377Sgblack@eecs.umich.edu Fpscr = fpscr; 9107377Sgblack@eecs.umich.edu ''' 9117377Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 9127377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 9137377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9147377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 9157377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 9167377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 9177377Sgblack@eecs.umich.edu 9187377Sgblack@eecs.umich.edu vcmpZeroDCode = ''' 9197377Sgblack@eecs.umich.edu IntDoubleUnion cDest; 9207377Sgblack@eecs.umich.edu cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 9217377Sgblack@eecs.umich.edu FPSCR fpscr = Fpscr; 9227377Sgblack@eecs.umich.edu if (cDest.fp == imm) { 9237377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 9247377Sgblack@eecs.umich.edu } else if (cDest.fp < imm) { 9257377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 9267377Sgblack@eecs.umich.edu } else if (cDest.fp > imm) { 9277377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 9287377Sgblack@eecs.umich.edu } else { 9297377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 9307377Sgblack@eecs.umich.edu } 9317377Sgblack@eecs.umich.edu Fpscr = fpscr; 9327377Sgblack@eecs.umich.edu ''' 9337377Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 9347377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 9357377Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 9367377Sgblack@eecs.umich.edu header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 9377377Sgblack@eecs.umich.edu decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 9387377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 9397322Sgblack@eecs.umich.edu}}; 940