fp.isa revision 7367
1837SN/A// -*- mode:c++ -*- 21762SN/A 3837SN/A// Copyright (c) 2010 ARM Limited 4837SN/A// All rights reserved 5837SN/A// 6837SN/A// The license below extends only to copyright in the software and shall 7837SN/A// not be construed as granting a license to any other intellectual 8837SN/A// property including but not limited to intellectual property relating 9837SN/A// to a hardware implementation of the functionality of the software 10837SN/A// licensed hereunder. You may use the software subject to the license 11837SN/A// terms below provided that you ensure that this notice is replicated 12837SN/A// unmodified and in its entirety in all distributions of the software, 13837SN/A// modified or unmodified, in source code or in binary form. 14837SN/A// 15837SN/A// Redistribution and use in source and binary forms, with or without 16837SN/A// modification, are permitted provided that the following conditions are 17837SN/A// met: redistributions of source code must retain the above copyright 18837SN/A// notice, this list of conditions and the following disclaimer; 19837SN/A// redistributions in binary form must reproduce the above copyright 20837SN/A// notice, this list of conditions and the following disclaimer in the 21837SN/A// documentation and/or other materials provided with the distribution; 22837SN/A// neither the name of the copyright holders nor the names of its 23837SN/A// contributors may be used to endorse or promote products derived from 24837SN/A// this software without specific prior written permission. 25837SN/A// 26837SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272665SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282760SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292760SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30837SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31837SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 321730SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33837SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34837SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35837SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3611263Sandreas.sandberg@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3711263Sandreas.sandberg@arm.com// 3811263Sandreas.sandberg@arm.com// Authors: Gabe Black 39837SN/A 4010469SN/Alet {{ 41837SN/A 42837SN/A header_output = "" 435882SN/A decoder_output = "" 44837SN/A exec_output = "" 456216SN/A 466658SN/A vmsrIop = InstObjParams("vmsr", "Vmsr", "RegRegOp", 478232SN/A { "code": "MiscDest = Op1;", 4811263Sandreas.sandberg@arm.com "predicate_test": predicateTest }, []) 492566SN/A header_output += RegRegOpDeclare.subst(vmsrIop); 503348SN/A decoder_output += RegRegOpConstructor.subst(vmsrIop); 514762SN/A exec_output += PredOpExecute.subst(vmsrIop); 522566SN/A 53854SN/A vmrsIop = InstObjParams("vmrs", "Vmrs", "RegRegOp", 548737SN/A { "code": "Dest = MiscOp1;", 558737SN/A "predicate_test": predicateTest }, []) 5610469SN/A header_output += RegRegOpDeclare.subst(vmrsIop); 578737SN/A decoder_output += RegRegOpConstructor.subst(vmrsIop); 588737SN/A exec_output += PredOpExecute.subst(vmrsIop); 598737SN/A 608737SN/A vmovImmSCode = ''' 61854SN/A FpDest.uw = bits(imm, 31, 0); 62854SN/A ''' 63854SN/A vmovImmSIop = InstObjParams("vmov", "VmovImmS", "RegImmOp", 64854SN/A { "code": vmovImmSCode, 65854SN/A "predicate_test": predicateTest }, []) 66854SN/A header_output += RegImmOpDeclare.subst(vmovImmSIop); 67854SN/A decoder_output += RegImmOpConstructor.subst(vmovImmSIop); 68854SN/A exec_output += PredOpExecute.subst(vmovImmSIop); 69854SN/A 70854SN/A vmovImmDCode = ''' 71854SN/A FpDestP0.uw = bits(imm, 31, 0); 72854SN/A FpDestP1.uw = bits(imm, 63, 32); 73854SN/A ''' 74854SN/A vmovImmDIop = InstObjParams("vmov", "VmovImmD", "RegImmOp", 75854SN/A { "code": vmovImmDCode, 76854SN/A "predicate_test": predicateTest }, []) 77854SN/A header_output += RegImmOpDeclare.subst(vmovImmDIop); 78854SN/A decoder_output += RegImmOpConstructor.subst(vmovImmDIop); 79854SN/A exec_output += PredOpExecute.subst(vmovImmDIop); 80854SN/A 81854SN/A vmovImmQCode = ''' 82854SN/A FpDestP0.uw = bits(imm, 31, 0); 83854SN/A FpDestP1.uw = bits(imm, 63, 32); 84854SN/A FpDestP2.uw = bits(imm, 31, 0); 85854SN/A FpDestP3.uw = bits(imm, 63, 32); 86854SN/A ''' 87854SN/A vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "RegImmOp", 88854SN/A { "code": vmovImmQCode, 89854SN/A "predicate_test": predicateTest }, []) 90854SN/A header_output += RegImmOpDeclare.subst(vmovImmQIop); 91837SN/A decoder_output += RegImmOpConstructor.subst(vmovImmQIop); 921114SN/A exec_output += PredOpExecute.subst(vmovImmQIop); 932107SN/A 94927SN/A vmovRegSCode = ''' 95837SN/A FpDest.uw = FpOp1.uw; 96837SN/A ''' 97879SN/A vmovRegSIop = InstObjParams("vmov", "VmovRegS", "RegRegOp", 98837SN/A { "code": vmovRegSCode, 991149SN/A "predicate_test": predicateTest }, []) 1009339SN/A header_output += RegRegOpDeclare.subst(vmovRegSIop); 1011149SN/A decoder_output += RegRegOpConstructor.subst(vmovRegSIop); 102915SN/A exec_output += PredOpExecute.subst(vmovRegSIop); 1034093SN/A 1044093SN/A vmovRegDCode = ''' 105854SN/A FpDestP0.uw = FpOp1P0.uw; 1064093SN/A FpDestP1.uw = FpOp1P1.uw; 107854SN/A ''' 1084093SN/A vmovRegDIop = InstObjParams("vmov", "VmovRegD", "RegRegOp", 1094093SN/A { "code": vmovRegDCode, 1104093SN/A "predicate_test": predicateTest }, []) 1114093SN/A header_output += RegRegOpDeclare.subst(vmovRegDIop); 1124093SN/A decoder_output += RegRegOpConstructor.subst(vmovRegDIop); 1134093SN/A exec_output += PredOpExecute.subst(vmovRegDIop); 11412087Sspwilson2@wisc.edu 11512087Sspwilson2@wisc.edu vmovRegQCode = ''' 11612087Sspwilson2@wisc.edu FpDestP0.uw = FpOp1P0.uw; 11712087Sspwilson2@wisc.edu FpDestP1.uw = FpOp1P1.uw; 1181149SN/A FpDestP2.uw = FpOp1P2.uw; 1191149SN/A FpDestP3.uw = FpOp1P3.uw; 12012087Sspwilson2@wisc.edu ''' 12112087Sspwilson2@wisc.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "RegRegOp", 12212087Sspwilson2@wisc.edu { "code": vmovRegQCode, 12312087Sspwilson2@wisc.edu "predicate_test": predicateTest }, []) 12412087Sspwilson2@wisc.edu header_output += RegRegOpDeclare.subst(vmovRegQIop); 12512087Sspwilson2@wisc.edu decoder_output += RegRegOpConstructor.subst(vmovRegQIop); 1264093SN/A exec_output += PredOpExecute.subst(vmovRegQIop); 1271843SN/A 1284093SN/A vmovCoreRegBCode = ''' 129995SN/A FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 130837SN/A ''' 131854SN/A vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "RegRegImmOp", 132854SN/A { "code": vmovCoreRegBCode, 1334981SN/A "predicate_test": predicateTest }, []) 1344981SN/A header_output += RegRegImmOpDeclare.subst(vmovCoreRegBIop); 135837SN/A decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegBIop); 1364762SN/A exec_output += PredOpExecute.subst(vmovCoreRegBIop); 1371909SN/A 1381909SN/A vmovCoreRegHCode = ''' 1391909SN/A FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 1401909SN/A ''' 1411909SN/A vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "RegRegImmOp", 142837SN/A { "code": vmovCoreRegHCode, 143837SN/A "predicate_test": predicateTest }, []) 144879SN/A header_output += RegRegImmOpDeclare.subst(vmovCoreRegHIop); 1459086SN/A decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegHIop); 1469086SN/A exec_output += PredOpExecute.subst(vmovCoreRegHIop); 1479086SN/A 148837SN/A vmovCoreRegWCode = ''' 149855SN/A FpDest.uw = Op1.uw; 150855SN/A ''' 151855SN/A vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "RegRegOp", 1522846SN/A { "code": vmovCoreRegWCode, 1533349SN/A "predicate_test": predicateTest }, []) 154837SN/A header_output += RegRegOpDeclare.subst(vmovCoreRegWIop); 1552846SN/A decoder_output += RegRegOpConstructor.subst(vmovCoreRegWIop); 156837SN/A exec_output += PredOpExecute.subst(vmovCoreRegWIop); 1579807SN/A 158837SN/A vmovRegCoreUBCode = ''' 159897SN/A Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 160897SN/A ''' 161897SN/A vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "RegRegImmOp", 1621027SN/A { "code": vmovRegCoreUBCode, 1631027SN/A "predicate_test": predicateTest }, []) 1641027SN/A header_output += RegRegImmOpDeclare.subst(vmovRegCoreUBIop); 165917SN/A decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUBIop); 166917SN/A exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 167927SN/A 168917SN/A vmovRegCoreUHCode = ''' 169927SN/A Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 170897SN/A ''' 171897SN/A vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "RegRegImmOp", 1724875SN/A { "code": vmovRegCoreUHCode, 1732846SN/A "predicate_test": predicateTest }, []) 174837SN/A header_output += RegRegImmOpDeclare.subst(vmovRegCoreUHIop); 175837SN/A decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUHIop); 17613784Sgabeblack@google.com exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 17713784Sgabeblack@google.com 1784981SN/A vmovRegCoreSBCode = ''' 17913784Sgabeblack@google.com Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 18013784Sgabeblack@google.com ''' 18113784Sgabeblack@google.com vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "RegRegImmOp", 1824981SN/A { "code": vmovRegCoreSBCode, 1834981SN/A "predicate_test": predicateTest }, []) 184855SN/A header_output += RegRegImmOpDeclare.subst(vmovRegCoreSBIop); 185855SN/A decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSBIop); 186855SN/A exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 187855SN/A 1882566SN/A vmovRegCoreSHCode = ''' 1893349SN/A Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 190837SN/A ''' 191927SN/A vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "RegRegImmOp", 192917SN/A { "code": vmovRegCoreSHCode, 193855SN/A "predicate_test": predicateTest }, []) 1942641SN/A header_output += RegRegImmOpDeclare.subst(vmovRegCoreSHIop); 1952566SN/A decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSHIop); 1962641SN/A exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 197837SN/A 198855SN/A vmovRegCoreWCode = ''' 1991027SN/A Dest = FpOp1.uw; 2001027SN/A ''' 201854SN/A vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "RegRegOp", 202837SN/A { "code": vmovRegCoreWCode, 203854SN/A "predicate_test": predicateTest }, []) 2042846SN/A header_output += RegRegOpDeclare.subst(vmovRegCoreWIop); 205854SN/A decoder_output += RegRegOpConstructor.subst(vmovRegCoreWIop); 206854SN/A exec_output += PredOpExecute.subst(vmovRegCoreWIop); 207854SN/A 208855SN/A vmov2Reg2CoreCode = ''' 20913342Sgabeblack@google.com FpDestP0.uw = Op1.uw; 2104870SN/A FpDestP1.uw = Op2.uw; 2112566SN/A ''' 212854SN/A vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "RegRegRegOp", 213854SN/A { "code": vmov2Reg2CoreCode, 214837SN/A "predicate_test": predicateTest }, []) 2152641SN/A header_output += RegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 2162630SN/A decoder_output += RegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 2172566SN/A exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 2182566SN/A 2192566SN/A vmov2Core2RegCode = ''' 2202566SN/A Dest.uw = FpOp2P0.uw; 2212566SN/A Op1.uw = FpOp2P1.uw; 2222566SN/A ''' 2232566SN/A vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp", 2242566SN/A { "code": vmov2Core2RegCode, 2252566SN/A "predicate_test": predicateTest }, []) 2262566SN/A header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop); 2272566SN/A decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop); 2282566SN/A exec_output += PredOpExecute.subst(vmov2Core2RegIop); 2292566SN/A 2302566SN/A vmulSCode = ''' 2312566SN/A FpDest = FpOp1 * FpOp2; 2322566SN/A if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 2332566SN/A FpDest = NAN; 2342566SN/A } 2352566SN/A ''' 2362566SN/A vmulSIop = InstObjParams("vmuls", "VmulS", "RegRegRegOp", 2372566SN/A { "code": vmulSCode, 2382566SN/A "predicate_test": predicateTest }, []) 2392566SN/A header_output += RegRegRegOpDeclare.subst(vmulSIop); 2402566SN/A decoder_output += RegRegRegOpConstructor.subst(vmulSIop); 2412566SN/A exec_output += PredOpExecute.subst(vmulSIop); 2422566SN/A 2432566SN/A vmulDCode = ''' 2442566SN/A IntDoubleUnion cOp1, cOp2, cDest; 2452566SN/A cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 2462566SN/A cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 2472566SN/A cDest.fp = cOp1.fp * cOp2.fp; 2482566SN/A if ((isinf(cOp1.fp) && cOp2.fp == 0) || 2492566SN/A (isinf(cOp2.fp) && cOp1.fp == 0)) { 2502566SN/A cDest.fp = NAN; 2512566SN/A } 2522566SN/A FpDestP0.uw = cDest.bits; 2532566SN/A FpDestP1.uw = cDest.bits >> 32; 2542566SN/A ''' 2552566SN/A vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp", 2562566SN/A { "code": vmulDCode, 2572566SN/A "predicate_test": predicateTest }, []) 2582566SN/A header_output += RegRegRegOpDeclare.subst(vmulDIop); 2592566SN/A decoder_output += RegRegRegOpConstructor.subst(vmulDIop); 2602566SN/A exec_output += PredOpExecute.subst(vmulDIop); 2612566SN/A 2622566SN/A vnegSCode = ''' 2632566SN/A FpDest = -FpOp1; 2642566SN/A ''' 2652566SN/A vnegSIop = InstObjParams("vnegs", "VnegS", "RegRegOp", 2662566SN/A { "code": vnegSCode, 2672566SN/A "predicate_test": predicateTest }, []) 2682566SN/A header_output += RegRegOpDeclare.subst(vnegSIop); 2692566SN/A decoder_output += RegRegOpConstructor.subst(vnegSIop); 2702566SN/A exec_output += PredOpExecute.subst(vnegSIop); 2712566SN/A 2722566SN/A vnegDCode = ''' 2732566SN/A IntDoubleUnion cOp1, cDest; 2742566SN/A cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 2752566SN/A cDest.fp = -cOp1.fp; 2762566SN/A FpDestP0.uw = cDest.bits; 2772566SN/A FpDestP1.uw = cDest.bits >> 32; 2782566SN/A ''' 2792566SN/A vnegDIop = InstObjParams("vnegd", "VnegD", "RegRegOp", 2802566SN/A { "code": vnegDCode, 2812566SN/A "predicate_test": predicateTest }, []) 2822566SN/A header_output += RegRegOpDeclare.subst(vnegDIop); 2832566SN/A decoder_output += RegRegOpConstructor.subst(vnegDIop); 2842566SN/A exec_output += PredOpExecute.subst(vnegDIop); 2852566SN/A 2862566SN/A vabsSCode = ''' 2872566SN/A FpDest = fabsf(FpOp1); 2882566SN/A ''' 2892566SN/A vabsSIop = InstObjParams("vabss", "VabsS", "RegRegOp", 2902566SN/A { "code": vabsSCode, 2912566SN/A "predicate_test": predicateTest }, []) 2922566SN/A header_output += RegRegOpDeclare.subst(vabsSIop); 2932566SN/A decoder_output += RegRegOpConstructor.subst(vabsSIop); 2942566SN/A exec_output += PredOpExecute.subst(vabsSIop); 2952566SN/A 2962566SN/A vabsDCode = ''' 2972566SN/A IntDoubleUnion cOp1, cDest; 2982566SN/A cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 2992566SN/A cDest.fp = fabs(cOp1.fp); 3002566SN/A FpDestP0.uw = cDest.bits; 3012566SN/A FpDestP1.uw = cDest.bits >> 32; 3022566SN/A ''' 3032566SN/A vabsDIop = InstObjParams("vabsd", "VabsD", "RegRegOp", 3042566SN/A { "code": vabsDCode, 3052566SN/A "predicate_test": predicateTest }, []) 3062566SN/A header_output += RegRegOpDeclare.subst(vabsDIop); 3072566SN/A decoder_output += RegRegOpConstructor.subst(vabsDIop); 3082566SN/A exec_output += PredOpExecute.subst(vabsDIop); 3092566SN/A 3102566SN/A vaddSCode = ''' 3112566SN/A FpDest = FpOp1 + FpOp2; 312837SN/A ''' 3132566SN/A vaddSIop = InstObjParams("vadds", "VaddS", "RegRegRegOp", 3142566SN/A { "code": vaddSCode, 3152566SN/A "predicate_test": predicateTest }, []) 316837SN/A header_output += RegRegRegOpDeclare.subst(vaddSIop); 3172566SN/A decoder_output += RegRegRegOpConstructor.subst(vaddSIop); 3182566SN/A exec_output += PredOpExecute.subst(vaddSIop); 3192566SN/A 320837SN/A vaddDCode = ''' 3212566SN/A IntDoubleUnion cOp1, cOp2, cDest; 3222566SN/A cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 3232566SN/A cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 3242566SN/A cDest.fp = cOp1.fp + cOp2.fp; 3252566SN/A FpDestP0.uw = cDest.bits; 3262566SN/A FpDestP1.uw = cDest.bits >> 32; 3272566SN/A ''' 3282566SN/A vaddDIop = InstObjParams("vaddd", "VaddD", "RegRegRegOp", 3292566SN/A { "code": vaddDCode, 3302566SN/A "predicate_test": predicateTest }, []) 3312566SN/A header_output += RegRegRegOpDeclare.subst(vaddDIop); 332837SN/A decoder_output += RegRegRegOpConstructor.subst(vaddDIop); 333837SN/A exec_output += PredOpExecute.subst(vaddDIop); 3342566SN/A}}; 3352566SN/A