fp.isa revision 7364
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407322Sgblack@eecs.umich.edulet {{ 417322Sgblack@eecs.umich.edu 427322Sgblack@eecs.umich.edu header_output = "" 437322Sgblack@eecs.umich.edu decoder_output = "" 447322Sgblack@eecs.umich.edu exec_output = "" 457322Sgblack@eecs.umich.edu 467322Sgblack@eecs.umich.edu vmsrIop = InstObjParams("vmsr", "Vmsr", "RegRegOp", 477322Sgblack@eecs.umich.edu { "code": "MiscDest = Op1;", 487322Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 497322Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(vmsrIop); 507322Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmsrIop); 517322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 527324Sgblack@eecs.umich.edu 537324Sgblack@eecs.umich.edu vmrsIop = InstObjParams("vmrs", "Vmrs", "RegRegOp", 547324Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 557324Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 567324Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(vmrsIop); 577324Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmrsIop); 587324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 597333Sgblack@eecs.umich.edu 607333Sgblack@eecs.umich.edu vmovImmSCode = ''' 617333Sgblack@eecs.umich.edu FpDest.uw = bits(imm, 31, 0); 627333Sgblack@eecs.umich.edu ''' 637333Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "RegImmOp", 647333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 657333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 667333Sgblack@eecs.umich.edu header_output += RegImmOpDeclare.subst(vmovImmSIop); 677333Sgblack@eecs.umich.edu decoder_output += RegImmOpConstructor.subst(vmovImmSIop); 687333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 697333Sgblack@eecs.umich.edu 707333Sgblack@eecs.umich.edu vmovImmDCode = ''' 717333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 727333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 737333Sgblack@eecs.umich.edu ''' 747333Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "RegImmOp", 757333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 767333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 777333Sgblack@eecs.umich.edu header_output += RegImmOpDeclare.subst(vmovImmDIop); 787333Sgblack@eecs.umich.edu decoder_output += RegImmOpConstructor.subst(vmovImmDIop); 797333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 807333Sgblack@eecs.umich.edu 817333Sgblack@eecs.umich.edu vmovImmQCode = ''' 827333Sgblack@eecs.umich.edu FpDestP0.uw = bits(imm, 31, 0); 837333Sgblack@eecs.umich.edu FpDestP1.uw = bits(imm, 63, 32); 847333Sgblack@eecs.umich.edu FpDestP2.uw = bits(imm, 31, 0); 857333Sgblack@eecs.umich.edu FpDestP3.uw = bits(imm, 63, 32); 867333Sgblack@eecs.umich.edu ''' 877333Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "RegImmOp", 887333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 897333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 907333Sgblack@eecs.umich.edu header_output += RegImmOpDeclare.subst(vmovImmQIop); 917333Sgblack@eecs.umich.edu decoder_output += RegImmOpConstructor.subst(vmovImmQIop); 927333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 937333Sgblack@eecs.umich.edu 947333Sgblack@eecs.umich.edu vmovRegSCode = ''' 957333Sgblack@eecs.umich.edu FpDest.uw = FpOp1.uw; 967333Sgblack@eecs.umich.edu ''' 977333Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "RegRegOp", 987333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 997333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1007333Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(vmovRegSIop); 1017333Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmovRegSIop); 1027333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 1037333Sgblack@eecs.umich.edu 1047333Sgblack@eecs.umich.edu vmovRegDCode = ''' 1057333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 1067333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 1077333Sgblack@eecs.umich.edu ''' 1087333Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "RegRegOp", 1097333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 1107333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1117333Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(vmovRegDIop); 1127333Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmovRegDIop); 1137333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 1147333Sgblack@eecs.umich.edu 1157333Sgblack@eecs.umich.edu vmovRegQCode = ''' 1167333Sgblack@eecs.umich.edu FpDestP0.uw = FpOp1P0.uw; 1177333Sgblack@eecs.umich.edu FpDestP1.uw = FpOp1P1.uw; 1187333Sgblack@eecs.umich.edu FpDestP2.uw = FpOp1P2.uw; 1197333Sgblack@eecs.umich.edu FpDestP3.uw = FpOp1P3.uw; 1207333Sgblack@eecs.umich.edu ''' 1217333Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "RegRegOp", 1227333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 1237333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1247333Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(vmovRegQIop); 1257333Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmovRegQIop); 1267333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 1277333Sgblack@eecs.umich.edu 1287333Sgblack@eecs.umich.edu vmovCoreRegBCode = ''' 1297333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 1307333Sgblack@eecs.umich.edu ''' 1317333Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "RegRegImmOp", 1327333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 1337333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1347333Sgblack@eecs.umich.edu header_output += RegRegImmOpDeclare.subst(vmovCoreRegBIop); 1357333Sgblack@eecs.umich.edu decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegBIop); 1367333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 1377333Sgblack@eecs.umich.edu 1387333Sgblack@eecs.umich.edu vmovCoreRegHCode = ''' 1397333Sgblack@eecs.umich.edu FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 1407333Sgblack@eecs.umich.edu ''' 1417333Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "RegRegImmOp", 1427333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 1437333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1447333Sgblack@eecs.umich.edu header_output += RegRegImmOpDeclare.subst(vmovCoreRegHIop); 1457333Sgblack@eecs.umich.edu decoder_output += RegRegImmOpConstructor.subst(vmovCoreRegHIop); 1467333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 1477333Sgblack@eecs.umich.edu 1487333Sgblack@eecs.umich.edu vmovCoreRegWCode = ''' 1497333Sgblack@eecs.umich.edu FpDest.uw = Op1.uw; 1507333Sgblack@eecs.umich.edu ''' 1517333Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "RegRegOp", 1527333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 1537333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1547333Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(vmovCoreRegWIop); 1557333Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmovCoreRegWIop); 1567333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 1577333Sgblack@eecs.umich.edu 1587333Sgblack@eecs.umich.edu vmovRegCoreUBCode = ''' 1597333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 1607333Sgblack@eecs.umich.edu ''' 1617333Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "RegRegImmOp", 1627333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 1637333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1647333Sgblack@eecs.umich.edu header_output += RegRegImmOpDeclare.subst(vmovRegCoreUBIop); 1657333Sgblack@eecs.umich.edu decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUBIop); 1667333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 1677333Sgblack@eecs.umich.edu 1687333Sgblack@eecs.umich.edu vmovRegCoreUHCode = ''' 1697333Sgblack@eecs.umich.edu Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 1707333Sgblack@eecs.umich.edu ''' 1717333Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "RegRegImmOp", 1727333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 1737333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1747333Sgblack@eecs.umich.edu header_output += RegRegImmOpDeclare.subst(vmovRegCoreUHIop); 1757333Sgblack@eecs.umich.edu decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreUHIop); 1767333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 1777333Sgblack@eecs.umich.edu 1787333Sgblack@eecs.umich.edu vmovRegCoreSBCode = ''' 1797333Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 1807333Sgblack@eecs.umich.edu ''' 1817333Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "RegRegImmOp", 1827333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 1837333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1847333Sgblack@eecs.umich.edu header_output += RegRegImmOpDeclare.subst(vmovRegCoreSBIop); 1857333Sgblack@eecs.umich.edu decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSBIop); 1867333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 1877333Sgblack@eecs.umich.edu 1887333Sgblack@eecs.umich.edu vmovRegCoreSHCode = ''' 1897333Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 1907333Sgblack@eecs.umich.edu ''' 1917333Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "RegRegImmOp", 1927333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 1937333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1947333Sgblack@eecs.umich.edu header_output += RegRegImmOpDeclare.subst(vmovRegCoreSHIop); 1957333Sgblack@eecs.umich.edu decoder_output += RegRegImmOpConstructor.subst(vmovRegCoreSHIop); 1967333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 1977333Sgblack@eecs.umich.edu 1987333Sgblack@eecs.umich.edu vmovRegCoreWCode = ''' 1997333Sgblack@eecs.umich.edu Dest = FpOp1.uw; 2007333Sgblack@eecs.umich.edu ''' 2017333Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "RegRegOp", 2027333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 2037333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2047333Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(vmovRegCoreWIop); 2057333Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(vmovRegCoreWIop); 2067333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 2077333Sgblack@eecs.umich.edu 2087333Sgblack@eecs.umich.edu vmov2Reg2CoreCode = ''' 2097333Sgblack@eecs.umich.edu FpDestP0.uw = Op1.uw; 2107333Sgblack@eecs.umich.edu FpDestP1.uw = Op2.uw; 2117333Sgblack@eecs.umich.edu ''' 2127333Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "RegRegRegOp", 2137333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 2147333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2157333Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 2167333Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 2177333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 2187333Sgblack@eecs.umich.edu 2197333Sgblack@eecs.umich.edu vmov2Core2RegCode = ''' 2207333Sgblack@eecs.umich.edu Dest.uw = FpOp2P0.uw; 2217333Sgblack@eecs.umich.edu Op1.uw = FpOp2P1.uw; 2227333Sgblack@eecs.umich.edu ''' 2237333Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "RegRegRegOp", 2247333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 2257333Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2267333Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(vmov2Core2RegIop); 2277333Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(vmov2Core2RegIop); 2287333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 2297364Sgblack@eecs.umich.edu 2307364Sgblack@eecs.umich.edu vmulSCode = ''' 2317364Sgblack@eecs.umich.edu FpDest = FpOp1 * FpOp2; 2327364Sgblack@eecs.umich.edu if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 2337364Sgblack@eecs.umich.edu FpDest = NAN; 2347364Sgblack@eecs.umich.edu } 2357364Sgblack@eecs.umich.edu ''' 2367364Sgblack@eecs.umich.edu vmulSIop = InstObjParams("vmuls", "VmulS", "RegRegRegOp", 2377364Sgblack@eecs.umich.edu { "code": vmulSCode, 2387364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2397364Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(vmulSIop); 2407364Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(vmulSIop); 2417364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulSIop); 2427364Sgblack@eecs.umich.edu 2437364Sgblack@eecs.umich.edu vmulDCode = ''' 2447364Sgblack@eecs.umich.edu IntDoubleUnion cOp1, cOp2, cDest; 2457364Sgblack@eecs.umich.edu cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 2467364Sgblack@eecs.umich.edu cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 2477364Sgblack@eecs.umich.edu cDest.fp = cOp1.fp * cOp2.fp; 2487364Sgblack@eecs.umich.edu if ((isinf(cOp1.fp) && cOp2.fp == 0) || 2497364Sgblack@eecs.umich.edu (isinf(cOp2.fp) && cOp1.fp == 0)) { 2507364Sgblack@eecs.umich.edu cDest.fp = NAN; 2517364Sgblack@eecs.umich.edu } 2527364Sgblack@eecs.umich.edu FpDestP0.uw = cDest.bits; 2537364Sgblack@eecs.umich.edu FpDestP1.uw = cDest.bits >> 32; 2547364Sgblack@eecs.umich.edu ''' 2557364Sgblack@eecs.umich.edu vmulDIop = InstObjParams("vmuld", "VmulD", "RegRegRegOp", 2567364Sgblack@eecs.umich.edu { "code": vmulDCode, 2577364Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2587364Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(vmulDIop); 2597364Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(vmulDIop); 2607364Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmulDIop); 2617322Sgblack@eecs.umich.edu}}; 262