fp.isa revision 13738
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 313738Sciro.santilli@arm.com// Copyright (c) 2010-2013,2016,2018-2019 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu}; 647376Sgblack@eecs.umich.edu 657376Sgblack@eecs.umich.edutemplate <class VfpOp> 6612032Sandreas.sandberg@arm.comStaticInstPtr 677376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 687376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 697376Sgblack@eecs.umich.edu{ 707376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 717376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 727376Sgblack@eecs.umich.edu } else { 737376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 747376Sgblack@eecs.umich.edu } 757376Sgblack@eecs.umich.edu} 767376Sgblack@eecs.umich.edu 777376Sgblack@eecs.umich.edutemplate <class Micro> 787376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 797376Sgblack@eecs.umich.edu{ 807376Sgblack@eecs.umich.edu public: 817376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 827376Sgblack@eecs.umich.edu bool _wide) : 837376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 847376Sgblack@eecs.umich.edu { 857376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 867376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 877376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 887376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 897376Sgblack@eecs.umich.edu if (i == 0) 907376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 917376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 927376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 937376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 947376Sgblack@eecs.umich.edu nextIdxs(_dest); 957376Sgblack@eecs.umich.edu } 967376Sgblack@eecs.umich.edu } 977376Sgblack@eecs.umich.edu}; 987376Sgblack@eecs.umich.edu 997376Sgblack@eecs.umich.edutemplate <class VfpOp> 10012032Sandreas.sandberg@arm.comStaticInstPtr 1017376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1027376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1037376Sgblack@eecs.umich.edu{ 1047376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1057376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1067376Sgblack@eecs.umich.edu } else { 1077376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1087376Sgblack@eecs.umich.edu } 1097376Sgblack@eecs.umich.edu} 1107376Sgblack@eecs.umich.edu 1117376Sgblack@eecs.umich.edutemplate <class Micro> 1127376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1137376Sgblack@eecs.umich.edu{ 1147376Sgblack@eecs.umich.edu public: 1157376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1167376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1177376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1187376Sgblack@eecs.umich.edu { 1197376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1207376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1217376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1227376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1237376Sgblack@eecs.umich.edu if (i == 0) 1247376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1257376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1267376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1277376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1287376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1297376Sgblack@eecs.umich.edu } 1307376Sgblack@eecs.umich.edu } 1317376Sgblack@eecs.umich.edu}; 1327376Sgblack@eecs.umich.edu 1337376Sgblack@eecs.umich.edutemplate <class VfpOp> 13412032Sandreas.sandberg@arm.comStaticInstPtr 1357376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1367376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1377376Sgblack@eecs.umich.edu{ 1387376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1397376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1407376Sgblack@eecs.umich.edu } else { 1417376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1427376Sgblack@eecs.umich.edu } 1437376Sgblack@eecs.umich.edu} 1447376Sgblack@eecs.umich.edu 1457376Sgblack@eecs.umich.edutemplate <class Micro> 1467376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1477376Sgblack@eecs.umich.edu{ 1487376Sgblack@eecs.umich.edu public: 1497376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1507376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1517376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1527376Sgblack@eecs.umich.edu { 1537376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1547376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1557376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1567376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1577376Sgblack@eecs.umich.edu if (i == 0) 1587376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1597376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1607376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1617376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1627376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1637376Sgblack@eecs.umich.edu } 1647376Sgblack@eecs.umich.edu } 1657376Sgblack@eecs.umich.edu}; 1667376Sgblack@eecs.umich.edu 1677376Sgblack@eecs.umich.edutemplate <class VfpOp> 16812032Sandreas.sandberg@arm.comStaticInstPtr 1697376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1707376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1717376Sgblack@eecs.umich.edu{ 1727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1747376Sgblack@eecs.umich.edu } else { 1757376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1767376Sgblack@eecs.umich.edu } 1777376Sgblack@eecs.umich.edu} 1787376Sgblack@eecs.umich.edu}}; 1797376Sgblack@eecs.umich.edu 1807322Sgblack@eecs.umich.edulet {{ 1817322Sgblack@eecs.umich.edu 1827322Sgblack@eecs.umich.edu header_output = "" 1837322Sgblack@eecs.umich.edu decoder_output = "" 1847322Sgblack@eecs.umich.edu exec_output = "" 1857322Sgblack@eecs.umich.edu 18610037SARM gem5 Developers vmsrCode = vmsrEnabledCheckCode + ''' 18710037SARM gem5 Developers MiscDest = Op1; 18810037SARM gem5 Developers ''' 18910037SARM gem5 Developers 19010037SARM gem5 Developers vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegImmOp", 19110037SARM gem5 Developers { "code": vmsrCode, 1927760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 1937760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 1947648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 19510037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmsrIop); 19610037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmsrIop); 1977322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 1987324Sgblack@eecs.umich.edu 1997644Sali.saidi@arm.com vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2007643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2017643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2027643Sgblack@eecs.umich.edu ''' 2037643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2047643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2057760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2067783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2078070SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative", 2088070SAli.Saidi@ARM.com "IsSquashAfter"]) 2097643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2107643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2117643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2127643Sgblack@eecs.umich.edu 21310037SARM gem5 Developers vmrsCode = vmrsEnabledCheckCode + ''' 21410037SARM gem5 Developers CPSR cpsr = Cpsr; 21510037SARM gem5 Developers SCR scr = Scr; 21610037SARM gem5 Developers if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 21710037SARM gem5 Developers HCR hcr = Hcr; 21810037SARM gem5 Developers bool hypTrap = false; 21912106SRekai.GonzalezAlberquilla@arm.com switch(xc->tcBase()->flattenRegId(RegId(MiscRegClass, op1)).index()) { 22010037SARM gem5 Developers case MISCREG_FPSID: 22110037SARM gem5 Developers hypTrap = hcr.tid0; 22210037SARM gem5 Developers break; 22310037SARM gem5 Developers case MISCREG_MVFR0: 22410037SARM gem5 Developers case MISCREG_MVFR1: 22510037SARM gem5 Developers hypTrap = hcr.tid3; 22610037SARM gem5 Developers break; 22710037SARM gem5 Developers } 22810037SARM gem5 Developers if (hypTrap) { 22910474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 23010037SARM gem5 Developers EC_TRAPPED_CP10_MRC_VMRS); 23110037SARM gem5 Developers } 23210037SARM gem5 Developers } 23310037SARM gem5 Developers Dest = MiscOp1; 23410037SARM gem5 Developers ''' 23510037SARM gem5 Developers 23610037SARM gem5 Developers vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegImmOp", 23710037SARM gem5 Developers { "code": vmrsCode, 2387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2397783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2407783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 24110037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmrsIop); 24210037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmrsIop); 2437324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2447333Sgblack@eecs.umich.edu 2457643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2467644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2477643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2487760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2497783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2507783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2517643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2527643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2537643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2547643Sgblack@eecs.umich.edu 25511513Sandreas.sandberg@arm.com vmrsApsrFpscrCode = vfpEnabledCheckCode + ''' 2568303SAli.Saidi@ARM.com FPSCR fpscr = FpCondCodes; 2578303SAli.Saidi@ARM.com CondCodesNZ = (fpscr.n << 1) | fpscr.z; 2588303SAli.Saidi@ARM.com CondCodesC = fpscr.c; 2598303SAli.Saidi@ARM.com CondCodesV = fpscr.v; 2607643Sgblack@eecs.umich.edu ''' 2618303SAli.Saidi@ARM.com vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", 2627643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2648303SAli.Saidi@ARM.com "op_class": "SimdFloatMiscOp" }) 2658303SAli.Saidi@ARM.com header_output += BasicDeclare.subst(vmrsApsrFpscrIop); 2668303SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); 2677643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2687643Sgblack@eecs.umich.edu 2697640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2708588Sgblack@eecs.umich.edu FpDest_uw = bits(imm, 31, 0); 2717333Sgblack@eecs.umich.edu ''' 2727396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2737333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2747760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2757760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2767396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2777396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2787333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2797333Sgblack@eecs.umich.edu 2807640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2818588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2828588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2837333Sgblack@eecs.umich.edu ''' 2847396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2857333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2887396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2897396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2907333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2917333Sgblack@eecs.umich.edu 2927640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 2938588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2948588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2958588Sgblack@eecs.umich.edu FpDestP2_uw = bits(imm, 31, 0); 2968588Sgblack@eecs.umich.edu FpDestP3_uw = bits(imm, 63, 32); 2977333Sgblack@eecs.umich.edu ''' 2987396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 2997333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 3007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3017760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3027396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 3037396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 3047333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 3057333Sgblack@eecs.umich.edu 3067640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 3078588Sgblack@eecs.umich.edu FpDest_uw = FpOp1_uw; 3087333Sgblack@eecs.umich.edu ''' 3097396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 3107333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 3117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3127760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3137396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 3147396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 3157333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 3167333Sgblack@eecs.umich.edu 3177640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 3188588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3198588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3207333Sgblack@eecs.umich.edu ''' 3217396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3227333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3247760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3257396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3267396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3277333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3287333Sgblack@eecs.umich.edu 3297640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3308588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3318588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3328588Sgblack@eecs.umich.edu FpDestP2_uw = FpOp1P2_uw; 3338588Sgblack@eecs.umich.edu FpDestP3_uw = FpOp1P3_uw; 3347333Sgblack@eecs.umich.edu ''' 3357396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3367333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3397396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3407396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3417333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3427333Sgblack@eecs.umich.edu 34310037SARM gem5 Developers vmovCoreRegBCode = simdEnabledCheckCode + ''' 3448588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); 3457333Sgblack@eecs.umich.edu ''' 3467396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3477333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3487760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3497760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3507396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3517396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3527333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3537333Sgblack@eecs.umich.edu 35410037SARM gem5 Developers vmovCoreRegHCode = simdEnabledCheckCode + ''' 3558588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); 3567333Sgblack@eecs.umich.edu ''' 3577396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3587333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3617396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3627396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3637333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3647333Sgblack@eecs.umich.edu 3657640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3668588Sgblack@eecs.umich.edu FpDest_uw = Op1_uw; 3677333Sgblack@eecs.umich.edu ''' 3687396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3697333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3707760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3717760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3727396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3737396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3747333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3757333Sgblack@eecs.umich.edu 3767640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3777639Sgblack@eecs.umich.edu assert(imm < 4); 3788588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8); 3797333Sgblack@eecs.umich.edu ''' 3807396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3817333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3837760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3847396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3857396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3867333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3877333Sgblack@eecs.umich.edu 3887640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3897639Sgblack@eecs.umich.edu assert(imm < 2); 3908588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16); 3917333Sgblack@eecs.umich.edu ''' 3927396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 3937333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 3947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3967396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 3977396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 3987333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 3997333Sgblack@eecs.umich.edu 4007640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 4017639Sgblack@eecs.umich.edu assert(imm < 4); 4028588Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8)); 4037333Sgblack@eecs.umich.edu ''' 4047396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 4057333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 4067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4087396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 4097396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 4107333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 4117333Sgblack@eecs.umich.edu 4127640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 4137639Sgblack@eecs.umich.edu assert(imm < 2); 4148588Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16)); 4157333Sgblack@eecs.umich.edu ''' 4167396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 4177333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 4187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4197760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4207396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 4217396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 4227333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 4237333Sgblack@eecs.umich.edu 4247640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 4258588Sgblack@eecs.umich.edu Dest = FpOp1_uw; 4267333Sgblack@eecs.umich.edu ''' 4277396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 4287333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 4297760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4307760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4317396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4327396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4337333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4347333Sgblack@eecs.umich.edu 4357640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4368588Sgblack@eecs.umich.edu FpDestP0_uw = Op1_uw; 4378588Sgblack@eecs.umich.edu FpDestP1_uw = Op2_uw; 4387333Sgblack@eecs.umich.edu ''' 4397396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4407333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4417760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4427760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4437396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4447396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4457333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4467333Sgblack@eecs.umich.edu 4477640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4488588Sgblack@eecs.umich.edu Dest_uw = FpOp2P0_uw; 4498588Sgblack@eecs.umich.edu Op1_uw = FpOp2P1_uw; 4507333Sgblack@eecs.umich.edu ''' 4517396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4527333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4537760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4547760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4557396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4567396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4577333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4587381Sgblack@eecs.umich.edu}}; 4597381Sgblack@eecs.umich.edu 4607381Sgblack@eecs.umich.edulet {{ 4617381Sgblack@eecs.umich.edu 4627381Sgblack@eecs.umich.edu header_output = "" 4637381Sgblack@eecs.umich.edu decoder_output = "" 4647381Sgblack@eecs.umich.edu exec_output = "" 4657364Sgblack@eecs.umich.edu 4667783SGiacomo.Gabrielli@arm.com singleSimpleCode = vfpEnabledCheckCode + ''' 4678607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4687396Sgblack@eecs.umich.edu FpDest = %(op)s; 4697783SGiacomo.Gabrielli@arm.com ''' 4707783SGiacomo.Gabrielli@arm.com singleCode = singleSimpleCode + ''' 4717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4727364Sgblack@eecs.umich.edu ''' 47310037SARM gem5 Developers singleTernOp = vfpEnabledCheckCode + ''' 47410037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 47510037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 47610037SARM gem5 Developers float cOp1 = FpOp1; 47710037SARM gem5 Developers float cOp2 = FpOp2; 47810037SARM gem5 Developers float cOp3 = FpDestP0; 47910037SARM gem5 Developers FpDestP0 = ternaryOp(fpscr, %(palam)s, %(op)s, 48010037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 48110037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 48210037SARM gem5 Developers FpscrExc = fpscr; 48310037SARM gem5 Developers ''' 4847396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4857639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4867396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4877640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4888607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4897396Sgblack@eecs.umich.edu double dest = %(op)s; 4908588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 4918588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 4927783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4937396Sgblack@eecs.umich.edu ''' 49410037SARM gem5 Developers doubleTernOp = vfpEnabledCheckCode + ''' 49510037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 49610037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 49710037SARM gem5 Developers double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 49810037SARM gem5 Developers double cOp2 = dbl(FpOp2P0_uw, FpOp2P1_uw); 49910037SARM gem5 Developers double cOp3 = dbl(FpDestP0_uw, FpDestP1_uw); 50010037SARM gem5 Developers double cDest = ternaryOp(fpscr, %(palam)s, %(op)s, 50110037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 50210037SARM gem5 Developers FpDestP0_uw = dblLow(cDest); 50310037SARM gem5 Developers FpDestP1_uw = dblHi(cDest); 50410037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 50510037SARM gem5 Developers FpscrExc = fpscr; 50610037SARM gem5 Developers ''' 5077396Sgblack@eecs.umich.edu doubleBinOp = ''' 5088588Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 5098588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 5107639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 5117396Sgblack@eecs.umich.edu ''' 5127396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 5138588Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s, 5147396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 5157396Sgblack@eecs.umich.edu ''' 5167364Sgblack@eecs.umich.edu 51710037SARM gem5 Developers def buildTernaryFpOp(Name, base, opClass, singleOp, doubleOp, paramStr): 51810037SARM gem5 Developers global header_output, decoder_output, exec_output 51910037SARM gem5 Developers 52010037SARM gem5 Developers code = singleTernOp % { "op": singleOp, "palam": paramStr } 52110037SARM gem5 Developers sIop = InstObjParams(Name.lower() + "s", Name + "S", base, 52210037SARM gem5 Developers { "code": code, 52310037SARM gem5 Developers "predicate_test": predicateTest, 52410037SARM gem5 Developers "op_class": opClass }, []) 52510037SARM gem5 Developers code = doubleTernOp % { "op": doubleOp, "palam": paramStr } 52610037SARM gem5 Developers dIop = InstObjParams(Name.lower() + "d", Name + "D", base, 52710037SARM gem5 Developers { "code": code, 52810037SARM gem5 Developers "predicate_test": predicateTest, 52910037SARM gem5 Developers "op_class": opClass }, []) 53010037SARM gem5 Developers 53110037SARM gem5 Developers declareTempl = eval(base + "Declare"); 53210037SARM gem5 Developers constructorTempl = eval(base + "Constructor"); 53310037SARM gem5 Developers 53410037SARM gem5 Developers for iop in sIop, dIop: 53510037SARM gem5 Developers header_output += declareTempl.subst(iop) 53610037SARM gem5 Developers decoder_output += constructorTempl.subst(iop) 53710037SARM gem5 Developers exec_output += PredOpExecute.subst(iop) 53810037SARM gem5 Developers 53910037SARM gem5 Developers buildTernaryFpOp("Vfma", "FpRegRegRegOp", "SimdFloatMultAccOp", 54010037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, cOp3" ) 54110037SARM gem5 Developers buildTernaryFpOp("Vfms", "FpRegRegRegOp", "SimdFloatMultAccOp", 54210037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, cOp3" ) 54310037SARM gem5 Developers buildTernaryFpOp("Vfnma", "FpRegRegRegOp", "SimdFloatMultAccOp", 54410037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, -cOp3" ) 54510037SARM gem5 Developers buildTernaryFpOp("Vfnms", "FpRegRegRegOp", "SimdFloatMultAccOp", 54610037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, -cOp3" ) 54710037SARM gem5 Developers 5487760SGiacomo.Gabrielli@arm.com def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 5497396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5507365Sgblack@eecs.umich.edu 5517396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 5527396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5537396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5547760SGiacomo.Gabrielli@arm.com { "code": code, 5557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5567760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5577396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 5587396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5597396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5607760SGiacomo.Gabrielli@arm.com { "code": code, 5617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5627760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5637365Sgblack@eecs.umich.edu 5647396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5657396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5667366Sgblack@eecs.umich.edu 5677396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5687396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5697396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5707396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5717366Sgblack@eecs.umich.edu 5727760SGiacomo.Gabrielli@arm.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS", 5737760SGiacomo.Gabrielli@arm.com "fpAddD") 5747760SGiacomo.Gabrielli@arm.com buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS", 5757760SGiacomo.Gabrielli@arm.com "fpSubD") 5767760SGiacomo.Gabrielli@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS", 5777760SGiacomo.Gabrielli@arm.com "fpDivD") 5787760SGiacomo.Gabrielli@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS", 5797760SGiacomo.Gabrielli@arm.com "fpMulD") 5807367Sgblack@eecs.umich.edu 5817760SGiacomo.Gabrielli@arm.com def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 5827396Sgblack@eecs.umich.edu if doubleOp is None: 5837396Sgblack@eecs.umich.edu doubleOp = singleOp 5847396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5857367Sgblack@eecs.umich.edu 5867396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 5877396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5887396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5897760SGiacomo.Gabrielli@arm.com { "code": code, 5907760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5917760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5927396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 5937396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5947396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5957760SGiacomo.Gabrielli@arm.com { "code": code, 5967760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5977760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5987368Sgblack@eecs.umich.edu 5997396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6007396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6017368Sgblack@eecs.umich.edu 6027396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6037396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6047396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6057396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6067369Sgblack@eecs.umich.edu 6077760SGiacomo.Gabrielli@arm.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "SimdFloatSqrtOp", "sqrtf", 6087760SGiacomo.Gabrielli@arm.com "sqrt") 6097369Sgblack@eecs.umich.edu 6107760SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 6117760SGiacomo.Gabrielli@arm.com doubleOp = None): 6127396Sgblack@eecs.umich.edu if doubleOp is None: 6137396Sgblack@eecs.umich.edu doubleOp = singleOp 6147396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 6157369Sgblack@eecs.umich.edu 6167396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 6177783SGiacomo.Gabrielli@arm.com { "code": singleSimpleCode % { "op": singleOp }, 6187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6197760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6207396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 6217396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 6227760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6237760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6247369Sgblack@eecs.umich.edu 6257396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6267396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6277396Sgblack@eecs.umich.edu 6287396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6297396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6307396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6317396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6327396Sgblack@eecs.umich.edu 6337760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", 6348588Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)") 6357760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", 6368588Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))") 63711671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintp", "VRIntP", "FpRegRegOp", "SimdFloatMiscOp", 63811671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_POSINF, false, fpscr)", 63911671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 64011671Smitch.hayenga@arm.com "FPRounding_POSINF, false, fpscr)" 64111671Smitch.hayenga@arm.com ) 64211671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintm", "VRIntM", "FpRegRegOp", "SimdFloatMiscOp", 64311671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_NEGINF, false, fpscr)", 64411671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 64511671Smitch.hayenga@arm.com "FPRounding_NEGINF, false, fpscr)" 64611671Smitch.hayenga@arm.com ) 64711671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrinta", "VRIntA", "FpRegRegOp", "SimdFloatMiscOp", 64811671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEAWAY, false, fpscr)", 64911671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 65011671Smitch.hayenga@arm.com "FPRounding_TIEAWAY, false, fpscr)" 65111671Smitch.hayenga@arm.com ) 65211671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintn", "VRIntN", "FpRegRegOp", "SimdFloatMiscOp", 65311671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEEVEN, false, fpscr)", 65411671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 65511671Smitch.hayenga@arm.com "FPRounding_TIEEVEN, false, fpscr)" 65611671Smitch.hayenga@arm.com ) 6577381Sgblack@eecs.umich.edu}}; 6587381Sgblack@eecs.umich.edu 6597381Sgblack@eecs.umich.edulet {{ 6607381Sgblack@eecs.umich.edu 6617381Sgblack@eecs.umich.edu header_output = "" 6627381Sgblack@eecs.umich.edu decoder_output = "" 6637381Sgblack@eecs.umich.edu exec_output = "" 6647370Sgblack@eecs.umich.edu 6657640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 6667783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6677396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6687639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6697639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 6707639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6727370Sgblack@eecs.umich.edu ''' 6737396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 6747370Sgblack@eecs.umich.edu { "code": vmlaSCode, 6757760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6767760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6777396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 6787396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 6797370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 6807370Sgblack@eecs.umich.edu 6817640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 6827783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6838588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 6848588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 6857639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6868588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 6877639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 6887639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6898588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 6908588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 6917783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6927370Sgblack@eecs.umich.edu ''' 6937396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 6947370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6957760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6967760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6977396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 6987396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 6997370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 7007370Sgblack@eecs.umich.edu 7017640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 7027783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7037396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7047639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7057639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 7067639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7077783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7087370Sgblack@eecs.umich.edu ''' 7097396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 7107370Sgblack@eecs.umich.edu { "code": vmlsSCode, 7117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7127760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7137396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 7147396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 7157370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 7167370Sgblack@eecs.umich.edu 7177640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 7187783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7198588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7208588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7217639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7228588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 7237639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 7247639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7258588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7268588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7277783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7287370Sgblack@eecs.umich.edu ''' 7297396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 7307370Sgblack@eecs.umich.edu { "code": vmlsDCode, 7317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7327760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7337396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 7347396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 7357370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 7367371Sgblack@eecs.umich.edu 7377640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 7387783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7397396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7407639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7417639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 7427639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7437783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7447371Sgblack@eecs.umich.edu ''' 7457396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 7467371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 7477760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7487760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7497396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 7507396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 7517371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 7527371Sgblack@eecs.umich.edu 7537640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 7547783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7558588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7568588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7577639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7588588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 7597639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 7607639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7618588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7628588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7637783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7647371Sgblack@eecs.umich.edu ''' 7657396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 7667371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 7677760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7687760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7697396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 7707396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 7717371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 7727371Sgblack@eecs.umich.edu 7737640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 7747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7757396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7767639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7777639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 7787639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7807371Sgblack@eecs.umich.edu ''' 7817396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 7827760SGiacomo.Gabrielli@arm.com { "code": vnmlsSCode, 7837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7857396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 7867396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 7877371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7887371Sgblack@eecs.umich.edu 7897640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 7907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7918588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7928588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7937639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7948588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 7957639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 7967639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7978588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7988588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7997783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8007371Sgblack@eecs.umich.edu ''' 8017396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 8027760SGiacomo.Gabrielli@arm.com { "code": vnmlsDCode, 8037760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8047760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 8057396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 8067396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 8077371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 8087371Sgblack@eecs.umich.edu 8097640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 8107783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8117639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 8127639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 8137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8147371Sgblack@eecs.umich.edu ''' 8157396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 8167760SGiacomo.Gabrielli@arm.com { "code": vnmulSCode, 8177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8197396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 8207396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 8217371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 8227371Sgblack@eecs.umich.edu 8237640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 8247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8258588Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 8268588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 8277639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 8287639Sgblack@eecs.umich.edu fpscr.rMode); 8298588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 8308588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 8317783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8327371Sgblack@eecs.umich.edu ''' 8337396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 8347371Sgblack@eecs.umich.edu { "code": vnmulDCode, 8357760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8367760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8377396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 8387396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 8397371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 8407381Sgblack@eecs.umich.edu}}; 8417381Sgblack@eecs.umich.edu 8427381Sgblack@eecs.umich.edulet {{ 8437381Sgblack@eecs.umich.edu 8447381Sgblack@eecs.umich.edu header_output = "" 8457381Sgblack@eecs.umich.edu decoder_output = "" 8467381Sgblack@eecs.umich.edu exec_output = "" 8477373Sgblack@eecs.umich.edu 8487640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 8497783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8507397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8518588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 8528588Sgblack@eecs.umich.edu FpDest = FpOp1_uw; 8537381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8547639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8557783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8567373Sgblack@eecs.umich.edu ''' 8577396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 8587373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 8597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8617396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 8627396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 8637373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 8647373Sgblack@eecs.umich.edu 8657640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 8667783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8677397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8688588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_uw) : "m" (FpOp1P0_uw)); 8698588Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0_uw; 8707397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8717639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8728588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 8738588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 8747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8757373Sgblack@eecs.umich.edu ''' 8767396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 8777373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 8787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 8817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 8827373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 8837373Sgblack@eecs.umich.edu 8847640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 8857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8867397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8878588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 8888588Sgblack@eecs.umich.edu FpDest = FpOp1_sw; 8897381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8907639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8917783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8927373Sgblack@eecs.umich.edu ''' 8937396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 8947373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 8957760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8967760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8977396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 8987396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 8997373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 9007373Sgblack@eecs.umich.edu 9017640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 9027783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9037397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9048588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_sw) : "m" (FpOp1P0_sw)); 9058588Sgblack@eecs.umich.edu double cDest = FpOp1P0_sw; 9067397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9077639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9088588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 9098588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 9107783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9117373Sgblack@eecs.umich.edu ''' 9127396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 9137373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 9147760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9157760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9167396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 9177396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 9187373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 9197373Sgblack@eecs.umich.edu 9207640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 9217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9227397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9237397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9247381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 92510037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0, false); 9268588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 9277639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9287783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9297380Sgblack@eecs.umich.edu ''' 9307396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 9317380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 9327760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9337760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9347396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 9357396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 9367380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 9377380Sgblack@eecs.umich.edu 9387640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 9397783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9408588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9417397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9427397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9437397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 94410037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0, false); 9457381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9467639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9478588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9487783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9497380Sgblack@eecs.umich.edu ''' 9507396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 9517380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 9527760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9537760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9547396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 9557396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 9567380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 9577380Sgblack@eecs.umich.edu 9587640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 9597783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9607397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9617397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9627381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 96310037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0, false); 9648588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 9657639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9667783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9677380Sgblack@eecs.umich.edu ''' 9687396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 9697380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 9707760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9717760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9727396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 9737396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 9747380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 9757380Sgblack@eecs.umich.edu 9767640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 9777783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9788588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9797397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9807397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9817397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 98210037SARM gem5 Developers int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0, false); 9837381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9847639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9858588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9867783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9877380Sgblack@eecs.umich.edu ''' 9887396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 9897380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 9907760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9917760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9927396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 9937396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 9947380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 9957380Sgblack@eecs.umich.edu 99613738Sciro.santilli@arm.com round_mode_suffix_to_mode = { 99713738Sciro.santilli@arm.com '': 'VfpRoundZero', 99813738Sciro.santilli@arm.com 'a': 'VfpRoundAway', 99913738Sciro.santilli@arm.com 'm': 'VfpRoundDown', 100013738Sciro.santilli@arm.com 'n': 'VfpRoundNearest', 100113738Sciro.santilli@arm.com 'p': 'VfpRoundUpward', 100213738Sciro.santilli@arm.com } 100313738Sciro.santilli@arm.com 100413738Sciro.santilli@arm.com def buildVcvt(code, className, roundModeSuffix): 100513738Sciro.santilli@arm.com global header_output, decoder_output, exec_output, \ 100613738Sciro.santilli@arm.com vfpEnabledCheckCode, round_mode_suffix_to_mode 100713738Sciro.santilli@arm.com full_code = vfpEnabledCheckCode + code.format( 100813738Sciro.santilli@arm.com round_mode=round_mode_suffix_to_mode[roundModeSuffix], 100913738Sciro.santilli@arm.com ) 101013738Sciro.santilli@arm.com iop = InstObjParams( 101113738Sciro.santilli@arm.com "vcvt{}".format(roundModeSuffix), 101213738Sciro.santilli@arm.com className.format(roundModeSuffix), 101313738Sciro.santilli@arm.com "FpRegRegOp", 101413738Sciro.santilli@arm.com { "code": full_code, 101513738Sciro.santilli@arm.com "predicate_test": predicateTest, 101613738Sciro.santilli@arm.com "op_class": "SimdFloatCvtOp" }, 101713738Sciro.santilli@arm.com [] 101813738Sciro.santilli@arm.com ) 101913738Sciro.santilli@arm.com header_output += FpRegRegOpDeclare.subst(iop); 102013738Sciro.santilli@arm.com decoder_output += FpRegRegOpConstructor.subst(iop); 102113738Sciro.santilli@arm.com exec_output += PredOpExecute.subst(iop); 102213738Sciro.santilli@arm.com 102313738Sciro.santilli@arm.com code = ''' 10247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10257397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10267397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10277380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10287381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 102913738Sciro.santilli@arm.com FpDest_uw = vfpFpToFixed<float>( 103013738Sciro.santilli@arm.com FpOp1, false, 32, 0, true, {round_mode}); 10318588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 10327639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10337783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10347373Sgblack@eecs.umich.edu ''' 103513738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 103613738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpUIntS", round_mode_suffix) 10377373Sgblack@eecs.umich.edu 103813738Sciro.santilli@arm.com code = ''' 10397783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10408588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10417397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10427397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10437380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10447397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 104513738Sciro.santilli@arm.com uint64_t result = vfpFpToFixed<double>( 104613738Sciro.santilli@arm.com cOp1, false, 32, 0, true, {round_mode}); 10477381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10487639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10498588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10507783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10517373Sgblack@eecs.umich.edu ''' 105213738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 105313738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpUIntD", round_mode_suffix) 10547373Sgblack@eecs.umich.edu 105513738Sciro.santilli@arm.com code = ''' 10567783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10577397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10587397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10597380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10607381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 106113738Sciro.santilli@arm.com FpDest_sw = vfpFpToFixed<float>( 106213738Sciro.santilli@arm.com FpOp1, true, 32, 0, true, {round_mode}); 10638588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 10647639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10657783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10667373Sgblack@eecs.umich.edu ''' 106713738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 106813738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpSIntS", round_mode_suffix) 10697373Sgblack@eecs.umich.edu 107013738Sciro.santilli@arm.com code = ''' 10717783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10728588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10737397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10747397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10757380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10767397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 107713738Sciro.santilli@arm.com int64_t result = vfpFpToFixed<double>( 107813738Sciro.santilli@arm.com cOp1, true, 32, 0, true, {round_mode}); 10797381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10807639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10818588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10827783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10837373Sgblack@eecs.umich.edu ''' 108413738Sciro.santilli@arm.com for round_mode_suffix in round_mode_suffix_to_mode: 108513738Sciro.santilli@arm.com buildVcvt(code, "Vcvt{}FpSIntD", round_mode_suffix) 10867374Sgblack@eecs.umich.edu 10877640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 10887783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10897397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10907397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10917381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10927783SGiacomo.Gabrielli@arm.com double cDest = fixFpSFpDDest(FpscrExc, FpOp1); 10937397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 10947639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10958588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 10968588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 10977783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10987374Sgblack@eecs.umich.edu ''' 10997396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 11007374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 11017760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11027760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11037396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 11047396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 11057374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 11067374Sgblack@eecs.umich.edu 11077640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 11087783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11098588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 11107397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 11117397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11127397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 11137783SGiacomo.Gabrielli@arm.com FpDest = fixFpDFpSDest(FpscrExc, cOp1); 11147381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11167783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11177374Sgblack@eecs.umich.edu ''' 11187396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 11197374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 11207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11227396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 11237396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 11247374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 11257377Sgblack@eecs.umich.edu 11267640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 11277783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11287398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11297398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11307398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11317639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 11327639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 11337398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11347639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11357783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11367398Sgblack@eecs.umich.edu ''' 11377398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 11387398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 11397760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11407760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11417398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 11427398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 11437398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 11447398Sgblack@eecs.umich.edu 11457640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 11467783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11477398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11487398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11497639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 11507639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 11517398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11527639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11537783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11547398Sgblack@eecs.umich.edu ''' 11557398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 11567398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 11577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11597398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 11607398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 11617398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 11627398Sgblack@eecs.umich.edu 11637640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 11647783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11657398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11667398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11678588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 11688588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 11698588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 31, 16,, 11707639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 11717639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 11728588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 11737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11757398Sgblack@eecs.umich.edu ''' 11767398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 11777398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 11787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11807398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 11817398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 11827398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 11837398Sgblack@eecs.umich.edu 11847640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 11857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11867398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11877398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11888588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 11898588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 11908588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 15, 0, 11917639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 11927639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 11938588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 11947639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11957783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11967398Sgblack@eecs.umich.edu ''' 11977398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 11987398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 11997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 12017398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 12027398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 12037398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 12047398Sgblack@eecs.umich.edu 12057640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 12067783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12077397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 12087377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12097377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12107377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12117377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12127377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12137377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12147377Sgblack@eecs.umich.edu } else { 12157389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 12167389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 12177396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 12187389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 12197396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 12207389Sgblack@eecs.umich.edu if (signal1 || signal2) 12217389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12227377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12237377Sgblack@eecs.umich.edu } 12247643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12257783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12267377Sgblack@eecs.umich.edu ''' 12277396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 12287377Sgblack@eecs.umich.edu { "code": vcmpSCode, 12297760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12307760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12317396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 12327396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 12337377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 12347377Sgblack@eecs.umich.edu 12357640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 12368588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 12378588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 12387783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12397397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 12407397Sgblack@eecs.umich.edu if (cDest == cOp1) { 12417377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12427397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 12437377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12447397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 12457377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12467377Sgblack@eecs.umich.edu } else { 12477389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12487397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 12497397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 12507397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 12517397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 12527389Sgblack@eecs.umich.edu if (signal1 || signal2) 12537389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12547377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12557377Sgblack@eecs.umich.edu } 12567643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12577783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12587377Sgblack@eecs.umich.edu ''' 12597396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 12607377Sgblack@eecs.umich.edu { "code": vcmpDCode, 12617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12627760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12637396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 12647396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 12657377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 12667377Sgblack@eecs.umich.edu 12677640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 12687783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12697397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 12707389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12717389Sgblack@eecs.umich.edu assert(imm == 0); 12727377Sgblack@eecs.umich.edu if (FpDest == imm) { 12737377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12747377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12757377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12767377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12777377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12787377Sgblack@eecs.umich.edu } else { 12797389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 12807389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 12817396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 12827389Sgblack@eecs.umich.edu if (signal) 12837389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12847377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12857377Sgblack@eecs.umich.edu } 12867643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12877783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12887377Sgblack@eecs.umich.edu ''' 12897396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 12907377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 12917760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12927760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12937396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 12947396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 12957377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 12967377Sgblack@eecs.umich.edu 12977640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 12987389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12997389Sgblack@eecs.umich.edu assert(imm == 0); 13008588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 13017783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13027397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 13037397Sgblack@eecs.umich.edu if (cDest == imm) { 13047377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13057397Sgblack@eecs.umich.edu } else if (cDest < imm) { 13067377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13077397Sgblack@eecs.umich.edu } else if (cDest > imm) { 13087377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13097377Sgblack@eecs.umich.edu } else { 13107389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 13117397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 13127397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 13137389Sgblack@eecs.umich.edu if (signal) 13147389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13157377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13167377Sgblack@eecs.umich.edu } 13177643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13187783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13197377Sgblack@eecs.umich.edu ''' 13207396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 13217377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 13227760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13237760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13247396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 13257396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 13267377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 13277389Sgblack@eecs.umich.edu 13287640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 13297783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13307397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 13317389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 13327389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13337389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 13347389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13357389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 13367389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13377389Sgblack@eecs.umich.edu } else { 13387389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13397389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13407389Sgblack@eecs.umich.edu } 13417643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13427783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13437389Sgblack@eecs.umich.edu ''' 13447396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 13457389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 13467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13477760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13487396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 13497396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 13507389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 13517389Sgblack@eecs.umich.edu 13527640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 13538588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 13548588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 13557783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13567397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 13577397Sgblack@eecs.umich.edu if (cDest == cOp1) { 13587389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13597397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 13607389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13617397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 13627389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13637389Sgblack@eecs.umich.edu } else { 13647389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13657389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13667389Sgblack@eecs.umich.edu } 13677643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13687783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13697389Sgblack@eecs.umich.edu ''' 13707396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 13717389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 13727760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13737760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13747396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 13757396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 13767389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 13777389Sgblack@eecs.umich.edu 13787640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 13797783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13807397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 13817389Sgblack@eecs.umich.edu if (FpDest == imm) { 13827389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13837389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 13847389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13857389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 13867389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13877389Sgblack@eecs.umich.edu } else { 13887389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13897389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13907389Sgblack@eecs.umich.edu } 13917643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13927783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13937389Sgblack@eecs.umich.edu ''' 13947396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 13957389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 13967760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13977760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13987396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 13997396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 14007389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 14017389Sgblack@eecs.umich.edu 14027640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 14038588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 14047783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14057397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 14067397Sgblack@eecs.umich.edu if (cDest == imm) { 14077389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 14087397Sgblack@eecs.umich.edu } else if (cDest < imm) { 14097389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 14107397Sgblack@eecs.umich.edu } else if (cDest > imm) { 14117389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 14127389Sgblack@eecs.umich.edu } else { 14137389Sgblack@eecs.umich.edu fpscr.ioc = 1; 14147389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 14157389Sgblack@eecs.umich.edu } 14167643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14177783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14187389Sgblack@eecs.umich.edu ''' 14197396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 14207389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 14217760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14227760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 14237396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 14247396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 14257389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 14267322Sgblack@eecs.umich.edu}}; 14277379Sgblack@eecs.umich.edu 14287379Sgblack@eecs.umich.edulet {{ 14297379Sgblack@eecs.umich.edu 14307379Sgblack@eecs.umich.edu header_output = "" 14317379Sgblack@eecs.umich.edu decoder_output = "" 14327379Sgblack@eecs.umich.edu exec_output = "" 14337379Sgblack@eecs.umich.edu 143411671Smitch.hayenga@arm.com vselSCode = vfpEnabledCheckCode + ''' 143511671Smitch.hayenga@arm.com if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) { 143611671Smitch.hayenga@arm.com FpDest = FpOp1; 143711671Smitch.hayenga@arm.com } else { 143811671Smitch.hayenga@arm.com FpDest = FpOp2; 143911671Smitch.hayenga@arm.com } ''' 144011671Smitch.hayenga@arm.com 144111671Smitch.hayenga@arm.com vselSIop = InstObjParams("vsels", "VselS", "FpRegRegRegCondOp", 144211671Smitch.hayenga@arm.com { "code" : vselSCode, 144311671Smitch.hayenga@arm.com "predicate_test" : predicateTest, 144411671Smitch.hayenga@arm.com "op_class" : "SimdFloatCmpOp" }, [] ) 144511671Smitch.hayenga@arm.com header_output += FpRegRegRegCondOpDeclare.subst(vselSIop); 144611671Smitch.hayenga@arm.com decoder_output += FpRegRegRegCondOpConstructor.subst(vselSIop); 144711671Smitch.hayenga@arm.com exec_output += PredOpExecute.subst(vselSIop); 144811671Smitch.hayenga@arm.com 144911671Smitch.hayenga@arm.com vselDCode = vfpEnabledCheckCode + ''' 145011671Smitch.hayenga@arm.com if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) { 145111671Smitch.hayenga@arm.com FpDestP0_uw = FpOp1P0_uw; 145211671Smitch.hayenga@arm.com FpDestP1_uw = FpOp1P1_uw; 145311671Smitch.hayenga@arm.com } else { 145411671Smitch.hayenga@arm.com FpDestP0_uw = FpOp2P0_uw; 145511671Smitch.hayenga@arm.com FpDestP1_uw = FpOp2P1_uw; 145611671Smitch.hayenga@arm.com } ''' 145711671Smitch.hayenga@arm.com 145811671Smitch.hayenga@arm.com vselDIop = InstObjParams("vseld", "VselD", "FpRegRegRegCondOp", 145911671Smitch.hayenga@arm.com { "code" : vselDCode, 146011671Smitch.hayenga@arm.com "predicate_test" : predicateTest, 146111671Smitch.hayenga@arm.com "op_class" : "SimdFloatCmpOp" }, [] ) 146211671Smitch.hayenga@arm.com header_output += FpRegRegRegCondOpDeclare.subst(vselDIop); 146311671Smitch.hayenga@arm.com decoder_output += FpRegRegRegCondOpConstructor.subst(vselDIop); 146411671Smitch.hayenga@arm.com exec_output += PredOpExecute.subst(vselDIop); 146511671Smitch.hayenga@arm.com}}; 146611671Smitch.hayenga@arm.com 146711671Smitch.hayenga@arm.com 146811671Smitch.hayenga@arm.comlet {{ 146911671Smitch.hayenga@arm.com 147011671Smitch.hayenga@arm.com header_output = "" 147111671Smitch.hayenga@arm.com decoder_output = "" 147211671Smitch.hayenga@arm.com exec_output = "" 147311671Smitch.hayenga@arm.com 14747640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 14757783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14767397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14777397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14787381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 147910037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, imm); 14808588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 14817639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14827783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14837379Sgblack@eecs.umich.edu ''' 14847396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 14857379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 14867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14887396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 14897396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 14907379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 14917379Sgblack@eecs.umich.edu 14927640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 14937783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14948588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 14957397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14967397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14977397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 149810037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, true, 32, imm); 14997381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15007639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15018588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 15028588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 15037783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15047379Sgblack@eecs.umich.edu ''' 15057396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 15067379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 15077760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15087760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15097396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 15107396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 15117379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 15127379Sgblack@eecs.umich.edu 15137640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 15147783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15157397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15167397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15177381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 151810037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, imm); 15198588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 15207639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15217783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15227379Sgblack@eecs.umich.edu ''' 15237396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 15247379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 15257760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15267760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15277396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 15287396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 15297379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 15307379Sgblack@eecs.umich.edu 15317640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 15327783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15338588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 15347397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15357397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15367397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 153710037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 32, imm); 15387381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15397639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15408588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 15418588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 15427783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15437379Sgblack@eecs.umich.edu ''' 15447396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 15457379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 15467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15477760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15487396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 15497396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 15507379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 15517379Sgblack@eecs.umich.edu 15527640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 15537783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15547397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15558588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 155610037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, 32, imm); 15577381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15587639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15597783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15607379Sgblack@eecs.umich.edu ''' 15617396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 15627379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 15637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15647760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15657396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 15667396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 15677379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 15687379Sgblack@eecs.umich.edu 15697640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 15707783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15718588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 15727397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15737381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 157410037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 15757397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15767639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15778588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 15788588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 15797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15807379Sgblack@eecs.umich.edu ''' 15817396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 15827379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 15837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15857396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 15867396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 15877379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 15887379Sgblack@eecs.umich.edu 15897640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 15907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15917397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15928588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 159310037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, 32, imm); 15947381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15957639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15967783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15977379Sgblack@eecs.umich.edu ''' 15987396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 15997379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 16007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16017760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16027396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 16037396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 16047379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 16057379Sgblack@eecs.umich.edu 16067640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 16077783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16088588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 16097397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16107381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 161110037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 16127397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16137639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16148588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 16158588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 16167783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16177379Sgblack@eecs.umich.edu ''' 16187396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 16197379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 16207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16227396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 16237396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 16247379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 16257379Sgblack@eecs.umich.edu 16267640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 16277783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16287397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 16297397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16307381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 163110037SARM gem5 Developers FpDest_sh = vfpFpToFixed<float>(FpOp1, true, 16, imm); 16328588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sh)); 16337639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16357379Sgblack@eecs.umich.edu ''' 16367379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 16377396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16387379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 16397760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16407760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16417396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 16427396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 16437379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 16447379Sgblack@eecs.umich.edu 16457640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 16467783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16478588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 16487397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 16497397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16507397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 165110037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, true, 16, imm); 16527381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 16537639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16548588Sgblack@eecs.umich.edu FpDestP0_uw = result; 16558588Sgblack@eecs.umich.edu FpDestP1_uw = result >> 32; 16567783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16577379Sgblack@eecs.umich.edu ''' 16587379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 16597396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16607379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 16617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16627760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16637396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 16647396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 16657379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 16667379Sgblack@eecs.umich.edu 16677640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 16687783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16697397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 16707397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16717381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 167210037SARM gem5 Developers FpDest_uh = vfpFpToFixed<float>(FpOp1, false, 16, imm); 16738588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uh)); 16747639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16757783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16767379Sgblack@eecs.umich.edu ''' 16777379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 16787396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16797379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 16807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16827396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 16837396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 16847379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 16857379Sgblack@eecs.umich.edu 16867640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 16877783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16888588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 16897397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 16907397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16917397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 169210037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 16, imm); 16937381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 16947639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16958588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 16968588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 16977783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16987379Sgblack@eecs.umich.edu ''' 16997379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 17007396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17017379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 17027760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17037760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17047396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 17057396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 17067379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 17077379Sgblack@eecs.umich.edu 17087640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 17097783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17107397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17118588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh)); 171210037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, 16, imm); 17137381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 17147639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17167379Sgblack@eecs.umich.edu ''' 17177379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 17187396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17197379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 17207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17227396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 17237396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 17247379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 17257379Sgblack@eecs.umich.edu 17267640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 17277783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17288588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 17297397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17307381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 173110037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 17327397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 17337639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17348588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 17358588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 17367783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17377379Sgblack@eecs.umich.edu ''' 17387379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 17397396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17407379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 17417760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17427760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17437396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 17447396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 17457379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 17467379Sgblack@eecs.umich.edu 17477640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 17487783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17497397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17508588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh)); 175110037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, 16, imm); 17527381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 17537639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17547783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17557379Sgblack@eecs.umich.edu ''' 17567379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 17577396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17587379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 17597760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17607760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17617396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 17627396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 17637379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 17647379Sgblack@eecs.umich.edu 17657640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 17667783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17678588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 17687397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17697381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 177010037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 17717397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 17727639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17738588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 17748588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 17757783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17767379Sgblack@eecs.umich.edu ''' 17777379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 17787396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17797379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 17807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17827396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 17837396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 17847379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 17857379Sgblack@eecs.umich.edu}}; 1786