fp.isa revision 12106
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 311671Smitch.hayenga@arm.com// Copyright (c) 2010-2013,2016 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 6812032Sandreas.sandberg@arm.comStaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 10412032Sandreas.sandberg@arm.comStaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 14012032Sandreas.sandberg@arm.comStaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 17612032Sandreas.sandberg@arm.comStaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 19410037SARM gem5 Developers vmsrCode = vmsrEnabledCheckCode + ''' 19510037SARM gem5 Developers MiscDest = Op1; 19610037SARM gem5 Developers ''' 19710037SARM gem5 Developers 19810037SARM gem5 Developers vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegImmOp", 19910037SARM gem5 Developers { "code": vmsrCode, 2007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2017760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2027648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 20310037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmsrIop); 20410037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmsrIop); 2057322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2067324Sgblack@eecs.umich.edu 2077644Sali.saidi@arm.com vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2087643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2097643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2107643Sgblack@eecs.umich.edu ''' 2117643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2127643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2137760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2147783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2158070SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative", 2168070SAli.Saidi@ARM.com "IsSquashAfter"]) 2177643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2187643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2197643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2207643Sgblack@eecs.umich.edu 22110037SARM gem5 Developers vmrsCode = vmrsEnabledCheckCode + ''' 22210037SARM gem5 Developers CPSR cpsr = Cpsr; 22310037SARM gem5 Developers SCR scr = Scr; 22410037SARM gem5 Developers if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 22510037SARM gem5 Developers HCR hcr = Hcr; 22610037SARM gem5 Developers bool hypTrap = false; 22712106SRekai.GonzalezAlberquilla@arm.com switch(xc->tcBase()->flattenRegId(RegId(MiscRegClass, op1)).index()) { 22810037SARM gem5 Developers case MISCREG_FPSID: 22910037SARM gem5 Developers hypTrap = hcr.tid0; 23010037SARM gem5 Developers break; 23110037SARM gem5 Developers case MISCREG_MVFR0: 23210037SARM gem5 Developers case MISCREG_MVFR1: 23310037SARM gem5 Developers hypTrap = hcr.tid3; 23410037SARM gem5 Developers break; 23510037SARM gem5 Developers } 23610037SARM gem5 Developers if (hypTrap) { 23710474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 23810037SARM gem5 Developers EC_TRAPPED_CP10_MRC_VMRS); 23910037SARM gem5 Developers } 24010037SARM gem5 Developers } 24110037SARM gem5 Developers Dest = MiscOp1; 24210037SARM gem5 Developers ''' 24310037SARM gem5 Developers 24410037SARM gem5 Developers vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegImmOp", 24510037SARM gem5 Developers { "code": vmrsCode, 2467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2477783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2487783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 24910037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmrsIop); 25010037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmrsIop); 2517324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2527333Sgblack@eecs.umich.edu 2537643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2547644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2557643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2577783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2587783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2597643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2607643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2617643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2627643Sgblack@eecs.umich.edu 26311513Sandreas.sandberg@arm.com vmrsApsrFpscrCode = vfpEnabledCheckCode + ''' 2648303SAli.Saidi@ARM.com FPSCR fpscr = FpCondCodes; 2658303SAli.Saidi@ARM.com CondCodesNZ = (fpscr.n << 1) | fpscr.z; 2668303SAli.Saidi@ARM.com CondCodesC = fpscr.c; 2678303SAli.Saidi@ARM.com CondCodesV = fpscr.v; 2687643Sgblack@eecs.umich.edu ''' 2698303SAli.Saidi@ARM.com vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", 2707643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2717760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2728303SAli.Saidi@ARM.com "op_class": "SimdFloatMiscOp" }) 2738303SAli.Saidi@ARM.com header_output += BasicDeclare.subst(vmrsApsrFpscrIop); 2748303SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); 2757643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2767643Sgblack@eecs.umich.edu 2777640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2788588Sgblack@eecs.umich.edu FpDest_uw = bits(imm, 31, 0); 2797333Sgblack@eecs.umich.edu ''' 2807396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2817333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2837760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2847396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2857396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2867333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2877333Sgblack@eecs.umich.edu 2887640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2898588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2908588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2917333Sgblack@eecs.umich.edu ''' 2927396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2937333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2967396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2977396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2987333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2997333Sgblack@eecs.umich.edu 3007640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 3018588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 3028588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 3038588Sgblack@eecs.umich.edu FpDestP2_uw = bits(imm, 31, 0); 3048588Sgblack@eecs.umich.edu FpDestP3_uw = bits(imm, 63, 32); 3057333Sgblack@eecs.umich.edu ''' 3067396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 3077333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 3087760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3097760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3107396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 3117396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 3127333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 3137333Sgblack@eecs.umich.edu 3147640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 3158588Sgblack@eecs.umich.edu FpDest_uw = FpOp1_uw; 3167333Sgblack@eecs.umich.edu ''' 3177396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 3187333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 3197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3217396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 3227396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 3237333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 3247333Sgblack@eecs.umich.edu 3257640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 3268588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3278588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3287333Sgblack@eecs.umich.edu ''' 3297396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3307333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3327760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3337396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3347396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3357333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3367333Sgblack@eecs.umich.edu 3377640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3388588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3398588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3408588Sgblack@eecs.umich.edu FpDestP2_uw = FpOp1P2_uw; 3418588Sgblack@eecs.umich.edu FpDestP3_uw = FpOp1P3_uw; 3427333Sgblack@eecs.umich.edu ''' 3437396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3447333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3457760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3467760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3477396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3487396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3497333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3507333Sgblack@eecs.umich.edu 35110037SARM gem5 Developers vmovCoreRegBCode = simdEnabledCheckCode + ''' 3528588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); 3537333Sgblack@eecs.umich.edu ''' 3547396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3557333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3577760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3587396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3597396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3607333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3617333Sgblack@eecs.umich.edu 36210037SARM gem5 Developers vmovCoreRegHCode = simdEnabledCheckCode + ''' 3638588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); 3647333Sgblack@eecs.umich.edu ''' 3657396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3667333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3677760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3687760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3697396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3707396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3717333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3727333Sgblack@eecs.umich.edu 3737640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3748588Sgblack@eecs.umich.edu FpDest_uw = Op1_uw; 3757333Sgblack@eecs.umich.edu ''' 3767396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3777333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3827333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3837333Sgblack@eecs.umich.edu 3847640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3857639Sgblack@eecs.umich.edu assert(imm < 4); 3868588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8); 3877333Sgblack@eecs.umich.edu ''' 3887396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3897333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3907760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3917760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3927396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3937396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3947333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3957333Sgblack@eecs.umich.edu 3967640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3977639Sgblack@eecs.umich.edu assert(imm < 2); 3988588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16); 3997333Sgblack@eecs.umich.edu ''' 4007396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 4017333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 4027760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4037760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4047396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 4057396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 4067333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 4077333Sgblack@eecs.umich.edu 4087640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 4097639Sgblack@eecs.umich.edu assert(imm < 4); 4108588Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8)); 4117333Sgblack@eecs.umich.edu ''' 4127396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 4137333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 4147760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4157760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4167396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 4177396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 4187333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 4197333Sgblack@eecs.umich.edu 4207640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 4217639Sgblack@eecs.umich.edu assert(imm < 2); 4228588Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16)); 4237333Sgblack@eecs.umich.edu ''' 4247396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 4257333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 4267760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4277760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4287396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 4297396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 4307333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 4317333Sgblack@eecs.umich.edu 4327640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 4338588Sgblack@eecs.umich.edu Dest = FpOp1_uw; 4347333Sgblack@eecs.umich.edu ''' 4357396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 4367333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 4377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4397396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4407396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4417333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4427333Sgblack@eecs.umich.edu 4437640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4448588Sgblack@eecs.umich.edu FpDestP0_uw = Op1_uw; 4458588Sgblack@eecs.umich.edu FpDestP1_uw = Op2_uw; 4467333Sgblack@eecs.umich.edu ''' 4477396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4487333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4497760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4507760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4517396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4527396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4537333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4547333Sgblack@eecs.umich.edu 4557640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4568588Sgblack@eecs.umich.edu Dest_uw = FpOp2P0_uw; 4578588Sgblack@eecs.umich.edu Op1_uw = FpOp2P1_uw; 4587333Sgblack@eecs.umich.edu ''' 4597396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4607333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4627760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4637396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4647396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4657333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4667381Sgblack@eecs.umich.edu}}; 4677381Sgblack@eecs.umich.edu 4687381Sgblack@eecs.umich.edulet {{ 4697381Sgblack@eecs.umich.edu 4707381Sgblack@eecs.umich.edu header_output = "" 4717381Sgblack@eecs.umich.edu decoder_output = "" 4727381Sgblack@eecs.umich.edu exec_output = "" 4737364Sgblack@eecs.umich.edu 4747783SGiacomo.Gabrielli@arm.com singleSimpleCode = vfpEnabledCheckCode + ''' 4758607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4767396Sgblack@eecs.umich.edu FpDest = %(op)s; 4777783SGiacomo.Gabrielli@arm.com ''' 4787783SGiacomo.Gabrielli@arm.com singleCode = singleSimpleCode + ''' 4797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4807364Sgblack@eecs.umich.edu ''' 48110037SARM gem5 Developers singleTernOp = vfpEnabledCheckCode + ''' 48210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 48310037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 48410037SARM gem5 Developers float cOp1 = FpOp1; 48510037SARM gem5 Developers float cOp2 = FpOp2; 48610037SARM gem5 Developers float cOp3 = FpDestP0; 48710037SARM gem5 Developers FpDestP0 = ternaryOp(fpscr, %(palam)s, %(op)s, 48810037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 48910037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 49010037SARM gem5 Developers FpscrExc = fpscr; 49110037SARM gem5 Developers ''' 4927396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4937639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4947396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4957640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4968607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4977396Sgblack@eecs.umich.edu double dest = %(op)s; 4988588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 4998588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 5007783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 5017396Sgblack@eecs.umich.edu ''' 50210037SARM gem5 Developers doubleTernOp = vfpEnabledCheckCode + ''' 50310037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 50410037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 50510037SARM gem5 Developers double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 50610037SARM gem5 Developers double cOp2 = dbl(FpOp2P0_uw, FpOp2P1_uw); 50710037SARM gem5 Developers double cOp3 = dbl(FpDestP0_uw, FpDestP1_uw); 50810037SARM gem5 Developers double cDest = ternaryOp(fpscr, %(palam)s, %(op)s, 50910037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 51010037SARM gem5 Developers FpDestP0_uw = dblLow(cDest); 51110037SARM gem5 Developers FpDestP1_uw = dblHi(cDest); 51210037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 51310037SARM gem5 Developers FpscrExc = fpscr; 51410037SARM gem5 Developers ''' 5157396Sgblack@eecs.umich.edu doubleBinOp = ''' 5168588Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 5178588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 5187639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 5197396Sgblack@eecs.umich.edu ''' 5207396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 5218588Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s, 5227396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 5237396Sgblack@eecs.umich.edu ''' 5247364Sgblack@eecs.umich.edu 52510037SARM gem5 Developers def buildTernaryFpOp(Name, base, opClass, singleOp, doubleOp, paramStr): 52610037SARM gem5 Developers global header_output, decoder_output, exec_output 52710037SARM gem5 Developers 52810037SARM gem5 Developers code = singleTernOp % { "op": singleOp, "palam": paramStr } 52910037SARM gem5 Developers sIop = InstObjParams(Name.lower() + "s", Name + "S", base, 53010037SARM gem5 Developers { "code": code, 53110037SARM gem5 Developers "predicate_test": predicateTest, 53210037SARM gem5 Developers "op_class": opClass }, []) 53310037SARM gem5 Developers code = doubleTernOp % { "op": doubleOp, "palam": paramStr } 53410037SARM gem5 Developers dIop = InstObjParams(Name.lower() + "d", Name + "D", base, 53510037SARM gem5 Developers { "code": code, 53610037SARM gem5 Developers "predicate_test": predicateTest, 53710037SARM gem5 Developers "op_class": opClass }, []) 53810037SARM gem5 Developers 53910037SARM gem5 Developers declareTempl = eval(base + "Declare"); 54010037SARM gem5 Developers constructorTempl = eval(base + "Constructor"); 54110037SARM gem5 Developers 54210037SARM gem5 Developers for iop in sIop, dIop: 54310037SARM gem5 Developers header_output += declareTempl.subst(iop) 54410037SARM gem5 Developers decoder_output += constructorTempl.subst(iop) 54510037SARM gem5 Developers exec_output += PredOpExecute.subst(iop) 54610037SARM gem5 Developers 54710037SARM gem5 Developers buildTernaryFpOp("Vfma", "FpRegRegRegOp", "SimdFloatMultAccOp", 54810037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, cOp3" ) 54910037SARM gem5 Developers buildTernaryFpOp("Vfms", "FpRegRegRegOp", "SimdFloatMultAccOp", 55010037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, cOp3" ) 55110037SARM gem5 Developers buildTernaryFpOp("Vfnma", "FpRegRegRegOp", "SimdFloatMultAccOp", 55210037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, -cOp3" ) 55310037SARM gem5 Developers buildTernaryFpOp("Vfnms", "FpRegRegRegOp", "SimdFloatMultAccOp", 55410037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, -cOp3" ) 55510037SARM gem5 Developers 5567760SGiacomo.Gabrielli@arm.com def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 5577396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5587365Sgblack@eecs.umich.edu 5597396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 5607396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5617396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5627760SGiacomo.Gabrielli@arm.com { "code": code, 5637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5647760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5657396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 5667396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5677396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5687760SGiacomo.Gabrielli@arm.com { "code": code, 5697760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5707760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5717365Sgblack@eecs.umich.edu 5727396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5737396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5747366Sgblack@eecs.umich.edu 5757396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5767396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5777396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5787396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5797366Sgblack@eecs.umich.edu 5807760SGiacomo.Gabrielli@arm.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS", 5817760SGiacomo.Gabrielli@arm.com "fpAddD") 5827760SGiacomo.Gabrielli@arm.com buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS", 5837760SGiacomo.Gabrielli@arm.com "fpSubD") 5847760SGiacomo.Gabrielli@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS", 5857760SGiacomo.Gabrielli@arm.com "fpDivD") 5867760SGiacomo.Gabrielli@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS", 5877760SGiacomo.Gabrielli@arm.com "fpMulD") 5887367Sgblack@eecs.umich.edu 5897760SGiacomo.Gabrielli@arm.com def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 5907396Sgblack@eecs.umich.edu if doubleOp is None: 5917396Sgblack@eecs.umich.edu doubleOp = singleOp 5927396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5937367Sgblack@eecs.umich.edu 5947396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 5957396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5967396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5977760SGiacomo.Gabrielli@arm.com { "code": code, 5987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5997760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6007396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 6017396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 6027396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 6037760SGiacomo.Gabrielli@arm.com { "code": code, 6047760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6057760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6067368Sgblack@eecs.umich.edu 6077396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6087396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6097368Sgblack@eecs.umich.edu 6107396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6117396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6127396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6137396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6147369Sgblack@eecs.umich.edu 6157760SGiacomo.Gabrielli@arm.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "SimdFloatSqrtOp", "sqrtf", 6167760SGiacomo.Gabrielli@arm.com "sqrt") 6177369Sgblack@eecs.umich.edu 6187760SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 6197760SGiacomo.Gabrielli@arm.com doubleOp = None): 6207396Sgblack@eecs.umich.edu if doubleOp is None: 6217396Sgblack@eecs.umich.edu doubleOp = singleOp 6227396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 6237369Sgblack@eecs.umich.edu 6247396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 6257783SGiacomo.Gabrielli@arm.com { "code": singleSimpleCode % { "op": singleOp }, 6267760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6277760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6287396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 6297396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 6307760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6317760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6327369Sgblack@eecs.umich.edu 6337396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6347396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6357396Sgblack@eecs.umich.edu 6367396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6377396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6387396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6397396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6407396Sgblack@eecs.umich.edu 6417760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", 6428588Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)") 6437760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", 6448588Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))") 64511671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintp", "VRIntP", "FpRegRegOp", "SimdFloatMiscOp", 64611671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_POSINF, false, fpscr)", 64711671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 64811671Smitch.hayenga@arm.com "FPRounding_POSINF, false, fpscr)" 64911671Smitch.hayenga@arm.com ) 65011671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintm", "VRIntM", "FpRegRegOp", "SimdFloatMiscOp", 65111671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_NEGINF, false, fpscr)", 65211671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 65311671Smitch.hayenga@arm.com "FPRounding_NEGINF, false, fpscr)" 65411671Smitch.hayenga@arm.com ) 65511671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrinta", "VRIntA", "FpRegRegOp", "SimdFloatMiscOp", 65611671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEAWAY, false, fpscr)", 65711671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 65811671Smitch.hayenga@arm.com "FPRounding_TIEAWAY, false, fpscr)" 65911671Smitch.hayenga@arm.com ) 66011671Smitch.hayenga@arm.com buildSimpleUnaryFpOp("vrintn", "VRIntN", "FpRegRegOp", "SimdFloatMiscOp", 66111671Smitch.hayenga@arm.com "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEEVEN, false, fpscr)", 66211671Smitch.hayenga@arm.com "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \ 66311671Smitch.hayenga@arm.com "FPRounding_TIEEVEN, false, fpscr)" 66411671Smitch.hayenga@arm.com ) 6657381Sgblack@eecs.umich.edu}}; 6667381Sgblack@eecs.umich.edu 6677381Sgblack@eecs.umich.edulet {{ 6687381Sgblack@eecs.umich.edu 6697381Sgblack@eecs.umich.edu header_output = "" 6707381Sgblack@eecs.umich.edu decoder_output = "" 6717381Sgblack@eecs.umich.edu exec_output = "" 6727370Sgblack@eecs.umich.edu 6737640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 6747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6757396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6767639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6777639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 6787639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6807370Sgblack@eecs.umich.edu ''' 6817396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 6827370Sgblack@eecs.umich.edu { "code": vmlaSCode, 6837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6857396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 6867396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 6877370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 6887370Sgblack@eecs.umich.edu 6897640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 6907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6918588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 6928588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 6937639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6948588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 6957639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 6967639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6978588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 6988588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 6997783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7007370Sgblack@eecs.umich.edu ''' 7017396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 7027370Sgblack@eecs.umich.edu { "code": vmlaDCode, 7037760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7047760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7057396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 7067396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 7077370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 7087370Sgblack@eecs.umich.edu 7097640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 7107783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7117396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7127639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7137639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 7147639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7167370Sgblack@eecs.umich.edu ''' 7177396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 7187370Sgblack@eecs.umich.edu { "code": vmlsSCode, 7197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7217396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 7227396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 7237370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 7247370Sgblack@eecs.umich.edu 7257640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 7267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7278588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7288588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7297639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7308588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 7317639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 7327639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7338588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7348588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7357783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7367370Sgblack@eecs.umich.edu ''' 7377396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 7387370Sgblack@eecs.umich.edu { "code": vmlsDCode, 7397760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7407760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7417396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 7427396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 7437370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 7447371Sgblack@eecs.umich.edu 7457640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 7467783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7477396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7487639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7497639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 7507639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7517783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7527371Sgblack@eecs.umich.edu ''' 7537396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 7547371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 7557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7567760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7577396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 7587396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 7597371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 7607371Sgblack@eecs.umich.edu 7617640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 7627783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7638588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7648588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7657639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7668588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 7677639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 7687639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7698588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7708588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7727371Sgblack@eecs.umich.edu ''' 7737396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 7747371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 7757760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7767760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7777396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 7787396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 7797371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 7807371Sgblack@eecs.umich.edu 7817640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 7827783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7837396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7847639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7857639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 7867639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7877783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7887371Sgblack@eecs.umich.edu ''' 7897396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 7907760SGiacomo.Gabrielli@arm.com { "code": vnmlsSCode, 7917760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7927760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7937396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 7947396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 7957371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7967371Sgblack@eecs.umich.edu 7977640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 7987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7998588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 8008588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 8017639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 8028588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 8037639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 8047639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 8058588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 8068588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 8077783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8087371Sgblack@eecs.umich.edu ''' 8097396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 8107760SGiacomo.Gabrielli@arm.com { "code": vnmlsDCode, 8117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8127760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 8137396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 8147396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 8157371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 8167371Sgblack@eecs.umich.edu 8177640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 8187783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8197639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 8207639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 8217783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8227371Sgblack@eecs.umich.edu ''' 8237396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 8247760SGiacomo.Gabrielli@arm.com { "code": vnmulSCode, 8257760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8267760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8277396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 8287396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 8297371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 8307371Sgblack@eecs.umich.edu 8317640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 8327783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8338588Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 8348588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 8357639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 8367639Sgblack@eecs.umich.edu fpscr.rMode); 8378588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 8388588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 8397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8407371Sgblack@eecs.umich.edu ''' 8417396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 8427371Sgblack@eecs.umich.edu { "code": vnmulDCode, 8437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8457396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 8467396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 8477371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 8487381Sgblack@eecs.umich.edu}}; 8497381Sgblack@eecs.umich.edu 8507381Sgblack@eecs.umich.edulet {{ 8517381Sgblack@eecs.umich.edu 8527381Sgblack@eecs.umich.edu header_output = "" 8537381Sgblack@eecs.umich.edu decoder_output = "" 8547381Sgblack@eecs.umich.edu exec_output = "" 8557373Sgblack@eecs.umich.edu 8567640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 8577783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8587397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8598588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 8608588Sgblack@eecs.umich.edu FpDest = FpOp1_uw; 8617381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8627639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8637783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8647373Sgblack@eecs.umich.edu ''' 8657396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 8667373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 8677760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8687760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8697396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 8707396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 8717373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 8727373Sgblack@eecs.umich.edu 8737640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 8747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8757397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8768588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_uw) : "m" (FpOp1P0_uw)); 8778588Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0_uw; 8787397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8797639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8808588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 8818588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 8827783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8837373Sgblack@eecs.umich.edu ''' 8847396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 8857373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 8867760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8877760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8887396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 8897396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 8907373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 8917373Sgblack@eecs.umich.edu 8927640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 8937783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8947397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8958588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 8968588Sgblack@eecs.umich.edu FpDest = FpOp1_sw; 8977381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8987639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8997783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9007373Sgblack@eecs.umich.edu ''' 9017396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 9027373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 9037760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9047760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9057396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 9067396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 9077373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 9087373Sgblack@eecs.umich.edu 9097640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 9107783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9117397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9128588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_sw) : "m" (FpOp1P0_sw)); 9138588Sgblack@eecs.umich.edu double cDest = FpOp1P0_sw; 9147397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 9157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9168588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 9178588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 9187783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9197373Sgblack@eecs.umich.edu ''' 9207396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 9217373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 9227760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9237760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9247396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 9257396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 9267373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 9277373Sgblack@eecs.umich.edu 9287640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 9297783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9317397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9327381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 93310037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0, false); 9348588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 9357639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9367783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9377380Sgblack@eecs.umich.edu ''' 9387396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 9397380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 9407760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9417760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9427396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 9437396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 9447380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 9457380Sgblack@eecs.umich.edu 9467640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 9477783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9488588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9497397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9507397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9517397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 95210037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0, false); 9537381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9547639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9558588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9567783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9577380Sgblack@eecs.umich.edu ''' 9587396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 9597380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 9607760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9617760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9627396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 9637396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 9647380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 9657380Sgblack@eecs.umich.edu 9667640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 9677783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9687397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9697397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9707381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 97110037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0, false); 9728588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 9737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9757380Sgblack@eecs.umich.edu ''' 9767396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 9777380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 9787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 9817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 9827380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 9837380Sgblack@eecs.umich.edu 9847640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 9857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9868588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9877397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9887397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9897397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 99010037SARM gem5 Developers int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0, false); 9917381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9927639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9938588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9947783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9957380Sgblack@eecs.umich.edu ''' 9967396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 9977380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 9987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10007396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 10017396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 10027380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 10037380Sgblack@eecs.umich.edu 10047640Sgblack@eecs.umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 10057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10067397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10077397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10087380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10097381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 101010037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0); 10118588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 10127639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10147373Sgblack@eecs.umich.edu ''' 10157396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 10167373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 10177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10197396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 10207396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 10217373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 10227373Sgblack@eecs.umich.edu 10237640Sgblack@eecs.umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 10247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10258588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10267397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10277397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10287380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10297397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 103010037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0); 10317381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10327639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10338588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10357373Sgblack@eecs.umich.edu ''' 10367396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 10377373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 10387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10397760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10407396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 10417396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 10427373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 10437373Sgblack@eecs.umich.edu 10447640Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 10457783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10467397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10477397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10487380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10497381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 105010037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0); 10518588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 10527639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10537783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10547373Sgblack@eecs.umich.edu ''' 10557396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 10567373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 10577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10597396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 10607396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 10617373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 10627373Sgblack@eecs.umich.edu 10637640Sgblack@eecs.umich.edu vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 10647783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10658588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10677397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10687380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10697397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 107010037SARM gem5 Developers int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0); 10717381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10727639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10738588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10757373Sgblack@eecs.umich.edu ''' 10767396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 10777373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 10787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 10817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 10827373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 10837374Sgblack@eecs.umich.edu 10847640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 10857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10867397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10877397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10887381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10897783SGiacomo.Gabrielli@arm.com double cDest = fixFpSFpDDest(FpscrExc, FpOp1); 10907397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 10917639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10928588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 10938588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 10947783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10957374Sgblack@eecs.umich.edu ''' 10967396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 10977374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 10987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11007396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 11017396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 11027374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 11037374Sgblack@eecs.umich.edu 11047640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 11057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11068588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 11077397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 11087397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11097397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 11107783SGiacomo.Gabrielli@arm.com FpDest = fixFpDFpSDest(FpscrExc, cOp1); 11117381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11127639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11147374Sgblack@eecs.umich.edu ''' 11157396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 11167374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 11177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11197396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 11207396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 11217374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 11227377Sgblack@eecs.umich.edu 11237640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 11247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11257398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11267398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11277398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11287639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 11297639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 11307398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11317639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11327783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11337398Sgblack@eecs.umich.edu ''' 11347398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 11357398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 11367760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11377760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11387398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 11397398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 11407398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 11417398Sgblack@eecs.umich.edu 11427640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 11437783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11447398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11457398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11467639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 11477639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 11487398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11497639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11507783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11517398Sgblack@eecs.umich.edu ''' 11527398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 11537398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 11547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11557760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11567398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 11577398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 11587398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 11597398Sgblack@eecs.umich.edu 11607640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 11617783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11627398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11637398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11648588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 11658588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 11668588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 31, 16,, 11677639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 11687639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 11698588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 11707639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11727398Sgblack@eecs.umich.edu ''' 11737398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 11747398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 11757760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11767760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11777398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 11787398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 11797398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 11807398Sgblack@eecs.umich.edu 11817640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 11827783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11837398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11847398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11858588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 11868588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 11878588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 15, 0, 11887639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 11897639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 11908588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 11917639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11927783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11937398Sgblack@eecs.umich.edu ''' 11947398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 11957398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 11967760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11977760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11987398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 11997398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 12007398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 12017398Sgblack@eecs.umich.edu 12027640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 12037783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12047397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 12057377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 12067377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12077377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 12087377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12097377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 12107377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12117377Sgblack@eecs.umich.edu } else { 12127389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 12137389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 12147396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 12157389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 12167396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 12177389Sgblack@eecs.umich.edu if (signal1 || signal2) 12187389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12197377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12207377Sgblack@eecs.umich.edu } 12217643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12227783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12237377Sgblack@eecs.umich.edu ''' 12247396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 12257377Sgblack@eecs.umich.edu { "code": vcmpSCode, 12267760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12277760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12287396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 12297396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 12307377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 12317377Sgblack@eecs.umich.edu 12327640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 12338588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 12348588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 12357783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12367397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 12377397Sgblack@eecs.umich.edu if (cDest == cOp1) { 12387377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12397397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 12407377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12417397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 12427377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12437377Sgblack@eecs.umich.edu } else { 12447389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12457397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 12467397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 12477397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 12487397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 12497389Sgblack@eecs.umich.edu if (signal1 || signal2) 12507389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12517377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12527377Sgblack@eecs.umich.edu } 12537643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12547783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12557377Sgblack@eecs.umich.edu ''' 12567396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 12577377Sgblack@eecs.umich.edu { "code": vcmpDCode, 12587760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12597760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12607396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 12617396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 12627377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 12637377Sgblack@eecs.umich.edu 12647640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 12657783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 12677389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12687389Sgblack@eecs.umich.edu assert(imm == 0); 12697377Sgblack@eecs.umich.edu if (FpDest == imm) { 12707377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12717377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12727377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12737377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12747377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12757377Sgblack@eecs.umich.edu } else { 12767389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 12777389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 12787396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 12797389Sgblack@eecs.umich.edu if (signal) 12807389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12817377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12827377Sgblack@eecs.umich.edu } 12837643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12847783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12857377Sgblack@eecs.umich.edu ''' 12867396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 12877377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 12887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12897760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12907396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 12917396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 12927377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 12937377Sgblack@eecs.umich.edu 12947640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 12957389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12967389Sgblack@eecs.umich.edu assert(imm == 0); 12978588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 12987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12997397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 13007397Sgblack@eecs.umich.edu if (cDest == imm) { 13017377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13027397Sgblack@eecs.umich.edu } else if (cDest < imm) { 13037377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13047397Sgblack@eecs.umich.edu } else if (cDest > imm) { 13057377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13067377Sgblack@eecs.umich.edu } else { 13077389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 13087397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 13097397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 13107389Sgblack@eecs.umich.edu if (signal) 13117389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13127377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13137377Sgblack@eecs.umich.edu } 13147643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13167377Sgblack@eecs.umich.edu ''' 13177396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 13187377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 13197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13217396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 13227396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 13237377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 13247389Sgblack@eecs.umich.edu 13257640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 13267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13277397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 13287389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 13297389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13307389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 13317389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13327389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 13337389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13347389Sgblack@eecs.umich.edu } else { 13357389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13367389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13377389Sgblack@eecs.umich.edu } 13387643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13407389Sgblack@eecs.umich.edu ''' 13417396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 13427389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 13437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13457396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 13467396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 13477389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 13487389Sgblack@eecs.umich.edu 13497640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 13508588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 13518588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 13527783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13537397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 13547397Sgblack@eecs.umich.edu if (cDest == cOp1) { 13557389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13567397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 13577389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13587397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 13597389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13607389Sgblack@eecs.umich.edu } else { 13617389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13627389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13637389Sgblack@eecs.umich.edu } 13647643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13657783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13667389Sgblack@eecs.umich.edu ''' 13677396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 13687389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 13697760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13707760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13717396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 13727396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 13737389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 13747389Sgblack@eecs.umich.edu 13757640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 13767783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13777397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 13787389Sgblack@eecs.umich.edu if (FpDest == imm) { 13797389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13807389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 13817389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13827389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 13837389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13847389Sgblack@eecs.umich.edu } else { 13857389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13867389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13877389Sgblack@eecs.umich.edu } 13887643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13897783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13907389Sgblack@eecs.umich.edu ''' 13917396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 13927389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 13937760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13947760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13957396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 13967396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 13977389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 13987389Sgblack@eecs.umich.edu 13997640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 14008588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 14017783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14027397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 14037397Sgblack@eecs.umich.edu if (cDest == imm) { 14047389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 14057397Sgblack@eecs.umich.edu } else if (cDest < imm) { 14067389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 14077397Sgblack@eecs.umich.edu } else if (cDest > imm) { 14087389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 14097389Sgblack@eecs.umich.edu } else { 14107389Sgblack@eecs.umich.edu fpscr.ioc = 1; 14117389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 14127389Sgblack@eecs.umich.edu } 14137643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 14147783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14157389Sgblack@eecs.umich.edu ''' 14167396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 14177389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 14187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14197760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 14207396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 14217396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 14227389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 14237322Sgblack@eecs.umich.edu}}; 14247379Sgblack@eecs.umich.edu 14257379Sgblack@eecs.umich.edulet {{ 14267379Sgblack@eecs.umich.edu 14277379Sgblack@eecs.umich.edu header_output = "" 14287379Sgblack@eecs.umich.edu decoder_output = "" 14297379Sgblack@eecs.umich.edu exec_output = "" 14307379Sgblack@eecs.umich.edu 143111671Smitch.hayenga@arm.com vselSCode = vfpEnabledCheckCode + ''' 143211671Smitch.hayenga@arm.com if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) { 143311671Smitch.hayenga@arm.com FpDest = FpOp1; 143411671Smitch.hayenga@arm.com } else { 143511671Smitch.hayenga@arm.com FpDest = FpOp2; 143611671Smitch.hayenga@arm.com } ''' 143711671Smitch.hayenga@arm.com 143811671Smitch.hayenga@arm.com vselSIop = InstObjParams("vsels", "VselS", "FpRegRegRegCondOp", 143911671Smitch.hayenga@arm.com { "code" : vselSCode, 144011671Smitch.hayenga@arm.com "predicate_test" : predicateTest, 144111671Smitch.hayenga@arm.com "op_class" : "SimdFloatCmpOp" }, [] ) 144211671Smitch.hayenga@arm.com header_output += FpRegRegRegCondOpDeclare.subst(vselSIop); 144311671Smitch.hayenga@arm.com decoder_output += FpRegRegRegCondOpConstructor.subst(vselSIop); 144411671Smitch.hayenga@arm.com exec_output += PredOpExecute.subst(vselSIop); 144511671Smitch.hayenga@arm.com 144611671Smitch.hayenga@arm.com vselDCode = vfpEnabledCheckCode + ''' 144711671Smitch.hayenga@arm.com if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) { 144811671Smitch.hayenga@arm.com FpDestP0_uw = FpOp1P0_uw; 144911671Smitch.hayenga@arm.com FpDestP1_uw = FpOp1P1_uw; 145011671Smitch.hayenga@arm.com } else { 145111671Smitch.hayenga@arm.com FpDestP0_uw = FpOp2P0_uw; 145211671Smitch.hayenga@arm.com FpDestP1_uw = FpOp2P1_uw; 145311671Smitch.hayenga@arm.com } ''' 145411671Smitch.hayenga@arm.com 145511671Smitch.hayenga@arm.com vselDIop = InstObjParams("vseld", "VselD", "FpRegRegRegCondOp", 145611671Smitch.hayenga@arm.com { "code" : vselDCode, 145711671Smitch.hayenga@arm.com "predicate_test" : predicateTest, 145811671Smitch.hayenga@arm.com "op_class" : "SimdFloatCmpOp" }, [] ) 145911671Smitch.hayenga@arm.com header_output += FpRegRegRegCondOpDeclare.subst(vselDIop); 146011671Smitch.hayenga@arm.com decoder_output += FpRegRegRegCondOpConstructor.subst(vselDIop); 146111671Smitch.hayenga@arm.com exec_output += PredOpExecute.subst(vselDIop); 146211671Smitch.hayenga@arm.com}}; 146311671Smitch.hayenga@arm.com 146411671Smitch.hayenga@arm.com 146511671Smitch.hayenga@arm.comlet {{ 146611671Smitch.hayenga@arm.com 146711671Smitch.hayenga@arm.com header_output = "" 146811671Smitch.hayenga@arm.com decoder_output = "" 146911671Smitch.hayenga@arm.com exec_output = "" 147011671Smitch.hayenga@arm.com 14717640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 14727783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14737397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14747397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14757381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 147610037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, imm); 14778588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 14787639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14807379Sgblack@eecs.umich.edu ''' 14817396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 14827379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 14837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14857396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 14867396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 14877379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 14887379Sgblack@eecs.umich.edu 14897640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 14907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14918588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 14927397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14937397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14947397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 149510037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, true, 32, imm); 14967381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 14977639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14988588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 14998588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 15007783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15017379Sgblack@eecs.umich.edu ''' 15027396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 15037379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 15047760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15057760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15067396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 15077396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 15087379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 15097379Sgblack@eecs.umich.edu 15107640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 15117783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15127397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15137397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15147381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 151510037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, imm); 15168588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 15177639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15187783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15197379Sgblack@eecs.umich.edu ''' 15207396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 15217379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 15227760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15237760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15247396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 15257396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 15267379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 15277379Sgblack@eecs.umich.edu 15287640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 15297783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15308588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 15317397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15327397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15337397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 153410037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 32, imm); 15357381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 15367639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15378588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 15388588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 15397783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15407379Sgblack@eecs.umich.edu ''' 15417396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 15427379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 15437760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15447760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15457396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 15467396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 15477379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 15487379Sgblack@eecs.umich.edu 15497640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 15507783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15517397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15528588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 155310037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, 32, imm); 15547381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15557639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15567783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15577379Sgblack@eecs.umich.edu ''' 15587396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 15597379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 15607760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15617760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15627396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 15637396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 15647379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 15657379Sgblack@eecs.umich.edu 15667640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 15677783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15688588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 15697397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15707381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 157110037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 15727397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15737639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15748588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 15758588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 15767783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15777379Sgblack@eecs.umich.edu ''' 15787396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 15797379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 15807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15817760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15827396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 15837396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 15847379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 15857379Sgblack@eecs.umich.edu 15867640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 15877783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15887397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15898588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 159010037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, 32, imm); 15917381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15927639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15937783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15947379Sgblack@eecs.umich.edu ''' 15957396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 15967379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 15977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15987760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15997396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 16007396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 16017379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 16027379Sgblack@eecs.umich.edu 16037640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 16047783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16058588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 16067397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16077381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 160810037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 16097397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16107639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16118588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 16128588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 16137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16147379Sgblack@eecs.umich.edu ''' 16157396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 16167379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 16177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16197396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 16207396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 16217379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 16227379Sgblack@eecs.umich.edu 16237640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 16247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16257397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 16267397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16277381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 162810037SARM gem5 Developers FpDest_sh = vfpFpToFixed<float>(FpOp1, true, 16, imm); 16298588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sh)); 16307639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16317783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16327379Sgblack@eecs.umich.edu ''' 16337379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 16347396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16357379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 16367760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16377760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16387396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 16397396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 16407379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 16417379Sgblack@eecs.umich.edu 16427640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 16437783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16448588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 16457397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 16467397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16477397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 164810037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, true, 16, imm); 16497381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 16507639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16518588Sgblack@eecs.umich.edu FpDestP0_uw = result; 16528588Sgblack@eecs.umich.edu FpDestP1_uw = result >> 32; 16537783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16547379Sgblack@eecs.umich.edu ''' 16557379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 16567396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16577379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 16587760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16597760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16607396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 16617396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 16627379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 16637379Sgblack@eecs.umich.edu 16647640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 16657783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 16677397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16687381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 166910037SARM gem5 Developers FpDest_uh = vfpFpToFixed<float>(FpOp1, false, 16, imm); 16708588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uh)); 16717639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16727783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16737379Sgblack@eecs.umich.edu ''' 16747379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 16757396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16767379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 16777760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16787760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16797396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 16807396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 16817379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 16827379Sgblack@eecs.umich.edu 16837640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 16847783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16858588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 16867397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 16877397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16887397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 168910037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 16, imm); 16907381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 16917639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16928588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 16938588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 16947783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16957379Sgblack@eecs.umich.edu ''' 16967379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 16977396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16987379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 16997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17017396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 17027396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 17037379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 17047379Sgblack@eecs.umich.edu 17057640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 17067783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17077397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17088588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh)); 170910037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, 16, imm); 17107381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 17117639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17127783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17137379Sgblack@eecs.umich.edu ''' 17147379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 17157396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17167379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 17177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17197396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 17207396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 17217379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 17227379Sgblack@eecs.umich.edu 17237640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 17247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17258588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 17267397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17277381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 172810037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 17297397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 17307639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17318588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 17328588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 17337783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17347379Sgblack@eecs.umich.edu ''' 17357379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 17367396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17377379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 17387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17397760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17407396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 17417396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 17427379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 17437379Sgblack@eecs.umich.edu 17447640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 17457783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17467397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17478588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh)); 174810037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, 16, imm); 17497381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 17507639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17517783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17527379Sgblack@eecs.umich.edu ''' 17537379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 17547396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17557379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 17567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17577760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17587396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 17597396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 17607379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 17617379Sgblack@eecs.umich.edu 17627640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 17637783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17648588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 17657397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17667381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 176710037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 17687397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 17697639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17708588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 17718588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 17727783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17737379Sgblack@eecs.umich.edu ''' 17747379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 17757396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17767379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 17777760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17787760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17797396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 17807396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 17817379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 17827379Sgblack@eecs.umich.edu}}; 1783