fp.isa revision 10474
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 310037SARM gem5 Developers// Copyright (c) 2010-2013 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247322Sgblack@eecs.umich.edu// this software without specific prior written permission. 257322Sgblack@eecs.umich.edu// 267322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377322Sgblack@eecs.umich.edu// 387322Sgblack@eecs.umich.edu// Authors: Gabe Black 397322Sgblack@eecs.umich.edu 407376Sgblack@eecs.umich.eduoutput header {{ 417376Sgblack@eecs.umich.edu 427376Sgblack@eecs.umich.edutemplate <class Micro> 437376Sgblack@eecs.umich.educlass VfpMacroRegRegOp : public VfpMacroOp 447376Sgblack@eecs.umich.edu{ 457376Sgblack@eecs.umich.edu public: 467376Sgblack@eecs.umich.edu VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 477376Sgblack@eecs.umich.edu IntRegIndex _op1, bool _wide) : 487376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 497376Sgblack@eecs.umich.edu { 507376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 517376Sgblack@eecs.umich.edu assert(numMicroops > 1); 527376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 537376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 547376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 557376Sgblack@eecs.umich.edu if (i == 0) 567376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 577376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 587376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 597376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, mode); 607376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 617376Sgblack@eecs.umich.edu } 627376Sgblack@eecs.umich.edu } 637376Sgblack@eecs.umich.edu 647376Sgblack@eecs.umich.edu %(BasicExecPanic)s 657376Sgblack@eecs.umich.edu}; 667376Sgblack@eecs.umich.edu 677376Sgblack@eecs.umich.edutemplate <class VfpOp> 687376Sgblack@eecs.umich.edustatic StaticInstPtr 697376Sgblack@eecs.umich.edudecodeVfpRegRegOp(ExtMachInst machInst, 707376Sgblack@eecs.umich.edu IntRegIndex dest, IntRegIndex op1, bool wide) 717376Sgblack@eecs.umich.edu{ 727376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 737376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1); 747376Sgblack@eecs.umich.edu } else { 757376Sgblack@eecs.umich.edu return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 767376Sgblack@eecs.umich.edu } 777376Sgblack@eecs.umich.edu} 787376Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edutemplate <class Micro> 807376Sgblack@eecs.umich.educlass VfpMacroRegImmOp : public VfpMacroOp 817376Sgblack@eecs.umich.edu{ 827376Sgblack@eecs.umich.edu public: 837376Sgblack@eecs.umich.edu VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 847376Sgblack@eecs.umich.edu bool _wide) : 857376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 887376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 897376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 907376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 917376Sgblack@eecs.umich.edu if (i == 0) 927376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 937376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 947376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 957376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _imm, mode); 967376Sgblack@eecs.umich.edu nextIdxs(_dest); 977376Sgblack@eecs.umich.edu } 987376Sgblack@eecs.umich.edu } 997376Sgblack@eecs.umich.edu 1007376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1017376Sgblack@eecs.umich.edu}; 1027376Sgblack@eecs.umich.edu 1037376Sgblack@eecs.umich.edutemplate <class VfpOp> 1047376Sgblack@eecs.umich.edustatic StaticInstPtr 1057376Sgblack@eecs.umich.edudecodeVfpRegImmOp(ExtMachInst machInst, 1067376Sgblack@eecs.umich.edu IntRegIndex dest, uint64_t imm, bool wide) 1077376Sgblack@eecs.umich.edu{ 1087376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1097376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, imm); 1107376Sgblack@eecs.umich.edu } else { 1117376Sgblack@eecs.umich.edu return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 1127376Sgblack@eecs.umich.edu } 1137376Sgblack@eecs.umich.edu} 1147376Sgblack@eecs.umich.edu 1157376Sgblack@eecs.umich.edutemplate <class Micro> 1167376Sgblack@eecs.umich.educlass VfpMacroRegRegImmOp : public VfpMacroOp 1177376Sgblack@eecs.umich.edu{ 1187376Sgblack@eecs.umich.edu public: 1197376Sgblack@eecs.umich.edu VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 1207376Sgblack@eecs.umich.edu IntRegIndex _op1, uint64_t _imm, bool _wide) : 1217376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1247376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1257376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1267376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1277376Sgblack@eecs.umich.edu if (i == 0) 1287376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1297376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1307376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1317376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 1327376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1); 1337376Sgblack@eecs.umich.edu } 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu 1367376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1377376Sgblack@eecs.umich.edu}; 1387376Sgblack@eecs.umich.edu 1397376Sgblack@eecs.umich.edutemplate <class VfpOp> 1407376Sgblack@eecs.umich.edustatic StaticInstPtr 1417376Sgblack@eecs.umich.edudecodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 1427376Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm, bool wide) 1437376Sgblack@eecs.umich.edu{ 1447376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1457376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, imm); 1467376Sgblack@eecs.umich.edu } else { 1477376Sgblack@eecs.umich.edu return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 1487376Sgblack@eecs.umich.edu } 1497376Sgblack@eecs.umich.edu} 1507376Sgblack@eecs.umich.edu 1517376Sgblack@eecs.umich.edutemplate <class Micro> 1527376Sgblack@eecs.umich.educlass VfpMacroRegRegRegOp : public VfpMacroOp 1537376Sgblack@eecs.umich.edu{ 1547376Sgblack@eecs.umich.edu public: 1557376Sgblack@eecs.umich.edu VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 1567376Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 1577376Sgblack@eecs.umich.edu VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 1587376Sgblack@eecs.umich.edu { 1597376Sgblack@eecs.umich.edu numMicroops = machInst.fpscrLen + 1; 1607376Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1617376Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops; i++) { 1627376Sgblack@eecs.umich.edu VfpMicroMode mode = VfpMicroop; 1637376Sgblack@eecs.umich.edu if (i == 0) 1647376Sgblack@eecs.umich.edu mode = VfpFirstMicroop; 1657376Sgblack@eecs.umich.edu else if (i == numMicroops - 1) 1667376Sgblack@eecs.umich.edu mode = VfpLastMicroop; 1677376Sgblack@eecs.umich.edu microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 1687376Sgblack@eecs.umich.edu nextIdxs(_dest, _op1, _op2); 1697376Sgblack@eecs.umich.edu } 1707376Sgblack@eecs.umich.edu } 1717376Sgblack@eecs.umich.edu 1727376Sgblack@eecs.umich.edu %(BasicExecPanic)s 1737376Sgblack@eecs.umich.edu}; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edutemplate <class VfpOp> 1767376Sgblack@eecs.umich.edustatic StaticInstPtr 1777376Sgblack@eecs.umich.edudecodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 1787376Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2, bool wide) 1797376Sgblack@eecs.umich.edu{ 1807376Sgblack@eecs.umich.edu if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 1817376Sgblack@eecs.umich.edu return new VfpOp(machInst, dest, op1, op2); 1827376Sgblack@eecs.umich.edu } else { 1837376Sgblack@eecs.umich.edu return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu} 1867376Sgblack@eecs.umich.edu}}; 1877376Sgblack@eecs.umich.edu 1887322Sgblack@eecs.umich.edulet {{ 1897322Sgblack@eecs.umich.edu 1907322Sgblack@eecs.umich.edu header_output = "" 1917322Sgblack@eecs.umich.edu decoder_output = "" 1927322Sgblack@eecs.umich.edu exec_output = "" 1937322Sgblack@eecs.umich.edu 19410037SARM gem5 Developers vmsrCode = vmsrEnabledCheckCode + ''' 19510037SARM gem5 Developers MiscDest = Op1; 19610037SARM gem5 Developers ''' 19710037SARM gem5 Developers 19810037SARM gem5 Developers vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegImmOp", 19910037SARM gem5 Developers { "code": vmsrCode, 2007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2017760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2027648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 20310037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmsrIop); 20410037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmsrIop); 2057322Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrIop); 2067324Sgblack@eecs.umich.edu 2077644Sali.saidi@arm.com vmsrFpscrCode = vmsrEnabledCheckCode + ''' 2087643Sgblack@eecs.umich.edu Fpscr = Op1 & ~FpCondCodesMask; 2097643Sgblack@eecs.umich.edu FpCondCodes = Op1 & FpCondCodesMask; 2107643Sgblack@eecs.umich.edu ''' 2117643Sgblack@eecs.umich.edu vmsrFpscrIop = InstObjParams("vmsr", "VmsrFpscr", "FpRegRegOp", 2127643Sgblack@eecs.umich.edu { "code": vmsrFpscrCode, 2137760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2147783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2158070SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative", 2168070SAli.Saidi@ARM.com "IsSquashAfter"]) 2177643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); 2187643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); 2197643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmsrFpscrIop); 2207643Sgblack@eecs.umich.edu 22110037SARM gem5 Developers vmrsCode = vmrsEnabledCheckCode + ''' 22210037SARM gem5 Developers CPSR cpsr = Cpsr; 22310037SARM gem5 Developers SCR scr = Scr; 22410037SARM gem5 Developers if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 22510037SARM gem5 Developers HCR hcr = Hcr; 22610037SARM gem5 Developers bool hypTrap = false; 22710037SARM gem5 Developers switch(xc->tcBase()->flattenMiscIndex(op1)) { 22810037SARM gem5 Developers case MISCREG_FPSID: 22910037SARM gem5 Developers hypTrap = hcr.tid0; 23010037SARM gem5 Developers break; 23110037SARM gem5 Developers case MISCREG_MVFR0: 23210037SARM gem5 Developers case MISCREG_MVFR1: 23310037SARM gem5 Developers hypTrap = hcr.tid3; 23410037SARM gem5 Developers break; 23510037SARM gem5 Developers } 23610037SARM gem5 Developers if (hypTrap) { 23710474Sandreas.hansson@arm.com return std::make_shared<HypervisorTrap>(machInst, imm, 23810037SARM gem5 Developers EC_TRAPPED_CP10_MRC_VMRS); 23910037SARM gem5 Developers } 24010037SARM gem5 Developers } 24110037SARM gem5 Developers Dest = MiscOp1; 24210037SARM gem5 Developers ''' 24310037SARM gem5 Developers 24410037SARM gem5 Developers vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegImmOp", 24510037SARM gem5 Developers { "code": vmrsCode, 2467760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2477783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2487783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 24910037SARM gem5 Developers header_output += FpRegRegImmOpDeclare.subst(vmrsIop); 25010037SARM gem5 Developers decoder_output += FpRegRegImmOpConstructor.subst(vmrsIop); 2517324Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsIop); 2527333Sgblack@eecs.umich.edu 2537643Sgblack@eecs.umich.edu vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", 2547644Sali.saidi@arm.com { "code": vmrsEnabledCheckCode + \ 2557643Sgblack@eecs.umich.edu "Dest = Fpscr | FpCondCodes;", 2567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2577783SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, 2587783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 2597643Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); 2607643Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); 2617643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsFpscrIop); 2627643Sgblack@eecs.umich.edu 2638303SAli.Saidi@ARM.com vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + ''' 2648303SAli.Saidi@ARM.com FPSCR fpscr = FpCondCodes; 2658303SAli.Saidi@ARM.com CondCodesNZ = (fpscr.n << 1) | fpscr.z; 2668303SAli.Saidi@ARM.com CondCodesC = fpscr.c; 2678303SAli.Saidi@ARM.com CondCodesV = fpscr.v; 2687643Sgblack@eecs.umich.edu ''' 2698303SAli.Saidi@ARM.com vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", 2707643Sgblack@eecs.umich.edu { "code": vmrsApsrFpscrCode, 2717760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2728303SAli.Saidi@ARM.com "op_class": "SimdFloatMiscOp" }) 2738303SAli.Saidi@ARM.com header_output += BasicDeclare.subst(vmrsApsrFpscrIop); 2748303SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); 2757643Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); 2767643Sgblack@eecs.umich.edu 2777640Sgblack@eecs.umich.edu vmovImmSCode = vfpEnabledCheckCode + ''' 2788588Sgblack@eecs.umich.edu FpDest_uw = bits(imm, 31, 0); 2797333Sgblack@eecs.umich.edu ''' 2807396Sgblack@eecs.umich.edu vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", 2817333Sgblack@eecs.umich.edu { "code": vmovImmSCode, 2827760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2837760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2847396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmSIop); 2857396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmSIop); 2867333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmSIop); 2877333Sgblack@eecs.umich.edu 2887640Sgblack@eecs.umich.edu vmovImmDCode = vfpEnabledCheckCode + ''' 2898588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 2908588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 2917333Sgblack@eecs.umich.edu ''' 2927396Sgblack@eecs.umich.edu vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", 2937333Sgblack@eecs.umich.edu { "code": vmovImmDCode, 2947760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 2957760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 2967396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmDIop); 2977396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmDIop); 2987333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmDIop); 2997333Sgblack@eecs.umich.edu 3007640Sgblack@eecs.umich.edu vmovImmQCode = vfpEnabledCheckCode + ''' 3018588Sgblack@eecs.umich.edu FpDestP0_uw = bits(imm, 31, 0); 3028588Sgblack@eecs.umich.edu FpDestP1_uw = bits(imm, 63, 32); 3038588Sgblack@eecs.umich.edu FpDestP2_uw = bits(imm, 31, 0); 3048588Sgblack@eecs.umich.edu FpDestP3_uw = bits(imm, 63, 32); 3057333Sgblack@eecs.umich.edu ''' 3067396Sgblack@eecs.umich.edu vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", 3077333Sgblack@eecs.umich.edu { "code": vmovImmQCode, 3087760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3097760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3107396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vmovImmQIop); 3117396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vmovImmQIop); 3127333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovImmQIop); 3137333Sgblack@eecs.umich.edu 3147640Sgblack@eecs.umich.edu vmovRegSCode = vfpEnabledCheckCode + ''' 3158588Sgblack@eecs.umich.edu FpDest_uw = FpOp1_uw; 3167333Sgblack@eecs.umich.edu ''' 3177396Sgblack@eecs.umich.edu vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", 3187333Sgblack@eecs.umich.edu { "code": vmovRegSCode, 3197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3217396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegSIop); 3227396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegSIop); 3237333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegSIop); 3247333Sgblack@eecs.umich.edu 3257640Sgblack@eecs.umich.edu vmovRegDCode = vfpEnabledCheckCode + ''' 3268588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3278588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3287333Sgblack@eecs.umich.edu ''' 3297396Sgblack@eecs.umich.edu vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", 3307333Sgblack@eecs.umich.edu { "code": vmovRegDCode, 3317760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3327760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3337396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegDIop); 3347396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegDIop); 3357333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegDIop); 3367333Sgblack@eecs.umich.edu 3377640Sgblack@eecs.umich.edu vmovRegQCode = vfpEnabledCheckCode + ''' 3388588Sgblack@eecs.umich.edu FpDestP0_uw = FpOp1P0_uw; 3398588Sgblack@eecs.umich.edu FpDestP1_uw = FpOp1P1_uw; 3408588Sgblack@eecs.umich.edu FpDestP2_uw = FpOp1P2_uw; 3418588Sgblack@eecs.umich.edu FpDestP3_uw = FpOp1P3_uw; 3427333Sgblack@eecs.umich.edu ''' 3437396Sgblack@eecs.umich.edu vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", 3447333Sgblack@eecs.umich.edu { "code": vmovRegQCode, 3457760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3467760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3477396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegQIop); 3487396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegQIop); 3497333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegQIop); 3507333Sgblack@eecs.umich.edu 35110037SARM gem5 Developers vmovCoreRegBCode = simdEnabledCheckCode + ''' 3528588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub); 3537333Sgblack@eecs.umich.edu ''' 3547396Sgblack@eecs.umich.edu vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", 3557333Sgblack@eecs.umich.edu { "code": vmovCoreRegBCode, 3567760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3577760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3587396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 3597396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 3607333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegBIop); 3617333Sgblack@eecs.umich.edu 36210037SARM gem5 Developers vmovCoreRegHCode = simdEnabledCheckCode + ''' 3638588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh); 3647333Sgblack@eecs.umich.edu ''' 3657396Sgblack@eecs.umich.edu vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", 3667333Sgblack@eecs.umich.edu { "code": vmovCoreRegHCode, 3677760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3687760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3697396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 3707396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 3717333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegHIop); 3727333Sgblack@eecs.umich.edu 3737640Sgblack@eecs.umich.edu vmovCoreRegWCode = vfpEnabledCheckCode + ''' 3748588Sgblack@eecs.umich.edu FpDest_uw = Op1_uw; 3757333Sgblack@eecs.umich.edu ''' 3767396Sgblack@eecs.umich.edu vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", 3777333Sgblack@eecs.umich.edu { "code": vmovCoreRegWCode, 3787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovCoreRegWIop); 3817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovCoreRegWIop); 3827333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovCoreRegWIop); 3837333Sgblack@eecs.umich.edu 3847640Sgblack@eecs.umich.edu vmovRegCoreUBCode = vfpEnabledCheckCode + ''' 3857639Sgblack@eecs.umich.edu assert(imm < 4); 3868588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8); 3877333Sgblack@eecs.umich.edu ''' 3887396Sgblack@eecs.umich.edu vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", 3897333Sgblack@eecs.umich.edu { "code": vmovRegCoreUBCode, 3907760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 3917760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 3927396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 3937396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 3947333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 3957333Sgblack@eecs.umich.edu 3967640Sgblack@eecs.umich.edu vmovRegCoreUHCode = vfpEnabledCheckCode + ''' 3977639Sgblack@eecs.umich.edu assert(imm < 2); 3988588Sgblack@eecs.umich.edu Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16); 3997333Sgblack@eecs.umich.edu ''' 4007396Sgblack@eecs.umich.edu vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", 4017333Sgblack@eecs.umich.edu { "code": vmovRegCoreUHCode, 4027760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4037760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4047396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 4057396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 4067333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 4077333Sgblack@eecs.umich.edu 4087640Sgblack@eecs.umich.edu vmovRegCoreSBCode = vfpEnabledCheckCode + ''' 4097639Sgblack@eecs.umich.edu assert(imm < 4); 4108588Sgblack@eecs.umich.edu Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8)); 4117333Sgblack@eecs.umich.edu ''' 4127396Sgblack@eecs.umich.edu vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", 4137333Sgblack@eecs.umich.edu { "code": vmovRegCoreSBCode, 4147760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4157760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4167396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 4177396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 4187333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 4197333Sgblack@eecs.umich.edu 4207640Sgblack@eecs.umich.edu vmovRegCoreSHCode = vfpEnabledCheckCode + ''' 4217639Sgblack@eecs.umich.edu assert(imm < 2); 4228588Sgblack@eecs.umich.edu Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16)); 4237333Sgblack@eecs.umich.edu ''' 4247396Sgblack@eecs.umich.edu vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", 4257333Sgblack@eecs.umich.edu { "code": vmovRegCoreSHCode, 4267760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4277760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4287396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 4297396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 4307333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 4317333Sgblack@eecs.umich.edu 4327640Sgblack@eecs.umich.edu vmovRegCoreWCode = vfpEnabledCheckCode + ''' 4338588Sgblack@eecs.umich.edu Dest = FpOp1_uw; 4347333Sgblack@eecs.umich.edu ''' 4357396Sgblack@eecs.umich.edu vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", 4367333Sgblack@eecs.umich.edu { "code": vmovRegCoreWCode, 4377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4397396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vmovRegCoreWIop); 4407396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vmovRegCoreWIop); 4417333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmovRegCoreWIop); 4427333Sgblack@eecs.umich.edu 4437640Sgblack@eecs.umich.edu vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' 4448588Sgblack@eecs.umich.edu FpDestP0_uw = Op1_uw; 4458588Sgblack@eecs.umich.edu FpDestP1_uw = Op2_uw; 4467333Sgblack@eecs.umich.edu ''' 4477396Sgblack@eecs.umich.edu vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", 4487333Sgblack@eecs.umich.edu { "code": vmov2Reg2CoreCode, 4497760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4507760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4517396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 4527396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 4537333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 4547333Sgblack@eecs.umich.edu 4557640Sgblack@eecs.umich.edu vmov2Core2RegCode = vfpEnabledCheckCode + ''' 4568588Sgblack@eecs.umich.edu Dest_uw = FpOp2P0_uw; 4578588Sgblack@eecs.umich.edu Op1_uw = FpOp2P1_uw; 4587333Sgblack@eecs.umich.edu ''' 4597396Sgblack@eecs.umich.edu vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", 4607333Sgblack@eecs.umich.edu { "code": vmov2Core2RegCode, 4617760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 4627760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMiscOp" }, []) 4637396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 4647396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 4657333Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmov2Core2RegIop); 4667381Sgblack@eecs.umich.edu}}; 4677381Sgblack@eecs.umich.edu 4687381Sgblack@eecs.umich.edulet {{ 4697381Sgblack@eecs.umich.edu 4707381Sgblack@eecs.umich.edu header_output = "" 4717381Sgblack@eecs.umich.edu decoder_output = "" 4727381Sgblack@eecs.umich.edu exec_output = "" 4737364Sgblack@eecs.umich.edu 4747783SGiacomo.Gabrielli@arm.com singleSimpleCode = vfpEnabledCheckCode + ''' 4758607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4767396Sgblack@eecs.umich.edu FpDest = %(op)s; 4777783SGiacomo.Gabrielli@arm.com ''' 4787783SGiacomo.Gabrielli@arm.com singleCode = singleSimpleCode + ''' 4797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 4807364Sgblack@eecs.umich.edu ''' 48110037SARM gem5 Developers singleTernOp = vfpEnabledCheckCode + ''' 48210037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 48310037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 48410037SARM gem5 Developers float cOp1 = FpOp1; 48510037SARM gem5 Developers float cOp2 = FpOp2; 48610037SARM gem5 Developers float cOp3 = FpDestP0; 48710037SARM gem5 Developers FpDestP0 = ternaryOp(fpscr, %(palam)s, %(op)s, 48810037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 48910037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 49010037SARM gem5 Developers FpscrExc = fpscr; 49110037SARM gem5 Developers ''' 4927396Sgblack@eecs.umich.edu singleBinOp = "binaryOp(fpscr, FpOp1, FpOp2," + \ 4937639Sgblack@eecs.umich.edu "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" 4947396Sgblack@eecs.umich.edu singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" 4957640Sgblack@eecs.umich.edu doubleCode = vfpEnabledCheckCode + ''' 4968607Sgblack@eecs.umich.edu FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; 4977396Sgblack@eecs.umich.edu double dest = %(op)s; 4988588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 4998588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 5007783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 5017396Sgblack@eecs.umich.edu ''' 50210037SARM gem5 Developers doubleTernOp = vfpEnabledCheckCode + ''' 50310037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 50410037SARM gem5 Developers VfpSavedState state = prepFpState(fpscr.rMode); 50510037SARM gem5 Developers double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 50610037SARM gem5 Developers double cOp2 = dbl(FpOp2P0_uw, FpOp2P1_uw); 50710037SARM gem5 Developers double cOp3 = dbl(FpDestP0_uw, FpDestP1_uw); 50810037SARM gem5 Developers double cDest = ternaryOp(fpscr, %(palam)s, %(op)s, 50910037SARM gem5 Developers fpscr.fz, fpscr.dn, fpscr.rMode); 51010037SARM gem5 Developers FpDestP0_uw = dblLow(cDest); 51110037SARM gem5 Developers FpDestP1_uw = dblHi(cDest); 51210037SARM gem5 Developers finishVfp(fpscr, state, fpscr.fz); 51310037SARM gem5 Developers FpscrExc = fpscr; 51410037SARM gem5 Developers ''' 5157396Sgblack@eecs.umich.edu doubleBinOp = ''' 5168588Sgblack@eecs.umich.edu binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 5178588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 5187639Sgblack@eecs.umich.edu %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); 5197396Sgblack@eecs.umich.edu ''' 5207396Sgblack@eecs.umich.edu doubleUnaryOp = ''' 5218588Sgblack@eecs.umich.edu unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s, 5227396Sgblack@eecs.umich.edu fpscr.fz, fpscr.rMode) 5237396Sgblack@eecs.umich.edu ''' 5247364Sgblack@eecs.umich.edu 52510037SARM gem5 Developers def buildTernaryFpOp(Name, base, opClass, singleOp, doubleOp, paramStr): 52610037SARM gem5 Developers global header_output, decoder_output, exec_output 52710037SARM gem5 Developers 52810037SARM gem5 Developers code = singleTernOp % { "op": singleOp, "palam": paramStr } 52910037SARM gem5 Developers sIop = InstObjParams(Name.lower() + "s", Name + "S", base, 53010037SARM gem5 Developers { "code": code, 53110037SARM gem5 Developers "predicate_test": predicateTest, 53210037SARM gem5 Developers "op_class": opClass }, []) 53310037SARM gem5 Developers code = doubleTernOp % { "op": doubleOp, "palam": paramStr } 53410037SARM gem5 Developers dIop = InstObjParams(Name.lower() + "d", Name + "D", base, 53510037SARM gem5 Developers { "code": code, 53610037SARM gem5 Developers "predicate_test": predicateTest, 53710037SARM gem5 Developers "op_class": opClass }, []) 53810037SARM gem5 Developers 53910037SARM gem5 Developers declareTempl = eval(base + "Declare"); 54010037SARM gem5 Developers constructorTempl = eval(base + "Constructor"); 54110037SARM gem5 Developers 54210037SARM gem5 Developers for iop in sIop, dIop: 54310037SARM gem5 Developers header_output += declareTempl.subst(iop) 54410037SARM gem5 Developers decoder_output += constructorTempl.subst(iop) 54510037SARM gem5 Developers exec_output += PredOpExecute.subst(iop) 54610037SARM gem5 Developers 54710037SARM gem5 Developers buildTernaryFpOp("Vfma", "FpRegRegRegOp", "SimdFloatMultAccOp", 54810037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, cOp3" ) 54910037SARM gem5 Developers buildTernaryFpOp("Vfms", "FpRegRegRegOp", "SimdFloatMultAccOp", 55010037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, cOp3" ) 55110037SARM gem5 Developers buildTernaryFpOp("Vfnma", "FpRegRegRegOp", "SimdFloatMultAccOp", 55210037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", "-cOp1, cOp2, -cOp3" ) 55310037SARM gem5 Developers buildTernaryFpOp("Vfnms", "FpRegRegRegOp", "SimdFloatMultAccOp", 55410037SARM gem5 Developers "fpMulAdd<float>", "fpMulAdd<double>", " cOp1, cOp2, -cOp3" ) 55510037SARM gem5 Developers 5567760SGiacomo.Gabrielli@arm.com def buildBinFpOp(name, Name, base, opClass, singleOp, doubleOp): 5577396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5587365Sgblack@eecs.umich.edu 5597396Sgblack@eecs.umich.edu code = singleCode % { "op": singleBinOp } 5607396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5617396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5627760SGiacomo.Gabrielli@arm.com { "code": code, 5637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5647760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5657396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleBinOp } 5667396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 5677396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 5687760SGiacomo.Gabrielli@arm.com { "code": code, 5697760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5707760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 5717365Sgblack@eecs.umich.edu 5727396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 5737396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 5747366Sgblack@eecs.umich.edu 5757396Sgblack@eecs.umich.edu for iop in sIop, dIop: 5767396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 5777396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 5787396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 5797366Sgblack@eecs.umich.edu 5807760SGiacomo.Gabrielli@arm.com buildBinFpOp("vadd", "Vadd", "FpRegRegRegOp", "SimdFloatAddOp", "fpAddS", 5817760SGiacomo.Gabrielli@arm.com "fpAddD") 5827760SGiacomo.Gabrielli@arm.com buildBinFpOp("vsub", "Vsub", "FpRegRegRegOp", "SimdFloatAddOp", "fpSubS", 5837760SGiacomo.Gabrielli@arm.com "fpSubD") 5847760SGiacomo.Gabrielli@arm.com buildBinFpOp("vdiv", "Vdiv", "FpRegRegRegOp", "SimdFloatDivOp", "fpDivS", 5857760SGiacomo.Gabrielli@arm.com "fpDivD") 5867760SGiacomo.Gabrielli@arm.com buildBinFpOp("vmul", "Vmul", "FpRegRegRegOp", "SimdFloatMultOp", "fpMulS", 5877760SGiacomo.Gabrielli@arm.com "fpMulD") 5887367Sgblack@eecs.umich.edu 5897760SGiacomo.Gabrielli@arm.com def buildUnaryFpOp(name, Name, base, opClass, singleOp, doubleOp = None): 5907396Sgblack@eecs.umich.edu if doubleOp is None: 5917396Sgblack@eecs.umich.edu doubleOp = singleOp 5927396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 5937367Sgblack@eecs.umich.edu 5947396Sgblack@eecs.umich.edu code = singleCode % { "op": singleUnaryOp } 5957396Sgblack@eecs.umich.edu code = code % { "func": singleOp } 5967396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 5977760SGiacomo.Gabrielli@arm.com { "code": code, 5987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 5997760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6007396Sgblack@eecs.umich.edu code = doubleCode % { "op": doubleUnaryOp } 6017396Sgblack@eecs.umich.edu code = code % { "func": doubleOp } 6027396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 6037760SGiacomo.Gabrielli@arm.com { "code": code, 6047760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6057760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6067368Sgblack@eecs.umich.edu 6077396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6087396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6097368Sgblack@eecs.umich.edu 6107396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6117396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6127396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6137396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6147369Sgblack@eecs.umich.edu 6157760SGiacomo.Gabrielli@arm.com buildUnaryFpOp("vsqrt", "Vsqrt", "FpRegRegOp", "SimdFloatSqrtOp", "sqrtf", 6167760SGiacomo.Gabrielli@arm.com "sqrt") 6177369Sgblack@eecs.umich.edu 6187760SGiacomo.Gabrielli@arm.com def buildSimpleUnaryFpOp(name, Name, base, opClass, singleOp, 6197760SGiacomo.Gabrielli@arm.com doubleOp = None): 6207396Sgblack@eecs.umich.edu if doubleOp is None: 6217396Sgblack@eecs.umich.edu doubleOp = singleOp 6227396Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 6237369Sgblack@eecs.umich.edu 6247396Sgblack@eecs.umich.edu sIop = InstObjParams(name + "s", Name + "S", base, 6257783SGiacomo.Gabrielli@arm.com { "code": singleSimpleCode % { "op": singleOp }, 6267760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6277760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6287396Sgblack@eecs.umich.edu dIop = InstObjParams(name + "d", Name + "D", base, 6297396Sgblack@eecs.umich.edu { "code": doubleCode % { "op": doubleOp }, 6307760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6317760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 6327369Sgblack@eecs.umich.edu 6337396Sgblack@eecs.umich.edu declareTempl = eval(base + "Declare"); 6347396Sgblack@eecs.umich.edu constructorTempl = eval(base + "Constructor"); 6357396Sgblack@eecs.umich.edu 6367396Sgblack@eecs.umich.edu for iop in sIop, dIop: 6377396Sgblack@eecs.umich.edu header_output += declareTempl.subst(iop) 6387396Sgblack@eecs.umich.edu decoder_output += constructorTempl.subst(iop) 6397396Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 6407396Sgblack@eecs.umich.edu 6417760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", 6428588Sgblack@eecs.umich.edu "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)") 6437760SGiacomo.Gabrielli@arm.com buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", 6448588Sgblack@eecs.umich.edu "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))") 6457381Sgblack@eecs.umich.edu}}; 6467381Sgblack@eecs.umich.edu 6477381Sgblack@eecs.umich.edulet {{ 6487381Sgblack@eecs.umich.edu 6497381Sgblack@eecs.umich.edu header_output = "" 6507381Sgblack@eecs.umich.edu decoder_output = "" 6517381Sgblack@eecs.umich.edu exec_output = "" 6527370Sgblack@eecs.umich.edu 6537640Sgblack@eecs.umich.edu vmlaSCode = vfpEnabledCheckCode + ''' 6547783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6557396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6567639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6577639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, mid, fpAddS, 6587639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6597783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6607370Sgblack@eecs.umich.edu ''' 6617396Sgblack@eecs.umich.edu vmlaSIop = InstObjParams("vmlas", "VmlaS", "FpRegRegRegOp", 6627370Sgblack@eecs.umich.edu { "code": vmlaSCode, 6637760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6647760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6657396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaSIop); 6667396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaSIop); 6677370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaSIop); 6687370Sgblack@eecs.umich.edu 6697640Sgblack@eecs.umich.edu vmlaDCode = vfpEnabledCheckCode + ''' 6707783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6718588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 6728588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 6737639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 6748588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 6757639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 6767639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 6778588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 6788588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 6797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6807370Sgblack@eecs.umich.edu ''' 6817396Sgblack@eecs.umich.edu vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", 6827370Sgblack@eecs.umich.edu { "code": vmlaDCode, 6837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 6847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 6857396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlaDIop); 6867396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlaDIop); 6877370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlaDIop); 6887370Sgblack@eecs.umich.edu 6897640Sgblack@eecs.umich.edu vmlsSCode = vfpEnabledCheckCode + ''' 6907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 6917396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 6927639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 6937639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, FpDest, -mid, fpAddS, 6947639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 6957783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 6967370Sgblack@eecs.umich.edu ''' 6977396Sgblack@eecs.umich.edu vmlsSIop = InstObjParams("vmlss", "VmlsS", "FpRegRegRegOp", 6987370Sgblack@eecs.umich.edu { "code": vmlsSCode, 6997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7017396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsSIop); 7027396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsSIop); 7037370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsSIop); 7047370Sgblack@eecs.umich.edu 7057640Sgblack@eecs.umich.edu vmlsDCode = vfpEnabledCheckCode + ''' 7067783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7078588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7088588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7097639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7108588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw), 7117639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 7127639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7138588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7148588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7157783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7167370Sgblack@eecs.umich.edu ''' 7177396Sgblack@eecs.umich.edu vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", 7187370Sgblack@eecs.umich.edu { "code": vmlsDCode, 7197760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7207760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7217396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vmlsDIop); 7227396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vmlsDIop); 7237370Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vmlsDIop); 7247371Sgblack@eecs.umich.edu 7257640Sgblack@eecs.umich.edu vnmlaSCode = vfpEnabledCheckCode + ''' 7267783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7277396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7287639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7297639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, -mid, fpAddS, 7307639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7317783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7327371Sgblack@eecs.umich.edu ''' 7337396Sgblack@eecs.umich.edu vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "FpRegRegRegOp", 7347371Sgblack@eecs.umich.edu { "code": vnmlaSCode, 7357760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7367760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7377396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaSIop); 7387396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaSIop); 7397371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaSIop); 7407371Sgblack@eecs.umich.edu 7417640Sgblack@eecs.umich.edu vnmlaDCode = vfpEnabledCheckCode + ''' 7427783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7438588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7448588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7457639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7468588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 7477639Sgblack@eecs.umich.edu -mid, fpAddD, fpscr.fz, 7487639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7498588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7508588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7517783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7527371Sgblack@eecs.umich.edu ''' 7537396Sgblack@eecs.umich.edu vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", 7547371Sgblack@eecs.umich.edu { "code": vnmlaDCode, 7557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7567760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7577396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlaDIop); 7587396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlaDIop); 7597371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlaDIop); 7607371Sgblack@eecs.umich.edu 7617640Sgblack@eecs.umich.edu vnmlsSCode = vfpEnabledCheckCode + ''' 7627783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7637396Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, FpOp1, FpOp2, 7647639Sgblack@eecs.umich.edu fpMulS, fpscr.fz, fpscr.dn, fpscr.rMode); 7657639Sgblack@eecs.umich.edu FpDest = binaryOp(fpscr, -FpDest, mid, fpAddS, 7667639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 7677783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7687371Sgblack@eecs.umich.edu ''' 7697396Sgblack@eecs.umich.edu vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "FpRegRegRegOp", 7707760SGiacomo.Gabrielli@arm.com { "code": vnmlsSCode, 7717760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7727760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7737396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsSIop); 7747396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsSIop); 7757371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsSIop); 7767371Sgblack@eecs.umich.edu 7777640Sgblack@eecs.umich.edu vnmlsDCode = vfpEnabledCheckCode + ''' 7787783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7798588Sgblack@eecs.umich.edu double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 7808588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 7817639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); 7828588Sgblack@eecs.umich.edu double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw), 7837639Sgblack@eecs.umich.edu mid, fpAddD, fpscr.fz, 7847639Sgblack@eecs.umich.edu fpscr.dn, fpscr.rMode); 7858588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 7868588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 7877783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 7887371Sgblack@eecs.umich.edu ''' 7897396Sgblack@eecs.umich.edu vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", 7907760SGiacomo.Gabrielli@arm.com { "code": vnmlsDCode, 7917760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 7927760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultAccOp" }, []) 7937396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmlsDIop); 7947396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmlsDIop); 7957371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmlsDIop); 7967371Sgblack@eecs.umich.edu 7977640Sgblack@eecs.umich.edu vnmulSCode = vfpEnabledCheckCode + ''' 7987783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 7997639Sgblack@eecs.umich.edu FpDest = -binaryOp(fpscr, FpOp1, FpOp2, fpMulS, 8007639Sgblack@eecs.umich.edu fpscr.fz, fpscr.dn, fpscr.rMode); 8017783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8027371Sgblack@eecs.umich.edu ''' 8037396Sgblack@eecs.umich.edu vnmulSIop = InstObjParams("vnmuls", "VnmulS", "FpRegRegRegOp", 8047760SGiacomo.Gabrielli@arm.com { "code": vnmulSCode, 8057760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8067760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8077396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulSIop); 8087396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulSIop); 8097371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulSIop); 8107371Sgblack@eecs.umich.edu 8117640Sgblack@eecs.umich.edu vnmulDCode = vfpEnabledCheckCode + ''' 8127783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8138588Sgblack@eecs.umich.edu double dest = -binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), 8148588Sgblack@eecs.umich.edu dbl(FpOp2P0_uw, FpOp2P1_uw), 8157639Sgblack@eecs.umich.edu fpMulD, fpscr.fz, fpscr.dn, 8167639Sgblack@eecs.umich.edu fpscr.rMode); 8178588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(dest); 8188588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(dest); 8197783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8207371Sgblack@eecs.umich.edu ''' 8217396Sgblack@eecs.umich.edu vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", 8227371Sgblack@eecs.umich.edu { "code": vnmulDCode, 8237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8247760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatMultOp" }, []) 8257396Sgblack@eecs.umich.edu header_output += FpRegRegRegOpDeclare.subst(vnmulDIop); 8267396Sgblack@eecs.umich.edu decoder_output += FpRegRegRegOpConstructor.subst(vnmulDIop); 8277371Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vnmulDIop); 8287381Sgblack@eecs.umich.edu}}; 8297381Sgblack@eecs.umich.edu 8307381Sgblack@eecs.umich.edulet {{ 8317381Sgblack@eecs.umich.edu 8327381Sgblack@eecs.umich.edu header_output = "" 8337381Sgblack@eecs.umich.edu decoder_output = "" 8347381Sgblack@eecs.umich.edu exec_output = "" 8357373Sgblack@eecs.umich.edu 8367640Sgblack@eecs.umich.edu vcvtUIntFpSCode = vfpEnabledCheckCode + ''' 8377783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8387397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8398588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 8408588Sgblack@eecs.umich.edu FpDest = FpOp1_uw; 8417381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8427639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8437783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8447373Sgblack@eecs.umich.edu ''' 8457396Sgblack@eecs.umich.edu vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "FpRegRegOp", 8467373Sgblack@eecs.umich.edu { "code": vcvtUIntFpSCode, 8477760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8487760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8497396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpSIop); 8507396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpSIop); 8517373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 8527373Sgblack@eecs.umich.edu 8537640Sgblack@eecs.umich.edu vcvtUIntFpDCode = vfpEnabledCheckCode + ''' 8547783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8557397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8568588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_uw) : "m" (FpOp1P0_uw)); 8578588Sgblack@eecs.umich.edu double cDest = (uint64_t)FpOp1P0_uw; 8587397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8597639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8608588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 8618588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 8627783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8637373Sgblack@eecs.umich.edu ''' 8647396Sgblack@eecs.umich.edu vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", 8657373Sgblack@eecs.umich.edu { "code": vcvtUIntFpDCode, 8667760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8677760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8687396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtUIntFpDIop); 8697396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtUIntFpDIop); 8707373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 8717373Sgblack@eecs.umich.edu 8727640Sgblack@eecs.umich.edu vcvtSIntFpSCode = vfpEnabledCheckCode + ''' 8737783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8747397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8758588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 8768588Sgblack@eecs.umich.edu FpDest = FpOp1_sw; 8777381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 8787639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8807373Sgblack@eecs.umich.edu ''' 8817396Sgblack@eecs.umich.edu vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "FpRegRegOp", 8827373Sgblack@eecs.umich.edu { "code": vcvtSIntFpSCode, 8837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 8847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 8857396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpSIop); 8867396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpSIop); 8877373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 8887373Sgblack@eecs.umich.edu 8897640Sgblack@eecs.umich.edu vcvtSIntFpDCode = vfpEnabledCheckCode + ''' 8907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 8917397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 8928588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1P0_sw) : "m" (FpOp1P0_sw)); 8938588Sgblack@eecs.umich.edu double cDest = FpOp1P0_sw; 8947397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 8957639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 8968588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 8978588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 8987783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 8997373Sgblack@eecs.umich.edu ''' 9007396Sgblack@eecs.umich.edu vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", 9017373Sgblack@eecs.umich.edu { "code": vcvtSIntFpDCode, 9027760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9037760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9047396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtSIntFpDIop); 9057396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtSIntFpDIop); 9067373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 9077373Sgblack@eecs.umich.edu 9087640Sgblack@eecs.umich.edu vcvtFpUIntSRCode = vfpEnabledCheckCode + ''' 9097783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9107397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9117397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9127381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 91310037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0, false); 9148588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 9157639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9167783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9177380Sgblack@eecs.umich.edu ''' 9187396Sgblack@eecs.umich.edu vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "FpRegRegOp", 9197380Sgblack@eecs.umich.edu { "code": vcvtFpUIntSRCode, 9207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9227396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 9237396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 9247380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 9257380Sgblack@eecs.umich.edu 9267640Sgblack@eecs.umich.edu vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' 9277783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9288588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9297397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9307397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9317397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 93210037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0, false); 9337381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9347639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9358588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9367783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9377380Sgblack@eecs.umich.edu ''' 9387396Sgblack@eecs.umich.edu vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", 9397380Sgblack@eecs.umich.edu { "code": vcvtFpUIntDRCode, 9407760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9417760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9427396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 9437396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 9447380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 9457380Sgblack@eecs.umich.edu 9467640Sgblack@eecs.umich.edu vcvtFpSIntSRCode = vfpEnabledCheckCode + ''' 9477783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9487397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9497397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9507381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 95110037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0, false); 9528588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 9537639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9547783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9557380Sgblack@eecs.umich.edu ''' 9567396Sgblack@eecs.umich.edu vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "FpRegRegOp", 9577380Sgblack@eecs.umich.edu { "code": vcvtFpSIntSRCode, 9587760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9597760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9607396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 9617396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 9627380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 9637380Sgblack@eecs.umich.edu 9647640Sgblack@eecs.umich.edu vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' 9657783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9668588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 9677397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 9687397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9697397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 97010037SARM gem5 Developers int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0, false); 9717381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 9727639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9738588Sgblack@eecs.umich.edu FpDestP0_uw = result; 9747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9757380Sgblack@eecs.umich.edu ''' 9767396Sgblack@eecs.umich.edu vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", 9777380Sgblack@eecs.umich.edu { "code": vcvtFpSIntDRCode, 9787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 9817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 9827380Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 9837380Sgblack@eecs.umich.edu 9847640Sgblack@eecs.umich.edu vcvtFpUIntSCode = vfpEnabledCheckCode + ''' 9857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 9867397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 9877397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 9887380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 9897381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 99010037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, 0); 9918588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 9927639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 9937783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 9947373Sgblack@eecs.umich.edu ''' 9957396Sgblack@eecs.umich.edu vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "FpRegRegOp", 9967373Sgblack@eecs.umich.edu { "code": vcvtFpUIntSCode, 9977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 9987760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 9997396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntSIop); 10007396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntSIop); 10017373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 10027373Sgblack@eecs.umich.edu 10037640Sgblack@eecs.umich.edu vcvtFpUIntDCode = vfpEnabledCheckCode + ''' 10047783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10058588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10067397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10077397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10087380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10097397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 101010037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, false, 32, 0); 10117381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10127639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10138588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10147783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10157373Sgblack@eecs.umich.edu ''' 10167396Sgblack@eecs.umich.edu vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", 10177373Sgblack@eecs.umich.edu { "code": vcvtFpUIntDCode, 10187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10197760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10207396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpUIntDIop); 10217396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpUIntDIop); 10227373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 10237373Sgblack@eecs.umich.edu 10247640Sgblack@eecs.umich.edu vcvtFpSIntSCode = vfpEnabledCheckCode + ''' 10257783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10267397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10277397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10287380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10297381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 103010037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, 0); 10318588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 10327639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10337783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10347373Sgblack@eecs.umich.edu ''' 10357396Sgblack@eecs.umich.edu vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "FpRegRegOp", 10367373Sgblack@eecs.umich.edu { "code": vcvtFpSIntSCode, 10377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10397396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntSIop); 10407396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntSIop); 10417373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 10427373Sgblack@eecs.umich.edu 10437640Sgblack@eecs.umich.edu vcvtFpSIntDCode = vfpEnabledCheckCode + ''' 10447783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10458588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10467397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10477397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10487380Sgblack@eecs.umich.edu fesetround(FeRoundZero); 10497397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 105010037SARM gem5 Developers int64_t result = vfpFpToFixed<double>(cOp1, true, 32, 0); 10517381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 10527639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10538588Sgblack@eecs.umich.edu FpDestP0_uw = result; 10547783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10557373Sgblack@eecs.umich.edu ''' 10567396Sgblack@eecs.umich.edu vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", 10577373Sgblack@eecs.umich.edu { "code": vcvtFpSIntDCode, 10587760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10597760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10607396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSIntDIop); 10617396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSIntDIop); 10627373Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 10637374Sgblack@eecs.umich.edu 10647640Sgblack@eecs.umich.edu vcvtFpSFpDCode = vfpEnabledCheckCode + ''' 10657783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10667397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 10677397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10687381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 10697783SGiacomo.Gabrielli@arm.com double cDest = fixFpSFpDDest(FpscrExc, FpOp1); 10707397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 10717639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10728588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 10738588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 10747783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10757374Sgblack@eecs.umich.edu ''' 10767396Sgblack@eecs.umich.edu vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", 10777374Sgblack@eecs.umich.edu { "code": vcvtFpSFpDCode, 10787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10807396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpDIop); 10817396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpDIop); 10827374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 10837374Sgblack@eecs.umich.edu 10847640Sgblack@eecs.umich.edu vcvtFpDFpSCode = vfpEnabledCheckCode + ''' 10857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 10868588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 10877397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 10887397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 10897397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 10907783SGiacomo.Gabrielli@arm.com FpDest = fixFpDFpSDest(FpscrExc, cOp1); 10917381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 10927639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 10937783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 10947374Sgblack@eecs.umich.edu ''' 10957396Sgblack@eecs.umich.edu vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "FpRegRegOp", 10967374Sgblack@eecs.umich.edu { "code": vcvtFpDFpSCode, 10977760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 10987760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 10997396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpDFpSIop); 11007396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpDFpSIop); 11017374Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 11027377Sgblack@eecs.umich.edu 11037640Sgblack@eecs.umich.edu vcvtFpHTFpSCode = vfpEnabledCheckCode + ''' 11047783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11057398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11067398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11077398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11087639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 11097639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 31, 16)); 11107398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11117639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11127783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11137398Sgblack@eecs.umich.edu ''' 11147398Sgblack@eecs.umich.edu vcvtFpHTFpSIop = InstObjParams("vcvtt", "VcvtFpHTFpS", "FpRegRegOp", 11157398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 11167760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11177760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11187398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHTFpSIop); 11197398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHTFpSIop); 11207398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHTFpSIop); 11217398Sgblack@eecs.umich.edu 11227640Sgblack@eecs.umich.edu vcvtFpHBFpSCode = vfpEnabledCheckCode + ''' 11237783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11247398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11257398Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 11267639Sgblack@eecs.umich.edu FpDest = vcvtFpHFpS(fpscr, fpscr.dn, fpscr.ahp, 11277639Sgblack@eecs.umich.edu bits(fpToBits(FpOp1), 15, 0)); 11287398Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 11297639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11307783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11317398Sgblack@eecs.umich.edu ''' 11327398Sgblack@eecs.umich.edu vcvtFpHBFpSIop = InstObjParams("vcvtb", "VcvtFpHBFpS", "FpRegRegOp", 11337398Sgblack@eecs.umich.edu { "code": vcvtFpHBFpSCode, 11347760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11357760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11367398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpHBFpSIop); 11377398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpHBFpSIop); 11387398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpHBFpSIop); 11397398Sgblack@eecs.umich.edu 11407640Sgblack@eecs.umich.edu vcvtFpSFpHTCode = vfpEnabledCheckCode + ''' 11417783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11427398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11437398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11448588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 11458588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 11468588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 31, 16,, 11477639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 11487639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 11498588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 11507639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11517783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11527398Sgblack@eecs.umich.edu ''' 11537398Sgblack@eecs.umich.edu vcvtFpSFpHTIop = InstObjParams("vcvtt", "VcvtFpSFpHT", "FpRegRegOp", 11547398Sgblack@eecs.umich.edu { "code": vcvtFpHTFpSCode, 11557760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11567760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11577398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHTIop); 11587398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHTIop); 11597398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHTIop); 11607398Sgblack@eecs.umich.edu 11617640Sgblack@eecs.umich.edu vcvtFpSFpHBCode = vfpEnabledCheckCode + ''' 11627783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11637398Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 11647398Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 11658588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw) 11668588Sgblack@eecs.umich.edu : "m" (FpOp1), "m" (FpDest_uw)); 11678588Sgblack@eecs.umich.edu FpDest_uw = insertBits(FpDest_uw, 15, 0, 11687639Sgblack@eecs.umich.edu vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, 11697639Sgblack@eecs.umich.edu fpscr.rMode, fpscr.ahp, FpOp1)); 11708588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 11717639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 11727783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 11737398Sgblack@eecs.umich.edu ''' 11747398Sgblack@eecs.umich.edu vcvtFpSFpHBIop = InstObjParams("vcvtb", "VcvtFpSFpHB", "FpRegRegOp", 11757398Sgblack@eecs.umich.edu { "code": vcvtFpSFpHBCode, 11767760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 11777760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 11787398Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcvtFpSFpHBIop); 11797398Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcvtFpSFpHBIop); 11807398Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFpHBIop); 11817398Sgblack@eecs.umich.edu 11827640Sgblack@eecs.umich.edu vcmpSCode = vfpEnabledCheckCode + ''' 11837783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 11847397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 11857377Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 11867377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 11877377Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 11887377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 11897377Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 11907377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 11917377Sgblack@eecs.umich.edu } else { 11927389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 11937389Sgblack@eecs.umich.edu const bool nan1 = std::isnan(FpDest); 11947396Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(FpDest) & qnan) != qnan); 11957389Sgblack@eecs.umich.edu const bool nan2 = std::isnan(FpOp1); 11967396Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(FpOp1) & qnan) != qnan); 11977389Sgblack@eecs.umich.edu if (signal1 || signal2) 11987389Sgblack@eecs.umich.edu fpscr.ioc = 1; 11997377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12007377Sgblack@eecs.umich.edu } 12017643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12027783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12037377Sgblack@eecs.umich.edu ''' 12047396Sgblack@eecs.umich.edu vcmpSIop = InstObjParams("vcmps", "VcmpS", "FpRegRegOp", 12057377Sgblack@eecs.umich.edu { "code": vcmpSCode, 12067760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12077760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12087396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpSIop); 12097396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpSIop); 12107377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpSIop); 12117377Sgblack@eecs.umich.edu 12127640Sgblack@eecs.umich.edu vcmpDCode = vfpEnabledCheckCode + ''' 12138588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 12148588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 12157783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12167397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 12177397Sgblack@eecs.umich.edu if (cDest == cOp1) { 12187377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12197397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 12207377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12217397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 12227377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12237377Sgblack@eecs.umich.edu } else { 12247389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12257397Sgblack@eecs.umich.edu const bool nan1 = std::isnan(cDest); 12267397Sgblack@eecs.umich.edu const bool signal1 = nan1 && ((fpToBits(cDest) & qnan) != qnan); 12277397Sgblack@eecs.umich.edu const bool nan2 = std::isnan(cOp1); 12287397Sgblack@eecs.umich.edu const bool signal2 = nan2 && ((fpToBits(cOp1) & qnan) != qnan); 12297389Sgblack@eecs.umich.edu if (signal1 || signal2) 12307389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12317377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12327377Sgblack@eecs.umich.edu } 12337643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12357377Sgblack@eecs.umich.edu ''' 12367396Sgblack@eecs.umich.edu vcmpDIop = InstObjParams("vcmpd", "VcmpD", "FpRegRegOp", 12377377Sgblack@eecs.umich.edu { "code": vcmpDCode, 12387760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12397760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12407396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpDIop); 12417396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpDIop); 12427377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpDIop); 12437377Sgblack@eecs.umich.edu 12447640Sgblack@eecs.umich.edu vcmpZeroSCode = vfpEnabledCheckCode + ''' 12457783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12467397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 12477389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12487389Sgblack@eecs.umich.edu assert(imm == 0); 12497377Sgblack@eecs.umich.edu if (FpDest == imm) { 12507377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12517377Sgblack@eecs.umich.edu } else if (FpDest < imm) { 12527377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12537377Sgblack@eecs.umich.edu } else if (FpDest > imm) { 12547377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12557377Sgblack@eecs.umich.edu } else { 12567389Sgblack@eecs.umich.edu const uint32_t qnan = 0x7fc00000; 12577389Sgblack@eecs.umich.edu const bool nan = std::isnan(FpDest); 12587396Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(FpDest) & qnan) != qnan); 12597389Sgblack@eecs.umich.edu if (signal) 12607389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12617377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12627377Sgblack@eecs.umich.edu } 12637643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12647783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12657377Sgblack@eecs.umich.edu ''' 12667396Sgblack@eecs.umich.edu vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "FpRegImmOp", 12677377Sgblack@eecs.umich.edu { "code": vcmpZeroSCode, 12687760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12697760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 12707396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroSIop); 12717396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroSIop); 12727377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroSIop); 12737377Sgblack@eecs.umich.edu 12747640Sgblack@eecs.umich.edu vcmpZeroDCode = vfpEnabledCheckCode + ''' 12757389Sgblack@eecs.umich.edu // This only handles imm == 0 for now. 12767389Sgblack@eecs.umich.edu assert(imm == 0); 12778588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 12787783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 12797397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 12807397Sgblack@eecs.umich.edu if (cDest == imm) { 12817377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 12827397Sgblack@eecs.umich.edu } else if (cDest < imm) { 12837377Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 12847397Sgblack@eecs.umich.edu } else if (cDest > imm) { 12857377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 12867377Sgblack@eecs.umich.edu } else { 12877389Sgblack@eecs.umich.edu const uint64_t qnan = ULL(0x7ff8000000000000); 12887397Sgblack@eecs.umich.edu const bool nan = std::isnan(cDest); 12897397Sgblack@eecs.umich.edu const bool signal = nan && ((fpToBits(cDest) & qnan) != qnan); 12907389Sgblack@eecs.umich.edu if (signal) 12917389Sgblack@eecs.umich.edu fpscr.ioc = 1; 12927377Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 12937377Sgblack@eecs.umich.edu } 12947643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 12957783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 12967377Sgblack@eecs.umich.edu ''' 12977396Sgblack@eecs.umich.edu vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "FpRegImmOp", 12987377Sgblack@eecs.umich.edu { "code": vcmpZeroDCode, 12997760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13007760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13017396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpZeroDIop); 13027396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpZeroDIop); 13037377Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpZeroDIop); 13047389Sgblack@eecs.umich.edu 13057640Sgblack@eecs.umich.edu vcmpeSCode = vfpEnabledCheckCode + ''' 13067783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13077397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest, FpOp1); 13087389Sgblack@eecs.umich.edu if (FpDest == FpOp1) { 13097389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13107389Sgblack@eecs.umich.edu } else if (FpDest < FpOp1) { 13117389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13127389Sgblack@eecs.umich.edu } else if (FpDest > FpOp1) { 13137389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13147389Sgblack@eecs.umich.edu } else { 13157389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13167389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13177389Sgblack@eecs.umich.edu } 13187643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13197783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13207389Sgblack@eecs.umich.edu ''' 13217396Sgblack@eecs.umich.edu vcmpeSIop = InstObjParams("vcmpes", "VcmpeS", "FpRegRegOp", 13227389Sgblack@eecs.umich.edu { "code": vcmpeSCode, 13237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13247760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13257396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeSIop); 13267396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeSIop); 13277389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeSIop); 13287389Sgblack@eecs.umich.edu 13297640Sgblack@eecs.umich.edu vcmpeDCode = vfpEnabledCheckCode + ''' 13308588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 13318588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 13327783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13337397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest, cOp1); 13347397Sgblack@eecs.umich.edu if (cDest == cOp1) { 13357389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13367397Sgblack@eecs.umich.edu } else if (cDest < cOp1) { 13377389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13387397Sgblack@eecs.umich.edu } else if (cDest > cOp1) { 13397389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13407389Sgblack@eecs.umich.edu } else { 13417389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13427389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13437389Sgblack@eecs.umich.edu } 13447643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13457783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13467389Sgblack@eecs.umich.edu ''' 13477396Sgblack@eecs.umich.edu vcmpeDIop = InstObjParams("vcmped", "VcmpeD", "FpRegRegOp", 13487389Sgblack@eecs.umich.edu { "code": vcmpeDCode, 13497760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13507760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13517396Sgblack@eecs.umich.edu header_output += FpRegRegOpDeclare.subst(vcmpeDIop); 13527396Sgblack@eecs.umich.edu decoder_output += FpRegRegOpConstructor.subst(vcmpeDIop); 13537389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeDIop); 13547389Sgblack@eecs.umich.edu 13557640Sgblack@eecs.umich.edu vcmpeZeroSCode = vfpEnabledCheckCode + ''' 13567783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13577397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpDest); 13587389Sgblack@eecs.umich.edu if (FpDest == imm) { 13597389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13607389Sgblack@eecs.umich.edu } else if (FpDest < imm) { 13617389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13627389Sgblack@eecs.umich.edu } else if (FpDest > imm) { 13637389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13647389Sgblack@eecs.umich.edu } else { 13657389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13667389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13677389Sgblack@eecs.umich.edu } 13687643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13697783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13707389Sgblack@eecs.umich.edu ''' 13717396Sgblack@eecs.umich.edu vcmpeZeroSIop = InstObjParams("vcmpeZeros", "VcmpeZeroS", "FpRegImmOp", 13727389Sgblack@eecs.umich.edu { "code": vcmpeZeroSCode, 13737760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13747760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 13757396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroSIop); 13767396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroSIop); 13777389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroSIop); 13787389Sgblack@eecs.umich.edu 13797640Sgblack@eecs.umich.edu vcmpeZeroDCode = vfpEnabledCheckCode + ''' 13808588Sgblack@eecs.umich.edu double cDest = dbl(FpDestP0_uw, FpDestP1_uw); 13817783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 13827397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cDest); 13837397Sgblack@eecs.umich.edu if (cDest == imm) { 13847389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 13857397Sgblack@eecs.umich.edu } else if (cDest < imm) { 13867389Sgblack@eecs.umich.edu fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 13877397Sgblack@eecs.umich.edu } else if (cDest > imm) { 13887389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 13897389Sgblack@eecs.umich.edu } else { 13907389Sgblack@eecs.umich.edu fpscr.ioc = 1; 13917389Sgblack@eecs.umich.edu fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 13927389Sgblack@eecs.umich.edu } 13937643Sgblack@eecs.umich.edu FpCondCodes = fpscr & FpCondCodesMask; 13947783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 13957389Sgblack@eecs.umich.edu ''' 13967396Sgblack@eecs.umich.edu vcmpeZeroDIop = InstObjParams("vcmpeZerod", "VcmpeZeroD", "FpRegImmOp", 13977389Sgblack@eecs.umich.edu { "code": vcmpeZeroDCode, 13987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCmpOp" }, []) 14007396Sgblack@eecs.umich.edu header_output += FpRegImmOpDeclare.subst(vcmpeZeroDIop); 14017396Sgblack@eecs.umich.edu decoder_output += FpRegImmOpConstructor.subst(vcmpeZeroDIop); 14027389Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcmpeZeroDIop); 14037322Sgblack@eecs.umich.edu}}; 14047379Sgblack@eecs.umich.edu 14057379Sgblack@eecs.umich.edulet {{ 14067379Sgblack@eecs.umich.edu 14077379Sgblack@eecs.umich.edu header_output = "" 14087379Sgblack@eecs.umich.edu decoder_output = "" 14097379Sgblack@eecs.umich.edu exec_output = "" 14107379Sgblack@eecs.umich.edu 14117640Sgblack@eecs.umich.edu vcvtFpSFixedSCode = vfpEnabledCheckCode + ''' 14127783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14137397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14147397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14157381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 141610037SARM gem5 Developers FpDest_sw = vfpFpToFixed<float>(FpOp1, true, 32, imm); 14178588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sw)); 14187639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14197783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14207379Sgblack@eecs.umich.edu ''' 14217396Sgblack@eecs.umich.edu vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "FpRegRegImmOp", 14227379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedSCode, 14237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14247760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14257396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 14267396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 14277379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 14287379Sgblack@eecs.umich.edu 14297640Sgblack@eecs.umich.edu vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' 14307783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14318588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 14327397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14337397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14347397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 143510037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, true, 32, imm); 14367381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 14377639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14388588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 14398588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 14407783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14417379Sgblack@eecs.umich.edu ''' 14427396Sgblack@eecs.umich.edu vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", 14437379Sgblack@eecs.umich.edu { "code": vcvtFpSFixedDCode, 14447760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14457760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14467396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 14477396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 14487379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 14497379Sgblack@eecs.umich.edu 14507640Sgblack@eecs.umich.edu vcvtFpUFixedSCode = vfpEnabledCheckCode + ''' 14517783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14527397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 14537397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14547381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 145510037SARM gem5 Developers FpDest_uw = vfpFpToFixed<float>(FpOp1, false, 32, imm); 14568588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uw)); 14577639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14587783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14597379Sgblack@eecs.umich.edu ''' 14607396Sgblack@eecs.umich.edu vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "FpRegRegImmOp", 14617379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedSCode, 14627760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14637760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14647396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 14657396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 14667379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 14677379Sgblack@eecs.umich.edu 14687640Sgblack@eecs.umich.edu vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' 14697783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14708588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 14717397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 14727397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14737397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 147410037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 32, imm); 14757381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 14767639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14778588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 14788588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 14797783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14807379Sgblack@eecs.umich.edu ''' 14817396Sgblack@eecs.umich.edu vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", 14827379Sgblack@eecs.umich.edu { "code": vcvtFpUFixedDCode, 14837760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14847760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 14857396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 14867396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 14877379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 14887379Sgblack@eecs.umich.edu 14897640Sgblack@eecs.umich.edu vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' 14907783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 14917397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 14928588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw)); 149310037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, 32, imm); 14947381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 14957639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 14967783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 14977379Sgblack@eecs.umich.edu ''' 14987396Sgblack@eecs.umich.edu vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "FpRegRegImmOp", 14997379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpSCode, 15007760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15017760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15027396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 15037396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 15047379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 15057379Sgblack@eecs.umich.edu 15067640Sgblack@eecs.umich.edu vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' 15077783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15088588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 15097397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15107381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 151110037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 15127397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15137639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15148588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 15158588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 15167783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15177379Sgblack@eecs.umich.edu ''' 15187396Sgblack@eecs.umich.edu vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", 15197379Sgblack@eecs.umich.edu { "code": vcvtSFixedFpDCode, 15207760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15217760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15227396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 15237396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 15247379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 15257379Sgblack@eecs.umich.edu 15267640Sgblack@eecs.umich.edu vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' 15277783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15287397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15298588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw)); 153010037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, 32, imm); 15317381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 15327639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15337783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15347379Sgblack@eecs.umich.edu ''' 15357396Sgblack@eecs.umich.edu vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "FpRegRegImmOp", 15367379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpSCode, 15377760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15387760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15397396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 15407396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 15417379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 15427379Sgblack@eecs.umich.edu 15437640Sgblack@eecs.umich.edu vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' 15447783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15458588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 15467397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15477381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 154810037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 32, imm); 15497397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 15507639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15518588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 15528588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 15537783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15547379Sgblack@eecs.umich.edu ''' 15557396Sgblack@eecs.umich.edu vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", 15567379Sgblack@eecs.umich.edu { "code": vcvtUFixedFpDCode, 15577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15597396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 15607396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 15617379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 15627379Sgblack@eecs.umich.edu 15637640Sgblack@eecs.umich.edu vcvtFpSHFixedSCode = vfpEnabledCheckCode + ''' 15647783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15657397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 15667397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15677381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 156810037SARM gem5 Developers FpDest_sh = vfpFpToFixed<float>(FpOp1, true, 16, imm); 15698588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_sh)); 15707639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15727379Sgblack@eecs.umich.edu ''' 15737379Sgblack@eecs.umich.edu vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 15747396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15757379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedSCode, 15767760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15777760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 15787396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 15797396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 15807379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 15817379Sgblack@eecs.umich.edu 15827640Sgblack@eecs.umich.edu vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' 15837783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 15848588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 15857397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 15867397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 15877397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 158810037SARM gem5 Developers uint64_t result = vfpFpToFixed<double>(cOp1, true, 16, imm); 15897381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (result)); 15907639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 15918588Sgblack@eecs.umich.edu FpDestP0_uw = result; 15928588Sgblack@eecs.umich.edu FpDestP1_uw = result >> 32; 15937783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 15947379Sgblack@eecs.umich.edu ''' 15957379Sgblack@eecs.umich.edu vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 15967396Sgblack@eecs.umich.edu "FpRegRegImmOp", 15977379Sgblack@eecs.umich.edu { "code": vcvtFpSHFixedDCode, 15987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15997760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16007396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 16017396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 16027379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 16037379Sgblack@eecs.umich.edu 16047640Sgblack@eecs.umich.edu vcvtFpUHFixedSCode = vfpEnabledCheckCode + ''' 16057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16067397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, FpOp1); 16077397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16087381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); 160910037SARM gem5 Developers FpDest_uh = vfpFpToFixed<float>(FpOp1, false, 16, imm); 16108588Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest_uh)); 16117639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16127783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16137379Sgblack@eecs.umich.edu ''' 16147379Sgblack@eecs.umich.edu vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 16157396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16167379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedSCode, 16177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16197396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 16207396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 16217379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 16227379Sgblack@eecs.umich.edu 16237640Sgblack@eecs.umich.edu vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' 16247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16258588Sgblack@eecs.umich.edu double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw); 16267397Sgblack@eecs.umich.edu vfpFlushToZero(fpscr, cOp1); 16277397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16287397Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); 162910037SARM gem5 Developers uint64_t mid = vfpFpToFixed<double>(cOp1, false, 16, imm); 16307381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (mid)); 16317639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16328588Sgblack@eecs.umich.edu FpDestP0_uw = mid; 16338588Sgblack@eecs.umich.edu FpDestP1_uw = mid >> 32; 16347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16357379Sgblack@eecs.umich.edu ''' 16367379Sgblack@eecs.umich.edu vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 16377396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16387379Sgblack@eecs.umich.edu { "code": vcvtFpUHFixedDCode, 16397760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16407760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16417396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 16427396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 16437379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 16447379Sgblack@eecs.umich.edu 16457640Sgblack@eecs.umich.edu vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' 16467783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16477397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16488588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh)); 164910037SARM gem5 Developers FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, 16, imm); 16507381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 16517639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16527783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16537379Sgblack@eecs.umich.edu ''' 16547379Sgblack@eecs.umich.edu vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 16557396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16567379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpSCode, 16577760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16587760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16597396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 16607396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 16617379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 16627379Sgblack@eecs.umich.edu 16637640Sgblack@eecs.umich.edu vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' 16647783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16658588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 16667397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16677381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 166810037SARM gem5 Developers double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 16697397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 16707639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16718588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 16728588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 16737783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16747379Sgblack@eecs.umich.edu ''' 16757379Sgblack@eecs.umich.edu vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 16767396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16777379Sgblack@eecs.umich.edu { "code": vcvtSHFixedFpDCode, 16787760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16797760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16807396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 16817396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 16827379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 16837379Sgblack@eecs.umich.edu 16847640Sgblack@eecs.umich.edu vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' 16857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 16867397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 16878588Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh)); 168810037SARM gem5 Developers FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, 16, imm); 16897381Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (FpDest)); 16907639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 16917783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 16927379Sgblack@eecs.umich.edu ''' 16937379Sgblack@eecs.umich.edu vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 16947396Sgblack@eecs.umich.edu "FpRegRegImmOp", 16957379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpSCode, 16967760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16977760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 16987396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 16997396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 17007379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 17017379Sgblack@eecs.umich.edu 17027640Sgblack@eecs.umich.edu vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' 17037783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 17048588Sgblack@eecs.umich.edu uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32)); 17057397Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(fpscr.rMode); 17067381Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (mid) : "m" (mid)); 170710037SARM gem5 Developers double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, 16, imm); 17087397Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (cDest)); 17097639Sgblack@eecs.umich.edu finishVfp(fpscr, state, fpscr.fz); 17108588Sgblack@eecs.umich.edu FpDestP0_uw = dblLow(cDest); 17118588Sgblack@eecs.umich.edu FpDestP1_uw = dblHi(cDest); 17127783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 17137379Sgblack@eecs.umich.edu ''' 17147379Sgblack@eecs.umich.edu vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 17157396Sgblack@eecs.umich.edu "FpRegRegImmOp", 17167379Sgblack@eecs.umich.edu { "code": vcvtUHFixedFpDCode, 17177760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17187760SGiacomo.Gabrielli@arm.com "op_class": "SimdFloatCvtOp" }, []) 17197396Sgblack@eecs.umich.edu header_output += FpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 17207396Sgblack@eecs.umich.edu decoder_output += FpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 17217379Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 17227379Sgblack@eecs.umich.edu}}; 1723