div.isa revision 7319:d4e9a5e31a38
12810SN/A// -*- mode:c++ -*- 22810SN/A 32810SN/A// Copyright (c) 2010 ARM Limited 42810SN/A// All rights reserved 52810SN/A// 62810SN/A// The license below extends only to copyright in the software and shall 72810SN/A// not be construed as granting a license to any other intellectual 82810SN/A// property including but not limited to intellectual property relating 92810SN/A// to a hardware implementation of the functionality of the software 102810SN/A// licensed hereunder. You may use the software subject to the license 112810SN/A// terms below provided that you ensure that this notice is replicated 122810SN/A// unmodified and in its entirety in all distributions of the software, 132810SN/A// modified or unmodified, in source code or in binary form. 142810SN/A// 152810SN/A// Redistribution and use in source and binary forms, with or without 162810SN/A// modification, are permitted provided that the following conditions are 172810SN/A// met: redistributions of source code must retain the above copyright 182810SN/A// notice, this list of conditions and the following disclaimer; 192810SN/A// redistributions in binary form must reproduce the above copyright 202810SN/A// notice, this list of conditions and the following disclaimer in the 212810SN/A// documentation and/or other materials provided with the distribution; 222810SN/A// neither the name of the copyright holders nor the names of its 232810SN/A// contributors may be used to endorse or promote products derived from 242810SN/A// this software without specific prior written permission. 252810SN/A// 262810SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272810SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282810SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292810SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 302810SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 312810SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 322810SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 333861SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 342810SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 352810SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 362810SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 372810SN/A// 382810SN/A// Authors: Gabe Black 398229Snate@binkert.org 408229Snate@binkert.orglet {{ 415338Sstever@gmail.com sdivCode = ''' 428831Smrinmoy.ghosh@arm.com if (Op2.sw == 0) { 432810SN/A Dest.sw = 0; 443861SN/A } else if (Op1.sw == INT_MIN && Op2.sw == -1) { 452810SN/A Dest.sw = INT_MIN; 462810SN/A } else { 472810SN/A Dest.sw = Op1.sw / Op2.sw; 485875Ssteve.reinhardt@amd.com } 495875Ssteve.reinhardt@amd.com ''' 505875Ssteve.reinhardt@amd.com sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", 515875Ssteve.reinhardt@amd.com { "code": sdivCode, 525875Ssteve.reinhardt@amd.com "predicate_test": predicateTest }, []) 535875Ssteve.reinhardt@amd.com header_output = RegRegRegOpDeclare.subst(sdivIop) 545875Ssteve.reinhardt@amd.com decoder_output = RegRegRegOpConstructor.subst(sdivIop) 555875Ssteve.reinhardt@amd.com exec_output = PredOpExecute.subst(sdivIop) 562810SN/A 572810SN/A udivCode = ''' 585875Ssteve.reinhardt@amd.com if (Op2.uw == 0) { 595875Ssteve.reinhardt@amd.com Dest.uw = 0; 602810SN/A } else { 615875Ssteve.reinhardt@amd.com Dest.uw = Op1.uw / Op2.uw; 625875Ssteve.reinhardt@amd.com } 632810SN/A ''' 645875Ssteve.reinhardt@amd.com udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", 652810SN/A { "code": udivCode, 665875Ssteve.reinhardt@amd.com "predicate_test": predicateTest }, []) 672810SN/A header_output += RegRegRegOpDeclare.subst(udivIop) 682810SN/A decoder_output += RegRegRegOpConstructor.subst(udivIop) 692810SN/A exec_output += PredOpExecute.subst(udivIop) 708831Smrinmoy.ghosh@arm.com}}; 718831Smrinmoy.ghosh@arm.com