data.isa revision 7797
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 calcGECode = ''' 47 CondCodes = insertBits(CondCodes, 19, 16, resTemp); 48 ''' 49 50 calcQCode = ''' 51 CondCodes = CondCodes | ((resTemp & 1) << 27); 52 ''' 53 54 calcCcCode = ''' 55 uint16_t _ic, _iv, _iz, _in; 56 _in = (resTemp >> %(negBit)d) & 1; 57 _iz = (resTemp == 0); 58 _iv = %(ivValue)s & 1; 59 _ic = %(icValue)s & 1; 60 61 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 62 (CondCodes & 0x0FFFFFFF); 63 64 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", 65 _in, _iz, _ic, _iv); 66 ''' 67 68 # Dict of code to set the carry flag. (imm, reg, reg-reg) 69 oldC = 'CondCodes<29:>' 70 oldV = 'CondCodes<28:>' 71 carryCode = { 72 "none": (oldC, oldC, oldC), 73 "llbit": (oldC, oldC, oldC), 74 "saturate": ('0', '0', '0'), 75 "overflow": ('0', '0', '0'), 76 "ge": ('0', '0', '0'), 77 "add": ('findCarry(32, resTemp, Op1, secondOp)', 78 'findCarry(32, resTemp, Op1, secondOp)', 79 'findCarry(32, resTemp, Op1, secondOp)'), 80 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)', 81 'findCarry(32, resTemp, Op1, ~secondOp)', 82 'findCarry(32, resTemp, Op1, ~secondOp)'), 83 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)', 84 'findCarry(32, resTemp, secondOp, ~Op1)', 85 'findCarry(32, resTemp, secondOp, ~Op1)'), 86 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC, 87 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC, 88 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC) 89 } 90 # Dict of code to set the overflow flag. 91 overflowCode = { 92 "none": oldV, 93 "llbit": oldV, 94 "saturate": '0', 95 "overflow": '0', 96 "ge": '0', 97 "add": 'findOverflow(32, resTemp, Op1, secondOp)', 98 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 99 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 100 "logic": oldV 101 } 102 103 secondOpRe = re.compile("secondOp") 104 immOp2 = "imm" 105 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 106 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 107 108 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ 109 buildCc = True, buildNonCc = True, instFlags = []): 110 cCode = carryCode[flagType] 111 vCode = overflowCode[flagType] 112 negBit = 31 113 if flagType == "llbit": 114 negBit = 63 115 if flagType == "saturate": 116 immCcCode = calcQCode 117 elif flagType == "ge": 118 immCcCode = calcGECode 119 else: 120 immCcCode = calcCcCode % { 121 "icValue": secondOpRe.sub(immOp2, cCode[0]), 122 "ivValue": secondOpRe.sub(immOp2, vCode), 123 "negBit": negBit 124 } 125 immCode = secondOpRe.sub(immOp2, code) 126 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", 127 {"code" : immCode, 128 "predicate_test": predicateTest}, instFlags) 129 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 130 "DataImmOp", 131 {"code" : immCode + immCcCode, 132 "predicate_test": condPredicateTest}, instFlags) 133 134 def subst(iop): 135 global header_output, decoder_output, exec_output 136 header_output += DataImmDeclare.subst(iop) 137 decoder_output += DataImmConstructor.subst(iop) 138 exec_output += PredOpExecute.subst(iop) 139 140 if buildNonCc: 141 subst(immIop) 142 if buildCc: 143 subst(immIopCc) 144 145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \ 146 buildCc = True, buildNonCc = True, instFlags = []): 147 cCode = carryCode[flagType] 148 vCode = overflowCode[flagType] 149 negBit = 31 150 if flagType == "llbit": 151 negBit = 63 152 if flagType == "saturate": 153 regCcCode = calcQCode 154 elif flagType == "ge": 155 regCcCode = calcGECode 156 else: 157 regCcCode = calcCcCode % { 158 "icValue": secondOpRe.sub(regOp2, cCode[1]), 159 "ivValue": secondOpRe.sub(regOp2, vCode), 160 "negBit": negBit 161 } 162 regCode = secondOpRe.sub(regOp2, code) 163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", 164 {"code" : regCode, 165 "predicate_test": predicateTest}, instFlags) 166 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 167 "DataRegOp", 168 {"code" : regCode + regCcCode, 169 "predicate_test": condPredicateTest}, 170 instFlags) 171 172 def subst(iop): 173 global header_output, decoder_output, exec_output 174 header_output += DataRegDeclare.subst(iop) 175 decoder_output += DataRegConstructor.subst(iop) 176 exec_output += PredOpExecute.subst(iop) 177 178 if buildNonCc: 179 subst(regIop) 180 if buildCc: 181 subst(regIopCc) 182 183 def buildRegRegDataInst(mnem, code, flagType = "logic", \ 184 suffix = "RegReg", \ 185 buildCc = True, buildNonCc = True): 186 cCode = carryCode[flagType] 187 vCode = overflowCode[flagType] 188 negBit = 31 189 if flagType == "llbit": 190 negBit = 63 191 if flagType == "saturate": 192 regRegCcCode = calcQCode 193 elif flagType == "ge": 194 regRegCcCode = calcGECode 195 else: 196 regRegCcCode = calcCcCode % { 197 "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 198 "ivValue": secondOpRe.sub(regRegOp2, vCode), 199 "negBit": negBit 200 } 201 regRegCode = secondOpRe.sub(regRegOp2, code) 202 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, 203 "DataRegRegOp", 204 {"code" : regRegCode, 205 "predicate_test": predicateTest}) 206 regRegIopCc = InstObjParams(mnem + "s", 207 mnem.capitalize() + suffix + "Cc", 208 "DataRegRegOp", 209 {"code" : regRegCode + regRegCcCode, 210 "predicate_test": condPredicateTest}) 211 212 def subst(iop): 213 global header_output, decoder_output, exec_output 214 header_output += DataRegRegDeclare.subst(iop) 215 decoder_output += DataRegRegConstructor.subst(iop) 216 exec_output += PredOpExecute.subst(iop) 217 218 if buildNonCc: 219 subst(regRegIop) 220 if buildCc: 221 subst(regRegIopCc) 222 223 def buildDataInst(mnem, code, flagType = "logic", \ 224 aiw = True, regRegAiw = True, 225 subsPcLr = True): 226 regRegCode = instCode = code 227 if aiw: 228 instCode = "AIW" + instCode 229 if regRegAiw: 230 regRegCode = "AIW" + regRegCode 231 232 buildImmDataInst(mnem, instCode, flagType) 233 buildRegDataInst(mnem, instCode, flagType) 234 buildRegRegDataInst(mnem, regRegCode, flagType) 235 if subsPcLr: 236 code += ''' 237 SCTLR sctlr = Sctlr; 238 uint32_t newCpsr = 239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 240 Cpsr = ~CondCodesMask & newCpsr; 241 CondCodes = CondCodesMask & newCpsr; 242 NextThumb = ((CPSR)newCpsr).t; 243 NextJazelle = ((CPSR)newCpsr).j; 244 ''' 245 buildImmDataInst(mnem + 's', code, flagType, 246 suffix = "ImmPclr", buildCc = False, 247 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 248 buildRegDataInst(mnem + 's', code, flagType, 249 suffix = "RegPclr", buildCc = False, 250 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 251 252 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 253 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 254 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 255 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 256 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") 257 buildImmDataInst("adr", ''' 258 Dest = resTemp = (PC & ~0x3) + 259 (op1 ? secondOp : -secondOp); 260 ''') 261 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") 262 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub") 263 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb") 264 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False) 265 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False) 266 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False) 267 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False) 268 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;") 269 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False) 270 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False) 271 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;") 272 buildDataInst("mvn", "Dest = resTemp = ~secondOp;") 273 buildDataInst("movt", 274 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);", 275 aiw = False) 276 277 buildRegDataInst("qadd", ''' 278 int32_t midRes; 279 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw); 280 Dest = midRes; 281 ''', flagType="saturate", buildNonCc=False) 282 buildRegDataInst("qadd16", ''' 283 int32_t midRes; 284 for (unsigned i = 0; i < 2; i++) { 285 int high = (i + 1) * 16 - 1; 286 int low = i * 16; 287 int64_t arg1 = sext<16>(bits(Op1.sw, high, low)); 288 int64_t arg2 = sext<16>(bits(Op2.sw, high, low)); 289 saturateOp<16>(midRes, arg1, arg2); 290 replaceBits(resTemp, high, low, midRes); 291 } 292 Dest = resTemp; 293 ''', flagType="none", buildCc=False) 294 buildRegDataInst("qadd8", ''' 295 int32_t midRes; 296 for (unsigned i = 0; i < 4; i++) { 297 int high = (i + 1) * 8 - 1; 298 int low = i * 8; 299 int64_t arg1 = sext<8>(bits(Op1.sw, high, low)); 300 int64_t arg2 = sext<8>(bits(Op2.sw, high, low)); 301 saturateOp<8>(midRes, arg1, arg2); 302 replaceBits(resTemp, high, low, midRes); 303 } 304 Dest = resTemp; 305 ''', flagType="none", buildCc=False) 306 buildRegDataInst("qdadd", ''' 307 int32_t midRes; 308 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) | 309 saturateOp<32>(midRes, Op1.sw, midRes); 310 Dest = midRes; 311 ''', flagType="saturate", buildNonCc=False) 312 buildRegDataInst("qsub", ''' 313 int32_t midRes; 314 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true); 315 Dest = midRes; 316 ''', flagType="saturate") 317 buildRegDataInst("qsub16", ''' 318 int32_t midRes; 319 for (unsigned i = 0; i < 2; i++) { 320 int high = (i + 1) * 16 - 1; 321 int low = i * 16; 322 int64_t arg1 = sext<16>(bits(Op1.sw, high, low)); 323 int64_t arg2 = sext<16>(bits(Op2.sw, high, low)); 324 saturateOp<16>(midRes, arg1, arg2, true); 325 replaceBits(resTemp, high, low, midRes); 326 } 327 Dest = resTemp; 328 ''', flagType="none", buildCc=False) 329 buildRegDataInst("qsub8", ''' 330 int32_t midRes; 331 for (unsigned i = 0; i < 4; i++) { 332 int high = (i + 1) * 8 - 1; 333 int low = i * 8; 334 int64_t arg1 = sext<8>(bits(Op1.sw, high, low)); 335 int64_t arg2 = sext<8>(bits(Op2.sw, high, low)); 336 saturateOp<8>(midRes, arg1, arg2, true); 337 replaceBits(resTemp, high, low, midRes); 338 } 339 Dest = resTemp; 340 ''', flagType="none", buildCc=False) 341 buildRegDataInst("qdsub", ''' 342 int32_t midRes; 343 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) | 344 saturateOp<32>(midRes, Op1.sw, midRes, true); 345 Dest = midRes; 346 ''', flagType="saturate", buildNonCc=False) 347 buildRegDataInst("qasx", ''' 348 int32_t midRes; 349 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 350 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 351 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 352 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 353 saturateOp<16>(midRes, arg1Low, arg2High, true); 354 replaceBits(resTemp, 15, 0, midRes); 355 saturateOp<16>(midRes, arg1High, arg2Low); 356 replaceBits(resTemp, 31, 16, midRes); 357 Dest = resTemp; 358 ''', flagType="none", buildCc=False) 359 buildRegDataInst("qsax", ''' 360 int32_t midRes; 361 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 362 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 363 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 364 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 365 saturateOp<16>(midRes, arg1Low, arg2High); 366 replaceBits(resTemp, 15, 0, midRes); 367 saturateOp<16>(midRes, arg1High, arg2Low, true); 368 replaceBits(resTemp, 31, 16, midRes); 369 Dest = resTemp; 370 ''', flagType="none", buildCc=False) 371 372 buildRegDataInst("sadd8", ''' 373 uint32_t geBits = 0; 374 resTemp = 0; 375 for (unsigned i = 0; i < 4; i++) { 376 int high = (i + 1) * 8 - 1; 377 int low = i * 8; 378 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) + 379 sext<8>(bits(Op2.sw, high, low)); 380 replaceBits(resTemp, high, low, midRes); 381 if (midRes >= 0) { 382 geBits = geBits | (1 << i); 383 } 384 } 385 Dest = resTemp; 386 resTemp = geBits; 387 ''', flagType="ge", buildNonCc=False) 388 buildRegDataInst("sadd16", ''' 389 uint32_t geBits = 0; 390 resTemp = 0; 391 for (unsigned i = 0; i < 2; i++) { 392 int high = (i + 1) * 16 - 1; 393 int low = i * 16; 394 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) + 395 sext<16>(bits(Op2.sw, high, low)); 396 replaceBits(resTemp, high, low, midRes); 397 if (midRes >= 0) { 398 geBits = geBits | (0x3 << (i * 2)); 399 } 400 } 401 Dest = resTemp; 402 resTemp = geBits; 403 ''', flagType="ge", buildNonCc=False) 404 405 buildRegDataInst("ssub8", ''' 406 uint32_t geBits = 0; 407 resTemp = 0; 408 for (unsigned i = 0; i < 4; i++) { 409 int high = (i + 1) * 8 - 1; 410 int low = i * 8; 411 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) - 412 sext<8>(bits(Op2.sw, high, low)); 413 replaceBits(resTemp, high, low, midRes); 414 if (midRes >= 0) { 415 geBits = geBits | (1 << i); 416 } 417 } 418 Dest = resTemp; 419 resTemp = geBits; 420 ''', flagType="ge", buildNonCc=False) 421 buildRegDataInst("ssub16", ''' 422 uint32_t geBits = 0; 423 resTemp = 0; 424 for (unsigned i = 0; i < 2; i++) { 425 int high = (i + 1) * 16 - 1; 426 int low = i * 16; 427 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) - 428 sext<16>(bits(Op2.sw, high, low)); 429 replaceBits(resTemp, high, low, midRes); 430 if (midRes >= 0) { 431 geBits = geBits | (0x3 << (i * 2)); 432 } 433 } 434 Dest = resTemp; 435 resTemp = geBits; 436 ''', flagType="ge", buildNonCc=False) 437 buildRegDataInst("sasx", ''' 438 int32_t midRes, geBits = 0; 439 resTemp = 0; 440 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 441 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 442 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 443 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 444 midRes = arg1Low - arg2High; 445 if (midRes >= 0) { 446 geBits = geBits | 0x3; 447 } 448 replaceBits(resTemp, 15, 0, midRes); 449 midRes = arg1High + arg2Low; 450 if (midRes >= 0) { 451 geBits = geBits | 0xc; 452 } 453 replaceBits(resTemp, 31, 16, midRes); 454 Dest = resTemp; 455 resTemp = geBits; 456 ''', flagType="ge", buildNonCc=True) 457 buildRegDataInst("ssax", ''' 458 int32_t midRes, geBits = 0; 459 resTemp = 0; 460 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 461 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 462 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 463 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 464 midRes = arg1Low + arg2High; 465 if (midRes >= 0) { 466 geBits = geBits | 0x3; 467 } 468 replaceBits(resTemp, 15, 0, midRes); 469 midRes = arg1High - arg2Low; 470 if (midRes >= 0) { 471 geBits = geBits | 0xc; 472 } 473 replaceBits(resTemp, 31, 16, midRes); 474 Dest = resTemp; 475 resTemp = geBits; 476 ''', flagType="ge", buildNonCc=True) 477 478 buildRegDataInst("shadd8", ''' 479 resTemp = 0; 480 for (unsigned i = 0; i < 4; i++) { 481 int high = (i + 1) * 8 - 1; 482 int low = i * 8; 483 int32_t midRes = 484 (uint64_t)(sext<8>(bits(Op1.sw, high, low)) + 485 sext<8>(bits(Op2.sw, high, low))) >> 1; 486 replaceBits(resTemp, high, low, midRes); 487 } 488 Dest = resTemp; 489 ''', flagType="none", buildCc=False) 490 buildRegDataInst("shadd16", ''' 491 resTemp = 0; 492 for (unsigned i = 0; i < 2; i++) { 493 int high = (i + 1) * 16 - 1; 494 int low = i * 16; 495 int32_t midRes = 496 (uint64_t)(sext<16>(bits(Op1.sw, high, low)) + 497 sext<16>(bits(Op2.sw, high, low))) >> 1; 498 replaceBits(resTemp, high, low, midRes); 499 } 500 Dest = resTemp; 501 ''', flagType="none", buildCc=False) 502 buildRegDataInst("shsub8", ''' 503 resTemp = 0; 504 for (unsigned i = 0; i < 4; i++) { 505 int high = (i + 1) * 8 - 1; 506 int low = i * 8; 507 int32_t midRes = 508 (uint64_t)(sext<8>(bits(Op1.sw, high, low)) - 509 sext<8>(bits(Op2.sw, high, low))) >> 1; 510 replaceBits(resTemp, high, low, midRes); 511 } 512 Dest = resTemp; 513 ''', flagType="none", buildCc=False) 514 buildRegDataInst("shsub16", ''' 515 resTemp = 0; 516 for (unsigned i = 0; i < 2; i++) { 517 int high = (i + 1) * 16 - 1; 518 int low = i * 16; 519 int32_t midRes = 520 (uint64_t)(sext<16>(bits(Op1.sw, high, low)) - 521 sext<16>(bits(Op2.sw, high, low))) >> 1; 522 replaceBits(resTemp, high, low, midRes); 523 } 524 Dest = resTemp; 525 ''', flagType="none", buildCc=False) 526 buildRegDataInst("shasx", ''' 527 int32_t midRes; 528 resTemp = 0; 529 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 530 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 531 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 532 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 533 midRes = (uint64_t)(arg1Low - arg2High) >> 1; 534 replaceBits(resTemp, 15, 0, midRes); 535 midRes = (arg1High + arg2Low) >> 1; 536 replaceBits(resTemp, 31, 16, midRes); 537 Dest = resTemp; 538 ''', flagType="none", buildCc=True) 539 buildRegDataInst("shsax", ''' 540 int32_t midRes; 541 resTemp = 0; 542 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); 543 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); 544 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 545 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 546 midRes = (uint64_t)(arg1Low + arg2High) >> 1; 547 replaceBits(resTemp, 15, 0, midRes); 548 midRes = (uint64_t)(arg1High - arg2Low) >> 1; 549 replaceBits(resTemp, 31, 16, midRes); 550 Dest = resTemp; 551 ''', flagType="none", buildCc=True) 552 553 buildRegDataInst("uqadd16", ''' 554 uint32_t midRes; 555 for (unsigned i = 0; i < 2; i++) { 556 int high = (i + 1) * 16 - 1; 557 int low = i * 16; 558 uint64_t arg1 = bits(Op1, high, low); 559 uint64_t arg2 = bits(Op2, high, low); 560 uSaturateOp<16>(midRes, arg1, arg2); 561 replaceBits(resTemp, high, low, midRes); 562 } 563 Dest = resTemp; 564 ''', flagType="none", buildCc=False) 565 buildRegDataInst("uqadd8", ''' 566 uint32_t midRes; 567 for (unsigned i = 0; i < 4; i++) { 568 int high = (i + 1) * 8 - 1; 569 int low = i * 8; 570 uint64_t arg1 = bits(Op1, high, low); 571 uint64_t arg2 = bits(Op2, high, low); 572 uSaturateOp<8>(midRes, arg1, arg2); 573 replaceBits(resTemp, high, low, midRes); 574 } 575 Dest = resTemp; 576 ''', flagType="none", buildCc=False) 577 buildRegDataInst("uqsub16", ''' 578 uint32_t midRes; 579 for (unsigned i = 0; i < 2; i++) { 580 int high = (i + 1) * 16 - 1; 581 int low = i * 16; 582 uint64_t arg1 = bits(Op1, high, low); 583 uint64_t arg2 = bits(Op2, high, low); 584 uSaturateOp<16>(midRes, arg1, arg2, true); 585 replaceBits(resTemp, high, low, midRes); 586 } 587 Dest = resTemp; 588 ''', flagType="none", buildCc=False) 589 buildRegDataInst("uqsub8", ''' 590 uint32_t midRes; 591 for (unsigned i = 0; i < 4; i++) { 592 int high = (i + 1) * 8 - 1; 593 int low = i * 8; 594 uint64_t arg1 = bits(Op1, high, low); 595 uint64_t arg2 = bits(Op2, high, low); 596 uSaturateOp<8>(midRes, arg1, arg2, true); 597 replaceBits(resTemp, high, low, midRes); 598 } 599 Dest = resTemp; 600 ''', flagType="none", buildCc=False) 601 buildRegDataInst("uqasx", ''' 602 uint32_t midRes; 603 uint64_t arg1Low = bits(Op1.sw, 15, 0); 604 uint64_t arg1High = bits(Op1.sw, 31, 16); 605 uint64_t arg2Low = bits(Op2.sw, 15, 0); 606 uint64_t arg2High = bits(Op2.sw, 31, 16); 607 uSaturateOp<16>(midRes, arg1Low, arg2High, true); 608 replaceBits(resTemp, 15, 0, midRes); 609 uSaturateOp<16>(midRes, arg1High, arg2Low); 610 replaceBits(resTemp, 31, 16, midRes); 611 Dest = resTemp; 612 ''', flagType="none", buildCc=False) 613 buildRegDataInst("uqsax", ''' 614 uint32_t midRes; 615 uint64_t arg1Low = bits(Op1.sw, 15, 0); 616 uint64_t arg1High = bits(Op1.sw, 31, 16); 617 uint64_t arg2Low = bits(Op2.sw, 15, 0); 618 uint64_t arg2High = bits(Op2.sw, 31, 16); 619 uSaturateOp<16>(midRes, arg1Low, arg2High); 620 replaceBits(resTemp, 15, 0, midRes); 621 uSaturateOp<16>(midRes, arg1High, arg2Low, true); 622 replaceBits(resTemp, 31, 16, midRes); 623 Dest = resTemp; 624 ''', flagType="none", buildCc=False) 625 626 buildRegDataInst("uadd16", ''' 627 uint32_t geBits = 0; 628 resTemp = 0; 629 for (unsigned i = 0; i < 2; i++) { 630 int high = (i + 1) * 16 - 1; 631 int low = i * 16; 632 int32_t midRes = bits(Op1, high, low) + 633 bits(Op2, high, low); 634 if (midRes >= 0x10000) { 635 geBits = geBits | (0x3 << (i * 2)); 636 } 637 replaceBits(resTemp, high, low, midRes); 638 } 639 Dest = resTemp; 640 resTemp = geBits; 641 ''', flagType="ge", buildNonCc=False) 642 buildRegDataInst("uadd8", ''' 643 uint32_t geBits = 0; 644 resTemp = 0; 645 for (unsigned i = 0; i < 4; i++) { 646 int high = (i + 1) * 8 - 1; 647 int low = i * 8; 648 int32_t midRes = bits(Op1, high, low) + 649 bits(Op2, high, low); 650 if (midRes >= 0x100) { 651 geBits = geBits | (1 << i); 652 } 653 replaceBits(resTemp, high, low, midRes); 654 } 655 Dest = resTemp; 656 resTemp = geBits; 657 ''', flagType="ge", buildNonCc=False) 658 buildRegDataInst("usub16", ''' 659 uint32_t geBits = 0; 660 resTemp = 0; 661 for (unsigned i = 0; i < 2; i++) { 662 int high = (i + 1) * 16 - 1; 663 int low = i * 16; 664 int32_t midRes = bits(Op1, high, low) - 665 bits(Op2, high, low); 666 if (midRes >= 0) { 667 geBits = geBits | (0x3 << (i * 2)); 668 } 669 replaceBits(resTemp, high, low, midRes); 670 } 671 Dest = resTemp; 672 resTemp = geBits; 673 ''', flagType="ge", buildNonCc=False) 674 buildRegDataInst("usub8", ''' 675 uint32_t geBits = 0; 676 resTemp = 0; 677 for (unsigned i = 0; i < 4; i++) { 678 int high = (i + 1) * 8 - 1; 679 int low = i * 8; 680 int32_t midRes = bits(Op1, high, low) - 681 bits(Op2, high, low); 682 if (midRes >= 0) { 683 geBits = geBits | (1 << i); 684 } 685 replaceBits(resTemp, high, low, midRes); 686 } 687 Dest = resTemp; 688 resTemp = geBits; 689 ''', flagType="ge", buildNonCc=False) 690 buildRegDataInst("uasx", ''' 691 int32_t midRes, geBits = 0; 692 resTemp = 0; 693 int64_t arg1Low = bits(Op1.sw, 15, 0); 694 int64_t arg1High = bits(Op1.sw, 31, 16); 695 int64_t arg2Low = bits(Op2.sw, 15, 0); 696 int64_t arg2High = bits(Op2.sw, 31, 16); 697 midRes = arg1Low - arg2High; 698 if (midRes >= 0) { 699 geBits = geBits | 0x3; 700 } 701 replaceBits(resTemp, 15, 0, midRes); 702 midRes = arg1High + arg2Low; 703 if (midRes >= 0x10000) { 704 geBits = geBits | 0xc; 705 } 706 replaceBits(resTemp, 31, 16, midRes); 707 Dest = resTemp; 708 resTemp = geBits; 709 ''', flagType="ge", buildNonCc=False) 710 buildRegDataInst("usax", ''' 711 int32_t midRes, geBits = 0; 712 resTemp = 0; 713 int64_t arg1Low = bits(Op1.sw, 15, 0); 714 int64_t arg1High = bits(Op1.sw, 31, 16); 715 int64_t arg2Low = bits(Op2.sw, 15, 0); 716 int64_t arg2High = bits(Op2.sw, 31, 16); 717 midRes = arg1Low + arg2High; 718 if (midRes >= 0x10000) { 719 geBits = geBits | 0x3; 720 } 721 replaceBits(resTemp, 15, 0, midRes); 722 midRes = arg1High - arg2Low; 723 if (midRes >= 0) { 724 geBits = geBits | 0xc; 725 } 726 replaceBits(resTemp, 31, 16, midRes); 727 Dest = resTemp; 728 resTemp = geBits; 729 ''', flagType="ge", buildNonCc=False) 730 731 buildRegDataInst("uhadd16", ''' 732 resTemp = 0; 733 for (unsigned i = 0; i < 2; i++) { 734 int high = (i + 1) * 16 - 1; 735 int low = i * 16; 736 int32_t midRes = (bits(Op1, high, low) + 737 bits(Op2, high, low)) >> 1; 738 replaceBits(resTemp, high, low, midRes); 739 } 740 Dest = resTemp; 741 ''', flagType="none", buildCc=False) 742 buildRegDataInst("uhadd8", ''' 743 resTemp = 0; 744 for (unsigned i = 0; i < 4; i++) { 745 int high = (i + 1) * 8 - 1; 746 int low = i * 8; 747 int32_t midRes = (bits(Op1, high, low) + 748 bits(Op2, high, low)) >> 1; 749 replaceBits(resTemp, high, low, midRes); 750 } 751 Dest = resTemp; 752 ''', flagType="none", buildCc=False) 753 buildRegDataInst("uhsub16", ''' 754 resTemp = 0; 755 for (unsigned i = 0; i < 2; i++) { 756 int high = (i + 1) * 16 - 1; 757 int low = i * 16; 758 int32_t midRes = (bits(Op1, high, low) - 759 bits(Op2, high, low)) >> 1; 760 replaceBits(resTemp, high, low, midRes); 761 } 762 Dest = resTemp; 763 ''', flagType="none", buildCc=False) 764 buildRegDataInst("uhsub8", ''' 765 resTemp = 0; 766 for (unsigned i = 0; i < 4; i++) { 767 int high = (i + 1) * 8 - 1; 768 int low = i * 8; 769 int32_t midRes = (bits(Op1, high, low) - 770 bits(Op2, high, low)) >> 1; 771 replaceBits(resTemp, high, low, midRes); 772 } 773 Dest = resTemp; 774 ''', flagType="none", buildCc=False) 775 buildRegDataInst("uhasx", ''' 776 int32_t midRes; 777 resTemp = 0; 778 int64_t arg1Low = bits(Op1.sw, 15, 0); 779 int64_t arg1High = bits(Op1.sw, 31, 16); 780 int64_t arg2Low = bits(Op2.sw, 15, 0); 781 int64_t arg2High = bits(Op2.sw, 31, 16); 782 midRes = (arg1Low - arg2High) >> 1; 783 replaceBits(resTemp, 15, 0, midRes); 784 midRes = (arg1High + arg2Low) >> 1; 785 replaceBits(resTemp, 31, 16, midRes); 786 Dest = resTemp; 787 ''', flagType="none", buildCc=False) 788 buildRegDataInst("uhsax", ''' 789 int32_t midRes; 790 resTemp = 0; 791 int64_t arg1Low = bits(Op1.sw, 15, 0); 792 int64_t arg1High = bits(Op1.sw, 31, 16); 793 int64_t arg2Low = bits(Op2.sw, 15, 0); 794 int64_t arg2High = bits(Op2.sw, 31, 16); 795 midRes = (arg1Low + arg2High) >> 1; 796 replaceBits(resTemp, 15, 0, midRes); 797 midRes = (arg1High - arg2Low) >> 1; 798 replaceBits(resTemp, 31, 16, midRes); 799 Dest = resTemp; 800 ''', flagType="none", buildCc=False) 801 802 buildRegDataInst("pkhbt", ''' 803 uint32_t resTemp = 0; 804 uint16_t arg1Low = bits(Op1, 15, 0); 805 uint16_t arg2High = bits(secondOp, 31, 16); 806 replaceBits(resTemp, 15, 0, arg1Low); 807 replaceBits(resTemp, 31, 16, arg2High); 808 Dest = resTemp; 809 ''', flagType="none", buildCc=False) 810 buildRegDataInst("pkhtb", ''' 811 uint32_t resTemp = 0; 812 uint16_t arg1High = bits(Op1, 31, 16); 813 uint16_t arg2Low = bits(secondOp, 15, 0); 814 replaceBits(resTemp, 15, 0, arg2Low); 815 replaceBits(resTemp, 31, 16, arg1High); 816 Dest = resTemp; 817 ''', flagType="none", buildCc=False) 818}}; 819