data.isa revision 7188
17138Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27138Sgblack@eecs.umich.edu 37138Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47138Sgblack@eecs.umich.edu// All rights reserved 57138Sgblack@eecs.umich.edu// 67138Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77138Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87138Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97138Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107138Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117138Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127138Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137138Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147138Sgblack@eecs.umich.edu// 157138Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167138Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177138Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187138Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197138Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207138Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217138Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227138Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237138Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247138Sgblack@eecs.umich.edu// this software without specific prior written permission. 257138Sgblack@eecs.umich.edu// 267138Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277138Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287138Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297138Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307138Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317138Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327138Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337138Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347138Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357138Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367138Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377138Sgblack@eecs.umich.edu// 387138Sgblack@eecs.umich.edu// Authors: Gabe Black 397138Sgblack@eecs.umich.edu 407138Sgblack@eecs.umich.edulet {{ 417138Sgblack@eecs.umich.edu 427138Sgblack@eecs.umich.edu header_output = "" 437138Sgblack@eecs.umich.edu decoder_output = "" 447138Sgblack@eecs.umich.edu exec_output = "" 457138Sgblack@eecs.umich.edu 467138Sgblack@eecs.umich.edu calcQCode = ''' 477138Sgblack@eecs.umich.edu cprintf("canOverflow: %%d\\n", Dest < resTemp); 487138Sgblack@eecs.umich.edu replaceBits(CondCodes, 27, Dest < resTemp); 497138Sgblack@eecs.umich.edu ''' 507138Sgblack@eecs.umich.edu 517138Sgblack@eecs.umich.edu calcCcCode = ''' 527138Sgblack@eecs.umich.edu uint16_t _ic, _iv, _iz, _in; 537138Sgblack@eecs.umich.edu _in = (resTemp >> %(negBit)d) & 1; 547138Sgblack@eecs.umich.edu _iz = (resTemp == 0); 557138Sgblack@eecs.umich.edu _iv = %(ivValue)s & 1; 567138Sgblack@eecs.umich.edu _ic = %(icValue)s & 1; 577138Sgblack@eecs.umich.edu 587138Sgblack@eecs.umich.edu CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 597138Sgblack@eecs.umich.edu (CondCodes & 0x0FFFFFFF); 607138Sgblack@eecs.umich.edu 617138Sgblack@eecs.umich.edu DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", 627138Sgblack@eecs.umich.edu _in, _iz, _ic, _iv); 637138Sgblack@eecs.umich.edu ''' 647138Sgblack@eecs.umich.edu 657138Sgblack@eecs.umich.edu # Dict of code to set the carry flag. (imm, reg, reg-reg) 667138Sgblack@eecs.umich.edu oldC = 'CondCodes<29:>' 677138Sgblack@eecs.umich.edu oldV = 'CondCodes<28:>' 687138Sgblack@eecs.umich.edu carryCode = { 697138Sgblack@eecs.umich.edu "none": (oldC, oldC, oldC), 707138Sgblack@eecs.umich.edu "llbit": (oldC, oldC, oldC), 717138Sgblack@eecs.umich.edu "overflow": ('0', '0', '0'), 727138Sgblack@eecs.umich.edu "add": ('findCarry(32, resTemp, Op1, secondOp)', 737138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, secondOp)', 747138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, secondOp)'), 757138Sgblack@eecs.umich.edu "sub": ('findCarry(32, resTemp, Op1, ~secondOp)', 767138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, ~secondOp)', 777138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, Op1, ~secondOp)'), 787138Sgblack@eecs.umich.edu "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)', 797138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, secondOp, ~Op1)', 807138Sgblack@eecs.umich.edu 'findCarry(32, resTemp, secondOp, ~Op1)'), 817138Sgblack@eecs.umich.edu "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC, 827138Sgblack@eecs.umich.edu 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC, 837138Sgblack@eecs.umich.edu 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC) 847138Sgblack@eecs.umich.edu } 857138Sgblack@eecs.umich.edu # Dict of code to set the overflow flag. 867138Sgblack@eecs.umich.edu overflowCode = { 877138Sgblack@eecs.umich.edu "none": oldV, 887138Sgblack@eecs.umich.edu "llbit": oldV, 897138Sgblack@eecs.umich.edu "overflow": '0', 907138Sgblack@eecs.umich.edu "add": 'findOverflow(32, resTemp, Op1, secondOp)', 917138Sgblack@eecs.umich.edu "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 927138Sgblack@eecs.umich.edu "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 937138Sgblack@eecs.umich.edu "logic": oldV 947138Sgblack@eecs.umich.edu } 957138Sgblack@eecs.umich.edu 967138Sgblack@eecs.umich.edu secondOpRe = re.compile("secondOp") 977138Sgblack@eecs.umich.edu immOp2 = "imm" 987138Sgblack@eecs.umich.edu regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 997181Sgblack@eecs.umich.edu regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 1007138Sgblack@eecs.umich.edu 1017188Sgblack@eecs.umich.edu def buildImmDataInst(mnem, code, flagType = "logic", \ 1027188Sgblack@eecs.umich.edu suffix = "Imm", buildCc = True): 1037138Sgblack@eecs.umich.edu cCode = carryCode[flagType] 1047138Sgblack@eecs.umich.edu vCode = overflowCode[flagType] 1057138Sgblack@eecs.umich.edu negBit = 31 1067138Sgblack@eecs.umich.edu if flagType == "llbit": 1077138Sgblack@eecs.umich.edu negBit = 63 1087138Sgblack@eecs.umich.edu if flagType == "overflow": 1097184Sgblack@eecs.umich.edu immCcCode = calcQCode 1107138Sgblack@eecs.umich.edu else: 1117138Sgblack@eecs.umich.edu immCcCode = calcCcCode % { 1127138Sgblack@eecs.umich.edu "icValue": secondOpRe.sub(immOp2, cCode[0]), 1137138Sgblack@eecs.umich.edu "ivValue": secondOpRe.sub(immOp2, vCode), 1147138Sgblack@eecs.umich.edu "negBit": negBit 1157138Sgblack@eecs.umich.edu } 1167184Sgblack@eecs.umich.edu immCode = secondOpRe.sub(immOp2, code) 1177188Sgblack@eecs.umich.edu immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", 1187184Sgblack@eecs.umich.edu {"code" : immCode, 1197184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1207188Sgblack@eecs.umich.edu immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 1217184Sgblack@eecs.umich.edu "DataImmOp", 1227184Sgblack@eecs.umich.edu {"code" : immCode + immCcCode, 1237184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1247184Sgblack@eecs.umich.edu 1257188Sgblack@eecs.umich.edu def subst(iop): 1267188Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1277188Sgblack@eecs.umich.edu header_output += DataImmDeclare.subst(iop) 1287188Sgblack@eecs.umich.edu decoder_output += DataImmConstructor.subst(iop) 1297188Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 1307188Sgblack@eecs.umich.edu 1317188Sgblack@eecs.umich.edu subst(immIop) 1327188Sgblack@eecs.umich.edu if buildCc: 1337188Sgblack@eecs.umich.edu subst(immIopCc) 1347188Sgblack@eecs.umich.edu 1357188Sgblack@eecs.umich.edu def buildRegDataInst(mnem, code, flagType = "logic", \ 1367188Sgblack@eecs.umich.edu suffix = "Reg", buildCc = True): 1377184Sgblack@eecs.umich.edu cCode = carryCode[flagType] 1387184Sgblack@eecs.umich.edu vCode = overflowCode[flagType] 1397184Sgblack@eecs.umich.edu negBit = 31 1407184Sgblack@eecs.umich.edu if flagType == "llbit": 1417184Sgblack@eecs.umich.edu negBit = 63 1427184Sgblack@eecs.umich.edu if flagType == "overflow": 1437184Sgblack@eecs.umich.edu regCcCode = calcQCode 1447184Sgblack@eecs.umich.edu else: 1457138Sgblack@eecs.umich.edu regCcCode = calcCcCode % { 1467138Sgblack@eecs.umich.edu "icValue": secondOpRe.sub(regOp2, cCode[1]), 1477138Sgblack@eecs.umich.edu "ivValue": secondOpRe.sub(regOp2, vCode), 1487138Sgblack@eecs.umich.edu "negBit": negBit 1497138Sgblack@eecs.umich.edu } 1507184Sgblack@eecs.umich.edu regCode = secondOpRe.sub(regOp2, code) 1517188Sgblack@eecs.umich.edu regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", 1527184Sgblack@eecs.umich.edu {"code" : regCode, 1537184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1547188Sgblack@eecs.umich.edu regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 1557184Sgblack@eecs.umich.edu "DataRegOp", 1567184Sgblack@eecs.umich.edu {"code" : regCode + regCcCode, 1577184Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1587184Sgblack@eecs.umich.edu 1597188Sgblack@eecs.umich.edu def subst(iop): 1607188Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1617188Sgblack@eecs.umich.edu header_output += DataRegDeclare.subst(iop) 1627188Sgblack@eecs.umich.edu decoder_output += DataRegConstructor.subst(iop) 1637188Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 1647188Sgblack@eecs.umich.edu 1657188Sgblack@eecs.umich.edu subst(regIop) 1667188Sgblack@eecs.umich.edu if buildCc: 1677188Sgblack@eecs.umich.edu subst(regIopCc) 1687188Sgblack@eecs.umich.edu 1697188Sgblack@eecs.umich.edu def buildRegRegDataInst(mnem, code, flagType = "logic", \ 1707188Sgblack@eecs.umich.edu suffix = "RegReg", buildCc = True): 1717184Sgblack@eecs.umich.edu cCode = carryCode[flagType] 1727184Sgblack@eecs.umich.edu vCode = overflowCode[flagType] 1737184Sgblack@eecs.umich.edu negBit = 31 1747184Sgblack@eecs.umich.edu if flagType == "llbit": 1757184Sgblack@eecs.umich.edu negBit = 63 1767184Sgblack@eecs.umich.edu if flagType == "overflow": 1777184Sgblack@eecs.umich.edu regRegCcCode = calcQCode 1787184Sgblack@eecs.umich.edu else: 1797138Sgblack@eecs.umich.edu regRegCcCode = calcCcCode % { 1807138Sgblack@eecs.umich.edu "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 1817138Sgblack@eecs.umich.edu "ivValue": secondOpRe.sub(regRegOp2, vCode), 1827138Sgblack@eecs.umich.edu "negBit": negBit 1837138Sgblack@eecs.umich.edu } 1847138Sgblack@eecs.umich.edu regRegCode = secondOpRe.sub(regRegOp2, code) 1857188Sgblack@eecs.umich.edu regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, 1867138Sgblack@eecs.umich.edu "DataRegRegOp", 1877138Sgblack@eecs.umich.edu {"code" : regRegCode, 1887138Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1897138Sgblack@eecs.umich.edu regRegIopCc = InstObjParams(mnem + "s", 1907188Sgblack@eecs.umich.edu mnem.capitalize() + suffix + "Cc", 1917138Sgblack@eecs.umich.edu "DataRegRegOp", 1927138Sgblack@eecs.umich.edu {"code" : regRegCode + regRegCcCode, 1937138Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 1947138Sgblack@eecs.umich.edu 1957188Sgblack@eecs.umich.edu def subst(iop): 1967188Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1977188Sgblack@eecs.umich.edu header_output += DataRegRegDeclare.subst(iop) 1987188Sgblack@eecs.umich.edu decoder_output += DataRegRegConstructor.subst(iop) 1997188Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 2007184Sgblack@eecs.umich.edu 2017188Sgblack@eecs.umich.edu subst(regRegIop) 2027188Sgblack@eecs.umich.edu if buildCc: 2037188Sgblack@eecs.umich.edu subst(regRegIopCc) 2047188Sgblack@eecs.umich.edu 2057188Sgblack@eecs.umich.edu def buildDataInst(mnem, code, flagType = "logic", \ 2067188Sgblack@eecs.umich.edu aiw = True, regRegAiw = True, 2077188Sgblack@eecs.umich.edu subsPcLr = True): 2087188Sgblack@eecs.umich.edu regRegCode = instCode = code 2097188Sgblack@eecs.umich.edu if aiw: 2107188Sgblack@eecs.umich.edu instCode = "AIW" + instCode 2117188Sgblack@eecs.umich.edu if regRegAiw: 2127188Sgblack@eecs.umich.edu regRegCode = "AIW" + regRegCode 2137188Sgblack@eecs.umich.edu 2147188Sgblack@eecs.umich.edu buildImmDataInst(mnem, instCode, flagType) 2157188Sgblack@eecs.umich.edu buildRegDataInst(mnem, instCode, flagType) 2167188Sgblack@eecs.umich.edu buildRegRegDataInst(mnem, regRegCode, flagType) 2177188Sgblack@eecs.umich.edu if subsPcLr: 2187188Sgblack@eecs.umich.edu code += ''' 2197188Sgblack@eecs.umich.edu uint32_t newCpsr = 2207188Sgblack@eecs.umich.edu cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true); 2217188Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 2227188Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 2237188Sgblack@eecs.umich.edu ''' 2247188Sgblack@eecs.umich.edu buildImmDataInst(mnem + 's', code, flagType, 2257188Sgblack@eecs.umich.edu suffix = "ImmPclr", buildCc = False) 2267188Sgblack@eecs.umich.edu buildRegDataInst(mnem + 's', code, flagType, 2277188Sgblack@eecs.umich.edu suffix = "RegPclr", buildCc = False) 2287188Sgblack@eecs.umich.edu 2297188Sgblack@eecs.umich.edu buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 2307188Sgblack@eecs.umich.edu buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 2317188Sgblack@eecs.umich.edu buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 2327188Sgblack@eecs.umich.edu buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 2337188Sgblack@eecs.umich.edu buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") 2347185Sgblack@eecs.umich.edu buildImmDataInst("adr", ''' 2357188Sgblack@eecs.umich.edu Dest = resTemp = (readPC(xc) & ~0x3) + 2367185Sgblack@eecs.umich.edu (op1 ? secondOp : -secondOp); 2377185Sgblack@eecs.umich.edu ''') 2387188Sgblack@eecs.umich.edu buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") 2397188Sgblack@eecs.umich.edu buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub") 2407188Sgblack@eecs.umich.edu buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb") 2417188Sgblack@eecs.umich.edu buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False) 2427188Sgblack@eecs.umich.edu buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False) 2437188Sgblack@eecs.umich.edu buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False) 2447188Sgblack@eecs.umich.edu buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False) 2457188Sgblack@eecs.umich.edu buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;") 2467188Sgblack@eecs.umich.edu buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False) 2477188Sgblack@eecs.umich.edu buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False) 2487188Sgblack@eecs.umich.edu buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;") 2497188Sgblack@eecs.umich.edu buildDataInst("mvn", "Dest = resTemp = ~secondOp;") 2507156Sgblack@eecs.umich.edu buildDataInst("movt", 2517188Sgblack@eecs.umich.edu "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);", 2527188Sgblack@eecs.umich.edu aiw = False) 2537138Sgblack@eecs.umich.edu}}; 254