branch64.isa revision 10037
1// -*- mode:c++ -*- 2 3// Copyright (c) 2011-2013 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39// Giacomo Gabrielli 40 41let {{ 42 43 header_output = "" 44 decoder_output = "" 45 exec_output = "" 46 47 # B, BL 48 for (mnem, link) in (("b", False), ("bl", True)): 49 bCode = ('NPC = purifyTaggedAddr(RawPC + imm, xc->tcBase(), ' 50 'currEL(xc->tcBase()));\n') 51 instFlags = ['IsDirectControl', 'IsUncondControl'] 52 if (link): 53 bCode += 'XLR = RawPC + 4;\n' 54 instFlags += ['IsCall'] 55 56 bIop = InstObjParams(mnem, mnem.capitalize() + "64", 57 "BranchImm64", bCode, instFlags) 58 header_output += BranchImm64Declare.subst(bIop) 59 decoder_output += BranchImm64Constructor.subst(bIop) 60 exec_output += BasicExecute.subst(bIop) 61 62 # BR, BLR 63 for (mnem, link) in (("br", False), ("blr", True)): 64 bCode = ('NPC = purifyTaggedAddr(XOp1, xc->tcBase(), ' 65 'currEL(xc->tcBase()));\n') 66 instFlags = ['IsIndirectControl', 'IsUncondControl'] 67 if (link): 68 bCode += 'XLR = RawPC + 4;\n' 69 instFlags += ['IsCall'] 70 71 bIop = InstObjParams(mnem, mnem.capitalize() + "64", 72 "BranchReg64", bCode, instFlags) 73 header_output += BranchReg64Declare.subst(bIop) 74 decoder_output += BranchReg64Constructor.subst(bIop) 75 exec_output += BasicExecute.subst(bIop) 76 77 # B conditional 78 bCode = ''' 79 if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)) 80 NPC = purifyTaggedAddr(RawPC + imm, xc->tcBase(), 81 currEL(xc->tcBase())); 82 else 83 NPC = NPC; 84 ''' 85 bIop = InstObjParams("b", "BCond64", "BranchImmCond64", bCode, 86 ['IsCondControl', 'IsDirectControl']) 87 header_output += BranchImmCond64Declare.subst(bIop) 88 decoder_output += BranchImmCond64Constructor.subst(bIop) 89 exec_output += BasicExecute.subst(bIop) 90 91 # RET 92 bCode = ('NPC = purifyTaggedAddr(XOp1, xc->tcBase(), ' 93 'currEL(xc->tcBase()));\n') 94 instFlags = ['IsIndirectControl', 'IsUncondControl', 'IsReturn'] 95 96 bIop = InstObjParams('ret', 'Ret64', "BranchRet64", bCode, instFlags) 97 header_output += BranchReg64Declare.subst(bIop) 98 decoder_output += BranchReg64Constructor.subst(bIop) 99 exec_output += BasicExecute.subst(bIop) 100 101 # ERET 102 bCode = '''Addr newPc; 103 CPSR cpsr = Cpsr; 104 CPSR spsr = Spsr; 105 106 ExceptionLevel curr_el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 107 switch (curr_el) { 108 case EL3: 109 newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL3); 110 break; 111 case EL2: 112 newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL2); 113 break; 114 case EL1: 115 newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL1); 116 break; 117 default: 118 return new UndefinedInstruction(machInst, false, mnemonic); 119 break; 120 } 121 if (spsr.width && (newPc & mask(2))) { 122 // To avoid PC Alignment fault when returning to AArch32 123 if (spsr.t) 124 newPc = newPc & ~mask(1); 125 else 126 newPc = newPc & ~mask(2); 127 } 128 spsr.q = 0; 129 spsr.it1 = 0; 130 spsr.j = 0; 131 spsr.res0_23_22 = 0; 132 spsr.ge = 0; 133 spsr.it2 = 0; 134 spsr.t = 0; 135 136 OperatingMode mode = (OperatingMode) (uint8_t) spsr.mode; 137 bool illegal = false; 138 ExceptionLevel target_el; 139 if (badMode(mode)) { 140 illegal = true; 141 } else { 142 target_el = opModeToEL(mode); 143 if (((target_el == EL2) && 144 !ArmSystem::haveVirtualization(xc->tcBase())) || 145 (target_el > curr_el) || 146 (spsr.width == 1)) { 147 illegal = true; 148 } else { 149 bool known = true; 150 bool from32 = (spsr.width == 1); 151 bool to32 = false; 152 if (false) { // TODO: !haveAArch32EL 153 to32 = false; 154 } else if (!ArmSystem::highestELIs64(xc->tcBase())) { 155 to32 = true; 156 } else { 157 bool scr_rw, hcr_rw; 158 if (ArmSystem::haveSecurity(xc->tcBase())) { 159 SCR scr = xc->tcBase()->readMiscReg(MISCREG_SCR_EL3); 160 scr_rw = scr.rw; 161 } else { 162 scr_rw = true; 163 } 164 165 if (ArmSystem::haveVirtualization(xc->tcBase())) { 166 HCR hcr = xc->tcBase()->readMiscReg(MISCREG_HCR_EL2); 167 hcr_rw = hcr.rw; 168 } else { 169 hcr_rw = scr_rw; 170 } 171 172 switch (target_el) { 173 case EL3: 174 to32 = false; 175 break; 176 case EL2: 177 to32 = !scr_rw; 178 break; 179 case EL1: 180 to32 = !scr_rw || !hcr_rw; 181 break; 182 case EL0: 183 if (curr_el == EL0) { 184 to32 = cpsr.width; 185 } else if (!scr_rw || !hcr_rw) { 186 // EL0 using AArch32 if EL1 using AArch32 187 to32 = true; 188 } else { 189 known = false; 190 to32 = false; 191 } 192 } 193 } 194 if (known) 195 illegal = (from32 != to32); 196 } 197 } 198 199 if (illegal) { 200 uint8_t old_mode = cpsr.mode; 201 spsr.mode = old_mode; // Preserve old mode when invalid 202 spsr.il = 1; 203 } else { 204 if (cpsr.width != spsr.width) 205 panic("AArch32/AArch64 interprocessing not supported yet"); 206 } 207 Cpsr = spsr; 208 209 CondCodesNZ = spsr.nz; 210 CondCodesC = spsr.c; 211 CondCodesV = spsr.v; 212 NPC = purifyTaggedAddr(newPc, xc->tcBase(), 213 opModeToEL((OperatingMode) (uint8_t) spsr.mode)); 214 LLSCLock = 0; // Clear exclusive monitor 215 SevMailbox = 1; //Set Event Register 216 ''' 217 instFlags = ['IsSerializeAfter', 'IsNonSpeculative', 'IsSquashAfter'] 218 bIop = InstObjParams('eret', 'Eret64', "BranchEret64", bCode, instFlags) 219 header_output += BasicDeclare.subst(bIop) 220 decoder_output += BasicConstructor64.subst(bIop) 221 exec_output += BasicExecute.subst(bIop) 222 223 # CBNZ, CBZ 224 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): 225 code = ('NPC = (Op164 %(test)s 0) ? ' 226 'purifyTaggedAddr(RawPC + imm, xc->tcBase(), ' 227 'currEL(xc->tcBase())) : NPC;\n') 228 code = code % {"test": test} 229 iop = InstObjParams(mnem, mnem.capitalize() + "64", 230 "BranchImmReg64", code, 231 ['IsCondControl', 'IsDirectControl']) 232 header_output += BranchImmReg64Declare.subst(iop) 233 decoder_output += BranchImmReg64Constructor.subst(iop) 234 exec_output += BasicExecute.subst(iop) 235 236 # TBNZ, TBZ 237 for (mnem, test) in (("tbz", "=="), ("tbnz", "!=")): 238 code = ('NPC = ((Op164 & imm1) %(test)s 0) ? ' 239 'purifyTaggedAddr(RawPC + imm2, xc->tcBase(), ' 240 'currEL(xc->tcBase())) : NPC;\n') 241 code = code % {"test": test} 242 iop = InstObjParams(mnem, mnem.capitalize() + "64", 243 "BranchImmImmReg64", code, 244 ['IsCondControl', 'IsDirectControl']) 245 header_output += BranchImmImmReg64Declare.subst(iop) 246 decoder_output += BranchImmImmReg64Constructor.subst(iop) 247 exec_output += BasicExecute.subst(iop) 248}}; 249