branch.isa revision 7692:8173327c9c65
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    # B, BL
47    for (mnem, link) in (("b", False), ("bl", True)):
48        bCode = '''
49        Addr curPc = readPC(xc);
50        NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32));
51        '''
52        if (link):
53            bCode += '''
54                if (!isThumb(curPc))
55                    LR = curPc - 4;
56                else
57                    LR = curPc | 1;
58            '''
59
60        bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
61                             {"code": bCode,
62                              "predicate_test": predicateTest})
63        header_output += BranchImmCondDeclare.subst(bIop)
64        decoder_output += BranchImmCondConstructor.subst(bIop)
65        exec_output += PredOpExecute.subst(bIop)
66
67    # BX, BLX
68    blxCode = '''
69    Addr curPc M5_VAR_USED = readPC(xc);
70    %(link)s
71    // Switch modes
72    %(branch)s
73    '''
74
75    blxList = (("blx", True, True),
76               ("blx", False, True),
77               ("bx", False, False))
78
79    for (mnem, imm, link) in blxList:
80        Name = mnem.capitalize()
81        if imm:
82            Name += "Imm"
83            # Since we're switching ISAs, the target ISA will be the opposite
84            # of the current ISA. !arm is whether the target is ARM.
85            newPC = '(isThumb(curPc) ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
86            base = "BranchImmCond"
87            declare = BranchImmCondDeclare
88            constructor = BranchImmCondConstructor
89        else:
90            Name += "Reg"
91            newPC = 'Op1'
92            base = "BranchRegCond"
93            declare = BranchRegCondDeclare
94            constructor = BranchRegCondConstructor
95        if link and imm:
96            linkStr = '''
97                // The immediate version of the blx thumb instruction
98                // is 32 bits wide, but "next pc" doesn't reflect that
99                // so we don't want to substract 2 from it at this point
100                if (!isThumb(curPc))
101                    LR = curPc - 4;
102                else
103                    LR = curPc  | 1;
104            '''
105        elif link:
106            linkStr = '''
107                if (!isThumb(curPc))
108                    LR = curPc - 4;
109                else
110                    LR = (curPc - 2) | 1;
111            '''
112        else:
113            linkStr = ""
114
115        if imm and link: #blx with imm
116            branchStr = '''
117                Addr tempPc = ((%(newPC)s) & mask(32)) | (curPc & ~mask(32));
118                FNPC = tempPc ^ PcTBit;
119            '''
120        else:
121            branchStr = "IWNPC = %(newPC)s;"
122        branchStr = branchStr % { "newPC" : newPC }
123
124        code = blxCode % {"link": linkStr,
125                          "newPC": newPC,
126                          "branch": branchStr}
127        blxIop = InstObjParams(mnem, Name, base,
128                               {"code": code,
129                                "predicate_test": predicateTest})
130        header_output += declare.subst(blxIop)
131        decoder_output += constructor.subst(blxIop)
132        exec_output += PredOpExecute.subst(blxIop)
133
134    #Ignore BXJ for now
135
136    #CBNZ, CBZ. These are always unconditional as far as predicates
137    for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
138        code = '''
139        Addr curPc = readPC(xc);
140        NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32));
141        '''
142        predTest = "Op1 %(test)s 0" % {"test": test}
143        iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
144                            {"code": code, "predicate_test": predTest})
145        header_output += BranchImmRegDeclare.subst(iop)
146        decoder_output += BranchImmRegConstructor.subst(iop)
147        exec_output += PredOpExecute.subst(iop)
148
149    #TBB, TBH
150    for isTbh in (0, 1):
151        if isTbh:
152            eaCode = '''
153            unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
154                                      ArmISA::TLB::AlignHalfWord |
155                                      ArmISA::TLB::MustBeOne;
156            EA = Op1 + Op2 * 2
157            '''
158            accCode = "NPC = readPC(xc) + 2 * (Mem.uh);"
159            mnem = "tbh"
160        else:
161            eaCode = '''
162            unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
163                                      ArmISA::TLB::AlignByte |
164                                      ArmISA::TLB::MustBeOne;
165            EA = Op1 + Op2
166            '''
167            accCode = "NPC = readPC(xc) + 2 * (Mem.ub);"
168            mnem = "tbb"
169        iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
170                            {'ea_code': eaCode,
171                             'memacc_code': accCode,
172                             'predicate_test': predicateTest})
173        header_output += BranchTableDeclare.subst(iop)
174        decoder_output += BranchRegRegConstructor.subst(iop)
175        exec_output += LoadExecute.subst(iop) + \
176                       LoadInitiateAcc.subst(iop) + \
177                       LoadCompleteAcc.subst(iop)
178}};
179