aarch64.isa revision 10037 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41    movzCode = 'Dest64 = ((uint64_t)imm1) << imm2;'
42    movzIop = InstObjParams("movz", "Movz", "RegImmImmOp", movzCode, [])
43    header_output += RegImmImmOpDeclare.subst(movzIop)
44    decoder_output += RegImmImmOpConstructor.subst(movzIop)
45    exec_output += BasicExecute.subst(movzIop)
46
47    movkCode = 'Dest64 = insertBits(Dest64, imm2 + 15, imm2, imm1);'
48    movkIop = InstObjParams("movk", "Movk", "RegImmImmOp", movkCode, [])
49    header_output += RegImmImmOpDeclare.subst(movkIop)
50    decoder_output += RegImmImmOpConstructor.subst(movkIop)
51    exec_output += BasicExecute.subst(movkIop)
52
53    movnCode = 'Dest64 = ~(((uint64_t)imm1) << imm2);'
54    movnIop = InstObjParams("movn", "Movn", "RegImmImmOp", movnCode, [])
55    header_output += RegImmImmOpDeclare.subst(movnIop)
56    decoder_output += RegImmImmOpConstructor.subst(movnIop)
57    exec_output += BasicExecute.subst(movnIop)
58}};
59